Commit | Line | Data |
---|---|---|
194de561 | 1 | /* |
1ba7a3ee | 2 | * Blackfin On-Chip Serial Driver |
194de561 | 3 | * |
d273e201 | 4 | * Copyright 2006-2008 Analog Devices Inc. |
194de561 | 5 | * |
1ba7a3ee | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
194de561 | 7 | * |
1ba7a3ee | 8 | * Licensed under the GPL-2 or later. |
194de561 BW |
9 | */ |
10 | ||
11 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
12 | #define SUPPORT_SYSRQ | |
13 | #endif | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/ioport.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/console.h> | |
19 | #include <linux/sysrq.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/tty.h> | |
22 | #include <linux/tty_flip.h> | |
23 | #include <linux/serial_core.h> | |
24 | ||
52e15f0e SZ |
25 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
26 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
474f1a66 SZ |
27 | #include <linux/kgdb.h> |
28 | #include <asm/irq_regs.h> | |
29 | #endif | |
30 | ||
194de561 | 31 | #include <asm/gpio.h> |
639f6571 | 32 | #include <mach/bfin_serial_5xx.h> |
194de561 BW |
33 | |
34 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
35 | #include <linux/dma-mapping.h> | |
36 | #include <asm/io.h> | |
37 | #include <asm/irq.h> | |
38 | #include <asm/cacheflush.h> | |
39 | #endif | |
40 | ||
41 | /* UART name and device definitions */ | |
42 | #define BFIN_SERIAL_NAME "ttyBF" | |
43 | #define BFIN_SERIAL_MAJOR 204 | |
44 | #define BFIN_SERIAL_MINOR 64 | |
45 | ||
c9607ecc MF |
46 | static struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS]; |
47 | static int nr_active_ports = ARRAY_SIZE(bfin_serial_resource); | |
48 | ||
52e15f0e SZ |
49 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
50 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
51 | ||
52 | # ifndef CONFIG_SERIAL_BFIN_PIO | |
53 | # error KGDB only support UART in PIO mode. | |
54 | # endif | |
55 | ||
56 | static int kgdboc_port_line; | |
57 | static int kgdboc_break_enabled; | |
58 | #endif | |
194de561 BW |
59 | /* |
60 | * Setup for console. Argument comes from the menuconfig | |
61 | */ | |
62 | #define DMA_RX_XCOUNT 512 | |
63 | #define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT) | |
64 | ||
0aef4564 | 65 | #define DMA_RX_FLUSH_JIFFIES (HZ / 50) |
194de561 BW |
66 | |
67 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
68 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart); | |
69 | #else | |
194de561 | 70 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart); |
194de561 BW |
71 | #endif |
72 | ||
80d5c474 GY |
73 | static void bfin_serial_reset_irda(struct uart_port *port); |
74 | ||
d307d36a SZ |
75 | #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \ |
76 | defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS) | |
77 | static unsigned int bfin_serial_get_mctrl(struct uart_port *port) | |
78 | { | |
79 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
80 | if (uart->cts_pin < 0) | |
81 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
82 | ||
83 | /* CTS PIN is negative assertive. */ | |
84 | if (UART_GET_CTS(uart)) | |
85 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
86 | else | |
87 | return TIOCM_DSR | TIOCM_CAR; | |
88 | } | |
89 | ||
90 | static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
91 | { | |
92 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
93 | if (uart->rts_pin < 0) | |
94 | return; | |
95 | ||
96 | /* RTS PIN is negative assertive. */ | |
97 | if (mctrl & TIOCM_RTS) | |
98 | UART_ENABLE_RTS(uart); | |
99 | else | |
100 | UART_DISABLE_RTS(uart); | |
101 | } | |
102 | ||
103 | /* | |
104 | * Handle any change of modem status signal. | |
105 | */ | |
106 | static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id) | |
107 | { | |
108 | struct bfin_serial_port *uart = dev_id; | |
109 | unsigned int status; | |
110 | ||
111 | status = bfin_serial_get_mctrl(&uart->port); | |
112 | uart_handle_cts_change(&uart->port, status & TIOCM_CTS); | |
113 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS | |
114 | uart->scts = 1; | |
115 | UART_CLEAR_SCTS(uart); | |
116 | UART_CLEAR_IER(uart, EDSSI); | |
117 | #endif | |
118 | ||
119 | return IRQ_HANDLED; | |
120 | } | |
121 | #else | |
122 | static unsigned int bfin_serial_get_mctrl(struct uart_port *port) | |
123 | { | |
124 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
125 | } | |
126 | ||
127 | static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
128 | { | |
129 | } | |
130 | #endif | |
131 | ||
194de561 BW |
132 | /* |
133 | * interrupts are disabled on entry | |
134 | */ | |
135 | static void bfin_serial_stop_tx(struct uart_port *port) | |
136 | { | |
137 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
68a784cb | 138 | #ifdef CONFIG_SERIAL_BFIN_DMA |
0711d857 | 139 | struct circ_buf *xmit = &uart->port.info->xmit; |
68a784cb | 140 | #endif |
194de561 | 141 | |
f4d640c9 | 142 | while (!(UART_GET_LSR(uart) & TEMT)) |
0711d857 | 143 | cpu_relax(); |
f4d640c9 | 144 | |
194de561 BW |
145 | #ifdef CONFIG_SERIAL_BFIN_DMA |
146 | disable_dma(uart->tx_dma_channel); | |
0711d857 SZ |
147 | xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1); |
148 | uart->port.icount.tx += uart->tx_count; | |
149 | uart->tx_count = 0; | |
150 | uart->tx_done = 1; | |
f4d640c9 RH |
151 | #else |
152 | #ifdef CONFIG_BF54x | |
f4d640c9 RH |
153 | /* Clear TFI bit */ |
154 | UART_PUT_LSR(uart, TFI); | |
194de561 | 155 | #endif |
89bf6dc5 | 156 | UART_CLEAR_IER(uart, ETBEI); |
f4d640c9 | 157 | #endif |
194de561 BW |
158 | } |
159 | ||
160 | /* | |
161 | * port is locked and interrupts are disabled | |
162 | */ | |
163 | static void bfin_serial_start_tx(struct uart_port *port) | |
164 | { | |
165 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
80d5c474 GY |
166 | struct tty_struct *tty = uart->port.info->port.tty; |
167 | ||
d307d36a | 168 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS |
daba0280 | 169 | if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) { |
d307d36a SZ |
170 | uart->scts = 0; |
171 | uart_handle_cts_change(&uart->port, uart->scts); | |
172 | } | |
173 | #endif | |
174 | ||
80d5c474 GY |
175 | /* |
176 | * To avoid losting RX interrupt, we reset IR function | |
177 | * before sending data. | |
178 | */ | |
179 | if (tty->termios->c_line == N_IRDA) | |
180 | bfin_serial_reset_irda(port); | |
194de561 BW |
181 | |
182 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
0711d857 SZ |
183 | if (uart->tx_done) |
184 | bfin_serial_dma_tx_chars(uart); | |
f4d640c9 | 185 | #else |
f4d640c9 | 186 | UART_SET_IER(uart, ETBEI); |
a359cca7 | 187 | bfin_serial_tx_chars(uart); |
f4d640c9 | 188 | #endif |
194de561 BW |
189 | } |
190 | ||
191 | /* | |
192 | * Interrupts are enabled | |
193 | */ | |
194 | static void bfin_serial_stop_rx(struct uart_port *port) | |
195 | { | |
196 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
52e15f0e | 197 | |
f4d640c9 | 198 | UART_CLEAR_IER(uart, ERBFI); |
194de561 BW |
199 | } |
200 | ||
201 | /* | |
202 | * Set the modem control timer to fire immediately. | |
203 | */ | |
204 | static void bfin_serial_enable_ms(struct uart_port *port) | |
205 | { | |
206 | } | |
207 | ||
474f1a66 | 208 | |
50e2e15a | 209 | #if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO) |
8851c71e MF |
210 | # define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold) |
211 | # define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v)) | |
212 | #else | |
213 | # define UART_GET_ANOMALY_THRESHOLD(uart) 0 | |
214 | # define UART_SET_ANOMALY_THRESHOLD(uart, v) | |
215 | #endif | |
216 | ||
194de561 | 217 | #ifdef CONFIG_SERIAL_BFIN_PIO |
194de561 BW |
218 | static void bfin_serial_rx_chars(struct bfin_serial_port *uart) |
219 | { | |
52e15f0e | 220 | struct tty_struct *tty = NULL; |
194de561 | 221 | unsigned int status, ch, flg; |
8851c71e | 222 | static struct timeval anomaly_start = { .tv_sec = 0 }; |
194de561 | 223 | |
759eb040 | 224 | status = UART_GET_LSR(uart); |
0bcfd70e MF |
225 | UART_CLEAR_LSR(uart); |
226 | ||
227 | ch = UART_GET_CHAR(uart); | |
194de561 BW |
228 | uart->port.icount.rx++; |
229 | ||
52e15f0e SZ |
230 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
231 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
232 | if (kgdb_connected && kgdboc_port_line == uart->port.line) | |
233 | if (ch == 0x3) {/* Ctrl + C */ | |
234 | kgdb_breakpoint(); | |
474f1a66 | 235 | return; |
474f1a66 | 236 | } |
52e15f0e | 237 | |
df04baf1 | 238 | if (!uart->port.info || !uart->port.info->port.tty) |
52e15f0e | 239 | return; |
474f1a66 | 240 | #endif |
df04baf1 | 241 | tty = uart->port.info->port.tty; |
bbf275f0 | 242 | |
50e2e15a | 243 | if (ANOMALY_05000363) { |
8851c71e MF |
244 | /* The BF533 (and BF561) family of processors have a nice anomaly |
245 | * where they continuously generate characters for a "single" break. | |
bbf275f0 | 246 | * We have to basically ignore this flood until the "next" valid |
8851c71e MF |
247 | * character comes across. Due to the nature of the flood, it is |
248 | * not possible to reliably catch bytes that are sent too quickly | |
249 | * after this break. So application code talking to the Blackfin | |
250 | * which sends a break signal must allow at least 1.5 character | |
251 | * times after the end of the break for things to stabilize. This | |
252 | * timeout was picked as it must absolutely be larger than 1 | |
253 | * character time +/- some percent. So 1.5 sounds good. All other | |
254 | * Blackfin families operate properly. Woo. | |
bbf275f0 | 255 | */ |
8851c71e MF |
256 | if (anomaly_start.tv_sec) { |
257 | struct timeval curr; | |
258 | suseconds_t usecs; | |
259 | ||
260 | if ((~ch & (~ch + 1)) & 0xff) | |
261 | goto known_good_char; | |
262 | ||
263 | do_gettimeofday(&curr); | |
264 | if (curr.tv_sec - anomaly_start.tv_sec > 1) | |
265 | goto known_good_char; | |
266 | ||
267 | usecs = 0; | |
268 | if (curr.tv_sec != anomaly_start.tv_sec) | |
269 | usecs += USEC_PER_SEC; | |
270 | usecs += curr.tv_usec - anomaly_start.tv_usec; | |
271 | ||
272 | if (usecs > UART_GET_ANOMALY_THRESHOLD(uart)) | |
273 | goto known_good_char; | |
274 | ||
275 | if (ch) | |
276 | anomaly_start.tv_sec = 0; | |
277 | else | |
278 | anomaly_start = curr; | |
279 | ||
280 | return; | |
281 | ||
282 | known_good_char: | |
e482a237 | 283 | status &= ~BI; |
8851c71e | 284 | anomaly_start.tv_sec = 0; |
bbf275f0 | 285 | } |
194de561 | 286 | } |
194de561 BW |
287 | |
288 | if (status & BI) { | |
50e2e15a | 289 | if (ANOMALY_05000363) |
8851c71e MF |
290 | if (bfin_revid() < 5) |
291 | do_gettimeofday(&anomaly_start); | |
194de561 BW |
292 | uart->port.icount.brk++; |
293 | if (uart_handle_break(&uart->port)) | |
294 | goto ignore_char; | |
9808901b | 295 | status &= ~(PE | FE); |
2ac5ee47 MF |
296 | } |
297 | if (status & PE) | |
194de561 | 298 | uart->port.icount.parity++; |
2ac5ee47 | 299 | if (status & OE) |
194de561 | 300 | uart->port.icount.overrun++; |
2ac5ee47 | 301 | if (status & FE) |
194de561 | 302 | uart->port.icount.frame++; |
2ac5ee47 MF |
303 | |
304 | status &= uart->port.read_status_mask; | |
305 | ||
306 | if (status & BI) | |
307 | flg = TTY_BREAK; | |
308 | else if (status & PE) | |
309 | flg = TTY_PARITY; | |
310 | else if (status & FE) | |
311 | flg = TTY_FRAME; | |
312 | else | |
194de561 BW |
313 | flg = TTY_NORMAL; |
314 | ||
315 | if (uart_handle_sysrq_char(&uart->port, ch)) | |
316 | goto ignore_char; | |
194de561 | 317 | |
2ac5ee47 MF |
318 | uart_insert_char(&uart->port, status, OE, ch, flg); |
319 | ||
320 | ignore_char: | |
321 | tty_flip_buffer_push(tty); | |
194de561 BW |
322 | } |
323 | ||
324 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart) | |
325 | { | |
326 | struct circ_buf *xmit = &uart->port.info->xmit; | |
327 | ||
194de561 | 328 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { |
5ffdeea2 SZ |
329 | #ifdef CONFIG_BF54x |
330 | /* Clear TFI bit */ | |
331 | UART_PUT_LSR(uart, TFI); | |
332 | #endif | |
333 | UART_CLEAR_IER(uart, ETBEI); | |
194de561 BW |
334 | return; |
335 | } | |
336 | ||
f30ac0ce SZ |
337 | if (uart->port.x_char) { |
338 | UART_PUT_CHAR(uart, uart->port.x_char); | |
339 | uart->port.icount.tx++; | |
340 | uart->port.x_char = 0; | |
341 | } | |
342 | ||
759eb040 SZ |
343 | while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) { |
344 | UART_PUT_CHAR(uart, xmit->buf[xmit->tail]); | |
345 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
346 | uart->port.icount.tx++; | |
347 | SSYNC(); | |
348 | } | |
194de561 BW |
349 | |
350 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
351 | uart_write_wakeup(&uart->port); | |
194de561 BW |
352 | } |
353 | ||
5c4e472b AL |
354 | static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id) |
355 | { | |
356 | struct bfin_serial_port *uart = dev_id; | |
357 | ||
f4d640c9 | 358 | spin_lock(&uart->port.lock); |
0bcfd70e | 359 | while (UART_GET_LSR(uart) & DR) |
f4d640c9 | 360 | bfin_serial_rx_chars(uart); |
f4d640c9 | 361 | spin_unlock(&uart->port.lock); |
759eb040 | 362 | |
5c4e472b AL |
363 | return IRQ_HANDLED; |
364 | } | |
365 | ||
366 | static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id) | |
194de561 BW |
367 | { |
368 | struct bfin_serial_port *uart = dev_id; | |
194de561 | 369 | |
d307d36a | 370 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS |
daba0280 | 371 | if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) { |
d307d36a SZ |
372 | uart->scts = 0; |
373 | uart_handle_cts_change(&uart->port, uart->scts); | |
374 | } | |
375 | #endif | |
f4d640c9 | 376 | spin_lock(&uart->port.lock); |
0bcfd70e | 377 | if (UART_GET_LSR(uart) & THRE) |
f4d640c9 | 378 | bfin_serial_tx_chars(uart); |
f4d640c9 | 379 | spin_unlock(&uart->port.lock); |
759eb040 | 380 | |
194de561 BW |
381 | return IRQ_HANDLED; |
382 | } | |
4cb4f22b | 383 | #endif |
194de561 | 384 | |
194de561 BW |
385 | #ifdef CONFIG_SERIAL_BFIN_DMA |
386 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart) | |
387 | { | |
388 | struct circ_buf *xmit = &uart->port.info->xmit; | |
194de561 | 389 | |
194de561 BW |
390 | uart->tx_done = 0; |
391 | ||
1b73351c | 392 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { |
0711d857 | 393 | uart->tx_count = 0; |
1b73351c SZ |
394 | uart->tx_done = 1; |
395 | return; | |
396 | } | |
397 | ||
194de561 BW |
398 | if (uart->port.x_char) { |
399 | UART_PUT_CHAR(uart, uart->port.x_char); | |
400 | uart->port.icount.tx++; | |
401 | uart->port.x_char = 0; | |
194de561 | 402 | } |
1b73351c | 403 | |
194de561 BW |
404 | uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE); |
405 | if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail)) | |
406 | uart->tx_count = UART_XMIT_SIZE - xmit->tail; | |
407 | blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail), | |
408 | (unsigned long)(xmit->buf+xmit->tail+uart->tx_count)); | |
409 | set_dma_config(uart->tx_dma_channel, | |
410 | set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP, | |
411 | INTR_ON_BUF, | |
412 | DIMENSION_LINEAR, | |
2047e40d MH |
413 | DATA_SIZE_8, |
414 | DMA_SYNC_RESTART)); | |
194de561 BW |
415 | set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail)); |
416 | set_dma_x_count(uart->tx_dma_channel, uart->tx_count); | |
417 | set_dma_x_modify(uart->tx_dma_channel, 1); | |
f9d36da9 | 418 | SSYNC(); |
194de561 | 419 | enable_dma(uart->tx_dma_channel); |
99ee7b5f | 420 | |
f4d640c9 | 421 | UART_SET_IER(uart, ETBEI); |
194de561 BW |
422 | } |
423 | ||
2ac5ee47 | 424 | static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart) |
194de561 | 425 | { |
a88487c7 | 426 | struct tty_struct *tty = uart->port.info->port.tty; |
194de561 BW |
427 | int i, flg, status; |
428 | ||
429 | status = UART_GET_LSR(uart); | |
0bcfd70e MF |
430 | UART_CLEAR_LSR(uart); |
431 | ||
56f5de8f SZ |
432 | uart->port.icount.rx += |
433 | CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail, | |
434 | UART_XMIT_SIZE); | |
194de561 BW |
435 | |
436 | if (status & BI) { | |
437 | uart->port.icount.brk++; | |
438 | if (uart_handle_break(&uart->port)) | |
439 | goto dma_ignore_char; | |
9808901b | 440 | status &= ~(PE | FE); |
2ac5ee47 MF |
441 | } |
442 | if (status & PE) | |
194de561 | 443 | uart->port.icount.parity++; |
2ac5ee47 | 444 | if (status & OE) |
194de561 | 445 | uart->port.icount.overrun++; |
2ac5ee47 | 446 | if (status & FE) |
194de561 | 447 | uart->port.icount.frame++; |
2ac5ee47 MF |
448 | |
449 | status &= uart->port.read_status_mask; | |
450 | ||
451 | if (status & BI) | |
452 | flg = TTY_BREAK; | |
453 | else if (status & PE) | |
454 | flg = TTY_PARITY; | |
455 | else if (status & FE) | |
456 | flg = TTY_FRAME; | |
457 | else | |
194de561 BW |
458 | flg = TTY_NORMAL; |
459 | ||
8c4210e3 | 460 | for (i = uart->rx_dma_buf.tail; ; i++) { |
56f5de8f SZ |
461 | if (i >= UART_XMIT_SIZE) |
462 | i = 0; | |
8c4210e3 SZ |
463 | if (i == uart->rx_dma_buf.head) |
464 | break; | |
56f5de8f SZ |
465 | if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i])) |
466 | uart_insert_char(&uart->port, status, OE, | |
467 | uart->rx_dma_buf.buf[i], flg); | |
194de561 | 468 | } |
2ac5ee47 MF |
469 | |
470 | dma_ignore_char: | |
194de561 BW |
471 | tty_flip_buffer_push(tty); |
472 | } | |
473 | ||
474 | void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart) | |
475 | { | |
59e4e3e6 MF |
476 | int x_pos, pos; |
477 | unsigned long flags; | |
68a784cb SZ |
478 | |
479 | spin_lock_irqsave(&uart->port.lock, flags); | |
194de561 | 480 | |
8516c568 SZ |
481 | /* 2D DMA RX buffer ring is used. Because curr_y_count and |
482 | * curr_x_count can't be read as an atomic operation, | |
483 | * curr_y_count should be read before curr_x_count. When | |
484 | * curr_x_count is read, curr_y_count may already indicate | |
485 | * next buffer line. But, the position calculated here is | |
486 | * still indicate the old line. The wrong position data may | |
487 | * be smaller than current buffer tail, which cause garbages | |
488 | * are received if it is not prohibit. | |
489 | */ | |
56f5de8f SZ |
490 | uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel); |
491 | x_pos = get_dma_curr_xcount(uart->rx_dma_channel); | |
492 | uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows; | |
493 | if (uart->rx_dma_nrows == DMA_RX_YCOUNT) | |
494 | uart->rx_dma_nrows = 0; | |
495 | x_pos = DMA_RX_XCOUNT - x_pos; | |
194de561 BW |
496 | if (x_pos == DMA_RX_XCOUNT) |
497 | x_pos = 0; | |
498 | ||
499 | pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos; | |
8516c568 SZ |
500 | /* Ignore receiving data if new position is in the same line of |
501 | * current buffer tail and small. | |
502 | */ | |
503 | if (pos > uart->rx_dma_buf.tail || | |
504 | uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) { | |
56f5de8f | 505 | uart->rx_dma_buf.head = pos; |
194de561 | 506 | bfin_serial_dma_rx_chars(uart); |
56f5de8f | 507 | uart->rx_dma_buf.tail = uart->rx_dma_buf.head; |
194de561 | 508 | } |
0aef4564 | 509 | |
68a784cb SZ |
510 | spin_unlock_irqrestore(&uart->port.lock, flags); |
511 | ||
0a278423 | 512 | mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES); |
194de561 BW |
513 | } |
514 | ||
515 | static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id) | |
516 | { | |
517 | struct bfin_serial_port *uart = dev_id; | |
518 | struct circ_buf *xmit = &uart->port.info->xmit; | |
194de561 | 519 | |
d307d36a | 520 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS |
daba0280 | 521 | if (uart->scts && !(bfin_serial_get_mctrl(&uart->port)&TIOCM_CTS)) { |
d307d36a SZ |
522 | uart->scts = 0; |
523 | uart_handle_cts_change(&uart->port, uart->scts); | |
524 | } | |
525 | #endif | |
526 | ||
194de561 BW |
527 | spin_lock(&uart->port.lock); |
528 | if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) { | |
194de561 | 529 | disable_dma(uart->tx_dma_channel); |
0711d857 | 530 | clear_dma_irqstat(uart->tx_dma_channel); |
f4d640c9 | 531 | UART_CLEAR_IER(uart, ETBEI); |
0711d857 SZ |
532 | xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1); |
533 | uart->port.icount.tx += uart->tx_count; | |
1b73351c | 534 | |
56f5de8f SZ |
535 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
536 | uart_write_wakeup(&uart->port); | |
537 | ||
1b73351c | 538 | bfin_serial_dma_tx_chars(uart); |
194de561 BW |
539 | } |
540 | ||
541 | spin_unlock(&uart->port.lock); | |
542 | return IRQ_HANDLED; | |
543 | } | |
544 | ||
545 | static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id) | |
546 | { | |
547 | struct bfin_serial_port *uart = dev_id; | |
548 | unsigned short irqstat; | |
8516c568 | 549 | int pos; |
0711d857 | 550 | |
194de561 BW |
551 | spin_lock(&uart->port.lock); |
552 | irqstat = get_dma_curr_irqstat(uart->rx_dma_channel); | |
553 | clear_dma_irqstat(uart->rx_dma_channel); | |
8516c568 SZ |
554 | |
555 | uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel); | |
556 | uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows; | |
557 | if (uart->rx_dma_nrows == DMA_RX_YCOUNT) | |
558 | uart->rx_dma_nrows = 0; | |
559 | ||
560 | pos = uart->rx_dma_nrows * DMA_RX_XCOUNT; | |
561 | if (pos > uart->rx_dma_buf.tail || | |
562 | uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) { | |
563 | uart->rx_dma_buf.head = pos; | |
564 | bfin_serial_dma_rx_chars(uart); | |
565 | uart->rx_dma_buf.tail = uart->rx_dma_buf.head; | |
566 | } | |
567 | ||
194de561 | 568 | spin_unlock(&uart->port.lock); |
0aef4564 | 569 | |
194de561 BW |
570 | return IRQ_HANDLED; |
571 | } | |
572 | #endif | |
573 | ||
574 | /* | |
575 | * Return TIOCSER_TEMT when transmitter is not busy. | |
576 | */ | |
577 | static unsigned int bfin_serial_tx_empty(struct uart_port *port) | |
578 | { | |
579 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
580 | unsigned short lsr; | |
581 | ||
582 | lsr = UART_GET_LSR(uart); | |
583 | if (lsr & TEMT) | |
584 | return TIOCSER_TEMT; | |
585 | else | |
586 | return 0; | |
587 | } | |
588 | ||
194de561 BW |
589 | static void bfin_serial_break_ctl(struct uart_port *port, int break_state) |
590 | { | |
cf686762 MF |
591 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; |
592 | u16 lcr = UART_GET_LCR(uart); | |
593 | if (break_state) | |
594 | lcr |= SB; | |
595 | else | |
596 | lcr &= ~SB; | |
597 | UART_PUT_LCR(uart, lcr); | |
598 | SSYNC(); | |
194de561 BW |
599 | } |
600 | ||
601 | static int bfin_serial_startup(struct uart_port *port) | |
602 | { | |
603 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
604 | ||
605 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
606 | dma_addr_t dma_handle; | |
607 | ||
608 | if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) { | |
609 | printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n"); | |
610 | return -EBUSY; | |
611 | } | |
612 | ||
613 | if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) { | |
614 | printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n"); | |
615 | free_dma(uart->rx_dma_channel); | |
616 | return -EBUSY; | |
617 | } | |
618 | ||
619 | set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart); | |
620 | set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart); | |
621 | ||
622 | uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA); | |
623 | uart->rx_dma_buf.head = 0; | |
624 | uart->rx_dma_buf.tail = 0; | |
625 | uart->rx_dma_nrows = 0; | |
626 | ||
627 | set_dma_config(uart->rx_dma_channel, | |
628 | set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO, | |
629 | INTR_ON_ROW, DIMENSION_2D, | |
2047e40d MH |
630 | DATA_SIZE_8, |
631 | DMA_SYNC_RESTART)); | |
194de561 BW |
632 | set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT); |
633 | set_dma_x_modify(uart->rx_dma_channel, 1); | |
634 | set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT); | |
635 | set_dma_y_modify(uart->rx_dma_channel, 1); | |
636 | set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf); | |
637 | enable_dma(uart->rx_dma_channel); | |
638 | ||
639 | uart->rx_dma_timer.data = (unsigned long)(uart); | |
640 | uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout; | |
641 | uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES; | |
642 | add_timer(&(uart->rx_dma_timer)); | |
643 | #else | |
6f95570e | 644 | # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
52e15f0e SZ |
645 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) |
646 | if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled) | |
647 | kgdboc_break_enabled = 0; | |
648 | else { | |
649 | # endif | |
a359cca7 SZ |
650 | if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED, |
651 | "BFIN_UART_RX", uart)) { | |
194de561 BW |
652 | printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n"); |
653 | return -EBUSY; | |
654 | } | |
655 | ||
656 | if (request_irq | |
5c4e472b | 657 | (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED, |
194de561 BW |
658 | "BFIN_UART_TX", uart)) { |
659 | printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n"); | |
660 | free_irq(uart->port.irq, uart); | |
661 | return -EBUSY; | |
662 | } | |
ab2375f2 SZ |
663 | |
664 | # ifdef CONFIG_BF54x | |
665 | { | |
666 | unsigned uart_dma_ch_rx, uart_dma_ch_tx; | |
667 | ||
668 | switch (uart->port.irq) { | |
669 | case IRQ_UART3_RX: | |
670 | uart_dma_ch_rx = CH_UART3_RX; | |
671 | uart_dma_ch_tx = CH_UART3_TX; | |
672 | break; | |
673 | case IRQ_UART2_RX: | |
674 | uart_dma_ch_rx = CH_UART2_RX; | |
675 | uart_dma_ch_tx = CH_UART2_TX; | |
676 | break; | |
677 | default: | |
678 | uart_dma_ch_rx = uart_dma_ch_tx = 0; | |
679 | break; | |
680 | }; | |
681 | ||
682 | if (uart_dma_ch_rx && | |
683 | request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) { | |
684 | printk(KERN_NOTICE"Fail to attach UART interrupt\n"); | |
685 | free_irq(uart->port.irq, uart); | |
686 | free_irq(uart->port.irq + 1, uart); | |
687 | return -EBUSY; | |
688 | } | |
689 | if (uart_dma_ch_tx && | |
690 | request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) { | |
691 | printk(KERN_NOTICE "Fail to attach UART interrupt\n"); | |
692 | free_dma(uart_dma_ch_rx); | |
693 | free_irq(uart->port.irq, uart); | |
694 | free_irq(uart->port.irq + 1, uart); | |
695 | return -EBUSY; | |
696 | } | |
697 | } | |
698 | # endif | |
6f95570e | 699 | # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
52e15f0e SZ |
700 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) |
701 | } | |
702 | # endif | |
6f95570e SZ |
703 | #endif |
704 | ||
705 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
706 | if (uart->cts_pin >= 0) { | |
707 | if (request_irq(gpio_to_irq(uart->cts_pin), | |
708 | bfin_serial_mctrl_cts_int, | |
709 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | | |
710 | IRQF_DISABLED, "BFIN_UART_CTS", uart)) { | |
711 | uart->cts_pin = -1; | |
712 | pr_info("Unable to attach BlackFin UART CTS interrupt.\ | |
713 | So, disable it.\n"); | |
714 | } | |
715 | } | |
716 | if (uart->rts_pin >= 0) { | |
717 | gpio_request(uart->rts_pin, DRIVER_NAME); | |
718 | gpio_direction_output(uart->rts_pin, 0); | |
719 | } | |
194de561 | 720 | #endif |
d307d36a SZ |
721 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS |
722 | if (request_irq(uart->status_irq, | |
723 | bfin_serial_mctrl_cts_int, | |
724 | IRQF_DISABLED, "BFIN_UART_MODEM_STATUS", uart)) { | |
725 | pr_info("Unable to attach BlackFin UART Modem \ | |
726 | Status interrupt.\n"); | |
727 | } | |
728 | ||
729 | if (uart->cts_pin >= 0) { | |
730 | gpio_request(uart->cts_pin, DRIVER_NAME); | |
731 | gpio_direction_output(uart->cts_pin, 1); | |
732 | } | |
733 | if (uart->rts_pin >= 0) { | |
734 | gpio_request(uart->rts_pin, DRIVER_NAME); | |
735 | gpio_direction_output(uart->rts_pin, 0); | |
736 | } | |
737 | ||
738 | /* CTS RTS PINs are negative assertive. */ | |
739 | UART_PUT_MCR(uart, ACTS); | |
740 | UART_SET_IER(uart, EDSSI); | |
741 | #endif | |
742 | ||
f4d640c9 | 743 | UART_SET_IER(uart, ERBFI); |
194de561 BW |
744 | return 0; |
745 | } | |
746 | ||
747 | static void bfin_serial_shutdown(struct uart_port *port) | |
748 | { | |
749 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
750 | ||
751 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
752 | disable_dma(uart->tx_dma_channel); | |
753 | free_dma(uart->tx_dma_channel); | |
754 | disable_dma(uart->rx_dma_channel); | |
755 | free_dma(uart->rx_dma_channel); | |
756 | del_timer(&(uart->rx_dma_timer)); | |
75b780bd | 757 | dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0); |
194de561 | 758 | #else |
ab2375f2 SZ |
759 | #ifdef CONFIG_BF54x |
760 | switch (uart->port.irq) { | |
761 | case IRQ_UART3_RX: | |
762 | free_dma(CH_UART3_RX); | |
763 | free_dma(CH_UART3_TX); | |
764 | break; | |
765 | case IRQ_UART2_RX: | |
766 | free_dma(CH_UART2_RX); | |
767 | free_dma(CH_UART2_TX); | |
768 | break; | |
769 | default: | |
770 | break; | |
771 | }; | |
474f1a66 | 772 | #endif |
194de561 BW |
773 | free_irq(uart->port.irq, uart); |
774 | free_irq(uart->port.irq+1, uart); | |
775 | #endif | |
6f95570e | 776 | |
d307d36a | 777 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
6f95570e SZ |
778 | if (uart->cts_pin >= 0) |
779 | free_irq(gpio_to_irq(uart->cts_pin), uart); | |
780 | if (uart->rts_pin >= 0) | |
781 | gpio_free(uart->rts_pin); | |
d307d36a SZ |
782 | #endif |
783 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS | |
784 | if (uart->cts_pin >= 0) | |
785 | gpio_free(uart->cts_pin); | |
786 | if (uart->rts_pin >= 0) | |
787 | gpio_free(uart->rts_pin); | |
788 | if (UART_GET_IER(uart) && EDSSI) | |
789 | free_irq(uart->status_irq, uart); | |
790 | #endif | |
194de561 BW |
791 | } |
792 | ||
793 | static void | |
794 | bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios, | |
795 | struct ktermios *old) | |
796 | { | |
797 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
798 | unsigned long flags; | |
799 | unsigned int baud, quot; | |
0c44a86d | 800 | unsigned short val, ier, lcr = 0; |
194de561 BW |
801 | |
802 | switch (termios->c_cflag & CSIZE) { | |
803 | case CS8: | |
804 | lcr = WLS(8); | |
805 | break; | |
806 | case CS7: | |
807 | lcr = WLS(7); | |
808 | break; | |
809 | case CS6: | |
810 | lcr = WLS(6); | |
811 | break; | |
812 | case CS5: | |
813 | lcr = WLS(5); | |
814 | break; | |
815 | default: | |
816 | printk(KERN_ERR "%s: word lengh not supported\n", | |
71cc2c21 | 817 | __func__); |
194de561 BW |
818 | } |
819 | ||
820 | if (termios->c_cflag & CSTOPB) | |
821 | lcr |= STB; | |
19aa6382 | 822 | if (termios->c_cflag & PARENB) |
194de561 | 823 | lcr |= PEN; |
19aa6382 MF |
824 | if (!(termios->c_cflag & PARODD)) |
825 | lcr |= EPS; | |
826 | if (termios->c_cflag & CMSPAR) | |
827 | lcr |= STP; | |
194de561 | 828 | |
2ac5ee47 MF |
829 | port->read_status_mask = OE; |
830 | if (termios->c_iflag & INPCK) | |
831 | port->read_status_mask |= (FE | PE); | |
832 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
833 | port->read_status_mask |= BI; | |
194de561 | 834 | |
2ac5ee47 MF |
835 | /* |
836 | * Characters to ignore | |
837 | */ | |
838 | port->ignore_status_mask = 0; | |
839 | if (termios->c_iflag & IGNPAR) | |
840 | port->ignore_status_mask |= FE | PE; | |
841 | if (termios->c_iflag & IGNBRK) { | |
842 | port->ignore_status_mask |= BI; | |
843 | /* | |
844 | * If we're ignoring parity and break indicators, | |
845 | * ignore overruns too (for real raw support). | |
846 | */ | |
847 | if (termios->c_iflag & IGNPAR) | |
848 | port->ignore_status_mask |= OE; | |
849 | } | |
194de561 BW |
850 | |
851 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
f4487101 | 852 | quot = uart_get_divisor(port, baud) - ANOMALY_05000230; |
194de561 BW |
853 | spin_lock_irqsave(&uart->port.lock, flags); |
854 | ||
8851c71e MF |
855 | UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15); |
856 | ||
194de561 BW |
857 | /* Disable UART */ |
858 | ier = UART_GET_IER(uart); | |
1feaa51d | 859 | UART_DISABLE_INTS(uart); |
194de561 BW |
860 | |
861 | /* Set DLAB in LCR to Access DLL and DLH */ | |
45828b81 | 862 | UART_SET_DLAB(uart); |
194de561 BW |
863 | |
864 | UART_PUT_DLL(uart, quot & 0xFF); | |
194de561 BW |
865 | UART_PUT_DLH(uart, (quot >> 8) & 0xFF); |
866 | SSYNC(); | |
867 | ||
868 | /* Clear DLAB in LCR to Access THR RBR IER */ | |
45828b81 | 869 | UART_CLEAR_DLAB(uart); |
194de561 BW |
870 | |
871 | UART_PUT_LCR(uart, lcr); | |
872 | ||
873 | /* Enable UART */ | |
1feaa51d | 874 | UART_ENABLE_INTS(uart, ier); |
194de561 BW |
875 | |
876 | val = UART_GET_GCTL(uart); | |
877 | val |= UCEN; | |
878 | UART_PUT_GCTL(uart, val); | |
879 | ||
b3ef5aba GY |
880 | /* Port speed changed, update the per-port timeout. */ |
881 | uart_update_timeout(port, termios->c_cflag, baud); | |
882 | ||
194de561 BW |
883 | spin_unlock_irqrestore(&uart->port.lock, flags); |
884 | } | |
885 | ||
886 | static const char *bfin_serial_type(struct uart_port *port) | |
887 | { | |
888 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
889 | ||
890 | return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL; | |
891 | } | |
892 | ||
893 | /* | |
894 | * Release the memory region(s) being used by 'port'. | |
895 | */ | |
896 | static void bfin_serial_release_port(struct uart_port *port) | |
897 | { | |
898 | } | |
899 | ||
900 | /* | |
901 | * Request the memory region(s) being used by 'port'. | |
902 | */ | |
903 | static int bfin_serial_request_port(struct uart_port *port) | |
904 | { | |
905 | return 0; | |
906 | } | |
907 | ||
908 | /* | |
909 | * Configure/autoconfigure the port. | |
910 | */ | |
911 | static void bfin_serial_config_port(struct uart_port *port, int flags) | |
912 | { | |
913 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
914 | ||
915 | if (flags & UART_CONFIG_TYPE && | |
916 | bfin_serial_request_port(&uart->port) == 0) | |
917 | uart->port.type = PORT_BFIN; | |
918 | } | |
919 | ||
920 | /* | |
921 | * Verify the new serial_struct (for TIOCSSERIAL). | |
922 | * The only change we allow are to the flags and type, and | |
923 | * even then only between PORT_BFIN and PORT_UNKNOWN | |
924 | */ | |
925 | static int | |
926 | bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser) | |
927 | { | |
928 | return 0; | |
929 | } | |
930 | ||
7d01b475 GY |
931 | /* |
932 | * Enable the IrDA function if tty->ldisc.num is N_IRDA. | |
933 | * In other cases, disable IrDA function. | |
934 | */ | |
3b8458a9 | 935 | static void bfin_serial_set_ldisc(struct uart_port *port) |
7d01b475 | 936 | { |
3b8458a9 | 937 | int line = port->line; |
7d01b475 GY |
938 | unsigned short val; |
939 | ||
a88487c7 | 940 | if (line >= port->info->port.tty->driver->num) |
7d01b475 GY |
941 | return; |
942 | ||
b1cbefe5 | 943 | switch (port->info->port.tty->termios->c_line) { |
7d01b475 GY |
944 | case N_IRDA: |
945 | val = UART_GET_GCTL(&bfin_serial_ports[line]); | |
946 | val |= (IREN | RPOLC); | |
947 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
948 | break; | |
949 | default: | |
950 | val = UART_GET_GCTL(&bfin_serial_ports[line]); | |
951 | val &= ~(IREN | RPOLC); | |
952 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
953 | } | |
954 | } | |
955 | ||
6f95570e SZ |
956 | static void bfin_serial_reset_irda(struct uart_port *port) |
957 | { | |
958 | int line = port->line; | |
959 | unsigned short val; | |
960 | ||
961 | val = UART_GET_GCTL(&bfin_serial_ports[line]); | |
962 | val &= ~(IREN | RPOLC); | |
963 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
964 | SSYNC(); | |
965 | val |= (IREN | RPOLC); | |
966 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
967 | SSYNC(); | |
968 | } | |
969 | ||
52e15f0e SZ |
970 | #ifdef CONFIG_CONSOLE_POLL |
971 | static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr) | |
972 | { | |
973 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
974 | ||
975 | while (!(UART_GET_LSR(uart) & THRE)) | |
976 | cpu_relax(); | |
977 | ||
978 | UART_CLEAR_DLAB(uart); | |
979 | UART_PUT_CHAR(uart, (unsigned char)chr); | |
980 | } | |
981 | ||
982 | static int bfin_serial_poll_get_char(struct uart_port *port) | |
983 | { | |
984 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
985 | unsigned char chr; | |
986 | ||
987 | while (!(UART_GET_LSR(uart) & DR)) | |
988 | cpu_relax(); | |
989 | ||
990 | UART_CLEAR_DLAB(uart); | |
991 | chr = UART_GET_CHAR(uart); | |
992 | ||
993 | return chr; | |
994 | } | |
995 | #endif | |
996 | ||
997 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ | |
998 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
999 | static void bfin_kgdboc_port_shutdown(struct uart_port *port) | |
1000 | { | |
1001 | if (kgdboc_break_enabled) { | |
1002 | kgdboc_break_enabled = 0; | |
1003 | bfin_serial_shutdown(port); | |
1004 | } | |
1005 | } | |
1006 | ||
1007 | static int bfin_kgdboc_port_startup(struct uart_port *port) | |
1008 | { | |
1009 | kgdboc_port_line = port->line; | |
1010 | kgdboc_break_enabled = !bfin_serial_startup(port); | |
1011 | return 0; | |
1012 | } | |
1013 | #endif | |
1014 | ||
194de561 BW |
1015 | static struct uart_ops bfin_serial_pops = { |
1016 | .tx_empty = bfin_serial_tx_empty, | |
1017 | .set_mctrl = bfin_serial_set_mctrl, | |
1018 | .get_mctrl = bfin_serial_get_mctrl, | |
1019 | .stop_tx = bfin_serial_stop_tx, | |
1020 | .start_tx = bfin_serial_start_tx, | |
1021 | .stop_rx = bfin_serial_stop_rx, | |
1022 | .enable_ms = bfin_serial_enable_ms, | |
1023 | .break_ctl = bfin_serial_break_ctl, | |
1024 | .startup = bfin_serial_startup, | |
1025 | .shutdown = bfin_serial_shutdown, | |
1026 | .set_termios = bfin_serial_set_termios, | |
3b8458a9 | 1027 | .set_ldisc = bfin_serial_set_ldisc, |
194de561 BW |
1028 | .type = bfin_serial_type, |
1029 | .release_port = bfin_serial_release_port, | |
1030 | .request_port = bfin_serial_request_port, | |
1031 | .config_port = bfin_serial_config_port, | |
1032 | .verify_port = bfin_serial_verify_port, | |
52e15f0e SZ |
1033 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
1034 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
1035 | .kgdboc_port_startup = bfin_kgdboc_port_startup, | |
1036 | .kgdboc_port_shutdown = bfin_kgdboc_port_shutdown, | |
1037 | #endif | |
1038 | #ifdef CONFIG_CONSOLE_POLL | |
1039 | .poll_put_char = bfin_serial_poll_put_char, | |
1040 | .poll_get_char = bfin_serial_poll_get_char, | |
1041 | #endif | |
194de561 BW |
1042 | }; |
1043 | ||
6f95570e SZ |
1044 | static void __init bfin_serial_hw_init(void) |
1045 | { | |
1046 | #ifdef CONFIG_SERIAL_BFIN_UART0 | |
1047 | peripheral_request(P_UART0_TX, DRIVER_NAME); | |
1048 | peripheral_request(P_UART0_RX, DRIVER_NAME); | |
1049 | #endif | |
1050 | ||
1051 | #ifdef CONFIG_SERIAL_BFIN_UART1 | |
1052 | peripheral_request(P_UART1_TX, DRIVER_NAME); | |
1053 | peripheral_request(P_UART1_RX, DRIVER_NAME); | |
1054 | ||
1055 | # if defined(CONFIG_BFIN_UART1_CTSRTS) && defined(CONFIG_BF54x) | |
1056 | peripheral_request(P_UART1_RTS, DRIVER_NAME); | |
1057 | peripheral_request(P_UART1_CTS, DRIVER_NAME); | |
1058 | # endif | |
1059 | #endif | |
1060 | ||
1061 | #ifdef CONFIG_SERIAL_BFIN_UART2 | |
1062 | peripheral_request(P_UART2_TX, DRIVER_NAME); | |
1063 | peripheral_request(P_UART2_RX, DRIVER_NAME); | |
1064 | #endif | |
1065 | ||
1066 | #ifdef CONFIG_SERIAL_BFIN_UART3 | |
1067 | peripheral_request(P_UART3_TX, DRIVER_NAME); | |
1068 | peripheral_request(P_UART3_RX, DRIVER_NAME); | |
1069 | ||
1070 | # if defined(CONFIG_BFIN_UART3_CTSRTS) && defined(CONFIG_BF54x) | |
1071 | peripheral_request(P_UART3_RTS, DRIVER_NAME); | |
1072 | peripheral_request(P_UART3_CTS, DRIVER_NAME); | |
1073 | # endif | |
1074 | #endif | |
1075 | } | |
1076 | ||
194de561 BW |
1077 | static void __init bfin_serial_init_ports(void) |
1078 | { | |
1079 | static int first = 1; | |
1080 | int i; | |
1081 | ||
1082 | if (!first) | |
1083 | return; | |
1084 | first = 0; | |
1085 | ||
6f95570e SZ |
1086 | bfin_serial_hw_init(); |
1087 | ||
c9607ecc | 1088 | for (i = 0; i < nr_active_ports; i++) { |
194de561 | 1089 | bfin_serial_ports[i].port.uartclk = get_sclk(); |
b3ef5aba | 1090 | bfin_serial_ports[i].port.fifosize = BFIN_UART_TX_FIFO_SIZE; |
194de561 BW |
1091 | bfin_serial_ports[i].port.ops = &bfin_serial_pops; |
1092 | bfin_serial_ports[i].port.line = i; | |
1093 | bfin_serial_ports[i].port.iotype = UPIO_MEM; | |
1094 | bfin_serial_ports[i].port.membase = | |
1095 | (void __iomem *)bfin_serial_resource[i].uart_base_addr; | |
1096 | bfin_serial_ports[i].port.mapbase = | |
1097 | bfin_serial_resource[i].uart_base_addr; | |
1098 | bfin_serial_ports[i].port.irq = | |
1099 | bfin_serial_resource[i].uart_irq; | |
d307d36a SZ |
1100 | bfin_serial_ports[i].status_irq = |
1101 | bfin_serial_resource[i].uart_status_irq; | |
194de561 BW |
1102 | bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF; |
1103 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
1104 | bfin_serial_ports[i].tx_done = 1; | |
1105 | bfin_serial_ports[i].tx_count = 0; | |
1106 | bfin_serial_ports[i].tx_dma_channel = | |
1107 | bfin_serial_resource[i].uart_tx_dma_channel; | |
1108 | bfin_serial_ports[i].rx_dma_channel = | |
1109 | bfin_serial_resource[i].uart_rx_dma_channel; | |
1110 | init_timer(&(bfin_serial_ports[i].rx_dma_timer)); | |
194de561 | 1111 | #endif |
d307d36a SZ |
1112 | #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \ |
1113 | defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS) | |
194de561 BW |
1114 | bfin_serial_ports[i].cts_pin = |
1115 | bfin_serial_resource[i].uart_cts_pin; | |
1116 | bfin_serial_ports[i].rts_pin = | |
1117 | bfin_serial_resource[i].uart_rts_pin; | |
1118 | #endif | |
194de561 BW |
1119 | } |
1120 | } | |
1121 | ||
b6efa1ea | 1122 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) |
194de561 BW |
1123 | /* |
1124 | * If the port was already initialised (eg, by a boot loader), | |
1125 | * try to determine the current setup. | |
1126 | */ | |
1127 | static void __init | |
1128 | bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud, | |
1129 | int *parity, int *bits) | |
1130 | { | |
1131 | unsigned short status; | |
1132 | ||
1133 | status = UART_GET_IER(uart) & (ERBFI | ETBEI); | |
1134 | if (status == (ERBFI | ETBEI)) { | |
1135 | /* ok, the port was enabled */ | |
45828b81 | 1136 | u16 lcr, dlh, dll; |
194de561 BW |
1137 | |
1138 | lcr = UART_GET_LCR(uart); | |
1139 | ||
1140 | *parity = 'n'; | |
1141 | if (lcr & PEN) { | |
1142 | if (lcr & EPS) | |
1143 | *parity = 'e'; | |
1144 | else | |
1145 | *parity = 'o'; | |
1146 | } | |
1147 | switch (lcr & 0x03) { | |
1148 | case 0: *bits = 5; break; | |
1149 | case 1: *bits = 6; break; | |
1150 | case 2: *bits = 7; break; | |
1151 | case 3: *bits = 8; break; | |
1152 | } | |
1153 | /* Set DLAB in LCR to Access DLL and DLH */ | |
45828b81 | 1154 | UART_SET_DLAB(uart); |
194de561 BW |
1155 | |
1156 | dll = UART_GET_DLL(uart); | |
1157 | dlh = UART_GET_DLH(uart); | |
1158 | ||
1159 | /* Clear DLAB in LCR to Access THR RBR IER */ | |
45828b81 | 1160 | UART_CLEAR_DLAB(uart); |
194de561 BW |
1161 | |
1162 | *baud = get_sclk() / (16*(dll | dlh << 8)); | |
1163 | } | |
71cc2c21 | 1164 | pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits); |
194de561 | 1165 | } |
0ae53640 | 1166 | |
0ae53640 | 1167 | static struct uart_driver bfin_serial_reg; |
194de561 BW |
1168 | |
1169 | static int __init | |
1170 | bfin_serial_console_setup(struct console *co, char *options) | |
1171 | { | |
1172 | struct bfin_serial_port *uart; | |
1173 | int baud = 57600; | |
1174 | int bits = 8; | |
1175 | int parity = 'n'; | |
d307d36a SZ |
1176 | # if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \ |
1177 | defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS) | |
194de561 | 1178 | int flow = 'r'; |
b6efa1ea | 1179 | # else |
194de561 | 1180 | int flow = 'n'; |
0ae53640 | 1181 | # endif |
194de561 BW |
1182 | |
1183 | /* | |
1184 | * Check whether an invalid uart number has been specified, and | |
1185 | * if so, search for the first available port that does have | |
1186 | * console support. | |
1187 | */ | |
c9607ecc | 1188 | if (co->index == -1 || co->index >= nr_active_ports) |
194de561 BW |
1189 | co->index = 0; |
1190 | uart = &bfin_serial_ports[co->index]; | |
1191 | ||
1192 | if (options) | |
1193 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1194 | else | |
1195 | bfin_serial_console_get_options(uart, &baud, &parity, &bits); | |
1196 | ||
1197 | return uart_set_options(&uart->port, co, baud, parity, bits, flow); | |
0ae53640 RG |
1198 | } |
1199 | #endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) || | |
1200 | defined (CONFIG_EARLY_PRINTK) */ | |
1201 | ||
1202 | #ifdef CONFIG_SERIAL_BFIN_CONSOLE | |
1203 | static void bfin_serial_console_putchar(struct uart_port *port, int ch) | |
1204 | { | |
1205 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1206 | while (!(UART_GET_LSR(uart) & THRE)) | |
1207 | barrier(); | |
1208 | UART_PUT_CHAR(uart, ch); | |
1209 | SSYNC(); | |
1210 | } | |
1211 | ||
1212 | /* | |
1213 | * Interrupts are disabled on entering | |
1214 | */ | |
1215 | static void | |
1216 | bfin_serial_console_write(struct console *co, const char *s, unsigned int count) | |
1217 | { | |
1218 | struct bfin_serial_port *uart = &bfin_serial_ports[co->index]; | |
59e4e3e6 | 1219 | unsigned long flags; |
0ae53640 RG |
1220 | |
1221 | spin_lock_irqsave(&uart->port.lock, flags); | |
1222 | uart_console_write(&uart->port, s, count, bfin_serial_console_putchar); | |
1223 | spin_unlock_irqrestore(&uart->port.lock, flags); | |
1224 | ||
194de561 BW |
1225 | } |
1226 | ||
194de561 BW |
1227 | static struct console bfin_serial_console = { |
1228 | .name = BFIN_SERIAL_NAME, | |
1229 | .write = bfin_serial_console_write, | |
1230 | .device = uart_console_device, | |
1231 | .setup = bfin_serial_console_setup, | |
1232 | .flags = CON_PRINTBUFFER, | |
1233 | .index = -1, | |
1234 | .data = &bfin_serial_reg, | |
1235 | }; | |
1236 | ||
1237 | static int __init bfin_serial_rs_console_init(void) | |
1238 | { | |
1239 | bfin_serial_init_ports(); | |
1240 | register_console(&bfin_serial_console); | |
52e15f0e | 1241 | |
194de561 BW |
1242 | return 0; |
1243 | } | |
1244 | console_initcall(bfin_serial_rs_console_init); | |
1245 | ||
1246 | #define BFIN_SERIAL_CONSOLE &bfin_serial_console | |
1247 | #else | |
1248 | #define BFIN_SERIAL_CONSOLE NULL | |
0ae53640 RG |
1249 | #endif /* CONFIG_SERIAL_BFIN_CONSOLE */ |
1250 | ||
1251 | ||
1252 | #ifdef CONFIG_EARLY_PRINTK | |
1253 | static __init void early_serial_putc(struct uart_port *port, int ch) | |
1254 | { | |
1255 | unsigned timeout = 0xffff; | |
1256 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1257 | ||
1258 | while ((!(UART_GET_LSR(uart) & THRE)) && --timeout) | |
1259 | cpu_relax(); | |
1260 | UART_PUT_CHAR(uart, ch); | |
1261 | } | |
1262 | ||
1263 | static __init void early_serial_write(struct console *con, const char *s, | |
1264 | unsigned int n) | |
1265 | { | |
1266 | struct bfin_serial_port *uart = &bfin_serial_ports[con->index]; | |
1267 | unsigned int i; | |
1268 | ||
1269 | for (i = 0; i < n; i++, s++) { | |
1270 | if (*s == '\n') | |
1271 | early_serial_putc(&uart->port, '\r'); | |
1272 | early_serial_putc(&uart->port, *s); | |
1273 | } | |
1274 | } | |
1275 | ||
7de7c55b RG |
1276 | /* |
1277 | * This should have a .setup or .early_setup in it, but then things get called | |
1278 | * without the command line options, and the baud rate gets messed up - so | |
1279 | * don't let the common infrastructure play with things. (see calls to setup | |
1280 | * & earlysetup in ./kernel/printk.c:register_console() | |
1281 | */ | |
c1113400 | 1282 | static struct __initdata console bfin_early_serial_console = { |
0ae53640 RG |
1283 | .name = "early_BFuart", |
1284 | .write = early_serial_write, | |
1285 | .device = uart_console_device, | |
1286 | .flags = CON_PRINTBUFFER, | |
0ae53640 RG |
1287 | .index = -1, |
1288 | .data = &bfin_serial_reg, | |
1289 | }; | |
1290 | ||
1291 | struct console __init *bfin_earlyserial_init(unsigned int port, | |
1292 | unsigned int cflag) | |
1293 | { | |
1294 | struct bfin_serial_port *uart; | |
1295 | struct ktermios t; | |
1296 | ||
c9607ecc | 1297 | if (port == -1 || port >= nr_active_ports) |
0ae53640 RG |
1298 | port = 0; |
1299 | bfin_serial_init_ports(); | |
1300 | bfin_early_serial_console.index = port; | |
0ae53640 RG |
1301 | uart = &bfin_serial_ports[port]; |
1302 | t.c_cflag = cflag; | |
1303 | t.c_iflag = 0; | |
1304 | t.c_oflag = 0; | |
1305 | t.c_lflag = ICANON; | |
1306 | t.c_line = port; | |
1307 | bfin_serial_set_termios(&uart->port, &t, &t); | |
1308 | return &bfin_early_serial_console; | |
1309 | } | |
1310 | ||
b6efa1ea | 1311 | #endif /* CONFIG_EARLY_PRINTK */ |
194de561 BW |
1312 | |
1313 | static struct uart_driver bfin_serial_reg = { | |
1314 | .owner = THIS_MODULE, | |
1315 | .driver_name = "bfin-uart", | |
1316 | .dev_name = BFIN_SERIAL_NAME, | |
1317 | .major = BFIN_SERIAL_MAJOR, | |
1318 | .minor = BFIN_SERIAL_MINOR, | |
2ade9729 | 1319 | .nr = BFIN_UART_NR_PORTS, |
194de561 BW |
1320 | .cons = BFIN_SERIAL_CONSOLE, |
1321 | }; | |
1322 | ||
1323 | static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state) | |
1324 | { | |
ccfbc3e1 | 1325 | int i; |
194de561 | 1326 | |
c9607ecc | 1327 | for (i = 0; i < nr_active_ports; i++) { |
ccfbc3e1 SZ |
1328 | if (bfin_serial_ports[i].port.dev != &dev->dev) |
1329 | continue; | |
1330 | uart_suspend_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
1331 | } | |
194de561 BW |
1332 | |
1333 | return 0; | |
1334 | } | |
1335 | ||
1336 | static int bfin_serial_resume(struct platform_device *dev) | |
1337 | { | |
ccfbc3e1 | 1338 | int i; |
194de561 | 1339 | |
c9607ecc | 1340 | for (i = 0; i < nr_active_ports; i++) { |
ccfbc3e1 SZ |
1341 | if (bfin_serial_ports[i].port.dev != &dev->dev) |
1342 | continue; | |
1343 | uart_resume_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
1344 | } | |
194de561 BW |
1345 | |
1346 | return 0; | |
1347 | } | |
1348 | ||
1349 | static int bfin_serial_probe(struct platform_device *dev) | |
1350 | { | |
1351 | struct resource *res = dev->resource; | |
1352 | int i; | |
1353 | ||
1354 | for (i = 0; i < dev->num_resources; i++, res++) | |
1355 | if (res->flags & IORESOURCE_MEM) | |
1356 | break; | |
1357 | ||
1358 | if (i < dev->num_resources) { | |
c9607ecc | 1359 | for (i = 0; i < nr_active_ports; i++, res++) { |
194de561 BW |
1360 | if (bfin_serial_ports[i].port.mapbase != res->start) |
1361 | continue; | |
1362 | bfin_serial_ports[i].port.dev = &dev->dev; | |
1363 | uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
194de561 BW |
1364 | } |
1365 | } | |
1366 | ||
1367 | return 0; | |
1368 | } | |
1369 | ||
ccfbc3e1 | 1370 | static int bfin_serial_remove(struct platform_device *dev) |
194de561 | 1371 | { |
ccfbc3e1 | 1372 | int i; |
194de561 | 1373 | |
c9607ecc | 1374 | for (i = 0; i < nr_active_ports; i++) { |
ccfbc3e1 SZ |
1375 | if (bfin_serial_ports[i].port.dev != &dev->dev) |
1376 | continue; | |
1377 | uart_remove_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
1378 | bfin_serial_ports[i].port.dev = NULL; | |
d307d36a SZ |
1379 | #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \ |
1380 | defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS) | |
ccfbc3e1 SZ |
1381 | gpio_free(bfin_serial_ports[i].cts_pin); |
1382 | gpio_free(bfin_serial_ports[i].rts_pin); | |
194de561 | 1383 | #endif |
ccfbc3e1 | 1384 | } |
194de561 BW |
1385 | |
1386 | return 0; | |
1387 | } | |
1388 | ||
1389 | static struct platform_driver bfin_serial_driver = { | |
1390 | .probe = bfin_serial_probe, | |
1391 | .remove = bfin_serial_remove, | |
1392 | .suspend = bfin_serial_suspend, | |
1393 | .resume = bfin_serial_resume, | |
1394 | .driver = { | |
1395 | .name = "bfin-uart", | |
e169c139 | 1396 | .owner = THIS_MODULE, |
194de561 BW |
1397 | }, |
1398 | }; | |
1399 | ||
1400 | static int __init bfin_serial_init(void) | |
1401 | { | |
1402 | int ret; | |
1403 | ||
1404 | pr_info("Serial: Blackfin serial driver\n"); | |
1405 | ||
1406 | bfin_serial_init_ports(); | |
1407 | ||
1408 | ret = uart_register_driver(&bfin_serial_reg); | |
1409 | if (ret == 0) { | |
1410 | ret = platform_driver_register(&bfin_serial_driver); | |
1411 | if (ret) { | |
1412 | pr_debug("uart register failed\n"); | |
1413 | uart_unregister_driver(&bfin_serial_reg); | |
1414 | } | |
1415 | } | |
1416 | return ret; | |
1417 | } | |
1418 | ||
1419 | static void __exit bfin_serial_exit(void) | |
1420 | { | |
1421 | platform_driver_unregister(&bfin_serial_driver); | |
1422 | uart_unregister_driver(&bfin_serial_reg); | |
1423 | } | |
1424 | ||
52e15f0e | 1425 | |
194de561 BW |
1426 | module_init(bfin_serial_init); |
1427 | module_exit(bfin_serial_exit); | |
1428 | ||
1429 | MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>"); | |
1430 | MODULE_DESCRIPTION("Blackfin generic serial port driver"); | |
1431 | MODULE_LICENSE("GPL"); | |
1432 | MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR); | |
e169c139 | 1433 | MODULE_ALIAS("platform:bfin-uart"); |