projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $ |
| 2 | * | |
| 3 | * linux/drivers/serial/sh-sci.h | |
| 4 | * | |
| 5 | * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) | |
| 6 | * Copyright (C) 1999, 2000 Niibe Yutaka | |
| 7 | * Copyright (C) 2000 Greg Banks | |
| 8 | * Copyright (C) 2002, 2003 Paul Mundt | |
| 9 | * Modified to support multiple serial ports. Stuart Menefy (May 2000). | |
| 10 | * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003). | |
| 11 | * Modified to support H8/300 Series Yoshinori Sato (Feb 2004). | |
| d89ddd1c | 12 | * Removed SH7300 support (Jul 2007). |
| 3ea6bc3d | 13 | * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Aug 2007). |
| 1da177e4 | 14 | */ |
| 1da177e4 | 15 | #include <linux/serial_core.h> |
| e108b2ca | 16 | #include <asm/io.h> |
| 1da177e4 | 17 | |
| 1da177e4 | 18 | #include <asm/gpio.h> |
| 3ea6bc3d | 19 | |
| 1da177e4 LT |
20 | #if defined(CONFIG_H83007) || defined(CONFIG_H83068) |
| 21 | #include <asm/regs306x.h> | |
| 22 | #endif | |
| 23 | #if defined(CONFIG_H8S2678) | |
| 24 | #include <asm/regs267x.h> | |
| 25 | #endif | |
| 1da177e4 | 26 | |
| 0fbde950 MD |
27 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
| 28 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | |
| 29 | defined(CONFIG_CPU_SUBTYPE_SH7708) || \ | |
| 30 | defined(CONFIG_CPU_SUBTYPE_SH7709) | |
| 1da177e4 LT |
31 | # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ |
| 32 | # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ | |
| 33 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | |
| 34 | # define SCI_AND_SCIF | |
| 35 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) | |
| 36 | # define SCIF0 0xA4400000 | |
| 37 | # define SCIF2 0xA4410000 | |
| b7a76e4b PM |
38 | # define SCSMR_Ir 0xA44A0000 |
| 39 | # define IRDA_SCIF SCIF0 | |
| 1da177e4 LT |
40 | # define SCPCR 0xA4000116 |
| 41 | # define SCPDR 0xA4000136 | |
| 42 | ||
| 43 | /* Set the clock source, | |
| 44 | * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input | |
| 45 | * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output | |
| 46 | */ | |
| 47 | # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 | |
| 48 | # define SCIF_ONLY | |
| 31a49c4b YS |
49 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 50 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
| 3ea6bc3d MB |
51 | # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ |
| 52 | # define SCIF_ONLY | |
| 53 | #define SCIF_ORER 0x0200 /* overrun error bit */ | |
| 1da177e4 | 54 | #elif defined(CONFIG_SH_RTS7751R2D) |
| 1da177e4 LT |
55 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ |
| 56 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 57 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 58 | # define SCIF_ONLY | |
| 05627486 PM |
59 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
| 60 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | |
| 61 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | |
| 62 | defined(CONFIG_CPU_SUBTYPE_SH7091) || \ | |
| 63 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | |
| 64 | defined(CONFIG_CPU_SUBTYPE_SH7751R) | |
| 1da177e4 LT |
65 | # define SCSPTR1 0xffe0001c /* 8 bit SCI */ |
| 66 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ | |
| 67 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 68 | # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ | |
| 69 | 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ | |
| 70 | 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) | |
| 71 | # define SCI_AND_SCIF | |
| 72 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) | |
| b7a76e4b PM |
73 | # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ |
| 74 | # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ | |
| 75 | # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ | |
| 1da177e4 LT |
76 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| 77 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 78 | # define SCIF_ONLY | |
| 2b1bd1ac | 79 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
| e108b2ca | 80 | # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ |
| 9465a54f NI |
81 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| 82 | # define PACR 0xa4050100 | |
| 83 | # define PBCR 0xa4050102 | |
| 84 | # define SCSCR_INIT(port) 0x3B | |
| e108b2ca | 85 | # define SCIF_ONLY |
| e108b2ca PM |
86 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) |
| 87 | # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ | |
| 88 | # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ | |
| 89 | # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ | |
| 90 | # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ | |
| 91 | # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ | |
| 92 | # define SCIF_ONLY | |
| 41504c39 PM |
93 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
| 94 | # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ | |
| 95 | # define SCSPTR0 SCPDR0 | |
| 96 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 97 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 98 | # define SCIF_ONLY | |
| 99 | # define PORT_PSCR 0xA405011E | |
| 9109a30e MD |
100 | #elif defined(CONFIG_CPU_SUBTYPE_SH7366) |
| 101 | # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ | |
| 102 | # define SCSPTR0 SCPDR0 | |
| 103 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 104 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 105 | # define SCIF_ONLY | |
| 1da177e4 | 106 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) |
| 1da177e4 LT |
107 | # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ |
| 108 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 109 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 110 | # define SCIF_ONLY | |
| 1da177e4 | 111 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) |
| 1da177e4 LT |
112 | # define SCIF_BASE_ADDR 0x01030000 |
| 113 | # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR | |
| 114 | # define SCIF_PTR2_OFFS 0x0000020 | |
| 115 | # define SCIF_LSR2_OFFS 0x0000024 | |
| 1da177e4 LT |
116 | # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ |
| 117 | # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ | |
| f9669187 | 118 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ |
| 1da177e4 LT |
119 | # define SCIF_ONLY |
| 120 | #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) | |
| 1da177e4 LT |
121 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
| 122 | # define SCI_ONLY | |
| 123 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) | |
| 124 | #elif defined(CONFIG_H8S2678) | |
| 1da177e4 LT |
125 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
| 126 | # define SCI_ONLY | |
| 127 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) | |
| 7d740a06 YS |
128 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
| 129 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | |
| 130 | # define SCSPTR1 0xffe08024 /* 16 bit SCIF */ | |
| 131 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 132 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 133 | # define SCIF_ONLY | |
| b7a76e4b PM |
134 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) |
| 135 | # define SCSPTR0 0xff923020 /* 16 bit SCIF */ | |
| 136 | # define SCSPTR1 0xff924020 /* 16 bit SCIF */ | |
| 137 | # define SCSPTR2 0xff925020 /* 16 bit SCIF */ | |
| 138 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 139 | # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ | |
| 140 | # define SCIF_ONLY | |
| 141 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) | |
| 142 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | |
| 143 | # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ | |
| e108b2ca | 144 | # define SCIF_ORER 0x0001 /* Overrun error bit */ |
| b7a76e4b PM |
145 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
| 146 | # define SCIF_ONLY | |
| 32351a28 PM |
147 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) |
| 148 | # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ | |
| 149 | # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ | |
| 150 | # define SCSPTR2 0xffec0024 /* 16 bit SCIF */ | |
| 151 | # define SCSPTR3 0xffed0024 /* 16 bit SCIF */ | |
| 152 | # define SCSPTR4 0xffee0024 /* 16 bit SCIF */ | |
| 153 | # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ | |
| 154 | # define SCIF_OPER 0x0001 /* Overrun error bit */ | |
| 155 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 156 | # define SCIF_ONLY | |
| 6d01f510 | 157 | #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \ |
| a8f67f4b PM |
158 | defined(CONFIG_CPU_SUBTYPE_SH7206) || \ |
| 159 | defined(CONFIG_CPU_SUBTYPE_SH7263) | |
| 9d4436a6 YS |
160 | # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ |
| 161 | # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ | |
| 162 | # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ | |
| 163 | # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ | |
| 164 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 165 | # define SCIF_ONLY | |
| 166 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) | |
| 167 | # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ | |
| 168 | # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ | |
| 169 | # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ | |
| 170 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 171 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 172 | # define SCIF_ONLY | |
| 2b1bd1ac PM |
173 | #elif defined(CONFIG_CPU_SUBTYPE_SHX3) |
| 174 | # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ | |
| 175 | # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ | |
| 176 | # define SCSPTR2 0xffc50020 /* 16 bit SCIF */ | |
| 177 | # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ | |
| 178 | # define SCIF_ORER 0x0001 /* Overrun error bit */ | |
| 179 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 180 | # define SCIF_ONLY | |
| 1da177e4 LT |
181 | #else |
| 182 | # error CPU subtype not defined | |
| 183 | #endif | |
| 184 | ||
| 185 | /* SCSCR */ | |
| 186 | #define SCI_CTRL_FLAGS_TIE 0x80 /* all */ | |
| 187 | #define SCI_CTRL_FLAGS_RIE 0x40 /* all */ | |
| 188 | #define SCI_CTRL_FLAGS_TE 0x20 /* all */ | |
| 189 | #define SCI_CTRL_FLAGS_RE 0x10 /* all */ | |
| 05627486 PM |
190 | #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
| 191 | defined(CONFIG_CPU_SUBTYPE_SH7091) || \ | |
| 192 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | |
| 193 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | |
| 194 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | |
| 195 | defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ | |
| 196 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
| 2b1bd1ac PM |
197 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
| 198 | defined(CONFIG_CPU_SUBTYPE_SHX3) | |
| 1da177e4 LT |
199 | #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ |
| 200 | #else | |
| 201 | #define SCI_CTRL_FLAGS_REIE 0 | |
| 202 | #endif | |
| 203 | /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 204 | /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 205 | /* SCI_CTRL_FLAGS_CKE1 0x02 * all */ | |
| 206 | /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */ | |
| 207 | ||
| 208 | /* SCxSR SCI */ | |
| 209 | #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 210 | #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 211 | #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 212 | #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 213 | #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 214 | #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 215 | /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 216 | /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 217 | ||
| 218 | #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER) | |
| 219 | ||
| 220 | /* SCxSR SCIF */ | |
| 221 | #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 222 | #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 223 | #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 224 | #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 225 | #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 226 | #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 227 | #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 228 | #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 229 | ||
| 3ea6bc3d | 230 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
| 31a49c4b YS |
231 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 232 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
| 1da177e4 LT |
233 | #define SCIF_ORER 0x0200 |
| 234 | #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) | |
| 235 | #define SCIF_RFDC_MASK 0x007f | |
| 236 | #define SCIF_TXROOM_MAX 64 | |
| 237 | #else | |
| 238 | #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) | |
| 239 | #define SCIF_RFDC_MASK 0x001f | |
| 240 | #define SCIF_TXROOM_MAX 16 | |
| 241 | #endif | |
| 242 | ||
| 243 | #if defined(SCI_ONLY) | |
| 244 | # define SCxSR_TEND(port) SCI_TEND | |
| 245 | # define SCxSR_ERRORS(port) SCI_ERRORS | |
| 246 | # define SCxSR_RDxF(port) SCI_RDRF | |
| 247 | # define SCxSR_TDxE(port) SCI_TDRE | |
| 248 | # define SCxSR_ORER(port) SCI_ORER | |
| 249 | # define SCxSR_FER(port) SCI_FER | |
| 250 | # define SCxSR_PER(port) SCI_PER | |
| 251 | # define SCxSR_BRK(port) 0x00 | |
| 252 | # define SCxSR_RDxF_CLEAR(port) 0xbc | |
| 253 | # define SCxSR_ERROR_CLEAR(port) 0xc4 | |
| 254 | # define SCxSR_TDxE_CLEAR(port) 0x78 | |
| b7a76e4b | 255 | # define SCxSR_BREAK_CLEAR(port) 0xc4 |
| 1da177e4 LT |
256 | #elif defined(SCIF_ONLY) |
| 257 | # define SCxSR_TEND(port) SCIF_TEND | |
| 258 | # define SCxSR_ERRORS(port) SCIF_ERRORS | |
| 259 | # define SCxSR_RDxF(port) SCIF_RDF | |
| 260 | # define SCxSR_TDxE(port) SCIF_TDFE | |
| d89ddd1c | 261 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) |
| 1da177e4 LT |
262 | # define SCxSR_ORER(port) SCIF_ORER |
| 263 | #else | |
| 264 | # define SCxSR_ORER(port) 0x0000 | |
| 265 | #endif | |
| 266 | # define SCxSR_FER(port) SCIF_FER | |
| 267 | # define SCxSR_PER(port) SCIF_PER | |
| 268 | # define SCxSR_BRK(port) SCIF_BRK | |
| 3ea6bc3d | 269 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
| 31a49c4b YS |
270 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 271 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
| 1da177e4 LT |
272 | # define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc) |
| 273 | # define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73) | |
| 274 | # define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf) | |
| 275 | # define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3) | |
| 276 | #else | |
| d89ddd1c | 277 | /* SH7705 can also use this, clearing is same between 7705 and 7709 */ |
| 1da177e4 LT |
278 | # define SCxSR_RDxF_CLEAR(port) 0x00fc |
| 279 | # define SCxSR_ERROR_CLEAR(port) 0x0073 | |
| 280 | # define SCxSR_TDxE_CLEAR(port) 0x00df | |
| b7a76e4b | 281 | # define SCxSR_BREAK_CLEAR(port) 0x00e3 |
| 1da177e4 LT |
282 | #endif |
| 283 | #else | |
| 284 | # define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) | |
| 285 | # define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) | |
| 286 | # define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) | |
| 287 | # define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) | |
| 288 | # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000) | |
| 289 | # define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) | |
| 290 | # define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) | |
| 291 | # define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) | |
| 292 | # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) | |
| 293 | # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) | |
| 294 | # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) | |
| 295 | # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) | |
| 296 | #endif | |
| 297 | ||
| 298 | /* SCFCR */ | |
| 299 | #define SCFCR_RFRST 0x0002 | |
| 300 | #define SCFCR_TFRST 0x0004 | |
| 301 | #define SCFCR_TCRST 0x4000 | |
| 302 | #define SCFCR_MCE 0x0008 | |
| 303 | ||
| 304 | #define SCI_MAJOR 204 | |
| 305 | #define SCI_MINOR_START 8 | |
| 306 | ||
| 307 | /* Generic serial flags */ | |
| 308 | #define SCI_RX_THROTTLE 0x0000001 | |
| 309 | ||
| 310 | #define SCI_MAGIC 0xbabeface | |
| 311 | ||
| 312 | /* | |
| 313 | * Events are used to schedule things to happen at timer-interrupt | |
| 314 | * time, instead of at rs interrupt time. | |
| 315 | */ | |
| 316 | #define SCI_EVENT_WRITE_WAKEUP 0 | |
| 317 | ||
| 1da177e4 LT |
318 | #define SCI_IN(size, offset) \ |
| 319 | unsigned int addr = port->mapbase + (offset); \ | |
| b7a76e4b | 320 | if ((size) == 8) { \ |
| 1da177e4 | 321 | return ctrl_inb(addr); \ |
| b7a76e4b | 322 | } else { \ |
| 1da177e4 LT |
323 | return ctrl_inw(addr); \ |
| 324 | } | |
| 325 | #define SCI_OUT(size, offset, value) \ | |
| 326 | unsigned int addr = port->mapbase + (offset); \ | |
| b7a76e4b | 327 | if ((size) == 8) { \ |
| 1da177e4 LT |
328 | ctrl_outb(value, addr); \ |
| 329 | } else { \ | |
| 330 | ctrl_outw(value, addr); \ | |
| 331 | } | |
| 332 | ||
| 333 | #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ | |
| 334 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ | |
| 335 | { \ | |
| b7a76e4b | 336 | if (port->type == PORT_SCI) { \ |
| 1da177e4 LT |
337 | SCI_IN(sci_size, sci_offset) \ |
| 338 | } else { \ | |
| b7a76e4b | 339 | SCI_IN(scif_size, scif_offset); \ |
| 1da177e4 LT |
340 | } \ |
| 341 | } \ | |
| 342 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ | |
| 343 | { \ | |
| 344 | if (port->type == PORT_SCI) { \ | |
| 345 | SCI_OUT(sci_size, sci_offset, value) \ | |
| 346 | } else { \ | |
| 347 | SCI_OUT(scif_size, scif_offset, value); \ | |
| 348 | } \ | |
| 349 | } | |
| 350 | ||
| 351 | #define CPU_SCIF_FNS(name, scif_offset, scif_size) \ | |
| 352 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ | |
| 353 | { \ | |
| b7a76e4b | 354 | SCI_IN(scif_size, scif_offset); \ |
| 1da177e4 LT |
355 | } \ |
| 356 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ | |
| 357 | { \ | |
| 358 | SCI_OUT(scif_size, scif_offset, value); \ | |
| 359 | } | |
| 360 | ||
| 361 | #define CPU_SCI_FNS(name, sci_offset, sci_size) \ | |
| 362 | static inline unsigned int sci_##name##_in(struct uart_port* port) \ | |
| 363 | { \ | |
| b7a76e4b | 364 | SCI_IN(sci_size, sci_offset); \ |
| 1da177e4 LT |
365 | } \ |
| 366 | static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \ | |
| 367 | { \ | |
| 368 | SCI_OUT(sci_size, sci_offset, value); \ | |
| 369 | } | |
| 370 | ||
| 371 | #ifdef CONFIG_CPU_SH3 | |
| 9465a54f NI |
372 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
| 373 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
| 374 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
| 375 | h8_sci_offset, h8_sci_size) \ | |
| 376 | CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) | |
| 377 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | |
| 378 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | |
| 3ea6bc3d | 379 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
| 31a49c4b YS |
380 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 381 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
| 1da177e4 LT |
382 | #define SCIF_FNS(name, scif_offset, scif_size) \ |
| 383 | CPU_SCIF_FNS(name, scif_offset, scif_size) | |
| 384 | #else | |
| 385 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
| 386 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
| 387 | h8_sci_offset, h8_sci_size) \ | |
| 388 | CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size) | |
| 389 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | |
| 390 | CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) | |
| 391 | #endif | |
| 392 | #elif defined(__H8300H__) || defined(__H8300S__) | |
| 393 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
| 394 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
| 395 | h8_sci_offset, h8_sci_size) \ | |
| 396 | CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) | |
| 397 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) | |
| 398 | #else | |
| 399 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
| 400 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
| 401 | h8_sci_offset, h8_sci_size) \ | |
| 402 | CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) | |
| 403 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | |
| 404 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | |
| 405 | #endif | |
| 406 | ||
| 3ea6bc3d | 407 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
| 31a49c4b YS |
408 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 409 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
| 9465a54f | 410 | |
| 1da177e4 LT |
411 | SCIF_FNS(SCSMR, 0x00, 16) |
| 412 | SCIF_FNS(SCBRR, 0x04, 8) | |
| 413 | SCIF_FNS(SCSCR, 0x08, 16) | |
| 414 | SCIF_FNS(SCTDSR, 0x0c, 8) | |
| 415 | SCIF_FNS(SCFER, 0x10, 16) | |
| 416 | SCIF_FNS(SCxSR, 0x14, 16) | |
| 417 | SCIF_FNS(SCFCR, 0x18, 16) | |
| 418 | SCIF_FNS(SCFDR, 0x1c, 16) | |
| 419 | SCIF_FNS(SCxTDR, 0x20, 8) | |
| 420 | SCIF_FNS(SCxRDR, 0x24, 8) | |
| 421 | SCIF_FNS(SCLSR, 0x24, 16) | |
| 422 | #else | |
| 423 | /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ | |
| 424 | /* name off sz off sz off sz off sz off sz*/ | |
| 425 | SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8) | |
| 426 | SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8) | |
| 427 | SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8) | |
| 428 | SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) | |
| 429 | SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) | |
| 430 | SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) | |
| 431 | SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) | |
| 32351a28 | 432 | #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ |
| 7d740a06 | 433 | defined(CONFIG_CPU_SUBTYPE_SH7763) || \ |
| 32351a28 PM |
434 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ |
| 435 | defined(CONFIG_CPU_SUBTYPE_SH7785) | |
| 6fc21b82 | 436 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) |
| b7a76e4b PM |
437 | SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) |
| 438 | SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) | |
| 439 | SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) | |
| 440 | SCIF_FNS(SCLSR, 0, 0, 0x28, 16) | |
| 441 | #else | |
| 1da177e4 LT |
442 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) |
| 443 | SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) | |
| 444 | SCIF_FNS(SCLSR, 0, 0, 0x24, 16) | |
| 445 | #endif | |
| b7a76e4b | 446 | #endif |
| 1da177e4 LT |
447 | #define sci_in(port, reg) sci_##reg##_in(port) |
| 448 | #define sci_out(port, reg, value) sci_##reg##_out(port, value) | |
| 449 | ||
| 450 | /* H8/300 series SCI pins assignment */ | |
| 451 | #if defined(__H8300H__) || defined(__H8300S__) | |
| 452 | static const struct __attribute__((packed)) { | |
| 453 | int port; /* GPIO port no */ | |
| 454 | unsigned short rx,tx; /* GPIO bit no */ | |
| 455 | } h8300_sci_pins[] = { | |
| 456 | #if defined(CONFIG_H83007) || defined(CONFIG_H83068) | |
| 457 | { /* SCI0 */ | |
| 458 | .port = H8300_GPIO_P9, | |
| 459 | .rx = H8300_GPIO_B2, | |
| 460 | .tx = H8300_GPIO_B0, | |
| 461 | }, | |
| 462 | { /* SCI1 */ | |
| 463 | .port = H8300_GPIO_P9, | |
| 464 | .rx = H8300_GPIO_B3, | |
| 465 | .tx = H8300_GPIO_B1, | |
| 466 | }, | |
| 467 | { /* SCI2 */ | |
| 468 | .port = H8300_GPIO_PB, | |
| 469 | .rx = H8300_GPIO_B7, | |
| 470 | .tx = H8300_GPIO_B6, | |
| 471 | } | |
| 472 | #elif defined(CONFIG_H8S2678) | |
| 473 | { /* SCI0 */ | |
| 474 | .port = H8300_GPIO_P3, | |
| 475 | .rx = H8300_GPIO_B2, | |
| 476 | .tx = H8300_GPIO_B0, | |
| 477 | }, | |
| 478 | { /* SCI1 */ | |
| 479 | .port = H8300_GPIO_P3, | |
| 480 | .rx = H8300_GPIO_B3, | |
| 481 | .tx = H8300_GPIO_B1, | |
| 482 | }, | |
| 483 | { /* SCI2 */ | |
| 484 | .port = H8300_GPIO_P5, | |
| 485 | .rx = H8300_GPIO_B1, | |
| 486 | .tx = H8300_GPIO_B0, | |
| 487 | } | |
| 488 | #endif | |
| 489 | }; | |
| 490 | #endif | |
| 491 | ||
| 0fbde950 MD |
492 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
| 493 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | |
| 494 | defined(CONFIG_CPU_SUBTYPE_SH7708) || \ | |
| 495 | defined(CONFIG_CPU_SUBTYPE_SH7709) | |
| 1da177e4 LT |
496 | static inline int sci_rxd_in(struct uart_port *port) |
| 497 | { | |
| 498 | if (port->mapbase == 0xfffffe80) | |
| 499 | return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */ | |
| 500 | if (port->mapbase == 0xa4000150) | |
| 501 | return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ | |
| 502 | if (port->mapbase == 0xa4000140) | |
| 503 | return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ | |
| 504 | return 1; | |
| 505 | } | |
| 506 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) | |
| 507 | static inline int sci_rxd_in(struct uart_port *port) | |
| 508 | { | |
| 509 | if (port->mapbase == SCIF0) | |
| 510 | return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ | |
| 511 | if (port->mapbase == SCIF2) | |
| 512 | return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ | |
| 513 | return 1; | |
| 514 | } | |
| 9465a54f | 515 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
| e108b2ca PM |
516 | static inline int sci_rxd_in(struct uart_port *port) |
| 517 | { | |
| 9465a54f NI |
518 | return sci_in(port,SCxSR)&0x0010 ? 1 : 0; |
| 519 | } | |
| 520 | static inline void set_sh771x_scif_pfc(struct uart_port *port) | |
| 521 | { | |
| 522 | if (port->mapbase == 0xA4400000){ | |
| 523 | ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR); | |
| 524 | ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR); | |
| 525 | return; | |
| 526 | } | |
| 527 | if (port->mapbase == 0xA4410000){ | |
| 528 | ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR); | |
| 529 | return; | |
| 530 | } | |
| e108b2ca | 531 | } |
| 31a49c4b YS |
532 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 533 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
| 3ea6bc3d MB |
534 | static inline int sci_rxd_in(struct uart_port *port) |
| 535 | { | |
| 536 | if (port->mapbase == 0xa4430000) | |
| 537 | return sci_in(port, SCxSR) & 0x0003 ? 1 : 0; | |
| 538 | else if (port->mapbase == 0xa4438000) | |
| 539 | return sci_in(port, SCxSR) & 0x0003 ? 1 : 0; | |
| 540 | return 1; | |
| 541 | } | |
| 05627486 PM |
542 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
| 543 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | |
| 544 | defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ | |
| 545 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | |
| 546 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | |
| 547 | defined(CONFIG_CPU_SUBTYPE_SH7091) || \ | |
| 1da177e4 LT |
548 | defined(CONFIG_CPU_SUBTYPE_SH4_202) |
| 549 | static inline int sci_rxd_in(struct uart_port *port) | |
| 550 | { | |
| 551 | #ifndef SCIF_ONLY | |
| 552 | if (port->mapbase == 0xffe00000) | |
| 553 | return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ | |
| 554 | #endif | |
| 555 | #ifndef SCI_ONLY | |
| 556 | if (port->mapbase == 0xffe80000) | |
| 557 | return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | |
| 558 | #endif | |
| 559 | return 1; | |
| 560 | } | |
| 561 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) | |
| 562 | static inline int sci_rxd_in(struct uart_port *port) | |
| 563 | { | |
| 564 | if (port->mapbase == 0xfe600000) | |
| 565 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 566 | if (port->mapbase == 0xfe610000) | |
| 567 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 568 | if (port->mapbase == 0xfe620000) | |
| 569 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 31388750 | 570 | return 1; |
| 1da177e4 | 571 | } |
| e108b2ca PM |
572 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) |
| 573 | static inline int sci_rxd_in(struct uart_port *port) | |
| 574 | { | |
| 575 | if (port->mapbase == 0xffe00000) | |
| 576 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 577 | if (port->mapbase == 0xffe10000) | |
| 578 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 579 | if (port->mapbase == 0xffe20000) | |
| 580 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 581 | if (port->mapbase == 0xffe30000) | |
| 582 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 583 | return 1; | |
| 584 | } | |
| 9109a30e | 585 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) || defined(CONFIG_CPU_SUBTYPE_SH7366) |
| 41504c39 PM |
586 | static inline int sci_rxd_in(struct uart_port *port) |
| 587 | { | |
| 588 | if (port->mapbase == 0xffe00000) | |
| 589 | return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */ | |
| 590 | return 1; | |
| 591 | } | |
| 1da177e4 LT |
592 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) |
| 593 | static inline int sci_rxd_in(struct uart_port *port) | |
| 594 | { | |
| 595 | return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */ | |
| 596 | } | |
| 597 | #elif defined(__H8300H__) || defined(__H8300S__) | |
| 598 | static inline int sci_rxd_in(struct uart_port *port) | |
| 599 | { | |
| 600 | int ch = (port->mapbase - SMR0) >> 3; | |
| 601 | return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; | |
| 602 | } | |
| 7d740a06 YS |
603 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
| 604 | static inline int sci_rxd_in(struct uart_port *port) | |
| 605 | { | |
| 606 | if (port->mapbase == 0xffe00000) | |
| 607 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 608 | if (port->mapbase == 0xffe08000) | |
| 609 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 610 | return 1; | |
| 611 | } | |
| b7a76e4b PM |
612 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) |
| 613 | static inline int sci_rxd_in(struct uart_port *port) | |
| 614 | { | |
| 615 | if (port->mapbase == 0xff923000) | |
| 616 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 617 | if (port->mapbase == 0xff924000) | |
| 618 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 619 | if (port->mapbase == 0xff925000) | |
| 620 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 31388750 | 621 | return 1; |
| b7a76e4b PM |
622 | } |
| 623 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) | |
| 624 | static inline int sci_rxd_in(struct uart_port *port) | |
| 625 | { | |
| 626 | if (port->mapbase == 0xffe00000) | |
| 627 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 628 | if (port->mapbase == 0xffe10000) | |
| 629 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 31388750 | 630 | return 1; |
| b7a76e4b | 631 | } |
| 32351a28 PM |
632 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) |
| 633 | static inline int sci_rxd_in(struct uart_port *port) | |
| 634 | { | |
| 635 | if (port->mapbase == 0xffea0000) | |
| 636 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 637 | if (port->mapbase == 0xffeb0000) | |
| 638 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 639 | if (port->mapbase == 0xffec0000) | |
| 640 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 641 | if (port->mapbase == 0xffed0000) | |
| 642 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 643 | if (port->mapbase == 0xffee0000) | |
| 644 | return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 645 | if (port->mapbase == 0xffef0000) | |
| 646 | return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 647 | return 1; | |
| 648 | } | |
| 6d01f510 | 649 | #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \ |
| a8f67f4b PM |
650 | defined(CONFIG_CPU_SUBTYPE_SH7206) || \ |
| 651 | defined(CONFIG_CPU_SUBTYPE_SH7263) | |
| 9d4436a6 YS |
652 | static inline int sci_rxd_in(struct uart_port *port) |
| 653 | { | |
| 654 | if (port->mapbase == 0xfffe8000) | |
| 655 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 656 | if (port->mapbase == 0xfffe8800) | |
| 657 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 658 | if (port->mapbase == 0xfffe9000) | |
| 659 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 660 | if (port->mapbase == 0xfffe9800) | |
| 661 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 31388750 | 662 | return 1; |
| 9d4436a6 YS |
663 | } |
| 664 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) | |
| 665 | static inline int sci_rxd_in(struct uart_port *port) | |
| 666 | { | |
| 667 | if (port->mapbase == 0xf8400000) | |
| 668 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 669 | if (port->mapbase == 0xf8410000) | |
| 670 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 671 | if (port->mapbase == 0xf8420000) | |
| 672 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 31388750 | 673 | return 1; |
| 9d4436a6 | 674 | } |
| 2b1bd1ac PM |
675 | #elif defined(CONFIG_CPU_SUBTYPE_SHX3) |
| 676 | static inline int sci_rxd_in(struct uart_port *port) | |
| 677 | { | |
| 678 | if (port->mapbase == 0xffc30000) | |
| 679 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 680 | if (port->mapbase == 0xffc40000) | |
| 681 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 682 | if (port->mapbase == 0xffc50000) | |
| 683 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 684 | if (port->mapbase == 0xffc60000) | |
| 685 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 1760b7d7 | 686 | return 1; |
| 2b1bd1ac | 687 | } |
| 1da177e4 LT |
688 | #endif |
| 689 | ||
| 690 | /* | |
| 691 | * Values for the BitRate Register (SCBRR) | |
| 692 | * | |
| 693 | * The values are actually divisors for a frequency which can | |
| 694 | * be internal to the SH3 (14.7456MHz) or derived from an external | |
| 695 | * clock source. This driver assumes the internal clock is used; | |
| 696 | * to support using an external clock source, config options or | |
| 697 | * possibly command-line options would need to be added. | |
| 698 | * | |
| 699 | * Also, to support speeds below 2400 (why?) the lower 2 bits of | |
| 700 | * the SCSMR register would also need to be set to non-zero values. | |
| 701 | * | |
| 702 | * -- Greg Banks 27Feb2000 | |
| 703 | * | |
| 704 | * Answer: The SCBRR register is only eight bits, and the value in | |
| 705 | * it gets larger with lower baud rates. At around 2400 (depending on | |
| 706 | * the peripherial module clock) you run out of bits. However the | |
| 707 | * lower two bits of SCSMR allow the module clock to be divided down, | |
| 708 | * scaling the value which is needed in SCBRR. | |
| 709 | * | |
| 710 | * -- Stuart Menefy - 23 May 2000 | |
| 711 | * | |
| 712 | * I meant, why would anyone bother with bitrates below 2400. | |
| 713 | * | |
| 714 | * -- Greg Banks - 7Jul2000 | |
| 715 | * | |
| 716 | * You "speedist"! How will I use my 110bps ASR-33 teletype with paper | |
| 717 | * tape reader as a console! | |
| 718 | * | |
| 719 | * -- Mitch Davis - 15 Jul 2000 | |
| 720 | */ | |
| 721 | ||
| 7d740a06 YS |
722 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \ |
| 723 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
| 32351a28 | 724 | defined(CONFIG_CPU_SUBTYPE_SH7785) |
| b7a76e4b | 725 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) |
| 3ea6bc3d | 726 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
| 31a49c4b YS |
727 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 728 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
| b7a76e4b PM |
729 | #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) |
| 730 | #elif defined(__H8300H__) || defined(__H8300S__) | |
| 1da177e4 | 731 | #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1) |
| b7a76e4b PM |
732 | #elif defined(CONFIG_SUPERH64) |
| 733 | #define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1) | |
| 734 | #else /* Generic SH */ | |
| 735 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) | |
| 1da177e4 | 736 | #endif |