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sh: Let INTC set IRQF_VALID on ARM platforms.
[deliverable/linux.git] / drivers / serial / sh-sci.h
CommitLineData
1da177e4 1#include <linux/serial_core.h>
edad1f20 2#include <linux/io.h>
69edbba0 3#include <linux/gpio.h>
3ea6bc3d 4
1da177e4
LT		 5#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
6#include <asm/regs306x.h>
7#endif
8#if defined(CONFIG_H8S2678)
9#include <asm/regs267x.h>
10#endif
1da177e4 11
0fbde950
MD		 12#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
14 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7709)
1da177e4
LT		 16# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
17# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
18# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
1da177e4
LT		 19#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
20# define SCIF0 0xA4400000
21# define SCIF2 0xA4410000
b7a76e4b
PM		 22# define SCSMR_Ir 0xA44A0000
23# define IRDA_SCIF SCIF0
1da177e4
LT		 24# define SCPCR 0xA4000116
25# define SCPDR 0xA4000136
26
27/* Set the clock source,
28 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
29 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
30 */
31# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
31a49c4b
YS		 32#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7721)
3ea6bc3d 34# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
fd88cac9
PM		 35# define PORT_PTCR 0xA405011EUL
36# define PORT_PVCR 0xA4050122UL
37# define SCIF_ORER 0x0200 /* overrun error bit */
1da177e4 38#elif defined(CONFIG_SH_RTS7751R2D)
7abc404a 39# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
1da177e4
LT		 40# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
41# define SCIF_ORER 0x0001 /* overrun error bit */
42# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
05627486
PM		 43#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
44 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
45 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
46 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
47 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
48 defined(CONFIG_CPU_SUBTYPE_SH7751R)
1da177e4
LT		 49# define SCSPTR1 0xffe0001c /* 8 bit SCI */
50# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
51# define SCIF_ORER 0x0001 /* overrun error bit */
52# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
53 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
54 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
1da177e4 55#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
b7a76e4b
PM		 56# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
57# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
58# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
1da177e4
LT		 59# define SCIF_ORER 0x0001 /* overrun error bit */
60# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
2b1bd1ac 61#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
e108b2ca 62# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
9465a54f
NI		 63# define SCIF_ORER 0x0001 /* overrun error bit */
64# define PACR 0xa4050100
65# define PBCR 0xa4050102
66# define SCSCR_INIT(port) 0x3B
e108b2ca
PM		 67#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
68# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
69# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
70# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
71# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
72# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
41504c39 73#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
346b7463
MD		 74# define PADR 0xA4050120
75# define PSDR 0xA405013e
76# define PWDR 0xA4050166
77# define PSCR 0xA405011E
41504c39
PM		 78# define SCIF_ORER 0x0001 /* overrun error bit */
79# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
9109a30e
MD		 80#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
81# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
82# define SCSPTR0 SCPDR0
83# define SCIF_ORER 0x0001 /* overrun error bit */
84# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
178dd0cd
PM		 85#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
86# define SCSPTR0 0xa4050160
87# define SCSPTR1 0xa405013e
88# define SCSPTR2 0xa4050160
89# define SCSPTR3 0xa405013e
90# define SCSPTR4 0xa4050128
91# define SCSPTR5 0xa4050128
92# define SCIF_ORER 0x0001 /* overrun error bit */
93# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
47948d2b
KM		 94#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
95# define SCIF_ORER 0x0001 /* overrun error bit */
96# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
1da177e4 97#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
1da177e4
LT		 98# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
99# define SCIF_ORER 0x0001 /* overrun error bit */
100# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
1da177e4 101#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1da177e4
LT		 102# define SCIF_BASE_ADDR 0x01030000
103# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
104# define SCIF_PTR2_OFFS 0x0000020
105# define SCIF_LSR2_OFFS 0x0000024
1da177e4
LT		 106# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
107# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
f9669187 108# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
1da177e4 109#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
1da177e4 110# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
1da177e4
LT		 111# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
112#elif defined(CONFIG_H8S2678)
1da177e4 113# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
1da177e4 114# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
c01f0f1a
YS		 115#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
116# define SCSPTR0 0xfe4b0020
117# define SCSPTR1 0xfe4b0020
118# define SCSPTR2 0xfe4b0020
119# define SCIF_ORER 0x0001
120# define SCSCR_INIT(port) 0x38
121# define SCIF_ONLY
7d740a06
YS		 122#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
123# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
124# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
c63847a3 125# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
7d740a06 126# define SCIF_ORER 0x0001 /* overrun error bit */
c63847a3 127# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
b7a76e4b
PM		 128#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
129# define SCSPTR0 0xff923020 /* 16 bit SCIF */
130# define SCSPTR1 0xff924020 /* 16 bit SCIF */
131# define SCSPTR2 0xff925020 /* 16 bit SCIF */
132# define SCIF_ORER 0x0001 /* overrun error bit */
133# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
b7a76e4b
PM		 134#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
135# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
136# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
e108b2ca 137# define SCIF_ORER 0x0001 /* Overrun error bit */
b7a76e4b 138# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
55ba99eb
KM		 139#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
140 defined(CONFIG_CPU_SUBTYPE_SH7786)
32351a28
PM		 141# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
142# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
143# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
144# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
145# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
146# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
34aeb43e 147# define SCIF_ORER 0x0001 /* Overrun error bit */
32351a28 148# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
2825999e
PG		 149#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
150 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
a8f67f4b
PM		 151 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
152 defined(CONFIG_CPU_SUBTYPE_SH7263)
9d4436a6
YS		 153# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
154# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
155# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
156# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
2825999e
PG		 157# if defined(CONFIG_CPU_SUBTYPE_SH7201)
158# define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
159# define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
160# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
161# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
162# endif
9d4436a6 163# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
9d4436a6
YS		 164#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
165# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
166# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
167# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
168# define SCIF_ORER 0x0001 /* overrun error bit */
169# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
2b1bd1ac
PM		 170#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
171# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
172# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
173# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
174# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
175# define SCIF_ORER 0x0001 /* Overrun error bit */
176# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
1da177e4
LT		 177#else
178# error CPU subtype not defined
179#endif
180
181/* SCSCR */
182#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
183#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
184#define SCI_CTRL_FLAGS_TE 0x20 /* all */
185#define SCI_CTRL_FLAGS_RE 0x10 /* all */
05627486
PM		 186#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
187 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
188 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
a8884e34 189 defined(CONFIG_CPU_SUBTYPE_SH7722) || \
05627486
PM		 190 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
191 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
192 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
c63847a3 193 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
05627486 194 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
2b1bd1ac 195 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
55ba99eb 196 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
2b1bd1ac 197 defined(CONFIG_CPU_SUBTYPE_SHX3)
1da177e4
LT		 198#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
199#else
200#define SCI_CTRL_FLAGS_REIE 0
201#endif
202/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
203/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
204/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
205/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
206
207/* SCxSR SCI */
208#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
209#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
210#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
211#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
212#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
213#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
214/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
215/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
216
217#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
218
219/* SCxSR SCIF */
220#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
221#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
222#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
223#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
224#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
225#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
226#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
227#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
228
3ea6bc3d 229#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b
YS		 230 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
231 defined(CONFIG_CPU_SUBTYPE_SH7721)
c63847a3
NI		 232# define SCIF_ORER 0x0200
233# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
234# define SCIF_RFDC_MASK 0x007f
235# define SCIF_TXROOM_MAX 64
236#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
237# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK )
238# define SCIF_RFDC_MASK 0x007f
239# define SCIF_TXROOM_MAX 64
240/* SH7763 SCIF2 support */
241# define SCIF2_RFDC_MASK 0x001f
242# define SCIF2_TXROOM_MAX 16
1da177e4 243#else
c63847a3
NI		 244# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
245# define SCIF_RFDC_MASK 0x001f
246# define SCIF_TXROOM_MAX 16
1da177e4
LT		 247#endif
248
d830fa45
PM		 249#ifndef SCIF_ORER
250#define SCIF_ORER 0x0000
251#endif
252
15c73aaa
PM		 253#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
254#define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
255#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
256#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
257#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
258#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
259#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
d830fa45 260#define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
15c73aaa 261
3ea6bc3d 262#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b
YS		 263 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
264 defined(CONFIG_CPU_SUBTYPE_SH7721)
15c73aaa
PM		 265# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
266# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
267# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
268# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
1da177e4 269#else
1da177e4
LT		 270# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
271# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
272# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
273# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
274#endif
275
276/* SCFCR */
277#define SCFCR_RFRST 0x0002
278#define SCFCR_TFRST 0x0004
279#define SCFCR_TCRST 0x4000
280#define SCFCR_MCE 0x0008
281
282#define SCI_MAJOR 204
283#define SCI_MINOR_START 8
284
285/* Generic serial flags */
286#define SCI_RX_THROTTLE 0x0000001
287
288#define SCI_MAGIC 0xbabeface
289
290/*
291 * Events are used to schedule things to happen at timer-interrupt
292 * time, instead of at rs interrupt time.
293 */
294#define SCI_EVENT_WRITE_WAKEUP 0
295
1da177e4 296#define SCI_IN(size, offset) \
b7a76e4b 297 if ((size) == 8) { \
7ff731ae 298 return ioread8(port->membase + (offset)); \
b7a76e4b 299 } else { \
7ff731ae 300 return ioread16(port->membase + (offset)); \
1da177e4
LT		 301 }
302#define SCI_OUT(size, offset, value) \
b7a76e4b 303 if ((size) == 8) { \
7ff731ae 304 iowrite8(value, port->membase + (offset)); \
3d2c2f3e 305 } else if ((size) == 16) { \
7ff731ae 306 iowrite16(value, port->membase + (offset)); \
1da177e4
LT		 307 }
308
309#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
310 static inline unsigned int sci_##name##_in(struct uart_port *port) \
311 { \
1a22f08d
YS		 312 if (port->type == PORT_SCIF) { \
313 SCI_IN(scif_size, scif_offset) \
314 } else { /* PORT_SCI or PORT_SCIFA */ \
315 SCI_IN(sci_size, sci_offset); \
1da177e4
LT		 316 } \
317 } \
318 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
319 { \
1a22f08d
YS		 320 if (port->type == PORT_SCIF) { \
321 SCI_OUT(scif_size, scif_offset, value) \
322 } else { /* PORT_SCI or PORT_SCIFA */ \
323 SCI_OUT(sci_size, sci_offset, value); \
1da177e4
LT		 324 } \
325 }
326
168f3623
YS		 327#ifdef CONFIG_H8300
328/* h8300 don't have SCIF */
329#define CPU_SCIF_FNS(name) \
330 static inline unsigned int sci_##name##_in(struct uart_port *port) \
331 { \
332 return 0; \
333 } \
334 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
335 { \
336 }
337#else
338#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
1da177e4
LT		 339 static inline unsigned int sci_##name##_in(struct uart_port *port) \
340 { \
b7a76e4b 341 SCI_IN(scif_size, scif_offset); \
1da177e4
LT		 342 } \
343 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
344 { \
345 SCI_OUT(scif_size, scif_offset, value); \
346 }
168f3623 347#endif
1da177e4
LT		 348
349#define CPU_SCI_FNS(name, sci_offset, sci_size) \
350 static inline unsigned int sci_##name##_in(struct uart_port* port) \
351 { \
b7a76e4b 352 SCI_IN(sci_size, sci_offset); \
1da177e4
LT		 353 } \
354 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
355 { \
356 SCI_OUT(sci_size, sci_offset, value); \
357 }
358
359#ifdef CONFIG_CPU_SH3
9465a54f
NI		 360#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
361#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
362 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
363 h8_sci_offset, h8_sci_size) \
364 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
365#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
366 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
3ea6bc3d 367#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b
YS		 368 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
369 defined(CONFIG_CPU_SUBTYPE_SH7721)
1da177e4
LT		 370#define SCIF_FNS(name, scif_offset, scif_size) \
371 CPU_SCIF_FNS(name, scif_offset, scif_size)
372#else
373#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
374 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
375 h8_sci_offset, h8_sci_size) \
376 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
377#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
378 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
379#endif
380#elif defined(__H8300H__) || defined(__H8300S__)
381#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
382 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
383 h8_sci_offset, h8_sci_size) \
384 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
168f3623
YS		 385#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
386 CPU_SCIF_FNS(name)
47948d2b
KM		 387#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
388 defined(CONFIG_CPU_SUBTYPE_SH7724)
178dd0cd
PM		 389 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
390 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
391 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
392 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
1da177e4
LT		 393#else
394#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
395 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
396 h8_sci_offset, h8_sci_size) \
397 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
398#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
399 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
400#endif
401
3ea6bc3d 402#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b
YS		 403 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
404 defined(CONFIG_CPU_SUBTYPE_SH7721)
9465a54f 405
1da177e4
LT		 406SCIF_FNS(SCSMR, 0x00, 16)
407SCIF_FNS(SCBRR, 0x04, 8)
408SCIF_FNS(SCSCR, 0x08, 16)
409SCIF_FNS(SCTDSR, 0x0c, 8)
410SCIF_FNS(SCFER, 0x10, 16)
411SCIF_FNS(SCxSR, 0x14, 16)
412SCIF_FNS(SCFCR, 0x18, 16)
413SCIF_FNS(SCFDR, 0x1c, 16)
414SCIF_FNS(SCxTDR, 0x20, 8)
415SCIF_FNS(SCxRDR, 0x24, 8)
416SCIF_FNS(SCLSR, 0x24, 16)
47948d2b
KM		 417#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
418 defined(CONFIG_CPU_SUBTYPE_SH7724)
178dd0cd
PM		 419SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
420SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
421SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
422SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
423SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
424SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
f686359e 425SCIx_FNS(SCSPTR, 0, 0, 0, 0)
178dd0cd
PM		 426SCIF_FNS(SCTDSR, 0x0c, 8)
427SCIF_FNS(SCFER, 0x10, 16)
428SCIF_FNS(SCFCR, 0x18, 16)
429SCIF_FNS(SCFDR, 0x1c, 16)
430SCIF_FNS(SCLSR, 0x24, 16)
1da177e4
LT		 431#else
432/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
433/* name off sz off sz off sz off sz off sz*/
434SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
435SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
436SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
437SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
438SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
439SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
440SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
32351a28
PM		 441#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
442 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
55ba99eb
KM		 443 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
444 defined(CONFIG_CPU_SUBTYPE_SH7786)
c2697968 445SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
b7a76e4b
PM		 446SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
447SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
448SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
449SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
c2697968 450#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
c63847a3
NI		 451SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
452SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
c2697968
PM		 453SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
454SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
455SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
456SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
457SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
b7a76e4b 458#else
1da177e4 459SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
9b4e466f
MD		 460#if defined(CONFIG_CPU_SUBTYPE_SH7722)
461SCIF_FNS(SCSPTR, 0, 0, 0, 0)
462#else
1da177e4 463SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
9b4e466f 464#endif
1da177e4
LT		 465SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
466#endif
b7a76e4b 467#endif
1da177e4
LT		 468#define sci_in(port, reg) sci_##reg##_in(port)
469#define sci_out(port, reg, value) sci_##reg##_out(port, value)
470
471/* H8/300 series SCI pins assignment */
472#if defined(__H8300H__) || defined(__H8300S__)
473static const struct __attribute__((packed)) {
474 int port; /* GPIO port no */
475 unsigned short rx,tx; /* GPIO bit no */
476} h8300_sci_pins[] = {
477#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
478 { /* SCI0 */
479 .port = H8300_GPIO_P9,
480 .rx = H8300_GPIO_B2,
481 .tx = H8300_GPIO_B0,
482 },
483 { /* SCI1 */
484 .port = H8300_GPIO_P9,
485 .rx = H8300_GPIO_B3,
486 .tx = H8300_GPIO_B1,
487 },
488 { /* SCI2 */
489 .port = H8300_GPIO_PB,
490 .rx = H8300_GPIO_B7,
491 .tx = H8300_GPIO_B6,
492 }
493#elif defined(CONFIG_H8S2678)
494 { /* SCI0 */
495 .port = H8300_GPIO_P3,
496 .rx = H8300_GPIO_B2,
497 .tx = H8300_GPIO_B0,
498 },
499 { /* SCI1 */
500 .port = H8300_GPIO_P3,
501 .rx = H8300_GPIO_B3,
502 .tx = H8300_GPIO_B1,
503 },
504 { /* SCI2 */
505 .port = H8300_GPIO_P5,
506 .rx = H8300_GPIO_B1,
507 .tx = H8300_GPIO_B0,
508 }
509#endif
510};
511#endif
512
0fbde950
MD		 513#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
514 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
515 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
516 defined(CONFIG_CPU_SUBTYPE_SH7709)
1da177e4
LT		 517static inline int sci_rxd_in(struct uart_port *port)
518{
519 if (port->mapbase == 0xfffffe80)
32b53076 520 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
3ea6bc3d
MB		 521 return 1;
522}
05627486
PM		 523#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
524 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
525 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
526 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
527 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
961e9ff9 528 defined(CONFIG_CPU_SUBTYPE_SH7091)
1da177e4
LT		 529static inline int sci_rxd_in(struct uart_port *port)
530{
1da177e4 531 if (port->mapbase == 0xffe00000)
32b53076 532 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
47948d2b
KM		 533 return 1;
534}
1da177e4
LT		 535#elif defined(__H8300H__) || defined(__H8300S__)
536static inline int sci_rxd_in(struct uart_port *port)
537{
538 int ch = (port->mapbase - SMR0) >> 3;
539 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
540}
9e9622d1 541#else /* default case for non-SCI processors */
2b1bd1ac
PM		 542static inline int sci_rxd_in(struct uart_port *port)
543{
1760b7d7 544 return 1;
2b1bd1ac 545}
1da177e4
LT		 546#endif
547
548/*
549 * Values for the BitRate Register (SCBRR)
550 *
551 * The values are actually divisors for a frequency which can
552 * be internal to the SH3 (14.7456MHz) or derived from an external
553 * clock source. This driver assumes the internal clock is used;
554 * to support using an external clock source, config options or
555 * possibly command-line options would need to be added.
556 *
557 * Also, to support speeds below 2400 (why?) the lower 2 bits of
558 * the SCSMR register would also need to be set to non-zero values.
559 *
560 * -- Greg Banks 27Feb2000
561 *
562 * Answer: The SCBRR register is only eight bits, and the value in
563 * it gets larger with lower baud rates. At around 2400 (depending on
564 * the peripherial module clock) you run out of bits. However the
565 * lower two bits of SCSMR allow the module clock to be divided down,
566 * scaling the value which is needed in SCBRR.
567 *
568 * -- Stuart Menefy - 23 May 2000
569 *
570 * I meant, why would anyone bother with bitrates below 2400.
571 *
572 * -- Greg Banks - 7Jul2000
573 *
574 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
575 * tape reader as a console!
576 *
577 * -- Mitch Davis - 15 Jul 2000
578 */
579
c63847a3 580#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
55ba99eb
KM		 581 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
582 defined(CONFIG_CPU_SUBTYPE_SH7786)
b7a76e4b 583#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
3ea6bc3d 584#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b
YS		 585 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
586 defined(CONFIG_CPU_SUBTYPE_SH7721)
b7a76e4b 587#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
47948d2b
KM		 588#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
589 defined(CONFIG_CPU_SUBTYPE_SH7724)
ba1d2818
NI		 590static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
591{
592 if (port->type == PORT_SCIF)
593 return (clk+16*bps)/(32*bps)-1;
594 else
595 return ((clk*2)+16*bps)/(16*bps)-1;
596}
597#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
b7a76e4b 598#elif defined(__H8300H__) || defined(__H8300S__)
a2159b52 599#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
b7a76e4b
PM		 600#else /* Generic SH */
601#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
1da177e4 602#endif
Linux kernel - Deliverables
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