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sh: Add gpio.h stubs for PFC definitions.
[deliverable/linux.git] / drivers / serial / sh-sci.h
CommitLineData
1da177e4
LT		 1/* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
2 *
3 * linux/drivers/serial/sh-sci.h
4 *
5 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6 * Copyright (C) 1999, 2000 Niibe Yutaka
7 * Copyright (C) 2000 Greg Banks
8 * Copyright (C) 2002, 2003 Paul Mundt
9 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
d89ddd1c 12 * Removed SH7300 support (Jul 2007).
1da177e4 13 */
1da177e4 14#include <linux/serial_core.h>
e108b2ca 15#include <asm/io.h>
1da177e4
LT		 16
17#if defined(__H8300H__) || defined(__H8300S__)
18#include <asm/gpio.h>
19#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
20#include <asm/regs306x.h>
21#endif
22#if defined(CONFIG_H8S2678)
23#include <asm/regs267x.h>
24#endif
25#endif
26
0fbde950
MD		 27#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
28 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
29 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
30 defined(CONFIG_CPU_SUBTYPE_SH7709)
1da177e4
LT		 31# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
32# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
33# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
34# define SCI_AND_SCIF
35#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
36# define SCIF0 0xA4400000
37# define SCIF2 0xA4410000
b7a76e4b
PM		 38# define SCSMR_Ir 0xA44A0000
39# define IRDA_SCIF SCIF0
1da177e4
LT		 40# define SCPCR 0xA4000116
41# define SCPDR 0xA4000136
42
43/* Set the clock source,
44 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
45 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
46 */
47# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
48# define SCIF_ONLY
49#elif defined(CONFIG_SH_RTS7751R2D)
1da177e4
LT		 50# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
51# define SCIF_ORER 0x0001 /* overrun error bit */
52# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
53# define SCIF_ONLY
05627486
PM		 54#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
55 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
56 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
57 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
58 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
59 defined(CONFIG_CPU_SUBTYPE_SH7751R)
1da177e4
LT		 60# define SCSPTR1 0xffe0001c /* 8 bit SCI */
61# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
62# define SCIF_ORER 0x0001 /* overrun error bit */
63# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
64 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
65 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
66# define SCI_AND_SCIF
67#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
b7a76e4b
PM		 68# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
69# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
70# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
1da177e4
LT		 71# define SCIF_ORER 0x0001 /* overrun error bit */
72# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
73# define SCIF_ONLY
2b1bd1ac 74#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
e108b2ca 75# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
9465a54f
NI		 76# define SCI_NPORTS 2
77# define SCIF_ORER 0x0001 /* overrun error bit */
78# define PACR 0xa4050100
79# define PBCR 0xa4050102
80# define SCSCR_INIT(port) 0x3B
e108b2ca 81# define SCIF_ONLY
e108b2ca
PM		 82#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
83# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
84# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
85# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
86# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
87# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
88# define SCIF_ONLY
41504c39
PM		 89#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
90# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
91# define SCSPTR0 SCPDR0
92# define SCIF_ORER 0x0001 /* overrun error bit */
93# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
94# define SCIF_ONLY
95# define PORT_PSCR 0xA405011E
1da177e4 96#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
1da177e4
LT		 97# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
98# define SCIF_ORER 0x0001 /* overrun error bit */
99# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
100# define SCIF_ONLY
101#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
1da177e4
LT		 102# define SCSPTR1 0xffe00020 /* 16 bit SCIF */
103# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
104# define SCIF_ORER 0x0001 /* overrun error bit */
105# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
106# define SCIF_ONLY
107#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
108# include <asm/hardware.h>
109# define SCIF_BASE_ADDR 0x01030000
110# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
111# define SCIF_PTR2_OFFS 0x0000020
112# define SCIF_LSR2_OFFS 0x0000024
1da177e4
LT		 113# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
114# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
115# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,
116 TE=1,RE=1,REIE=1 */
117# define SCIF_ONLY
118#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
1da177e4
LT		 119# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
120# define SCI_ONLY
121# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
122#elif defined(CONFIG_H8S2678)
1da177e4
LT		 123# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
124# define SCI_ONLY
125# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
b7a76e4b
PM		 126#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
127# define SCSPTR0 0xff923020 /* 16 bit SCIF */
128# define SCSPTR1 0xff924020 /* 16 bit SCIF */
129# define SCSPTR2 0xff925020 /* 16 bit SCIF */
130# define SCIF_ORER 0x0001 /* overrun error bit */
131# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
132# define SCIF_ONLY
133#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
134# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
135# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
e108b2ca 136# define SCIF_ORER 0x0001 /* Overrun error bit */
b7a76e4b
PM		 137# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
138# define SCIF_ONLY
32351a28
PM		 139#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
140# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
141# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
142# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
143# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
144# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
145# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
146# define SCIF_OPER 0x0001 /* Overrun error bit */
147# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
148# define SCIF_ONLY
9d4436a6
YS		 149#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
150# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
151# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
152# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
153# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
154# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
155# define SCIF_ONLY
156#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
157# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
158# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
159# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
160# define SCIF_ORER 0x0001 /* overrun error bit */
161# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
162# define SCIF_ONLY
2b1bd1ac
PM		 163#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
164# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
165# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
166# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
167# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
168# define SCIF_ORER 0x0001 /* Overrun error bit */
169# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
170# define SCIF_ONLY
1da177e4
LT		 171#else
172# error CPU subtype not defined
173#endif
174
175/* SCSCR */
176#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
177#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
178#define SCI_CTRL_FLAGS_TE 0x20 /* all */
179#define SCI_CTRL_FLAGS_RE 0x10 /* all */
05627486
PM		 180#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
181 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
182 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
183 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
184 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
185 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
186 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
2b1bd1ac
PM		 187 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
188 defined(CONFIG_CPU_SUBTYPE_SHX3)
1da177e4
LT		 189#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
190#else
191#define SCI_CTRL_FLAGS_REIE 0
192#endif
193/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
194/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
195/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
196/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
197
198/* SCxSR SCI */
199#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
200#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
201#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
202#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
203#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
204#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
205/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
206/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
207
208#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
209
210/* SCxSR SCIF */
211#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
212#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
213#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
214#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
215#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
216#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
217#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
218#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
219
d89ddd1c 220#if defined(CONFIG_CPU_SUBTYPE_SH7705)
1da177e4
LT		 221#define SCIF_ORER 0x0200
222#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
223#define SCIF_RFDC_MASK 0x007f
224#define SCIF_TXROOM_MAX 64
225#else
226#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
227#define SCIF_RFDC_MASK 0x001f
228#define SCIF_TXROOM_MAX 16
229#endif
230
231#if defined(SCI_ONLY)
232# define SCxSR_TEND(port) SCI_TEND
233# define SCxSR_ERRORS(port) SCI_ERRORS
234# define SCxSR_RDxF(port) SCI_RDRF
235# define SCxSR_TDxE(port) SCI_TDRE
236# define SCxSR_ORER(port) SCI_ORER
237# define SCxSR_FER(port) SCI_FER
238# define SCxSR_PER(port) SCI_PER
239# define SCxSR_BRK(port) 0x00
240# define SCxSR_RDxF_CLEAR(port) 0xbc
241# define SCxSR_ERROR_CLEAR(port) 0xc4
242# define SCxSR_TDxE_CLEAR(port) 0x78
b7a76e4b 243# define SCxSR_BREAK_CLEAR(port) 0xc4
1da177e4
LT		 244#elif defined(SCIF_ONLY)
245# define SCxSR_TEND(port) SCIF_TEND
246# define SCxSR_ERRORS(port) SCIF_ERRORS
247# define SCxSR_RDxF(port) SCIF_RDF
248# define SCxSR_TDxE(port) SCIF_TDFE
d89ddd1c 249#if defined(CONFIG_CPU_SUBTYPE_SH7705)
1da177e4
LT		 250# define SCxSR_ORER(port) SCIF_ORER
251#else
252# define SCxSR_ORER(port) 0x0000
253#endif
254# define SCxSR_FER(port) SCIF_FER
255# define SCxSR_PER(port) SCIF_PER
256# define SCxSR_BRK(port) SCIF_BRK
d89ddd1c 257#if defined(CONFIG_CPU_SUBTYPE_SH7705)
1da177e4
LT		 258# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
259# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
260# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
261# define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3)
262#else
d89ddd1c 263/* SH7705 can also use this, clearing is same between 7705 and 7709 */
1da177e4
LT		 264# define SCxSR_RDxF_CLEAR(port) 0x00fc
265# define SCxSR_ERROR_CLEAR(port) 0x0073
266# define SCxSR_TDxE_CLEAR(port) 0x00df
b7a76e4b 267# define SCxSR_BREAK_CLEAR(port) 0x00e3
1da177e4
LT		 268#endif
269#else
270# define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
271# define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
272# define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
273# define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
274# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
275# define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
276# define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
277# define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
278# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
279# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
280# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
281# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
282#endif
283
284/* SCFCR */
285#define SCFCR_RFRST 0x0002
286#define SCFCR_TFRST 0x0004
287#define SCFCR_TCRST 0x4000
288#define SCFCR_MCE 0x0008
289
290#define SCI_MAJOR 204
291#define SCI_MINOR_START 8
292
293/* Generic serial flags */
294#define SCI_RX_THROTTLE 0x0000001
295
296#define SCI_MAGIC 0xbabeface
297
298/*
299 * Events are used to schedule things to happen at timer-interrupt
300 * time, instead of at rs interrupt time.
301 */
302#define SCI_EVENT_WRITE_WAKEUP 0
303
1da177e4
LT		 304#define SCI_IN(size, offset) \
305 unsigned int addr = port->mapbase + (offset); \
b7a76e4b 306 if ((size) == 8) { \
1da177e4 307 return ctrl_inb(addr); \
b7a76e4b 308 } else { \
1da177e4
LT		 309 return ctrl_inw(addr); \
310 }
311#define SCI_OUT(size, offset, value) \
312 unsigned int addr = port->mapbase + (offset); \
b7a76e4b 313 if ((size) == 8) { \
1da177e4
LT		 314 ctrl_outb(value, addr); \
315 } else { \
316 ctrl_outw(value, addr); \
317 }
318
319#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
320 static inline unsigned int sci_##name##_in(struct uart_port *port) \
321 { \
b7a76e4b 322 if (port->type == PORT_SCI) { \
1da177e4
LT		 323 SCI_IN(sci_size, sci_offset) \
324 } else { \
b7a76e4b 325 SCI_IN(scif_size, scif_offset); \
1da177e4
LT		 326 } \
327 } \
328 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
329 { \
330 if (port->type == PORT_SCI) { \
331 SCI_OUT(sci_size, sci_offset, value) \
332 } else { \
333 SCI_OUT(scif_size, scif_offset, value); \
334 } \
335 }
336
337#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
338 static inline unsigned int sci_##name##_in(struct uart_port *port) \
339 { \
b7a76e4b 340 SCI_IN(scif_size, scif_offset); \
1da177e4
LT		 341 } \
342 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
343 { \
344 SCI_OUT(scif_size, scif_offset, value); \
345 }
346
347#define CPU_SCI_FNS(name, sci_offset, sci_size) \
348 static inline unsigned int sci_##name##_in(struct uart_port* port) \
349 { \
b7a76e4b 350 SCI_IN(sci_size, sci_offset); \
1da177e4
LT		 351 } \
352 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
353 { \
354 SCI_OUT(sci_size, sci_offset, value); \
355 }
356
357#ifdef CONFIG_CPU_SH3
9465a54f
NI		 358#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
359#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
360 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
361 h8_sci_offset, h8_sci_size) \
362 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
363#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
364 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
d89ddd1c 365#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
1da177e4
LT		 366#define SCIF_FNS(name, scif_offset, scif_size) \
367 CPU_SCIF_FNS(name, scif_offset, scif_size)
368#else
369#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
370 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
371 h8_sci_offset, h8_sci_size) \
372 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
373#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
374 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
375#endif
376#elif defined(__H8300H__) || defined(__H8300S__)
377#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
378 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
379 h8_sci_offset, h8_sci_size) \
380 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
381#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
382#else
383#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
384 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
385 h8_sci_offset, h8_sci_size) \
386 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
387#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
388 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
389#endif
390
d89ddd1c 391#if defined(CONFIG_CPU_SUBTYPE_SH7705)
9465a54f 392
1da177e4
LT		 393SCIF_FNS(SCSMR, 0x00, 16)
394SCIF_FNS(SCBRR, 0x04, 8)
395SCIF_FNS(SCSCR, 0x08, 16)
396SCIF_FNS(SCTDSR, 0x0c, 8)
397SCIF_FNS(SCFER, 0x10, 16)
398SCIF_FNS(SCxSR, 0x14, 16)
399SCIF_FNS(SCFCR, 0x18, 16)
400SCIF_FNS(SCFDR, 0x1c, 16)
401SCIF_FNS(SCxTDR, 0x20, 8)
402SCIF_FNS(SCxRDR, 0x24, 8)
403SCIF_FNS(SCLSR, 0x24, 16)
404#else
405/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
406/* name off sz off sz off sz off sz off sz*/
407SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
408SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
409SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
410SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
411SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
412SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
413SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
32351a28
PM		 414#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
415 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
416 defined(CONFIG_CPU_SUBTYPE_SH7785)
6fc21b82 417SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
b7a76e4b
PM		 418SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
419SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
420SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
421SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
422#else
1da177e4
LT		 423SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
424SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
425SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
426#endif
b7a76e4b 427#endif
1da177e4
LT		 428#define sci_in(port, reg) sci_##reg##_in(port)
429#define sci_out(port, reg, value) sci_##reg##_out(port, value)
430
431/* H8/300 series SCI pins assignment */
432#if defined(__H8300H__) || defined(__H8300S__)
433static const struct __attribute__((packed)) {
434 int port; /* GPIO port no */
435 unsigned short rx,tx; /* GPIO bit no */
436} h8300_sci_pins[] = {
437#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
438 { /* SCI0 */
439 .port = H8300_GPIO_P9,
440 .rx = H8300_GPIO_B2,
441 .tx = H8300_GPIO_B0,
442 },
443 { /* SCI1 */
444 .port = H8300_GPIO_P9,
445 .rx = H8300_GPIO_B3,
446 .tx = H8300_GPIO_B1,
447 },
448 { /* SCI2 */
449 .port = H8300_GPIO_PB,
450 .rx = H8300_GPIO_B7,
451 .tx = H8300_GPIO_B6,
452 }
453#elif defined(CONFIG_H8S2678)
454 { /* SCI0 */
455 .port = H8300_GPIO_P3,
456 .rx = H8300_GPIO_B2,
457 .tx = H8300_GPIO_B0,
458 },
459 { /* SCI1 */
460 .port = H8300_GPIO_P3,
461 .rx = H8300_GPIO_B3,
462 .tx = H8300_GPIO_B1,
463 },
464 { /* SCI2 */
465 .port = H8300_GPIO_P5,
466 .rx = H8300_GPIO_B1,
467 .tx = H8300_GPIO_B0,
468 }
469#endif
470};
471#endif
472
0fbde950
MD		 473#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
474 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
475 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
476 defined(CONFIG_CPU_SUBTYPE_SH7709)
1da177e4
LT		 477static inline int sci_rxd_in(struct uart_port *port)
478{
479 if (port->mapbase == 0xfffffe80)
480 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
481 if (port->mapbase == 0xa4000150)
482 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
483 if (port->mapbase == 0xa4000140)
484 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
485 return 1;
486}
487#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
488static inline int sci_rxd_in(struct uart_port *port)
489{
490 if (port->mapbase == SCIF0)
491 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
492 if (port->mapbase == SCIF2)
493 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
494 return 1;
495}
9465a54f 496#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
e108b2ca
PM		 497static inline int sci_rxd_in(struct uart_port *port)
498{
9465a54f
NI		 499 return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
500}
501static inline void set_sh771x_scif_pfc(struct uart_port *port)
502{
503 if (port->mapbase == 0xA4400000){
504 ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
505 ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
506 return;
507 }
508 if (port->mapbase == 0xA4410000){
509 ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
510 return;
511 }
e108b2ca 512}
9465a54f 513
05627486
PM		 514#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
515 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
516 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
517 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
518 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
519 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
1da177e4
LT		 520 defined(CONFIG_CPU_SUBTYPE_SH4_202)
521static inline int sci_rxd_in(struct uart_port *port)
522{
523#ifndef SCIF_ONLY
524 if (port->mapbase == 0xffe00000)
525 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
526#endif
527#ifndef SCI_ONLY
528 if (port->mapbase == 0xffe80000)
529 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
530#endif
531 return 1;
532}
533#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
534static inline int sci_rxd_in(struct uart_port *port)
535{
536 if (port->mapbase == 0xfe600000)
537 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
538 if (port->mapbase == 0xfe610000)
539 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
540 if (port->mapbase == 0xfe620000)
541 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
31388750 542 return 1;
1da177e4 543}
e108b2ca
PM		 544#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
545static inline int sci_rxd_in(struct uart_port *port)
546{
547 if (port->mapbase == 0xffe00000)
548 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
549 if (port->mapbase == 0xffe10000)
550 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
551 if (port->mapbase == 0xffe20000)
552 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
553 if (port->mapbase == 0xffe30000)
554 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
555 return 1;
556}
41504c39
PM		 557#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
558static inline int sci_rxd_in(struct uart_port *port)
559{
560 if (port->mapbase == 0xffe00000)
561 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
562 return 1;
563}
1da177e4
LT		 564#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
565static inline int sci_rxd_in(struct uart_port *port)
566{
567 if (port->mapbase == 0xffe00000)
568 return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */
569 else
570 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
571
572}
573#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
574static inline int sci_rxd_in(struct uart_port *port)
575{
576 return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
577}
578#elif defined(__H8300H__) || defined(__H8300S__)
579static inline int sci_rxd_in(struct uart_port *port)
580{
581 int ch = (port->mapbase - SMR0) >> 3;
582 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
583}
b7a76e4b
PM		 584#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
585static inline int sci_rxd_in(struct uart_port *port)
586{
587 if (port->mapbase == 0xff923000)
588 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
589 if (port->mapbase == 0xff924000)
590 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
591 if (port->mapbase == 0xff925000)
592 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
31388750 593 return 1;
b7a76e4b
PM		 594}
595#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
596static inline int sci_rxd_in(struct uart_port *port)
597{
598 if (port->mapbase == 0xffe00000)
599 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
600 if (port->mapbase == 0xffe10000)
601 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
31388750 602 return 1;
b7a76e4b 603}
32351a28
PM		 604#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
605static inline int sci_rxd_in(struct uart_port *port)
606{
607 if (port->mapbase == 0xffea0000)
608 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
609 if (port->mapbase == 0xffeb0000)
610 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
611 if (port->mapbase == 0xffec0000)
612 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
613 if (port->mapbase == 0xffed0000)
614 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
615 if (port->mapbase == 0xffee0000)
616 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
617 if (port->mapbase == 0xffef0000)
618 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
619 return 1;
620}
9d4436a6
YS		 621#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
622static inline int sci_rxd_in(struct uart_port *port)
623{
624 if (port->mapbase == 0xfffe8000)
625 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
626 if (port->mapbase == 0xfffe8800)
627 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
628 if (port->mapbase == 0xfffe9000)
629 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
630 if (port->mapbase == 0xfffe9800)
631 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
31388750 632 return 1;
9d4436a6
YS		 633}
634#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
635static inline int sci_rxd_in(struct uart_port *port)
636{
637 if (port->mapbase == 0xf8400000)
638 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
639 if (port->mapbase == 0xf8410000)
640 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
641 if (port->mapbase == 0xf8420000)
642 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
31388750 643 return 1;
9d4436a6 644}
2b1bd1ac
PM		 645#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
646static inline int sci_rxd_in(struct uart_port *port)
647{
648 if (port->mapbase == 0xffc30000)
649 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
650 if (port->mapbase == 0xffc40000)
651 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
652 if (port->mapbase == 0xffc50000)
653 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
654 if (port->mapbase == 0xffc60000)
655 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
1760b7d7 656 return 1;
2b1bd1ac 657}
1da177e4
LT		 658#endif
659
660/*
661 * Values for the BitRate Register (SCBRR)
662 *
663 * The values are actually divisors for a frequency which can
664 * be internal to the SH3 (14.7456MHz) or derived from an external
665 * clock source. This driver assumes the internal clock is used;
666 * to support using an external clock source, config options or
667 * possibly command-line options would need to be added.
668 *
669 * Also, to support speeds below 2400 (why?) the lower 2 bits of
670 * the SCSMR register would also need to be set to non-zero values.
671 *
672 * -- Greg Banks 27Feb2000
673 *
674 * Answer: The SCBRR register is only eight bits, and the value in
675 * it gets larger with lower baud rates. At around 2400 (depending on
676 * the peripherial module clock) you run out of bits. However the
677 * lower two bits of SCSMR allow the module clock to be divided down,
678 * scaling the value which is needed in SCBRR.
679 *
680 * -- Stuart Menefy - 23 May 2000
681 *
682 * I meant, why would anyone bother with bitrates below 2400.
683 *
684 * -- Greg Banks - 7Jul2000
685 *
686 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
687 * tape reader as a console!
688 *
689 * -- Mitch Davis - 15 Jul 2000
690 */
691
d89ddd1c 692#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
32351a28 693 defined(CONFIG_CPU_SUBTYPE_SH7785)
b7a76e4b 694#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
1da177e4 695#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
b7a76e4b
PM		 696#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
697#elif defined(__H8300H__) || defined(__H8300S__)
1da177e4 698#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
b7a76e4b
PM		 699#elif defined(CONFIG_SUPERH64)
700#define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
701#else /* Generic SH */
702#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
1da177e4 703#endif
Linux kernel - Deliverables
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