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[PATCH] SELinux: fix size-128 slab leak
[deliverable/linux.git] / drivers / serial / sunsu.c
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1da177e4
LT		 1/* $Id: su.c,v 1.55 2002/01/08 16:00:16 davem Exp $
2 * su.c: Small serial driver for keyboard/mouse interface on sparc32/PCI
3 *
4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1998-1999 Pete Zaitcev (zaitcev@yahoo.com)
6 *
7 * This is mainly a variation of 8250.c, credits go to authors mentioned
8 * therein. In fact this driver should be merged into the generic 8250.c
9 * infrastructure perhaps using a 8250_sparc.c module.
10 *
11 * Fixed to use tty_get_baud_rate().
12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
13 *
14 * Converted to new 2.5.x UART layer.
15 * David S. Miller (davem@redhat.com), 2002-Jul-29
16 */
17
18#include <linux/config.h>
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/sched.h>
22#include <linux/spinlock.h>
23#include <linux/errno.h>
24#include <linux/tty.h>
25#include <linux/tty_flip.h>
26#include <linux/major.h>
27#include <linux/string.h>
28#include <linux/ptrace.h>
29#include <linux/ioport.h>
30#include <linux/circ_buf.h>
31#include <linux/serial.h>
32#include <linux/sysrq.h>
33#include <linux/console.h>
34#ifdef CONFIG_SERIO
35#include <linux/serio.h>
36#endif
37#include <linux/serial_reg.h>
38#include <linux/init.h>
39#include <linux/delay.h>
40
41#include <asm/io.h>
42#include <asm/irq.h>
43#include <asm/oplib.h>
44#include <asm/ebus.h>
45#ifdef CONFIG_SPARC64
46#include <asm/isa.h>
47#endif
48
49#if defined(CONFIG_SERIAL_SUNSU_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
50#define SUPPORT_SYSRQ
51#endif
52
53#include <linux/serial_core.h>
54
55#include "suncore.h"
56
57/* We are on a NS PC87303 clocked with 24.0 MHz, which results
58 * in a UART clock of 1.8462 MHz.
59 */
60#define SU_BASE_BAUD (1846200 / 16)
61
62enum su_type { SU_PORT_NONE, SU_PORT_MS, SU_PORT_KBD, SU_PORT_PORT };
63static char *su_typev[] = { "su(???)", "su(mouse)", "su(kbd)", "su(serial)" };
64
65/*
66 * Here we define the default xmit fifo size used for each type of UART.
67 */
68static const struct serial_uart_config uart_config[PORT_MAX_8250+1] = {
69 { "unknown", 1, 0 },
70 { "8250", 1, 0 },
71 { "16450", 1, 0 },
72 { "16550", 1, 0 },
73 { "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO },
74 { "Cirrus", 1, 0 },
75 { "ST16650", 1, UART_CLEAR_FIFO | UART_STARTECH },
76 { "ST16650V2", 32, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
77 { "TI16750", 64, UART_CLEAR_FIFO | UART_USE_FIFO },
78 { "Startech", 1, 0 },
79 { "16C950/954", 128, UART_CLEAR_FIFO | UART_USE_FIFO },
80 { "ST16654", 64, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
81 { "XR16850", 128, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
82 { "RSA", 2048, UART_CLEAR_FIFO | UART_USE_FIFO }
83};
84
85struct uart_sunsu_port {
86 struct uart_port port;
87 unsigned char acr;
88 unsigned char ier;
89 unsigned short rev;
90 unsigned char lcr;
91 unsigned int lsr_break_flag;
92 unsigned int cflag;
93
94 /* Probing information. */
95 enum su_type su_type;
96 unsigned int type_probed; /* XXX Stupid */
97 int port_node;
98
99#ifdef CONFIG_SERIO
100 struct serio *serio;
101 int serio_open;
102#endif
103};
104
105#define _INLINE_
106
107static _INLINE_ unsigned int serial_in(struct uart_sunsu_port *up, int offset)
108{
109 offset <<= up->port.regshift;
110
111 switch (up->port.iotype) {
112 case SERIAL_IO_HUB6:
113 outb(up->port.hub6 - 1 + offset, up->port.iobase);
114 return inb(up->port.iobase + 1);
115
116 case SERIAL_IO_MEM:
117 return readb(up->port.membase + offset);
118
119 default:
120 return inb(up->port.iobase + offset);
121 }
122}
123
124static _INLINE_ void
125serial_out(struct uart_sunsu_port *up, int offset, int value)
126{
127#ifndef CONFIG_SPARC64
128 /*
129 * MrCoffee has weird schematics: IRQ4 & P10(?) pins of SuperIO are
130 * connected with a gate then go to SlavIO. When IRQ4 goes tristated
131 * gate outputs a logical one. Since we use level triggered interrupts
132 * we have lockup and watchdog reset. We cannot mask IRQ because
133 * keyboard shares IRQ with us (Word has it as Bob Smelik's design).
134 * This problem is similar to what Alpha people suffer, see serial.c.
135 */
136 if (offset == UART_MCR)
137 value |= UART_MCR_OUT2;
138#endif
139 offset <<= up->port.regshift;
140
141 switch (up->port.iotype) {
142 case SERIAL_IO_HUB6:
143 outb(up->port.hub6 - 1 + offset, up->port.iobase);
144 outb(value, up->port.iobase + 1);
145 break;
146
147 case SERIAL_IO_MEM:
148 writeb(value, up->port.membase + offset);
149 break;
150
151 default:
152 outb(value, up->port.iobase + offset);
153 }
154}
155
156/*
157 * We used to support using pause I/O for certain machines. We
158 * haven't supported this for a while, but just in case it's badly
159 * needed for certain old 386 machines, I've left these #define's
160 * in....
161 */
162#define serial_inp(up, offset) serial_in(up, offset)
163#define serial_outp(up, offset, value) serial_out(up, offset, value)
164
165
166/*
167 * For the 16C950
168 */
169static void serial_icr_write(struct uart_sunsu_port *up, int offset, int value)
170{
171 serial_out(up, UART_SCR, offset);
172 serial_out(up, UART_ICR, value);
173}
174
175#if 0 /* Unused currently */
176static unsigned int serial_icr_read(struct uart_sunsu_port *up, int offset)
177{
178 unsigned int value;
179
180 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
181 serial_out(up, UART_SCR, offset);
182 value = serial_in(up, UART_ICR);
183 serial_icr_write(up, UART_ACR, up->acr);
184
185 return value;
186}
187#endif
188
189#ifdef CONFIG_SERIAL_8250_RSA
190/*
191 * Attempts to turn on the RSA FIFO. Returns zero on failure.
192 * We set the port uart clock rate if we succeed.
193 */
194static int __enable_rsa(struct uart_sunsu_port *up)
195{
196 unsigned char mode;
197 int result;
198
199 mode = serial_inp(up, UART_RSA_MSR);
200 result = mode & UART_RSA_MSR_FIFO;
201
202 if (!result) {
203 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
204 mode = serial_inp(up, UART_RSA_MSR);
205 result = mode & UART_RSA_MSR_FIFO;
206 }
207
208 if (result)
209 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
210
211 return result;
212}
213
214static void enable_rsa(struct uart_sunsu_port *up)
215{
216 if (up->port.type == PORT_RSA) {
217 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
218 spin_lock_irq(&up->port.lock);
219 __enable_rsa(up);
220 spin_unlock_irq(&up->port.lock);
221 }
222 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
223 serial_outp(up, UART_RSA_FRR, 0);
224 }
225}
226
227/*
228 * Attempts to turn off the RSA FIFO. Returns zero on failure.
229 * It is unknown why interrupts were disabled in here. However,
230 * the caller is expected to preserve this behaviour by grabbing
231 * the spinlock before calling this function.
232 */
233static void disable_rsa(struct uart_sunsu_port *up)
234{
235 unsigned char mode;
236 int result;
237
238 if (up->port.type == PORT_RSA &&
239 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
240 spin_lock_irq(&up->port.lock);
241
242 mode = serial_inp(up, UART_RSA_MSR);
243 result = !(mode & UART_RSA_MSR_FIFO);
244
245 if (!result) {
246 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
247 mode = serial_inp(up, UART_RSA_MSR);
248 result = !(mode & UART_RSA_MSR_FIFO);
249 }
250
251 if (result)
252 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
253 spin_unlock_irq(&up->port.lock);
254 }
255}
256#endif /* CONFIG_SERIAL_8250_RSA */
257
b129a8cc
RK		 258static inline void __stop_tx(struct uart_sunsu_port *p)
259{
260 if (p->ier & UART_IER_THRI) {
261 p->ier &= ~UART_IER_THRI;
262 serial_out(p, UART_IER, p->ier);
263 }
264}
265
266static void sunsu_stop_tx(struct uart_port *port)
1da177e4
LT		 267{
268 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
269
b129a8cc
RK		 270 __stop_tx(up);
271
3d9c9948
AV		 272 /*
273 * We really want to stop the transmitter from sending.
274 */
275 if (up->port.type == PORT_16C950) {
1da177e4
LT		 276 up->acr |= UART_ACR_TXDIS;
277 serial_icr_write(up, UART_ACR, up->acr);
278 }
279}
280
b129a8cc 281static void sunsu_start_tx(struct uart_port *port)
1da177e4
LT		 282{
283 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
284
285 if (!(up->ier & UART_IER_THRI)) {
286 up->ier |= UART_IER_THRI;
287 serial_out(up, UART_IER, up->ier);
288 }
3d9c9948 289
1da177e4 290 /*
3d9c9948 291 * Re-enable the transmitter if we disabled it.
1da177e4 292 */
3d9c9948 293 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 294 up->acr &= ~UART_ACR_TXDIS;
295 serial_icr_write(up, UART_ACR, up->acr);
296 }
297}
298
299static void sunsu_stop_rx(struct uart_port *port)
300{
301 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
302 unsigned long flags;
303
304 spin_lock_irqsave(&up->port.lock, flags);
305 up->ier &= ~UART_IER_RLSI;
306 up->port.read_status_mask &= ~UART_LSR_DR;
307 serial_out(up, UART_IER, up->ier);
308 spin_unlock_irqrestore(&up->port.lock, flags);
309}
310
311static void sunsu_enable_ms(struct uart_port *port)
312{
313 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
314 unsigned long flags;
315
316 spin_lock_irqsave(&up->port.lock, flags);
317 up->ier |= UART_IER_MSI;
318 serial_out(up, UART_IER, up->ier);
319 spin_unlock_irqrestore(&up->port.lock, flags);
320}
321
322static _INLINE_ struct tty_struct *
323receive_chars(struct uart_sunsu_port *up, unsigned char *status, struct pt_regs *regs)
324{
325 struct tty_struct *tty = up->port.info->tty;
33f0f88f 326 unsigned char ch, flag;
1da177e4
LT		 327 int max_count = 256;
328 int saw_console_brk = 0;
329
330 do {
1da177e4 331 ch = serial_inp(up, UART_RX);
33f0f88f 332 flag = TTY_NORMAL;
1da177e4
LT		 333 up->port.icount.rx++;
334
335 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
336 UART_LSR_FE | UART_LSR_OE))) {
337 /*
338 * For statistics only
339 */
340 if (*status & UART_LSR_BI) {
341 *status &= ~(UART_LSR_FE | UART_LSR_PE);
342 up->port.icount.brk++;
343 if (up->port.cons != NULL &&
344 up->port.line == up->port.cons->index)
345 saw_console_brk = 1;
346 /*
347 * We do the SysRQ and SAK checking
348 * here because otherwise the break
349 * may get masked by ignore_status_mask
350 * or read_status_mask.
351 */
352 if (uart_handle_break(&up->port))
353 goto ignore_char;
354 } else if (*status & UART_LSR_PE)
355 up->port.icount.parity++;
356 else if (*status & UART_LSR_FE)
357 up->port.icount.frame++;
358 if (*status & UART_LSR_OE)
359 up->port.icount.overrun++;
360
361 /*
362 * Mask off conditions which should be ingored.
363 */
364 *status &= up->port.read_status_mask;
365
366 if (up->port.cons != NULL &&
367 up->port.line == up->port.cons->index) {
368 /* Recover the break flag from console xmit */
369 *status |= up->lsr_break_flag;
370 up->lsr_break_flag = 0;
371 }
372
373 if (*status & UART_LSR_BI) {
33f0f88f 374 flag = TTY_BREAK;
1da177e4 375 } else if (*status & UART_LSR_PE)
33f0f88f 376 flag = TTY_PARITY;
1da177e4 377 else if (*status & UART_LSR_FE)
33f0f88f 378 flag = TTY_FRAME;
1da177e4
LT		 379 }
380 if (uart_handle_sysrq_char(&up->port, ch, regs))
381 goto ignore_char;
33f0f88f
AC		 382 if ((*status & up->port.ignore_status_mask) == 0)
383 tty_insert_flip_char(tty, ch, flag);
384 if (*status & UART_LSR_OE)
1da177e4
LT		 385 /*
386 * Overrun is special, since it's reported
387 * immediately, and doesn't affect the current
388 * character.
389 */
33f0f88f 390 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1da177e4
LT		 391 ignore_char:
392 *status = serial_inp(up, UART_LSR);
393 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
394
395 if (saw_console_brk)
396 sun_do_break();
397
398 return tty;
399}
400
401static _INLINE_ void transmit_chars(struct uart_sunsu_port *up)
402{
403 struct circ_buf *xmit = &up->port.info->xmit;
404 int count;
405
406 if (up->port.x_char) {
407 serial_outp(up, UART_TX, up->port.x_char);
408 up->port.icount.tx++;
409 up->port.x_char = 0;
410 return;
411 }
b129a8cc
RK		 412 if (uart_tx_stopped(&up->port)) {
413 sunsu_stop_tx(&up->port);
414 return;
415 }
416 if (uart_circ_empty(xmit)) {
417 __stop_tx(up);
1da177e4
LT		 418 return;
419 }
420
421 count = up->port.fifosize;
422 do {
423 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
424 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
425 up->port.icount.tx++;
426 if (uart_circ_empty(xmit))
427 break;
428 } while (--count > 0);
429
430 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
431 uart_write_wakeup(&up->port);
432
433 if (uart_circ_empty(xmit))
b129a8cc 434 __stop_tx(up);
1da177e4
LT		 435}
436
437static _INLINE_ void check_modem_status(struct uart_sunsu_port *up)
438{
439 int status;
440
441 status = serial_in(up, UART_MSR);
442
443 if ((status & UART_MSR_ANY_DELTA) == 0)
444 return;
445
446 if (status & UART_MSR_TERI)
447 up->port.icount.rng++;
448 if (status & UART_MSR_DDSR)
449 up->port.icount.dsr++;
450 if (status & UART_MSR_DDCD)
451 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
452 if (status & UART_MSR_DCTS)
453 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
454
455 wake_up_interruptible(&up->port.info->delta_msr_wait);
456}
457
458static irqreturn_t sunsu_serial_interrupt(int irq, void *dev_id, struct pt_regs *regs)
459{
460 struct uart_sunsu_port *up = dev_id;
461 unsigned long flags;
462 unsigned char status;
463
464 spin_lock_irqsave(&up->port.lock, flags);
465
466 do {
467 struct tty_struct *tty;
468
469 status = serial_inp(up, UART_LSR);
470 tty = NULL;
471 if (status & UART_LSR_DR)
472 tty = receive_chars(up, &status, regs);
473 check_modem_status(up);
474 if (status & UART_LSR_THRE)
475 transmit_chars(up);
476
477 spin_unlock_irqrestore(&up->port.lock, flags);
478
479 if (tty)
480 tty_flip_buffer_push(tty);
481
482 spin_lock_irqsave(&up->port.lock, flags);
483
484 } while (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT));
485
486 spin_unlock_irqrestore(&up->port.lock, flags);
487
488 return IRQ_HANDLED;
489}
490
491/* Separate interrupt handling path for keyboard/mouse ports. */
492
493static void
494sunsu_change_speed(struct uart_port *port, unsigned int cflag,
495 unsigned int iflag, unsigned int quot);
496
497static void sunsu_change_mouse_baud(struct uart_sunsu_port *up)
498{
499 unsigned int cur_cflag = up->cflag;
500 int quot, new_baud;
501
502 up->cflag &= ~CBAUD;
503 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
504
505 quot = up->port.uartclk / (16 * new_baud);
506
1da177e4 507 sunsu_change_speed(&up->port, up->cflag, 0, quot);
1da177e4
LT		 508}
509
510static void receive_kbd_ms_chars(struct uart_sunsu_port *up, struct pt_regs *regs, int is_break)
511{
512 do {
513 unsigned char ch = serial_inp(up, UART_RX);
514
515 /* Stop-A is handled by drivers/char/keyboard.c now. */
516 if (up->su_type == SU_PORT_KBD) {
517#ifdef CONFIG_SERIO
518 serio_interrupt(up->serio, ch, 0, regs);
519#endif
520 } else if (up->su_type == SU_PORT_MS) {
521 int ret = suncore_mouse_baud_detection(ch, is_break);
522
523 switch (ret) {
524 case 2:
525 sunsu_change_mouse_baud(up);
526 /* fallthru */
527 case 1:
528 break;
529
530 case 0:
531#ifdef CONFIG_SERIO
532 serio_interrupt(up->serio, ch, 0, regs);
533#endif
534 break;
535 };
536 }
537 } while (serial_in(up, UART_LSR) & UART_LSR_DR);
538}
539
540static irqreturn_t sunsu_kbd_ms_interrupt(int irq, void *dev_id, struct pt_regs *regs)
541{
542 struct uart_sunsu_port *up = dev_id;
543
544 if (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT)) {
545 unsigned char status = serial_inp(up, UART_LSR);
546
547 if ((status & UART_LSR_DR) || (status & UART_LSR_BI))
548 receive_kbd_ms_chars(up, regs,
549 (status & UART_LSR_BI) != 0);
550 }
551
552 return IRQ_HANDLED;
553}
554
555static unsigned int sunsu_tx_empty(struct uart_port *port)
556{
557 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
558 unsigned long flags;
559 unsigned int ret;
560
561 spin_lock_irqsave(&up->port.lock, flags);
562 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
563 spin_unlock_irqrestore(&up->port.lock, flags);
564
565 return ret;
566}
567
568static unsigned int sunsu_get_mctrl(struct uart_port *port)
569{
570 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
1da177e4
LT		 571 unsigned char status;
572 unsigned int ret;
573
1da177e4 574 status = serial_in(up, UART_MSR);
1da177e4
LT		 575
576 ret = 0;
577 if (status & UART_MSR_DCD)
578 ret |= TIOCM_CAR;
579 if (status & UART_MSR_RI)
580 ret |= TIOCM_RNG;
581 if (status & UART_MSR_DSR)
582 ret |= TIOCM_DSR;
583 if (status & UART_MSR_CTS)
584 ret |= TIOCM_CTS;
585 return ret;
586}
587
588static void sunsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
589{
590 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
591 unsigned char mcr = 0;
592
593 if (mctrl & TIOCM_RTS)
594 mcr |= UART_MCR_RTS;
595 if (mctrl & TIOCM_DTR)
596 mcr |= UART_MCR_DTR;
597 if (mctrl & TIOCM_OUT1)
598 mcr |= UART_MCR_OUT1;
599 if (mctrl & TIOCM_OUT2)
600 mcr |= UART_MCR_OUT2;
601 if (mctrl & TIOCM_LOOP)
602 mcr |= UART_MCR_LOOP;
603
604 serial_out(up, UART_MCR, mcr);
605}
606
607static void sunsu_break_ctl(struct uart_port *port, int break_state)
608{
609 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
610 unsigned long flags;
611
612 spin_lock_irqsave(&up->port.lock, flags);
613 if (break_state == -1)
614 up->lcr |= UART_LCR_SBC;
615 else
616 up->lcr &= ~UART_LCR_SBC;
617 serial_out(up, UART_LCR, up->lcr);
618 spin_unlock_irqrestore(&up->port.lock, flags);
619}
620
621static int sunsu_startup(struct uart_port *port)
622{
623 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
624 unsigned long flags;
625 int retval;
626
627 if (up->port.type == PORT_16C950) {
628 /* Wake up and initialize UART */
629 up->acr = 0;
630 serial_outp(up, UART_LCR, 0xBF);
631 serial_outp(up, UART_EFR, UART_EFR_ECB);
632 serial_outp(up, UART_IER, 0);
633 serial_outp(up, UART_LCR, 0);
634 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
635 serial_outp(up, UART_LCR, 0xBF);
636 serial_outp(up, UART_EFR, UART_EFR_ECB);
637 serial_outp(up, UART_LCR, 0);
638 }
639
640#ifdef CONFIG_SERIAL_8250_RSA
641 /*
642 * If this is an RSA port, see if we can kick it up to the
643 * higher speed clock.
644 */
645 enable_rsa(up);
646#endif
647
648 /*
649 * Clear the FIFO buffers and disable them.
650 * (they will be reeanbled in set_termios())
651 */
652 if (uart_config[up->port.type].flags & UART_CLEAR_FIFO) {
653 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
654 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
655 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
656 serial_outp(up, UART_FCR, 0);
657 }
658
659 /*
660 * Clear the interrupt registers.
661 */
662 (void) serial_inp(up, UART_LSR);
663 (void) serial_inp(up, UART_RX);
664 (void) serial_inp(up, UART_IIR);
665 (void) serial_inp(up, UART_MSR);
666
667 /*
668 * At this point, there's no way the LSR could still be 0xff;
669 * if it is, then bail out, because there's likely no UART
670 * here.
671 */
ce8337cb 672 if (!(up->port.flags & UPF_BUGGY_UART) &&
1da177e4
LT		 673 (serial_inp(up, UART_LSR) == 0xff)) {
674 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
675 return -ENODEV;
676 }
677
678 if (up->su_type != SU_PORT_PORT) {
679 retval = request_irq(up->port.irq, sunsu_kbd_ms_interrupt,
680 SA_SHIRQ, su_typev[up->su_type], up);
681 } else {
682 retval = request_irq(up->port.irq, sunsu_serial_interrupt,
683 SA_SHIRQ, su_typev[up->su_type], up);
684 }
685 if (retval) {
686 printk("su: Cannot register IRQ %d\n", up->port.irq);
687 return retval;
688 }
689
690 /*
691 * Now, initialize the UART
692 */
693 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
694
695 spin_lock_irqsave(&up->port.lock, flags);
696
697 up->port.mctrl |= TIOCM_OUT2;
698
699 sunsu_set_mctrl(&up->port, up->port.mctrl);
700 spin_unlock_irqrestore(&up->port.lock, flags);
701
702 /*
703 * Finally, enable interrupts. Note: Modem status interrupts
704 * are set via set_termios(), which will be occurring imminently
705 * anyway, so we don't enable them here.
706 */
707 up->ier = UART_IER_RLSI | UART_IER_RDI;
708 serial_outp(up, UART_IER, up->ier);
709
ce8337cb 710 if (up->port.flags & UPF_FOURPORT) {
1da177e4
LT		 711 unsigned int icp;
712 /*
713 * Enable interrupts on the AST Fourport board
714 */
715 icp = (up->port.iobase & 0xfe0) | 0x01f;
716 outb_p(0x80, icp);
717 (void) inb_p(icp);
718 }
719
720 /*
721 * And clear the interrupt registers again for luck.
722 */
723 (void) serial_inp(up, UART_LSR);
724 (void) serial_inp(up, UART_RX);
725 (void) serial_inp(up, UART_IIR);
726 (void) serial_inp(up, UART_MSR);
727
728 return 0;
729}
730
731static void sunsu_shutdown(struct uart_port *port)
732{
733 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
734 unsigned long flags;
735
736 /*
737 * Disable interrupts from this port
738 */
739 up->ier = 0;
740 serial_outp(up, UART_IER, 0);
741
742 spin_lock_irqsave(&up->port.lock, flags);
ce8337cb 743 if (up->port.flags & UPF_FOURPORT) {
1da177e4
LT		 744 /* reset interrupts on the AST Fourport board */
745 inb((up->port.iobase & 0xfe0) | 0x1f);
746 up->port.mctrl |= TIOCM_OUT1;
747 } else
748 up->port.mctrl &= ~TIOCM_OUT2;
749
750 sunsu_set_mctrl(&up->port, up->port.mctrl);
751 spin_unlock_irqrestore(&up->port.lock, flags);
752
753 /*
754 * Disable break condition and FIFOs
755 */
756 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
757 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
758 UART_FCR_CLEAR_RCVR |
759 UART_FCR_CLEAR_XMIT);
760 serial_outp(up, UART_FCR, 0);
761
762#ifdef CONFIG_SERIAL_8250_RSA
763 /*
764 * Reset the RSA board back to 115kbps compat mode.
765 */
766 disable_rsa(up);
767#endif
768
769 /*
770 * Read data port to reset things.
771 */
772 (void) serial_in(up, UART_RX);
773
774 free_irq(up->port.irq, up);
775}
776
777static void
778sunsu_change_speed(struct uart_port *port, unsigned int cflag,
779 unsigned int iflag, unsigned int quot)
780{
781 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
782 unsigned char cval, fcr = 0;
783 unsigned long flags;
784
785 switch (cflag & CSIZE) {
786 case CS5:
787 cval = 0x00;
788 break;
789 case CS6:
790 cval = 0x01;
791 break;
792 case CS7:
793 cval = 0x02;
794 break;
795 default:
796 case CS8:
797 cval = 0x03;
798 break;
799 }
800
801 if (cflag & CSTOPB)
802 cval |= 0x04;
803 if (cflag & PARENB)
804 cval |= UART_LCR_PARITY;
805 if (!(cflag & PARODD))
806 cval |= UART_LCR_EPAR;
807#ifdef CMSPAR
808 if (cflag & CMSPAR)
809 cval |= UART_LCR_SPAR;
810#endif
811
812 /*
813 * Work around a bug in the Oxford Semiconductor 952 rev B
814 * chip which causes it to seriously miscalculate baud rates
815 * when DLL is 0.
816 */
817 if ((quot & 0xff) == 0 && up->port.type == PORT_16C950 &&
818 up->rev == 0x5201)
819 quot ++;
820
821 if (uart_config[up->port.type].flags & UART_USE_FIFO) {
822 if ((up->port.uartclk / quot) < (2400 * 16))
823 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
824#ifdef CONFIG_SERIAL_8250_RSA
825 else if (up->port.type == PORT_RSA)
826 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_14;
827#endif
828 else
829 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8;
830 }
831 if (up->port.type == PORT_16750)
832 fcr |= UART_FCR7_64BYTE;
833
834 /*
835 * Ok, we're now changing the port state. Do it with
836 * interrupts disabled.
837 */
838 spin_lock_irqsave(&up->port.lock, flags);
839
840 /*
841 * Update the per-port timeout.
842 */
843 uart_update_timeout(port, cflag, (port->uartclk / (16 * quot)));
844
845 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
846 if (iflag & INPCK)
847 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
848 if (iflag & (BRKINT | PARMRK))
849 up->port.read_status_mask |= UART_LSR_BI;
850
851 /*
852 * Characteres to ignore
853 */
854 up->port.ignore_status_mask = 0;
855 if (iflag & IGNPAR)
856 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
857 if (iflag & IGNBRK) {
858 up->port.ignore_status_mask |= UART_LSR_BI;
859 /*
860 * If we're ignoring parity and break indicators,
861 * ignore overruns too (for real raw support).
862 */
863 if (iflag & IGNPAR)
864 up->port.ignore_status_mask |= UART_LSR_OE;
865 }
866
867 /*
868 * ignore all characters if CREAD is not set
869 */
870 if ((cflag & CREAD) == 0)
871 up->port.ignore_status_mask |= UART_LSR_DR;
872
873 /*
874 * CTS flow control flag and modem status interrupts
875 */
876 up->ier &= ~UART_IER_MSI;
877 if (UART_ENABLE_MS(&up->port, cflag))
878 up->ier |= UART_IER_MSI;
879
880 serial_out(up, UART_IER, up->ier);
881
882 if (uart_config[up->port.type].flags & UART_STARTECH) {
883 serial_outp(up, UART_LCR, 0xBF);
884 serial_outp(up, UART_EFR, cflag & CRTSCTS ? UART_EFR_CTS :0);
885 }
886 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
887 serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */
888 serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */
889 if (up->port.type == PORT_16750)
890 serial_outp(up, UART_FCR, fcr); /* set fcr */
891 serial_outp(up, UART_LCR, cval); /* reset DLAB */
892 up->lcr = cval; /* Save LCR */
893 if (up->port.type != PORT_16750) {
894 if (fcr & UART_FCR_ENABLE_FIFO) {
895 /* emulated UARTs (Lucent Venus 167x) need two steps */
896 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
897 }
898 serial_outp(up, UART_FCR, fcr); /* set fcr */
899 }
900
901 up->cflag = cflag;
902
903 spin_unlock_irqrestore(&up->port.lock, flags);
904}
905
906static void
907sunsu_set_termios(struct uart_port *port, struct termios *termios,
908 struct termios *old)
909{
910 unsigned int baud, quot;
911
912 /*
913 * Ask the core to calculate the divisor for us.
914 */
915 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
916 quot = uart_get_divisor(port, baud);
917
918 sunsu_change_speed(port, termios->c_cflag, termios->c_iflag, quot);
919}
920
921static void sunsu_release_port(struct uart_port *port)
922{
923}
924
925static int sunsu_request_port(struct uart_port *port)
926{
927 return 0;
928}
929
930static void sunsu_config_port(struct uart_port *port, int flags)
931{
932 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
933
934 if (flags & UART_CONFIG_TYPE) {
935 /*
936 * We are supposed to call autoconfig here, but this requires
937 * splitting all the OBP probing crap from the UART probing.
938 * We'll do it when we kill sunsu.c altogether.
939 */
940 port->type = up->type_probed; /* XXX */
941 }
942}
943
944static int
945sunsu_verify_port(struct uart_port *port, struct serial_struct *ser)
946{
947 return -EINVAL;
948}
949
950static const char *
951sunsu_type(struct uart_port *port)
952{
953 int type = port->type;
954
955 if (type >= ARRAY_SIZE(uart_config))
956 type = 0;
957 return uart_config[type].name;
958}
959
960static struct uart_ops sunsu_pops = {
961 .tx_empty = sunsu_tx_empty,
962 .set_mctrl = sunsu_set_mctrl,
963 .get_mctrl = sunsu_get_mctrl,
964 .stop_tx = sunsu_stop_tx,
965 .start_tx = sunsu_start_tx,
966 .stop_rx = sunsu_stop_rx,
967 .enable_ms = sunsu_enable_ms,
968 .break_ctl = sunsu_break_ctl,
969 .startup = sunsu_startup,
970 .shutdown = sunsu_shutdown,
971 .set_termios = sunsu_set_termios,
972 .type = sunsu_type,
973 .release_port = sunsu_release_port,
974 .request_port = sunsu_request_port,
975 .config_port = sunsu_config_port,
976 .verify_port = sunsu_verify_port,
977};
978
979#define UART_NR 4
980
981static struct uart_sunsu_port sunsu_ports[UART_NR];
982
983#ifdef CONFIG_SERIO
984
985static DEFINE_SPINLOCK(sunsu_serio_lock);
986
987static int sunsu_serio_write(struct serio *serio, unsigned char ch)
988{
989 struct uart_sunsu_port *up = serio->port_data;
990 unsigned long flags;
991 int lsr;
992
993 spin_lock_irqsave(&sunsu_serio_lock, flags);
994
995 do {
996 lsr = serial_in(up, UART_LSR);
997 } while (!(lsr & UART_LSR_THRE));
998
999 /* Send the character out. */
1000 serial_out(up, UART_TX, ch);
1001
1002 spin_unlock_irqrestore(&sunsu_serio_lock, flags);
1003
1004 return 0;
1005}
1006
1007static int sunsu_serio_open(struct serio *serio)
1008{
1009 struct uart_sunsu_port *up = serio->port_data;
1010 unsigned long flags;
1011 int ret;
1012
1013 spin_lock_irqsave(&sunsu_serio_lock, flags);
1014 if (!up->serio_open) {
1015 up->serio_open = 1;
1016 ret = 0;
1017 } else
1018 ret = -EBUSY;
1019 spin_unlock_irqrestore(&sunsu_serio_lock, flags);
1020
1021 return ret;
1022}
1023
1024static void sunsu_serio_close(struct serio *serio)
1025{
1026 struct uart_sunsu_port *up = serio->port_data;
1027 unsigned long flags;
1028
1029 spin_lock_irqsave(&sunsu_serio_lock, flags);
1030 up->serio_open = 0;
1031 spin_unlock_irqrestore(&sunsu_serio_lock, flags);
1032}
1033
1034#endif /* CONFIG_SERIO */
1035
1036static void sunsu_autoconfig(struct uart_sunsu_port *up)
1037{
1038 unsigned char status1, status2, scratch, scratch2, scratch3;
1039 unsigned char save_lcr, save_mcr;
1040 struct linux_ebus_device *dev = NULL;
1041 struct linux_ebus *ebus;
1042#ifdef CONFIG_SPARC64
1043 struct sparc_isa_bridge *isa_br;
1044 struct sparc_isa_device *isa_dev;
1045#endif
1046#ifndef CONFIG_SPARC64
1047 struct linux_prom_registers reg0;
1048#endif
1049 unsigned long flags;
1050
1051 if (!up->port_node || !up->su_type)
1052 return;
1053
1054 up->type_probed = PORT_UNKNOWN;
1055 up->port.iotype = SERIAL_IO_MEM;
1056
1057 /*
1058 * First we look for Ebus-bases su's
1059 */
1060 for_each_ebus(ebus) {
1061 for_each_ebusdev(dev, ebus) {
1062 if (dev->prom_node == up->port_node) {
1063 /*
1064 * The EBus is broken on sparc; it delivers
1065 * virtual addresses in resources. Oh well...
1066 * This is correct on sparc64, though.
1067 */
1068 up->port.membase = (char *) dev->resource[0].start;
1069 /*
1070 * This is correct on both architectures.
1071 */
1072 up->port.mapbase = dev->resource[0].start;
1073 up->port.irq = dev->irqs[0];
1074 goto ebus_done;
1075 }
1076 }
1077 }
1078
1079#ifdef CONFIG_SPARC64
1080 for_each_isa(isa_br) {
1081 for_each_isadev(isa_dev, isa_br) {
1082 if (isa_dev->prom_node == up->port_node) {
1083 /* Same on sparc64. Cool architecure... */
1084 up->port.membase = (char *) isa_dev->resource.start;
1085 up->port.mapbase = isa_dev->resource.start;
1086 up->port.irq = isa_dev->irq;
1087 goto ebus_done;
1088 }
1089 }
1090 }
1091#endif
1092
1093#ifdef CONFIG_SPARC64
1094 /*
1095 * Not on Ebus, bailing.
1096 */
1097 return;
1098#else
1099 /*
1100 * Not on Ebus, must be OBIO.
1101 */
1102 if (prom_getproperty(up->port_node, "reg",
1103 (char *)&reg0, sizeof(reg0)) == -1) {
1104 prom_printf("sunsu: no \"reg\" property\n");
1105 return;
1106 }
1107 prom_apply_obio_ranges(&reg0, 1);
1108 if (reg0.which_io != 0) { /* Just in case... */
1109 prom_printf("sunsu: bus number nonzero: 0x%x:%x\n",
1110 reg0.which_io, reg0.phys_addr);
1111 return;
1112 }
1113 up->port.mapbase = reg0.phys_addr;
1114 if ((up->port.membase = ioremap(reg0.phys_addr, reg0.reg_size)) == 0) {
1115 prom_printf("sunsu: Cannot map registers.\n");
1116 return;
1117 }
1118
1119 /*
1120 * 0x20 is sun4m thing, Dave Redman heritage.
1121 * See arch/sparc/kernel/irq.c.
1122 */
1123#define IRQ_4M(n) ((n)|0x20)
1124
1125 /*
1126 * There is no intr property on MrCoffee, so hardwire it.
1127 */
1128 up->port.irq = IRQ_4M(13);
1129#endif
1130
1131ebus_done:
1132
1133 spin_lock_irqsave(&up->port.lock, flags);
1134
ce8337cb 1135 if (!(up->port.flags & UPF_BUGGY_UART)) {
1da177e4
LT		 1136 /*
1137 * Do a simple existence test first; if we fail this, there's
1138 * no point trying anything else.
1139 *
1140 * 0x80 is used as a nonsense port to prevent against false
1141 * positives due to ISA bus float. The assumption is that
1142 * 0x80 is a non-existent port; which should be safe since
1143 * include/asm/io.h also makes this assumption.
1144 */
1145 scratch = serial_inp(up, UART_IER);
1146 serial_outp(up, UART_IER, 0);
1147#ifdef __i386__
1148 outb(0xff, 0x080);
1149#endif
1150 scratch2 = serial_inp(up, UART_IER);
1151 serial_outp(up, UART_IER, 0x0f);
1152#ifdef __i386__
1153 outb(0, 0x080);
1154#endif
1155 scratch3 = serial_inp(up, UART_IER);
1156 serial_outp(up, UART_IER, scratch);
1157 if (scratch2 != 0 || scratch3 != 0x0F)
1158 goto out; /* We failed; there's nothing here */
1159 }
1160
1161 save_mcr = serial_in(up, UART_MCR);
1162 save_lcr = serial_in(up, UART_LCR);
1163
1164 /*
1165 * Check to see if a UART is really there. Certain broken
1166 * internal modems based on the Rockwell chipset fail this
1167 * test, because they apparently don't implement the loopback
1168 * test mode. So this test is skipped on the COM 1 through
1169 * COM 4 ports. This *should* be safe, since no board
1170 * manufacturer would be stupid enough to design a board
1171 * that conflicts with COM 1-4 --- we hope!
1172 */
ce8337cb 1173 if (!(up->port.flags & UPF_SKIP_TEST)) {
1da177e4
LT		 1174 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1175 status1 = serial_inp(up, UART_MSR) & 0xF0;
1176 serial_outp(up, UART_MCR, save_mcr);
1177 if (status1 != 0x90)
1178 goto out; /* We failed loopback test */
1179 }
1180 serial_outp(up, UART_LCR, 0xBF); /* set up for StarTech test */
1181 serial_outp(up, UART_EFR, 0); /* EFR is the same as FCR */
1182 serial_outp(up, UART_LCR, 0);
1183 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1184 scratch = serial_in(up, UART_IIR) >> 6;
1185 switch (scratch) {
1186 case 0:
1187 up->port.type = PORT_16450;
1188 break;
1189 case 1:
1190 up->port.type = PORT_UNKNOWN;
1191 break;
1192 case 2:
1193 up->port.type = PORT_16550;
1194 break;
1195 case 3:
1196 up->port.type = PORT_16550A;
1197 break;
1198 }
1199 if (up->port.type == PORT_16550A) {
1200 /* Check for Startech UART's */
1201 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1202 if (serial_in(up, UART_EFR) == 0) {
1203 up->port.type = PORT_16650;
1204 } else {
1205 serial_outp(up, UART_LCR, 0xBF);
1206 if (serial_in(up, UART_EFR) == 0)
1207 up->port.type = PORT_16650V2;
1208 }
1209 }
1210 if (up->port.type == PORT_16550A) {
1211 /* Check for TI 16750 */
1212 serial_outp(up, UART_LCR, save_lcr | UART_LCR_DLAB);
1213 serial_outp(up, UART_FCR,
1214 UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1215 scratch = serial_in(up, UART_IIR) >> 5;
1216 if (scratch == 7) {
1217 /*
1218 * If this is a 16750, and not a cheap UART
1219 * clone, then it should only go into 64 byte
1220 * mode if the UART_FCR7_64BYTE bit was set
1221 * while UART_LCR_DLAB was latched.
1222 */
1223 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1224 serial_outp(up, UART_LCR, 0);
1225 serial_outp(up, UART_FCR,
1226 UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1227 scratch = serial_in(up, UART_IIR) >> 5;
1228 if (scratch == 6)
1229 up->port.type = PORT_16750;
1230 }
1231 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1232 }
1233 serial_outp(up, UART_LCR, save_lcr);
1234 if (up->port.type == PORT_16450) {
1235 scratch = serial_in(up, UART_SCR);
1236 serial_outp(up, UART_SCR, 0xa5);
1237 status1 = serial_in(up, UART_SCR);
1238 serial_outp(up, UART_SCR, 0x5a);
1239 status2 = serial_in(up, UART_SCR);
1240 serial_outp(up, UART_SCR, scratch);
1241
1242 if ((status1 != 0xa5) || (status2 != 0x5a))
1243 up->port.type = PORT_8250;
1244 }
1245
1246 up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size;
1247
1248 if (up->port.type == PORT_UNKNOWN)
1249 goto out;
1250 up->type_probed = up->port.type; /* XXX */
1251
1252 /*
1253 * Reset the UART.
1254 */
1255#ifdef CONFIG_SERIAL_8250_RSA
1256 if (up->port.type == PORT_RSA)
1257 serial_outp(up, UART_RSA_FRR, 0);
1258#endif
1259 serial_outp(up, UART_MCR, save_mcr);
1260 serial_outp(up, UART_FCR, (UART_FCR_ENABLE_FIFO |
1261 UART_FCR_CLEAR_RCVR |
1262 UART_FCR_CLEAR_XMIT));
1263 serial_outp(up, UART_FCR, 0);
1264 (void)serial_in(up, UART_RX);
1265 serial_outp(up, UART_IER, 0);
1266
1267out:
1268 spin_unlock_irqrestore(&up->port.lock, flags);
1269}
1270
1271static struct uart_driver sunsu_reg = {
1272 .owner = THIS_MODULE,
1273 .driver_name = "serial",
1274 .devfs_name = "tts/",
1275 .dev_name = "ttyS",
1276 .major = TTY_MAJOR,
1277};
1278
1279static int __init sunsu_kbd_ms_init(struct uart_sunsu_port *up, int channel)
1280{
623f41eb 1281 int quot, baud;
1da177e4
LT		 1282#ifdef CONFIG_SERIO
1283 struct serio *serio;
1284#endif
1285
1286 up->port.line = channel;
1287 up->port.type = PORT_UNKNOWN;
1288 up->port.uartclk = (SU_BASE_BAUD * 16);
1289
623f41eb 1290 if (up->su_type == SU_PORT_KBD) {
1da177e4 1291 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
623f41eb
DM		 1292 baud = 1200;
1293 } else {
1da177e4 1294 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
623f41eb
DM		 1295 baud = 4800;
1296 }
1297 quot = up->port.uartclk / (16 * baud);
1da177e4
LT		 1298
1299 sunsu_autoconfig(up);
1300 if (up->port.type == PORT_UNKNOWN)
1301 return -1;
1302
1303 printk(KERN_INFO "su%d at 0x%p (irq = %s) is a %s\n",
1304 channel,
1305 up->port.membase, __irq_itoa(up->port.irq),
1306 sunsu_type(&up->port));
1307
1308#ifdef CONFIG_SERIO
1309 up->serio = serio = kmalloc(sizeof(struct serio), GFP_KERNEL);
1310 if (serio) {
1311 memset(serio, 0, sizeof(*serio));
1312
1313 serio->port_data = up;
1314
1315 serio->id.type = SERIO_RS232;
1316 if (up->su_type == SU_PORT_KBD) {
1317 serio->id.proto = SERIO_SUNKBD;
1318 strlcpy(serio->name, "sukbd", sizeof(serio->name));
1319 } else {
1320 serio->id.proto = SERIO_SUN;
1321 serio->id.extra = 1;
1322 strlcpy(serio->name, "sums", sizeof(serio->name));
1323 }
1324 strlcpy(serio->phys, (channel == 0 ? "su/serio0" : "su/serio1"),
1325 sizeof(serio->phys));
1326
1327 serio->write = sunsu_serio_write;
1328 serio->open = sunsu_serio_open;
1329 serio->close = sunsu_serio_close;
1330
1331 serio_register_port(serio);
1332 } else {
1333 printk(KERN_WARNING "su%d: not enough memory for serio port\n",
1334 channel);
1335 }
1336#endif
1337
623f41eb
DM		 1338 sunsu_change_speed(&up->port, up->cflag, 0, quot);
1339
1da177e4
LT		 1340 sunsu_startup(&up->port);
1341 return 0;
1342}
1343
1344/*
1345 * ------------------------------------------------------------
1346 * Serial console driver
1347 * ------------------------------------------------------------
1348 */
1349
1350#ifdef CONFIG_SERIAL_SUNSU_CONSOLE
1351
1352#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1353
1354/*
1355 * Wait for transmitter & holding register to empty
1356 */
1357static __inline__ void wait_for_xmitr(struct uart_sunsu_port *up)
1358{
1359 unsigned int status, tmout = 10000;
1360
1361 /* Wait up to 10ms for the character(s) to be sent. */
1362 do {
1363 status = serial_in(up, UART_LSR);
1364
1365 if (status & UART_LSR_BI)
1366 up->lsr_break_flag = UART_LSR_BI;
1367
1368 if (--tmout == 0)
1369 break;
1370 udelay(1);
1371 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1372
1373 /* Wait up to 1s for flow control if necessary */
ce8337cb 1374 if (up->port.flags & UPF_CONS_FLOW) {
1da177e4
LT		 1375 tmout = 1000000;
1376 while (--tmout &&
1377 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1378 udelay(1);
1379 }
1380}
1381
1382/*
1383 * Print a string to the serial port trying not to disturb
1384 * any possible real use of the port...
1385 */
1386static void sunsu_console_write(struct console *co, const char *s,
1387 unsigned int count)
1388{
1389 struct uart_sunsu_port *up = &sunsu_ports[co->index];
1390 unsigned int ier;
1391 int i;
1392
1393 /*
1394 * First save the UER then disable the interrupts
1395 */
1396 ier = serial_in(up, UART_IER);
1397 serial_out(up, UART_IER, 0);
1398
1399 /*
1400 * Now, do each character
1401 */
1402 for (i = 0; i < count; i++, s++) {
1403 wait_for_xmitr(up);
1404
1405 /*
1406 * Send the character out.
1407 * If a LF, also do CR...
1408 */
1409 serial_out(up, UART_TX, *s);
1410 if (*s == 10) {
1411 wait_for_xmitr(up);
1412 serial_out(up, UART_TX, 13);
1413 }
1414 }
1415
1416 /*
1417 * Finally, wait for transmitter to become empty
1418 * and restore the IER
1419 */
1420 wait_for_xmitr(up);
1421 serial_out(up, UART_IER, ier);
1422}
1423
1424/*
1425 * Setup initial baud/bits/parity. We do two things here:
1426 * - construct a cflag setting for the first su_open()
1427 * - initialize the serial port
1428 * Return non-zero if we didn't find a serial port.
1429 */
48377246 1430static int sunsu_console_setup(struct console *co, char *options)
1da177e4
LT		 1431{
1432 struct uart_port *port;
1433 int baud = 9600;
1434 int bits = 8;
1435 int parity = 'n';
1436 int flow = 'n';
1437
1438 printk("Console: ttyS%d (SU)\n",
1439 (sunsu_reg.minor - 64) + co->index);
1440
1441 /*
1442 * Check whether an invalid uart number has been specified, and
1443 * if so, search for the first available port that does have
1444 * console support.
1445 */
1446 if (co->index >= UART_NR)
1447 co->index = 0;
1448 port = &sunsu_ports[co->index].port;
1449
1450 /*
1451 * Temporary fix.
1452 */
1453 spin_lock_init(&port->lock);
1454
1455 if (options)
1456 uart_parse_options(options, &baud, &parity, &bits, &flow);
1457
1458 return uart_set_options(port, co, baud, parity, bits, flow);
1459}
1460
1461static struct console sunsu_cons = {
1462 .name = "ttyS",
1463 .write = sunsu_console_write,
1464 .device = uart_console_device,
1465 .setup = sunsu_console_setup,
1466 .flags = CON_PRINTBUFFER,
1467 .index = -1,
1468 .data = &sunsu_reg,
1469};
1470#define SUNSU_CONSOLE (&sunsu_cons)
1471
1472/*
1473 * Register console.
1474 */
1475
1476static int __init sunsu_serial_console_init(void)
1477{
1478 int i;
1479
1480 if (con_is_present())
1481 return 0;
1482
1483 for (i = 0; i < UART_NR; i++) {
1484 int this_minor = sunsu_reg.minor + i;
1485
1486 if ((this_minor - 64) == (serial_console - 1))
1487 break;
1488 }
1489 if (i == UART_NR)
1490 return 0;
1491 if (sunsu_ports[i].port_node == 0)
1492 return 0;
1493
1494 sunsu_cons.index = i;
1495 register_console(&sunsu_cons);
1496 return 0;
1497}
1498#else
1499#define SUNSU_CONSOLE (NULL)
1500#define sunsu_serial_console_init() do { } while (0)
1501#endif
1502
1503static int __init sunsu_serial_init(void)
1504{
1505 int instance, ret, i;
1506
1507 /* How many instances do we need? */
1508 instance = 0;
1509 for (i = 0; i < UART_NR; i++) {
1510 struct uart_sunsu_port *up = &sunsu_ports[i];
1511
1512 if (up->su_type == SU_PORT_MS ||
1513 up->su_type == SU_PORT_KBD)
1514 continue;
1515
ce8337cb 1516 up->port.flags |= UPF_BOOT_AUTOCONF;
1da177e4
LT		 1517 up->port.type = PORT_UNKNOWN;
1518 up->port.uartclk = (SU_BASE_BAUD * 16);
1519
1520 sunsu_autoconfig(up);
1521 if (up->port.type == PORT_UNKNOWN)
1522 continue;
1523
1524 up->port.line = instance++;
1525 up->port.ops = &sunsu_pops;
1526 }
1527
1528 sunsu_reg.minor = sunserial_current_minor;
1529 sunserial_current_minor += instance;
1530
1531 sunsu_reg.nr = instance;
1532 sunsu_reg.cons = SUNSU_CONSOLE;
1533
1534 ret = uart_register_driver(&sunsu_reg);
1535 if (ret < 0)
1536 return ret;
1537
1538 sunsu_serial_console_init();
1539 for (i = 0; i < UART_NR; i++) {
1540 struct uart_sunsu_port *up = &sunsu_ports[i];
1541
1542 /* Do not register Keyboard/Mouse lines with UART
1543 * layer.
1544 */
1545 if (up->su_type == SU_PORT_MS ||
1546 up->su_type == SU_PORT_KBD)
1547 continue;
1548
1549 if (up->port.type == PORT_UNKNOWN)
1550 continue;
1551
1552 uart_add_one_port(&sunsu_reg, &up->port);
1553 }
1554
1555 return 0;
1556}
1557
1558static int su_node_ok(int node, char *name, int namelen)
1559{
1560 if (strncmp(name, "su", namelen) == 0 ||
1561 strncmp(name, "su_pnp", namelen) == 0)
1562 return 1;
1563
1564 if (strncmp(name, "serial", namelen) == 0) {
1565 char compat[32];
1566 int clen;
1567
1568 /* Is it _really_ a 'su' device? */
1569 clen = prom_getproperty(node, "compatible", compat, sizeof(compat));
1570 if (clen > 0) {
1571 if (strncmp(compat, "sab82532", 8) == 0) {
1572 /* Nope, Siemens serial, not for us. */
1573 return 0;
1574 }
1575 }
1576 return 1;
1577 }
1578
1579 return 0;
1580}
1581
1582#define SU_PROPSIZE 128
1583
1584/*
1585 * Scan status structure.
1586 * "prop" is a local variable but it eats stack to keep it in each
1587 * stack frame of a recursive procedure.
1588 */
1589struct su_probe_scan {
1590 int msnode, kbnode; /* PROM nodes for mouse and keyboard */
1591 int msx, kbx; /* minors for mouse and keyboard */
1592 int devices; /* scan index */
1593 char prop[SU_PROPSIZE];
1594};
1595
1596/*
1597 * We have several platforms which present 'su' in different parts
1598 * of the device tree. 'su' may be found under obio, ebus, isa and pci.
1599 * We walk over the tree and find them wherever PROM hides them.
1600 */
1601static void __init su_probe_any(struct su_probe_scan *t, int sunode)
1602{
1603 struct uart_sunsu_port *up;
1604 int len;
1605
1606 if (t->devices >= UART_NR)
1607 return;
1608
1609 for (; sunode != 0; sunode = prom_getsibling(sunode)) {
1610 len = prom_getproperty(sunode, "name", t->prop, SU_PROPSIZE);
1611 if (len <= 1)
1612 continue; /* Broken PROM node */
1613
1614 if (su_node_ok(sunode, t->prop, len)) {
1615 up = &sunsu_ports[t->devices];
1616 if (t->kbnode != 0 && sunode == t->kbnode) {
1617 t->kbx = t->devices;
1618 up->su_type = SU_PORT_KBD;
1619 } else if (t->msnode != 0 && sunode == t->msnode) {
1620 t->msx = t->devices;
1621 up->su_type = SU_PORT_MS;
1622 } else {
1623#ifdef CONFIG_SPARC64
1624 /*
1625 * Do not attempt to use the truncated
1626 * keyboard/mouse ports as serial ports
1627 * on Ultras with PC keyboard attached.
1628 */
1629 if (prom_getbool(sunode, "mouse"))
1630 continue;
1631 if (prom_getbool(sunode, "keyboard"))
1632 continue;
1633#endif
1634 up->su_type = SU_PORT_PORT;
1635 }
1636 up->port_node = sunode;
1637 ++t->devices;
1638 } else {
1639 su_probe_any(t, prom_getchild(sunode));
1640 }
1641 }
1642}
1643
1644static int __init sunsu_probe(void)
1645{
1646 int node;
1647 int len;
1648 struct su_probe_scan scan;
1649
1650 /*
1651 * First, we scan the tree.
1652 */
1653 scan.devices = 0;
1654 scan.msx = -1;
1655 scan.kbx = -1;
1656 scan.kbnode = 0;
1657 scan.msnode = 0;
1658
1659 /*
1660 * Get the nodes for keyboard and mouse from 'aliases'...
1661 */
1662 node = prom_getchild(prom_root_node);
1663 node = prom_searchsiblings(node, "aliases");
1664 if (node != 0) {
1665 len = prom_getproperty(node, "keyboard", scan.prop, SU_PROPSIZE);
1666 if (len > 0) {
1667 scan.prop[len] = 0;
1668 scan.kbnode = prom_finddevice(scan.prop);
1669 }
1670
1671 len = prom_getproperty(node, "mouse", scan.prop, SU_PROPSIZE);
1672 if (len > 0) {
1673 scan.prop[len] = 0;
1674 scan.msnode = prom_finddevice(scan.prop);
1675 }
1676 }
1677
1678 su_probe_any(&scan, prom_getchild(prom_root_node));
1679
1680 /*
1681 * Second, we process the special case of keyboard and mouse.
1682 *
1683 * Currently if we got keyboard and mouse hooked to "su" ports
1684 * we do not use any possible remaining "su" as a serial port.
1685 * Thus, we ignore values of .msx and .kbx, then compact ports.
1686 */
1687 if (scan.msx != -1 && scan.kbx != -1) {
1688 sunsu_ports[0].su_type = SU_PORT_MS;
1689 sunsu_ports[0].port_node = scan.msnode;
1690 sunsu_kbd_ms_init(&sunsu_ports[0], 0);
1691
1692 sunsu_ports[1].su_type = SU_PORT_KBD;
1693 sunsu_ports[1].port_node = scan.kbnode;
1694 sunsu_kbd_ms_init(&sunsu_ports[1], 1);
1695
1696 return 0;
1697 }
1698
1699 if (scan.msx != -1 || scan.kbx != -1) {
1700 printk("sunsu_probe: cannot match keyboard and mouse, confused\n");
1701 return -ENODEV;
1702 }
1703
1704 if (scan.devices == 0)
1705 return -ENODEV;
1706
1707 /*
1708 * Console must be initiated after the generic initialization.
1709 */
1710 sunsu_serial_init();
1711
1712 return 0;
1713}
1714
1715static void __exit sunsu_exit(void)
1716{
1717 int i, saw_uart;
1718
1719 saw_uart = 0;
1720 for (i = 0; i < UART_NR; i++) {
1721 struct uart_sunsu_port *up = &sunsu_ports[i];
1722
1723 if (up->su_type == SU_PORT_MS ||
1724 up->su_type == SU_PORT_KBD) {
1725#ifdef CONFIG_SERIO
1726 if (up->serio) {
1727 serio_unregister_port(up->serio);
1728 up->serio = NULL;
1729 }
1730#endif
1731 } else if (up->port.type != PORT_UNKNOWN) {
1732 uart_remove_one_port(&sunsu_reg, &up->port);
1733 saw_uart++;
1734 }
1735 }
1736
1737 if (saw_uart)
1738 uart_unregister_driver(&sunsu_reg);
1739}
1740
1741module_init(sunsu_probe);
1742module_exit(sunsu_exit);
Linux kernel - Deliverables
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