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1da177e4 LT |
1 | /* $Id: su.c,v 1.55 2002/01/08 16:00:16 davem Exp $ |
2 | * su.c: Small serial driver for keyboard/mouse interface on sparc32/PCI | |
3 | * | |
4 | * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be) | |
5 | * Copyright (C) 1998-1999 Pete Zaitcev (zaitcev@yahoo.com) | |
6 | * | |
7 | * This is mainly a variation of 8250.c, credits go to authors mentioned | |
8 | * therein. In fact this driver should be merged into the generic 8250.c | |
9 | * infrastructure perhaps using a 8250_sparc.c module. | |
10 | * | |
11 | * Fixed to use tty_get_baud_rate(). | |
12 | * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12 | |
13 | * | |
14 | * Converted to new 2.5.x UART layer. | |
15 | * David S. Miller (davem@redhat.com), 2002-Jul-29 | |
16 | */ | |
17 | ||
18 | #include <linux/config.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/sched.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/tty.h> | |
25 | #include <linux/tty_flip.h> | |
26 | #include <linux/major.h> | |
27 | #include <linux/string.h> | |
28 | #include <linux/ptrace.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/circ_buf.h> | |
31 | #include <linux/serial.h> | |
32 | #include <linux/sysrq.h> | |
33 | #include <linux/console.h> | |
34 | #ifdef CONFIG_SERIO | |
35 | #include <linux/serio.h> | |
36 | #endif | |
37 | #include <linux/serial_reg.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/delay.h> | |
40 | ||
41 | #include <asm/io.h> | |
42 | #include <asm/irq.h> | |
43 | #include <asm/oplib.h> | |
44 | #include <asm/ebus.h> | |
45 | #ifdef CONFIG_SPARC64 | |
46 | #include <asm/isa.h> | |
47 | #endif | |
48 | ||
49 | #if defined(CONFIG_SERIAL_SUNSU_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
50 | #define SUPPORT_SYSRQ | |
51 | #endif | |
52 | ||
53 | #include <linux/serial_core.h> | |
54 | ||
55 | #include "suncore.h" | |
56 | ||
57 | /* We are on a NS PC87303 clocked with 24.0 MHz, which results | |
58 | * in a UART clock of 1.8462 MHz. | |
59 | */ | |
60 | #define SU_BASE_BAUD (1846200 / 16) | |
61 | ||
62 | enum su_type { SU_PORT_NONE, SU_PORT_MS, SU_PORT_KBD, SU_PORT_PORT }; | |
63 | static char *su_typev[] = { "su(???)", "su(mouse)", "su(kbd)", "su(serial)" }; | |
64 | ||
65 | /* | |
66 | * Here we define the default xmit fifo size used for each type of UART. | |
67 | */ | |
68 | static const struct serial_uart_config uart_config[PORT_MAX_8250+1] = { | |
69 | { "unknown", 1, 0 }, | |
70 | { "8250", 1, 0 }, | |
71 | { "16450", 1, 0 }, | |
72 | { "16550", 1, 0 }, | |
73 | { "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO }, | |
74 | { "Cirrus", 1, 0 }, | |
75 | { "ST16650", 1, UART_CLEAR_FIFO | UART_STARTECH }, | |
76 | { "ST16650V2", 32, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH }, | |
77 | { "TI16750", 64, UART_CLEAR_FIFO | UART_USE_FIFO }, | |
78 | { "Startech", 1, 0 }, | |
79 | { "16C950/954", 128, UART_CLEAR_FIFO | UART_USE_FIFO }, | |
80 | { "ST16654", 64, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH }, | |
81 | { "XR16850", 128, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH }, | |
82 | { "RSA", 2048, UART_CLEAR_FIFO | UART_USE_FIFO } | |
83 | }; | |
84 | ||
85 | struct uart_sunsu_port { | |
86 | struct uart_port port; | |
87 | unsigned char acr; | |
88 | unsigned char ier; | |
89 | unsigned short rev; | |
90 | unsigned char lcr; | |
91 | unsigned int lsr_break_flag; | |
92 | unsigned int cflag; | |
93 | ||
94 | /* Probing information. */ | |
95 | enum su_type su_type; | |
96 | unsigned int type_probed; /* XXX Stupid */ | |
97 | int port_node; | |
98 | ||
99 | #ifdef CONFIG_SERIO | |
100 | struct serio *serio; | |
101 | int serio_open; | |
102 | #endif | |
103 | }; | |
104 | ||
105 | #define _INLINE_ | |
106 | ||
107 | static _INLINE_ unsigned int serial_in(struct uart_sunsu_port *up, int offset) | |
108 | { | |
109 | offset <<= up->port.regshift; | |
110 | ||
111 | switch (up->port.iotype) { | |
112 | case SERIAL_IO_HUB6: | |
113 | outb(up->port.hub6 - 1 + offset, up->port.iobase); | |
114 | return inb(up->port.iobase + 1); | |
115 | ||
116 | case SERIAL_IO_MEM: | |
117 | return readb(up->port.membase + offset); | |
118 | ||
119 | default: | |
120 | return inb(up->port.iobase + offset); | |
121 | } | |
122 | } | |
123 | ||
124 | static _INLINE_ void | |
125 | serial_out(struct uart_sunsu_port *up, int offset, int value) | |
126 | { | |
127 | #ifndef CONFIG_SPARC64 | |
128 | /* | |
129 | * MrCoffee has weird schematics: IRQ4 & P10(?) pins of SuperIO are | |
130 | * connected with a gate then go to SlavIO. When IRQ4 goes tristated | |
131 | * gate outputs a logical one. Since we use level triggered interrupts | |
132 | * we have lockup and watchdog reset. We cannot mask IRQ because | |
133 | * keyboard shares IRQ with us (Word has it as Bob Smelik's design). | |
134 | * This problem is similar to what Alpha people suffer, see serial.c. | |
135 | */ | |
136 | if (offset == UART_MCR) | |
137 | value |= UART_MCR_OUT2; | |
138 | #endif | |
139 | offset <<= up->port.regshift; | |
140 | ||
141 | switch (up->port.iotype) { | |
142 | case SERIAL_IO_HUB6: | |
143 | outb(up->port.hub6 - 1 + offset, up->port.iobase); | |
144 | outb(value, up->port.iobase + 1); | |
145 | break; | |
146 | ||
147 | case SERIAL_IO_MEM: | |
148 | writeb(value, up->port.membase + offset); | |
149 | break; | |
150 | ||
151 | default: | |
152 | outb(value, up->port.iobase + offset); | |
153 | } | |
154 | } | |
155 | ||
156 | /* | |
157 | * We used to support using pause I/O for certain machines. We | |
158 | * haven't supported this for a while, but just in case it's badly | |
159 | * needed for certain old 386 machines, I've left these #define's | |
160 | * in.... | |
161 | */ | |
162 | #define serial_inp(up, offset) serial_in(up, offset) | |
163 | #define serial_outp(up, offset, value) serial_out(up, offset, value) | |
164 | ||
165 | ||
166 | /* | |
167 | * For the 16C950 | |
168 | */ | |
169 | static void serial_icr_write(struct uart_sunsu_port *up, int offset, int value) | |
170 | { | |
171 | serial_out(up, UART_SCR, offset); | |
172 | serial_out(up, UART_ICR, value); | |
173 | } | |
174 | ||
175 | #if 0 /* Unused currently */ | |
176 | static unsigned int serial_icr_read(struct uart_sunsu_port *up, int offset) | |
177 | { | |
178 | unsigned int value; | |
179 | ||
180 | serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); | |
181 | serial_out(up, UART_SCR, offset); | |
182 | value = serial_in(up, UART_ICR); | |
183 | serial_icr_write(up, UART_ACR, up->acr); | |
184 | ||
185 | return value; | |
186 | } | |
187 | #endif | |
188 | ||
189 | #ifdef CONFIG_SERIAL_8250_RSA | |
190 | /* | |
191 | * Attempts to turn on the RSA FIFO. Returns zero on failure. | |
192 | * We set the port uart clock rate if we succeed. | |
193 | */ | |
194 | static int __enable_rsa(struct uart_sunsu_port *up) | |
195 | { | |
196 | unsigned char mode; | |
197 | int result; | |
198 | ||
199 | mode = serial_inp(up, UART_RSA_MSR); | |
200 | result = mode & UART_RSA_MSR_FIFO; | |
201 | ||
202 | if (!result) { | |
203 | serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO); | |
204 | mode = serial_inp(up, UART_RSA_MSR); | |
205 | result = mode & UART_RSA_MSR_FIFO; | |
206 | } | |
207 | ||
208 | if (result) | |
209 | up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16; | |
210 | ||
211 | return result; | |
212 | } | |
213 | ||
214 | static void enable_rsa(struct uart_sunsu_port *up) | |
215 | { | |
216 | if (up->port.type == PORT_RSA) { | |
217 | if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { | |
218 | spin_lock_irq(&up->port.lock); | |
219 | __enable_rsa(up); | |
220 | spin_unlock_irq(&up->port.lock); | |
221 | } | |
222 | if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) | |
223 | serial_outp(up, UART_RSA_FRR, 0); | |
224 | } | |
225 | } | |
226 | ||
227 | /* | |
228 | * Attempts to turn off the RSA FIFO. Returns zero on failure. | |
229 | * It is unknown why interrupts were disabled in here. However, | |
230 | * the caller is expected to preserve this behaviour by grabbing | |
231 | * the spinlock before calling this function. | |
232 | */ | |
233 | static void disable_rsa(struct uart_sunsu_port *up) | |
234 | { | |
235 | unsigned char mode; | |
236 | int result; | |
237 | ||
238 | if (up->port.type == PORT_RSA && | |
239 | up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { | |
240 | spin_lock_irq(&up->port.lock); | |
241 | ||
242 | mode = serial_inp(up, UART_RSA_MSR); | |
243 | result = !(mode & UART_RSA_MSR_FIFO); | |
244 | ||
245 | if (!result) { | |
246 | serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO); | |
247 | mode = serial_inp(up, UART_RSA_MSR); | |
248 | result = !(mode & UART_RSA_MSR_FIFO); | |
249 | } | |
250 | ||
251 | if (result) | |
252 | up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; | |
253 | spin_unlock_irq(&up->port.lock); | |
254 | } | |
255 | } | |
256 | #endif /* CONFIG_SERIAL_8250_RSA */ | |
257 | ||
258 | static void sunsu_stop_tx(struct uart_port *port, unsigned int tty_stop) | |
259 | { | |
260 | struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; | |
261 | ||
262 | if (up->ier & UART_IER_THRI) { | |
263 | up->ier &= ~UART_IER_THRI; | |
264 | serial_out(up, UART_IER, up->ier); | |
265 | } | |
266 | if (up->port.type == PORT_16C950 && tty_stop) { | |
267 | up->acr |= UART_ACR_TXDIS; | |
268 | serial_icr_write(up, UART_ACR, up->acr); | |
269 | } | |
270 | } | |
271 | ||
272 | static void sunsu_start_tx(struct uart_port *port, unsigned int tty_start) | |
273 | { | |
274 | struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; | |
275 | ||
276 | if (!(up->ier & UART_IER_THRI)) { | |
277 | up->ier |= UART_IER_THRI; | |
278 | serial_out(up, UART_IER, up->ier); | |
279 | } | |
280 | /* | |
281 | * We only do this from uart_start | |
282 | */ | |
283 | if (tty_start && up->port.type == PORT_16C950) { | |
284 | up->acr &= ~UART_ACR_TXDIS; | |
285 | serial_icr_write(up, UART_ACR, up->acr); | |
286 | } | |
287 | } | |
288 | ||
289 | static void sunsu_stop_rx(struct uart_port *port) | |
290 | { | |
291 | struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; | |
292 | unsigned long flags; | |
293 | ||
294 | spin_lock_irqsave(&up->port.lock, flags); | |
295 | up->ier &= ~UART_IER_RLSI; | |
296 | up->port.read_status_mask &= ~UART_LSR_DR; | |
297 | serial_out(up, UART_IER, up->ier); | |
298 | spin_unlock_irqrestore(&up->port.lock, flags); | |
299 | } | |
300 | ||
301 | static void sunsu_enable_ms(struct uart_port *port) | |
302 | { | |
303 | struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; | |
304 | unsigned long flags; | |
305 | ||
306 | spin_lock_irqsave(&up->port.lock, flags); | |
307 | up->ier |= UART_IER_MSI; | |
308 | serial_out(up, UART_IER, up->ier); | |
309 | spin_unlock_irqrestore(&up->port.lock, flags); | |
310 | } | |
311 | ||
312 | static _INLINE_ struct tty_struct * | |
313 | receive_chars(struct uart_sunsu_port *up, unsigned char *status, struct pt_regs *regs) | |
314 | { | |
315 | struct tty_struct *tty = up->port.info->tty; | |
316 | unsigned char ch; | |
317 | int max_count = 256; | |
318 | int saw_console_brk = 0; | |
319 | ||
320 | do { | |
321 | if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) { | |
322 | tty->flip.work.func((void *)tty); | |
323 | if (tty->flip.count >= TTY_FLIPBUF_SIZE) | |
324 | return tty; // if TTY_DONT_FLIP is set | |
325 | } | |
326 | ch = serial_inp(up, UART_RX); | |
327 | *tty->flip.char_buf_ptr = ch; | |
328 | *tty->flip.flag_buf_ptr = TTY_NORMAL; | |
329 | up->port.icount.rx++; | |
330 | ||
331 | if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | | |
332 | UART_LSR_FE | UART_LSR_OE))) { | |
333 | /* | |
334 | * For statistics only | |
335 | */ | |
336 | if (*status & UART_LSR_BI) { | |
337 | *status &= ~(UART_LSR_FE | UART_LSR_PE); | |
338 | up->port.icount.brk++; | |
339 | if (up->port.cons != NULL && | |
340 | up->port.line == up->port.cons->index) | |
341 | saw_console_brk = 1; | |
342 | /* | |
343 | * We do the SysRQ and SAK checking | |
344 | * here because otherwise the break | |
345 | * may get masked by ignore_status_mask | |
346 | * or read_status_mask. | |
347 | */ | |
348 | if (uart_handle_break(&up->port)) | |
349 | goto ignore_char; | |
350 | } else if (*status & UART_LSR_PE) | |
351 | up->port.icount.parity++; | |
352 | else if (*status & UART_LSR_FE) | |
353 | up->port.icount.frame++; | |
354 | if (*status & UART_LSR_OE) | |
355 | up->port.icount.overrun++; | |
356 | ||
357 | /* | |
358 | * Mask off conditions which should be ingored. | |
359 | */ | |
360 | *status &= up->port.read_status_mask; | |
361 | ||
362 | if (up->port.cons != NULL && | |
363 | up->port.line == up->port.cons->index) { | |
364 | /* Recover the break flag from console xmit */ | |
365 | *status |= up->lsr_break_flag; | |
366 | up->lsr_break_flag = 0; | |
367 | } | |
368 | ||
369 | if (*status & UART_LSR_BI) { | |
370 | *tty->flip.flag_buf_ptr = TTY_BREAK; | |
371 | } else if (*status & UART_LSR_PE) | |
372 | *tty->flip.flag_buf_ptr = TTY_PARITY; | |
373 | else if (*status & UART_LSR_FE) | |
374 | *tty->flip.flag_buf_ptr = TTY_FRAME; | |
375 | } | |
376 | if (uart_handle_sysrq_char(&up->port, ch, regs)) | |
377 | goto ignore_char; | |
378 | if ((*status & up->port.ignore_status_mask) == 0) { | |
379 | tty->flip.flag_buf_ptr++; | |
380 | tty->flip.char_buf_ptr++; | |
381 | tty->flip.count++; | |
382 | } | |
383 | if ((*status & UART_LSR_OE) && | |
384 | tty->flip.count < TTY_FLIPBUF_SIZE) { | |
385 | /* | |
386 | * Overrun is special, since it's reported | |
387 | * immediately, and doesn't affect the current | |
388 | * character. | |
389 | */ | |
390 | *tty->flip.flag_buf_ptr = TTY_OVERRUN; | |
391 | tty->flip.flag_buf_ptr++; | |
392 | tty->flip.char_buf_ptr++; | |
393 | tty->flip.count++; | |
394 | } | |
395 | ignore_char: | |
396 | *status = serial_inp(up, UART_LSR); | |
397 | } while ((*status & UART_LSR_DR) && (max_count-- > 0)); | |
398 | ||
399 | if (saw_console_brk) | |
400 | sun_do_break(); | |
401 | ||
402 | return tty; | |
403 | } | |
404 | ||
405 | static _INLINE_ void transmit_chars(struct uart_sunsu_port *up) | |
406 | { | |
407 | struct circ_buf *xmit = &up->port.info->xmit; | |
408 | int count; | |
409 | ||
410 | if (up->port.x_char) { | |
411 | serial_outp(up, UART_TX, up->port.x_char); | |
412 | up->port.icount.tx++; | |
413 | up->port.x_char = 0; | |
414 | return; | |
415 | } | |
416 | if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { | |
417 | sunsu_stop_tx(&up->port, 0); | |
418 | return; | |
419 | } | |
420 | ||
421 | count = up->port.fifosize; | |
422 | do { | |
423 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
424 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
425 | up->port.icount.tx++; | |
426 | if (uart_circ_empty(xmit)) | |
427 | break; | |
428 | } while (--count > 0); | |
429 | ||
430 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
431 | uart_write_wakeup(&up->port); | |
432 | ||
433 | if (uart_circ_empty(xmit)) | |
434 | sunsu_stop_tx(&up->port, 0); | |
435 | } | |
436 | ||
437 | static _INLINE_ void check_modem_status(struct uart_sunsu_port *up) | |
438 | { | |
439 | int status; | |
440 | ||
441 | status = serial_in(up, UART_MSR); | |
442 | ||
443 | if ((status & UART_MSR_ANY_DELTA) == 0) | |
444 | return; | |
445 | ||
446 | if (status & UART_MSR_TERI) | |
447 | up->port.icount.rng++; | |
448 | if (status & UART_MSR_DDSR) | |
449 | up->port.icount.dsr++; | |
450 | if (status & UART_MSR_DDCD) | |
451 | uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); | |
452 | if (status & UART_MSR_DCTS) | |
453 | uart_handle_cts_change(&up->port, status & UART_MSR_CTS); | |
454 | ||
455 | wake_up_interruptible(&up->port.info->delta_msr_wait); | |
456 | } | |
457 | ||
458 | static irqreturn_t sunsu_serial_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
459 | { | |
460 | struct uart_sunsu_port *up = dev_id; | |
461 | unsigned long flags; | |
462 | unsigned char status; | |
463 | ||
464 | spin_lock_irqsave(&up->port.lock, flags); | |
465 | ||
466 | do { | |
467 | struct tty_struct *tty; | |
468 | ||
469 | status = serial_inp(up, UART_LSR); | |
470 | tty = NULL; | |
471 | if (status & UART_LSR_DR) | |
472 | tty = receive_chars(up, &status, regs); | |
473 | check_modem_status(up); | |
474 | if (status & UART_LSR_THRE) | |
475 | transmit_chars(up); | |
476 | ||
477 | spin_unlock_irqrestore(&up->port.lock, flags); | |
478 | ||
479 | if (tty) | |
480 | tty_flip_buffer_push(tty); | |
481 | ||
482 | spin_lock_irqsave(&up->port.lock, flags); | |
483 | ||
484 | } while (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT)); | |
485 | ||
486 | spin_unlock_irqrestore(&up->port.lock, flags); | |
487 | ||
488 | return IRQ_HANDLED; | |
489 | } | |
490 | ||
491 | /* Separate interrupt handling path for keyboard/mouse ports. */ | |
492 | ||
493 | static void | |
494 | sunsu_change_speed(struct uart_port *port, unsigned int cflag, | |
495 | unsigned int iflag, unsigned int quot); | |
496 | ||
497 | static void sunsu_change_mouse_baud(struct uart_sunsu_port *up) | |
498 | { | |
499 | unsigned int cur_cflag = up->cflag; | |
500 | int quot, new_baud; | |
501 | ||
502 | up->cflag &= ~CBAUD; | |
503 | up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud); | |
504 | ||
505 | quot = up->port.uartclk / (16 * new_baud); | |
506 | ||
507 | spin_unlock(&up->port.lock); | |
508 | ||
509 | sunsu_change_speed(&up->port, up->cflag, 0, quot); | |
510 | ||
511 | spin_lock(&up->port.lock); | |
512 | } | |
513 | ||
514 | static void receive_kbd_ms_chars(struct uart_sunsu_port *up, struct pt_regs *regs, int is_break) | |
515 | { | |
516 | do { | |
517 | unsigned char ch = serial_inp(up, UART_RX); | |
518 | ||
519 | /* Stop-A is handled by drivers/char/keyboard.c now. */ | |
520 | if (up->su_type == SU_PORT_KBD) { | |
521 | #ifdef CONFIG_SERIO | |
522 | serio_interrupt(up->serio, ch, 0, regs); | |
523 | #endif | |
524 | } else if (up->su_type == SU_PORT_MS) { | |
525 | int ret = suncore_mouse_baud_detection(ch, is_break); | |
526 | ||
527 | switch (ret) { | |
528 | case 2: | |
529 | sunsu_change_mouse_baud(up); | |
530 | /* fallthru */ | |
531 | case 1: | |
532 | break; | |
533 | ||
534 | case 0: | |
535 | #ifdef CONFIG_SERIO | |
536 | serio_interrupt(up->serio, ch, 0, regs); | |
537 | #endif | |
538 | break; | |
539 | }; | |
540 | } | |
541 | } while (serial_in(up, UART_LSR) & UART_LSR_DR); | |
542 | } | |
543 | ||
544 | static irqreturn_t sunsu_kbd_ms_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
545 | { | |
546 | struct uart_sunsu_port *up = dev_id; | |
547 | ||
548 | if (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT)) { | |
549 | unsigned char status = serial_inp(up, UART_LSR); | |
550 | ||
551 | if ((status & UART_LSR_DR) || (status & UART_LSR_BI)) | |
552 | receive_kbd_ms_chars(up, regs, | |
553 | (status & UART_LSR_BI) != 0); | |
554 | } | |
555 | ||
556 | return IRQ_HANDLED; | |
557 | } | |
558 | ||
559 | static unsigned int sunsu_tx_empty(struct uart_port *port) | |
560 | { | |
561 | struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; | |
562 | unsigned long flags; | |
563 | unsigned int ret; | |
564 | ||
565 | spin_lock_irqsave(&up->port.lock, flags); | |
566 | ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; | |
567 | spin_unlock_irqrestore(&up->port.lock, flags); | |
568 | ||
569 | return ret; | |
570 | } | |
571 | ||
572 | static unsigned int sunsu_get_mctrl(struct uart_port *port) | |
573 | { | |
574 | struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; | |
575 | unsigned long flags; | |
576 | unsigned char status; | |
577 | unsigned int ret; | |
578 | ||
579 | spin_lock_irqsave(&up->port.lock, flags); | |
580 | status = serial_in(up, UART_MSR); | |
581 | spin_unlock_irqrestore(&up->port.lock, flags); | |
582 | ||
583 | ret = 0; | |
584 | if (status & UART_MSR_DCD) | |
585 | ret |= TIOCM_CAR; | |
586 | if (status & UART_MSR_RI) | |
587 | ret |= TIOCM_RNG; | |
588 | if (status & UART_MSR_DSR) | |
589 | ret |= TIOCM_DSR; | |
590 | if (status & UART_MSR_CTS) | |
591 | ret |= TIOCM_CTS; | |
592 | return ret; | |
593 | } | |
594 | ||
595 | static void sunsu_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
596 | { | |
597 | struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; | |
598 | unsigned char mcr = 0; | |
599 | ||
600 | if (mctrl & TIOCM_RTS) | |
601 | mcr |= UART_MCR_RTS; | |
602 | if (mctrl & TIOCM_DTR) | |
603 | mcr |= UART_MCR_DTR; | |
604 | if (mctrl & TIOCM_OUT1) | |
605 | mcr |= UART_MCR_OUT1; | |
606 | if (mctrl & TIOCM_OUT2) | |
607 | mcr |= UART_MCR_OUT2; | |
608 | if (mctrl & TIOCM_LOOP) | |
609 | mcr |= UART_MCR_LOOP; | |
610 | ||
611 | serial_out(up, UART_MCR, mcr); | |
612 | } | |
613 | ||
614 | static void sunsu_break_ctl(struct uart_port *port, int break_state) | |
615 | { | |
616 | struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; | |
617 | unsigned long flags; | |
618 | ||
619 | spin_lock_irqsave(&up->port.lock, flags); | |
620 | if (break_state == -1) | |
621 | up->lcr |= UART_LCR_SBC; | |
622 | else | |
623 | up->lcr &= ~UART_LCR_SBC; | |
624 | serial_out(up, UART_LCR, up->lcr); | |
625 | spin_unlock_irqrestore(&up->port.lock, flags); | |
626 | } | |
627 | ||
628 | static int sunsu_startup(struct uart_port *port) | |
629 | { | |
630 | struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; | |
631 | unsigned long flags; | |
632 | int retval; | |
633 | ||
634 | if (up->port.type == PORT_16C950) { | |
635 | /* Wake up and initialize UART */ | |
636 | up->acr = 0; | |
637 | serial_outp(up, UART_LCR, 0xBF); | |
638 | serial_outp(up, UART_EFR, UART_EFR_ECB); | |
639 | serial_outp(up, UART_IER, 0); | |
640 | serial_outp(up, UART_LCR, 0); | |
641 | serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ | |
642 | serial_outp(up, UART_LCR, 0xBF); | |
643 | serial_outp(up, UART_EFR, UART_EFR_ECB); | |
644 | serial_outp(up, UART_LCR, 0); | |
645 | } | |
646 | ||
647 | #ifdef CONFIG_SERIAL_8250_RSA | |
648 | /* | |
649 | * If this is an RSA port, see if we can kick it up to the | |
650 | * higher speed clock. | |
651 | */ | |
652 | enable_rsa(up); | |
653 | #endif | |
654 | ||
655 | /* | |
656 | * Clear the FIFO buffers and disable them. | |
657 | * (they will be reeanbled in set_termios()) | |
658 | */ | |
659 | if (uart_config[up->port.type].flags & UART_CLEAR_FIFO) { | |
660 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
661 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
662 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
663 | serial_outp(up, UART_FCR, 0); | |
664 | } | |
665 | ||
666 | /* | |
667 | * Clear the interrupt registers. | |
668 | */ | |
669 | (void) serial_inp(up, UART_LSR); | |
670 | (void) serial_inp(up, UART_RX); | |
671 | (void) serial_inp(up, UART_IIR); | |
672 | (void) serial_inp(up, UART_MSR); | |
673 | ||
674 | /* | |
675 | * At this point, there's no way the LSR could still be 0xff; | |
676 | * if it is, then bail out, because there's likely no UART | |
677 | * here. | |
678 | */ | |
679 | if (!(up->port.flags & ASYNC_BUGGY_UART) && | |
680 | (serial_inp(up, UART_LSR) == 0xff)) { | |
681 | printk("ttyS%d: LSR safety check engaged!\n", up->port.line); | |
682 | return -ENODEV; | |
683 | } | |
684 | ||
685 | if (up->su_type != SU_PORT_PORT) { | |
686 | retval = request_irq(up->port.irq, sunsu_kbd_ms_interrupt, | |
687 | SA_SHIRQ, su_typev[up->su_type], up); | |
688 | } else { | |
689 | retval = request_irq(up->port.irq, sunsu_serial_interrupt, | |
690 | SA_SHIRQ, su_typev[up->su_type], up); | |
691 | } | |
692 | if (retval) { | |
693 | printk("su: Cannot register IRQ %d\n", up->port.irq); | |
694 | return retval; | |
695 | } | |
696 | ||
697 | /* | |
698 | * Now, initialize the UART | |
699 | */ | |
700 | serial_outp(up, UART_LCR, UART_LCR_WLEN8); | |
701 | ||
702 | spin_lock_irqsave(&up->port.lock, flags); | |
703 | ||
704 | up->port.mctrl |= TIOCM_OUT2; | |
705 | ||
706 | sunsu_set_mctrl(&up->port, up->port.mctrl); | |
707 | spin_unlock_irqrestore(&up->port.lock, flags); | |
708 | ||
709 | /* | |
710 | * Finally, enable interrupts. Note: Modem status interrupts | |
711 | * are set via set_termios(), which will be occurring imminently | |
712 | * anyway, so we don't enable them here. | |
713 | */ | |
714 | up->ier = UART_IER_RLSI | UART_IER_RDI; | |
715 | serial_outp(up, UART_IER, up->ier); | |
716 | ||
717 | if (up->port.flags & ASYNC_FOURPORT) { | |
718 | unsigned int icp; | |
719 | /* | |
720 | * Enable interrupts on the AST Fourport board | |
721 | */ | |
722 | icp = (up->port.iobase & 0xfe0) | 0x01f; | |
723 | outb_p(0x80, icp); | |
724 | (void) inb_p(icp); | |
725 | } | |
726 | ||
727 | /* | |
728 | * And clear the interrupt registers again for luck. | |
729 | */ | |
730 | (void) serial_inp(up, UART_LSR); | |
731 | (void) serial_inp(up, UART_RX); | |
732 | (void) serial_inp(up, UART_IIR); | |
733 | (void) serial_inp(up, UART_MSR); | |
734 | ||
735 | return 0; | |
736 | } | |
737 | ||
738 | static void sunsu_shutdown(struct uart_port *port) | |
739 | { | |
740 | struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; | |
741 | unsigned long flags; | |
742 | ||
743 | /* | |
744 | * Disable interrupts from this port | |
745 | */ | |
746 | up->ier = 0; | |
747 | serial_outp(up, UART_IER, 0); | |
748 | ||
749 | spin_lock_irqsave(&up->port.lock, flags); | |
750 | if (up->port.flags & ASYNC_FOURPORT) { | |
751 | /* reset interrupts on the AST Fourport board */ | |
752 | inb((up->port.iobase & 0xfe0) | 0x1f); | |
753 | up->port.mctrl |= TIOCM_OUT1; | |
754 | } else | |
755 | up->port.mctrl &= ~TIOCM_OUT2; | |
756 | ||
757 | sunsu_set_mctrl(&up->port, up->port.mctrl); | |
758 | spin_unlock_irqrestore(&up->port.lock, flags); | |
759 | ||
760 | /* | |
761 | * Disable break condition and FIFOs | |
762 | */ | |
763 | serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC); | |
764 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
765 | UART_FCR_CLEAR_RCVR | | |
766 | UART_FCR_CLEAR_XMIT); | |
767 | serial_outp(up, UART_FCR, 0); | |
768 | ||
769 | #ifdef CONFIG_SERIAL_8250_RSA | |
770 | /* | |
771 | * Reset the RSA board back to 115kbps compat mode. | |
772 | */ | |
773 | disable_rsa(up); | |
774 | #endif | |
775 | ||
776 | /* | |
777 | * Read data port to reset things. | |
778 | */ | |
779 | (void) serial_in(up, UART_RX); | |
780 | ||
781 | free_irq(up->port.irq, up); | |
782 | } | |
783 | ||
784 | static void | |
785 | sunsu_change_speed(struct uart_port *port, unsigned int cflag, | |
786 | unsigned int iflag, unsigned int quot) | |
787 | { | |
788 | struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; | |
789 | unsigned char cval, fcr = 0; | |
790 | unsigned long flags; | |
791 | ||
792 | switch (cflag & CSIZE) { | |
793 | case CS5: | |
794 | cval = 0x00; | |
795 | break; | |
796 | case CS6: | |
797 | cval = 0x01; | |
798 | break; | |
799 | case CS7: | |
800 | cval = 0x02; | |
801 | break; | |
802 | default: | |
803 | case CS8: | |
804 | cval = 0x03; | |
805 | break; | |
806 | } | |
807 | ||
808 | if (cflag & CSTOPB) | |
809 | cval |= 0x04; | |
810 | if (cflag & PARENB) | |
811 | cval |= UART_LCR_PARITY; | |
812 | if (!(cflag & PARODD)) | |
813 | cval |= UART_LCR_EPAR; | |
814 | #ifdef CMSPAR | |
815 | if (cflag & CMSPAR) | |
816 | cval |= UART_LCR_SPAR; | |
817 | #endif | |
818 | ||
819 | /* | |
820 | * Work around a bug in the Oxford Semiconductor 952 rev B | |
821 | * chip which causes it to seriously miscalculate baud rates | |
822 | * when DLL is 0. | |
823 | */ | |
824 | if ((quot & 0xff) == 0 && up->port.type == PORT_16C950 && | |
825 | up->rev == 0x5201) | |
826 | quot ++; | |
827 | ||
828 | if (uart_config[up->port.type].flags & UART_USE_FIFO) { | |
829 | if ((up->port.uartclk / quot) < (2400 * 16)) | |
830 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1; | |
831 | #ifdef CONFIG_SERIAL_8250_RSA | |
832 | else if (up->port.type == PORT_RSA) | |
833 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_14; | |
834 | #endif | |
835 | else | |
836 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8; | |
837 | } | |
838 | if (up->port.type == PORT_16750) | |
839 | fcr |= UART_FCR7_64BYTE; | |
840 | ||
841 | /* | |
842 | * Ok, we're now changing the port state. Do it with | |
843 | * interrupts disabled. | |
844 | */ | |
845 | spin_lock_irqsave(&up->port.lock, flags); | |
846 | ||
847 | /* | |
848 | * Update the per-port timeout. | |
849 | */ | |
850 | uart_update_timeout(port, cflag, (port->uartclk / (16 * quot))); | |
851 | ||
852 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
853 | if (iflag & INPCK) | |
854 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
855 | if (iflag & (BRKINT | PARMRK)) | |
856 | up->port.read_status_mask |= UART_LSR_BI; | |
857 | ||
858 | /* | |
859 | * Characteres to ignore | |
860 | */ | |
861 | up->port.ignore_status_mask = 0; | |
862 | if (iflag & IGNPAR) | |
863 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
864 | if (iflag & IGNBRK) { | |
865 | up->port.ignore_status_mask |= UART_LSR_BI; | |
866 | /* | |
867 | * If we're ignoring parity and break indicators, | |
868 | * ignore overruns too (for real raw support). | |
869 | */ | |
870 | if (iflag & IGNPAR) | |
871 | up->port.ignore_status_mask |= UART_LSR_OE; | |
872 | } | |
873 | ||
874 | /* | |
875 | * ignore all characters if CREAD is not set | |
876 | */ | |
877 | if ((cflag & CREAD) == 0) | |
878 | up->port.ignore_status_mask |= UART_LSR_DR; | |
879 | ||
880 | /* | |
881 | * CTS flow control flag and modem status interrupts | |
882 | */ | |
883 | up->ier &= ~UART_IER_MSI; | |
884 | if (UART_ENABLE_MS(&up->port, cflag)) | |
885 | up->ier |= UART_IER_MSI; | |
886 | ||
887 | serial_out(up, UART_IER, up->ier); | |
888 | ||
889 | if (uart_config[up->port.type].flags & UART_STARTECH) { | |
890 | serial_outp(up, UART_LCR, 0xBF); | |
891 | serial_outp(up, UART_EFR, cflag & CRTSCTS ? UART_EFR_CTS :0); | |
892 | } | |
893 | serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */ | |
894 | serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */ | |
895 | serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */ | |
896 | if (up->port.type == PORT_16750) | |
897 | serial_outp(up, UART_FCR, fcr); /* set fcr */ | |
898 | serial_outp(up, UART_LCR, cval); /* reset DLAB */ | |
899 | up->lcr = cval; /* Save LCR */ | |
900 | if (up->port.type != PORT_16750) { | |
901 | if (fcr & UART_FCR_ENABLE_FIFO) { | |
902 | /* emulated UARTs (Lucent Venus 167x) need two steps */ | |
903 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
904 | } | |
905 | serial_outp(up, UART_FCR, fcr); /* set fcr */ | |
906 | } | |
907 | ||
908 | up->cflag = cflag; | |
909 | ||
910 | spin_unlock_irqrestore(&up->port.lock, flags); | |
911 | } | |
912 | ||
913 | static void | |
914 | sunsu_set_termios(struct uart_port *port, struct termios *termios, | |
915 | struct termios *old) | |
916 | { | |
917 | unsigned int baud, quot; | |
918 | ||
919 | /* | |
920 | * Ask the core to calculate the divisor for us. | |
921 | */ | |
922 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
923 | quot = uart_get_divisor(port, baud); | |
924 | ||
925 | sunsu_change_speed(port, termios->c_cflag, termios->c_iflag, quot); | |
926 | } | |
927 | ||
928 | static void sunsu_release_port(struct uart_port *port) | |
929 | { | |
930 | } | |
931 | ||
932 | static int sunsu_request_port(struct uart_port *port) | |
933 | { | |
934 | return 0; | |
935 | } | |
936 | ||
937 | static void sunsu_config_port(struct uart_port *port, int flags) | |
938 | { | |
939 | struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; | |
940 | ||
941 | if (flags & UART_CONFIG_TYPE) { | |
942 | /* | |
943 | * We are supposed to call autoconfig here, but this requires | |
944 | * splitting all the OBP probing crap from the UART probing. | |
945 | * We'll do it when we kill sunsu.c altogether. | |
946 | */ | |
947 | port->type = up->type_probed; /* XXX */ | |
948 | } | |
949 | } | |
950 | ||
951 | static int | |
952 | sunsu_verify_port(struct uart_port *port, struct serial_struct *ser) | |
953 | { | |
954 | return -EINVAL; | |
955 | } | |
956 | ||
957 | static const char * | |
958 | sunsu_type(struct uart_port *port) | |
959 | { | |
960 | int type = port->type; | |
961 | ||
962 | if (type >= ARRAY_SIZE(uart_config)) | |
963 | type = 0; | |
964 | return uart_config[type].name; | |
965 | } | |
966 | ||
967 | static struct uart_ops sunsu_pops = { | |
968 | .tx_empty = sunsu_tx_empty, | |
969 | .set_mctrl = sunsu_set_mctrl, | |
970 | .get_mctrl = sunsu_get_mctrl, | |
971 | .stop_tx = sunsu_stop_tx, | |
972 | .start_tx = sunsu_start_tx, | |
973 | .stop_rx = sunsu_stop_rx, | |
974 | .enable_ms = sunsu_enable_ms, | |
975 | .break_ctl = sunsu_break_ctl, | |
976 | .startup = sunsu_startup, | |
977 | .shutdown = sunsu_shutdown, | |
978 | .set_termios = sunsu_set_termios, | |
979 | .type = sunsu_type, | |
980 | .release_port = sunsu_release_port, | |
981 | .request_port = sunsu_request_port, | |
982 | .config_port = sunsu_config_port, | |
983 | .verify_port = sunsu_verify_port, | |
984 | }; | |
985 | ||
986 | #define UART_NR 4 | |
987 | ||
988 | static struct uart_sunsu_port sunsu_ports[UART_NR]; | |
989 | ||
990 | #ifdef CONFIG_SERIO | |
991 | ||
992 | static DEFINE_SPINLOCK(sunsu_serio_lock); | |
993 | ||
994 | static int sunsu_serio_write(struct serio *serio, unsigned char ch) | |
995 | { | |
996 | struct uart_sunsu_port *up = serio->port_data; | |
997 | unsigned long flags; | |
998 | int lsr; | |
999 | ||
1000 | spin_lock_irqsave(&sunsu_serio_lock, flags); | |
1001 | ||
1002 | do { | |
1003 | lsr = serial_in(up, UART_LSR); | |
1004 | } while (!(lsr & UART_LSR_THRE)); | |
1005 | ||
1006 | /* Send the character out. */ | |
1007 | serial_out(up, UART_TX, ch); | |
1008 | ||
1009 | spin_unlock_irqrestore(&sunsu_serio_lock, flags); | |
1010 | ||
1011 | return 0; | |
1012 | } | |
1013 | ||
1014 | static int sunsu_serio_open(struct serio *serio) | |
1015 | { | |
1016 | struct uart_sunsu_port *up = serio->port_data; | |
1017 | unsigned long flags; | |
1018 | int ret; | |
1019 | ||
1020 | spin_lock_irqsave(&sunsu_serio_lock, flags); | |
1021 | if (!up->serio_open) { | |
1022 | up->serio_open = 1; | |
1023 | ret = 0; | |
1024 | } else | |
1025 | ret = -EBUSY; | |
1026 | spin_unlock_irqrestore(&sunsu_serio_lock, flags); | |
1027 | ||
1028 | return ret; | |
1029 | } | |
1030 | ||
1031 | static void sunsu_serio_close(struct serio *serio) | |
1032 | { | |
1033 | struct uart_sunsu_port *up = serio->port_data; | |
1034 | unsigned long flags; | |
1035 | ||
1036 | spin_lock_irqsave(&sunsu_serio_lock, flags); | |
1037 | up->serio_open = 0; | |
1038 | spin_unlock_irqrestore(&sunsu_serio_lock, flags); | |
1039 | } | |
1040 | ||
1041 | #endif /* CONFIG_SERIO */ | |
1042 | ||
1043 | static void sunsu_autoconfig(struct uart_sunsu_port *up) | |
1044 | { | |
1045 | unsigned char status1, status2, scratch, scratch2, scratch3; | |
1046 | unsigned char save_lcr, save_mcr; | |
1047 | struct linux_ebus_device *dev = NULL; | |
1048 | struct linux_ebus *ebus; | |
1049 | #ifdef CONFIG_SPARC64 | |
1050 | struct sparc_isa_bridge *isa_br; | |
1051 | struct sparc_isa_device *isa_dev; | |
1052 | #endif | |
1053 | #ifndef CONFIG_SPARC64 | |
1054 | struct linux_prom_registers reg0; | |
1055 | #endif | |
1056 | unsigned long flags; | |
1057 | ||
1058 | if (!up->port_node || !up->su_type) | |
1059 | return; | |
1060 | ||
1061 | up->type_probed = PORT_UNKNOWN; | |
1062 | up->port.iotype = SERIAL_IO_MEM; | |
1063 | ||
1064 | /* | |
1065 | * First we look for Ebus-bases su's | |
1066 | */ | |
1067 | for_each_ebus(ebus) { | |
1068 | for_each_ebusdev(dev, ebus) { | |
1069 | if (dev->prom_node == up->port_node) { | |
1070 | /* | |
1071 | * The EBus is broken on sparc; it delivers | |
1072 | * virtual addresses in resources. Oh well... | |
1073 | * This is correct on sparc64, though. | |
1074 | */ | |
1075 | up->port.membase = (char *) dev->resource[0].start; | |
1076 | /* | |
1077 | * This is correct on both architectures. | |
1078 | */ | |
1079 | up->port.mapbase = dev->resource[0].start; | |
1080 | up->port.irq = dev->irqs[0]; | |
1081 | goto ebus_done; | |
1082 | } | |
1083 | } | |
1084 | } | |
1085 | ||
1086 | #ifdef CONFIG_SPARC64 | |
1087 | for_each_isa(isa_br) { | |
1088 | for_each_isadev(isa_dev, isa_br) { | |
1089 | if (isa_dev->prom_node == up->port_node) { | |
1090 | /* Same on sparc64. Cool architecure... */ | |
1091 | up->port.membase = (char *) isa_dev->resource.start; | |
1092 | up->port.mapbase = isa_dev->resource.start; | |
1093 | up->port.irq = isa_dev->irq; | |
1094 | goto ebus_done; | |
1095 | } | |
1096 | } | |
1097 | } | |
1098 | #endif | |
1099 | ||
1100 | #ifdef CONFIG_SPARC64 | |
1101 | /* | |
1102 | * Not on Ebus, bailing. | |
1103 | */ | |
1104 | return; | |
1105 | #else | |
1106 | /* | |
1107 | * Not on Ebus, must be OBIO. | |
1108 | */ | |
1109 | if (prom_getproperty(up->port_node, "reg", | |
1110 | (char *)®0, sizeof(reg0)) == -1) { | |
1111 | prom_printf("sunsu: no \"reg\" property\n"); | |
1112 | return; | |
1113 | } | |
1114 | prom_apply_obio_ranges(®0, 1); | |
1115 | if (reg0.which_io != 0) { /* Just in case... */ | |
1116 | prom_printf("sunsu: bus number nonzero: 0x%x:%x\n", | |
1117 | reg0.which_io, reg0.phys_addr); | |
1118 | return; | |
1119 | } | |
1120 | up->port.mapbase = reg0.phys_addr; | |
1121 | if ((up->port.membase = ioremap(reg0.phys_addr, reg0.reg_size)) == 0) { | |
1122 | prom_printf("sunsu: Cannot map registers.\n"); | |
1123 | return; | |
1124 | } | |
1125 | ||
1126 | /* | |
1127 | * 0x20 is sun4m thing, Dave Redman heritage. | |
1128 | * See arch/sparc/kernel/irq.c. | |
1129 | */ | |
1130 | #define IRQ_4M(n) ((n)|0x20) | |
1131 | ||
1132 | /* | |
1133 | * There is no intr property on MrCoffee, so hardwire it. | |
1134 | */ | |
1135 | up->port.irq = IRQ_4M(13); | |
1136 | #endif | |
1137 | ||
1138 | ebus_done: | |
1139 | ||
1140 | spin_lock_irqsave(&up->port.lock, flags); | |
1141 | ||
1142 | if (!(up->port.flags & ASYNC_BUGGY_UART)) { | |
1143 | /* | |
1144 | * Do a simple existence test first; if we fail this, there's | |
1145 | * no point trying anything else. | |
1146 | * | |
1147 | * 0x80 is used as a nonsense port to prevent against false | |
1148 | * positives due to ISA bus float. The assumption is that | |
1149 | * 0x80 is a non-existent port; which should be safe since | |
1150 | * include/asm/io.h also makes this assumption. | |
1151 | */ | |
1152 | scratch = serial_inp(up, UART_IER); | |
1153 | serial_outp(up, UART_IER, 0); | |
1154 | #ifdef __i386__ | |
1155 | outb(0xff, 0x080); | |
1156 | #endif | |
1157 | scratch2 = serial_inp(up, UART_IER); | |
1158 | serial_outp(up, UART_IER, 0x0f); | |
1159 | #ifdef __i386__ | |
1160 | outb(0, 0x080); | |
1161 | #endif | |
1162 | scratch3 = serial_inp(up, UART_IER); | |
1163 | serial_outp(up, UART_IER, scratch); | |
1164 | if (scratch2 != 0 || scratch3 != 0x0F) | |
1165 | goto out; /* We failed; there's nothing here */ | |
1166 | } | |
1167 | ||
1168 | save_mcr = serial_in(up, UART_MCR); | |
1169 | save_lcr = serial_in(up, UART_LCR); | |
1170 | ||
1171 | /* | |
1172 | * Check to see if a UART is really there. Certain broken | |
1173 | * internal modems based on the Rockwell chipset fail this | |
1174 | * test, because they apparently don't implement the loopback | |
1175 | * test mode. So this test is skipped on the COM 1 through | |
1176 | * COM 4 ports. This *should* be safe, since no board | |
1177 | * manufacturer would be stupid enough to design a board | |
1178 | * that conflicts with COM 1-4 --- we hope! | |
1179 | */ | |
1180 | if (!(up->port.flags & ASYNC_SKIP_TEST)) { | |
1181 | serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A); | |
1182 | status1 = serial_inp(up, UART_MSR) & 0xF0; | |
1183 | serial_outp(up, UART_MCR, save_mcr); | |
1184 | if (status1 != 0x90) | |
1185 | goto out; /* We failed loopback test */ | |
1186 | } | |
1187 | serial_outp(up, UART_LCR, 0xBF); /* set up for StarTech test */ | |
1188 | serial_outp(up, UART_EFR, 0); /* EFR is the same as FCR */ | |
1189 | serial_outp(up, UART_LCR, 0); | |
1190 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
1191 | scratch = serial_in(up, UART_IIR) >> 6; | |
1192 | switch (scratch) { | |
1193 | case 0: | |
1194 | up->port.type = PORT_16450; | |
1195 | break; | |
1196 | case 1: | |
1197 | up->port.type = PORT_UNKNOWN; | |
1198 | break; | |
1199 | case 2: | |
1200 | up->port.type = PORT_16550; | |
1201 | break; | |
1202 | case 3: | |
1203 | up->port.type = PORT_16550A; | |
1204 | break; | |
1205 | } | |
1206 | if (up->port.type == PORT_16550A) { | |
1207 | /* Check for Startech UART's */ | |
1208 | serial_outp(up, UART_LCR, UART_LCR_DLAB); | |
1209 | if (serial_in(up, UART_EFR) == 0) { | |
1210 | up->port.type = PORT_16650; | |
1211 | } else { | |
1212 | serial_outp(up, UART_LCR, 0xBF); | |
1213 | if (serial_in(up, UART_EFR) == 0) | |
1214 | up->port.type = PORT_16650V2; | |
1215 | } | |
1216 | } | |
1217 | if (up->port.type == PORT_16550A) { | |
1218 | /* Check for TI 16750 */ | |
1219 | serial_outp(up, UART_LCR, save_lcr | UART_LCR_DLAB); | |
1220 | serial_outp(up, UART_FCR, | |
1221 | UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); | |
1222 | scratch = serial_in(up, UART_IIR) >> 5; | |
1223 | if (scratch == 7) { | |
1224 | /* | |
1225 | * If this is a 16750, and not a cheap UART | |
1226 | * clone, then it should only go into 64 byte | |
1227 | * mode if the UART_FCR7_64BYTE bit was set | |
1228 | * while UART_LCR_DLAB was latched. | |
1229 | */ | |
1230 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
1231 | serial_outp(up, UART_LCR, 0); | |
1232 | serial_outp(up, UART_FCR, | |
1233 | UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); | |
1234 | scratch = serial_in(up, UART_IIR) >> 5; | |
1235 | if (scratch == 6) | |
1236 | up->port.type = PORT_16750; | |
1237 | } | |
1238 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
1239 | } | |
1240 | serial_outp(up, UART_LCR, save_lcr); | |
1241 | if (up->port.type == PORT_16450) { | |
1242 | scratch = serial_in(up, UART_SCR); | |
1243 | serial_outp(up, UART_SCR, 0xa5); | |
1244 | status1 = serial_in(up, UART_SCR); | |
1245 | serial_outp(up, UART_SCR, 0x5a); | |
1246 | status2 = serial_in(up, UART_SCR); | |
1247 | serial_outp(up, UART_SCR, scratch); | |
1248 | ||
1249 | if ((status1 != 0xa5) || (status2 != 0x5a)) | |
1250 | up->port.type = PORT_8250; | |
1251 | } | |
1252 | ||
1253 | up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size; | |
1254 | ||
1255 | if (up->port.type == PORT_UNKNOWN) | |
1256 | goto out; | |
1257 | up->type_probed = up->port.type; /* XXX */ | |
1258 | ||
1259 | /* | |
1260 | * Reset the UART. | |
1261 | */ | |
1262 | #ifdef CONFIG_SERIAL_8250_RSA | |
1263 | if (up->port.type == PORT_RSA) | |
1264 | serial_outp(up, UART_RSA_FRR, 0); | |
1265 | #endif | |
1266 | serial_outp(up, UART_MCR, save_mcr); | |
1267 | serial_outp(up, UART_FCR, (UART_FCR_ENABLE_FIFO | | |
1268 | UART_FCR_CLEAR_RCVR | | |
1269 | UART_FCR_CLEAR_XMIT)); | |
1270 | serial_outp(up, UART_FCR, 0); | |
1271 | (void)serial_in(up, UART_RX); | |
1272 | serial_outp(up, UART_IER, 0); | |
1273 | ||
1274 | out: | |
1275 | spin_unlock_irqrestore(&up->port.lock, flags); | |
1276 | } | |
1277 | ||
1278 | static struct uart_driver sunsu_reg = { | |
1279 | .owner = THIS_MODULE, | |
1280 | .driver_name = "serial", | |
1281 | .devfs_name = "tts/", | |
1282 | .dev_name = "ttyS", | |
1283 | .major = TTY_MAJOR, | |
1284 | }; | |
1285 | ||
1286 | static int __init sunsu_kbd_ms_init(struct uart_sunsu_port *up, int channel) | |
1287 | { | |
1288 | #ifdef CONFIG_SERIO | |
1289 | struct serio *serio; | |
1290 | #endif | |
1291 | ||
1292 | up->port.line = channel; | |
1293 | up->port.type = PORT_UNKNOWN; | |
1294 | up->port.uartclk = (SU_BASE_BAUD * 16); | |
1295 | ||
1296 | if (up->su_type == SU_PORT_KBD) | |
1297 | up->cflag = B1200 | CS8 | CLOCAL | CREAD; | |
1298 | else | |
1299 | up->cflag = B4800 | CS8 | CLOCAL | CREAD; | |
1300 | ||
1301 | sunsu_autoconfig(up); | |
1302 | if (up->port.type == PORT_UNKNOWN) | |
1303 | return -1; | |
1304 | ||
1305 | printk(KERN_INFO "su%d at 0x%p (irq = %s) is a %s\n", | |
1306 | channel, | |
1307 | up->port.membase, __irq_itoa(up->port.irq), | |
1308 | sunsu_type(&up->port)); | |
1309 | ||
1310 | #ifdef CONFIG_SERIO | |
1311 | up->serio = serio = kmalloc(sizeof(struct serio), GFP_KERNEL); | |
1312 | if (serio) { | |
1313 | memset(serio, 0, sizeof(*serio)); | |
1314 | ||
1315 | serio->port_data = up; | |
1316 | ||
1317 | serio->id.type = SERIO_RS232; | |
1318 | if (up->su_type == SU_PORT_KBD) { | |
1319 | serio->id.proto = SERIO_SUNKBD; | |
1320 | strlcpy(serio->name, "sukbd", sizeof(serio->name)); | |
1321 | } else { | |
1322 | serio->id.proto = SERIO_SUN; | |
1323 | serio->id.extra = 1; | |
1324 | strlcpy(serio->name, "sums", sizeof(serio->name)); | |
1325 | } | |
1326 | strlcpy(serio->phys, (channel == 0 ? "su/serio0" : "su/serio1"), | |
1327 | sizeof(serio->phys)); | |
1328 | ||
1329 | serio->write = sunsu_serio_write; | |
1330 | serio->open = sunsu_serio_open; | |
1331 | serio->close = sunsu_serio_close; | |
1332 | ||
1333 | serio_register_port(serio); | |
1334 | } else { | |
1335 | printk(KERN_WARNING "su%d: not enough memory for serio port\n", | |
1336 | channel); | |
1337 | } | |
1338 | #endif | |
1339 | ||
1340 | sunsu_startup(&up->port); | |
1341 | return 0; | |
1342 | } | |
1343 | ||
1344 | /* | |
1345 | * ------------------------------------------------------------ | |
1346 | * Serial console driver | |
1347 | * ------------------------------------------------------------ | |
1348 | */ | |
1349 | ||
1350 | #ifdef CONFIG_SERIAL_SUNSU_CONSOLE | |
1351 | ||
1352 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) | |
1353 | ||
1354 | /* | |
1355 | * Wait for transmitter & holding register to empty | |
1356 | */ | |
1357 | static __inline__ void wait_for_xmitr(struct uart_sunsu_port *up) | |
1358 | { | |
1359 | unsigned int status, tmout = 10000; | |
1360 | ||
1361 | /* Wait up to 10ms for the character(s) to be sent. */ | |
1362 | do { | |
1363 | status = serial_in(up, UART_LSR); | |
1364 | ||
1365 | if (status & UART_LSR_BI) | |
1366 | up->lsr_break_flag = UART_LSR_BI; | |
1367 | ||
1368 | if (--tmout == 0) | |
1369 | break; | |
1370 | udelay(1); | |
1371 | } while ((status & BOTH_EMPTY) != BOTH_EMPTY); | |
1372 | ||
1373 | /* Wait up to 1s for flow control if necessary */ | |
1374 | if (up->port.flags & ASYNC_CONS_FLOW) { | |
1375 | tmout = 1000000; | |
1376 | while (--tmout && | |
1377 | ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0)) | |
1378 | udelay(1); | |
1379 | } | |
1380 | } | |
1381 | ||
1382 | /* | |
1383 | * Print a string to the serial port trying not to disturb | |
1384 | * any possible real use of the port... | |
1385 | */ | |
1386 | static void sunsu_console_write(struct console *co, const char *s, | |
1387 | unsigned int count) | |
1388 | { | |
1389 | struct uart_sunsu_port *up = &sunsu_ports[co->index]; | |
1390 | unsigned int ier; | |
1391 | int i; | |
1392 | ||
1393 | /* | |
1394 | * First save the UER then disable the interrupts | |
1395 | */ | |
1396 | ier = serial_in(up, UART_IER); | |
1397 | serial_out(up, UART_IER, 0); | |
1398 | ||
1399 | /* | |
1400 | * Now, do each character | |
1401 | */ | |
1402 | for (i = 0; i < count; i++, s++) { | |
1403 | wait_for_xmitr(up); | |
1404 | ||
1405 | /* | |
1406 | * Send the character out. | |
1407 | * If a LF, also do CR... | |
1408 | */ | |
1409 | serial_out(up, UART_TX, *s); | |
1410 | if (*s == 10) { | |
1411 | wait_for_xmitr(up); | |
1412 | serial_out(up, UART_TX, 13); | |
1413 | } | |
1414 | } | |
1415 | ||
1416 | /* | |
1417 | * Finally, wait for transmitter to become empty | |
1418 | * and restore the IER | |
1419 | */ | |
1420 | wait_for_xmitr(up); | |
1421 | serial_out(up, UART_IER, ier); | |
1422 | } | |
1423 | ||
1424 | /* | |
1425 | * Setup initial baud/bits/parity. We do two things here: | |
1426 | * - construct a cflag setting for the first su_open() | |
1427 | * - initialize the serial port | |
1428 | * Return non-zero if we didn't find a serial port. | |
1429 | */ | |
1430 | static int __init sunsu_console_setup(struct console *co, char *options) | |
1431 | { | |
1432 | struct uart_port *port; | |
1433 | int baud = 9600; | |
1434 | int bits = 8; | |
1435 | int parity = 'n'; | |
1436 | int flow = 'n'; | |
1437 | ||
1438 | printk("Console: ttyS%d (SU)\n", | |
1439 | (sunsu_reg.minor - 64) + co->index); | |
1440 | ||
1441 | /* | |
1442 | * Check whether an invalid uart number has been specified, and | |
1443 | * if so, search for the first available port that does have | |
1444 | * console support. | |
1445 | */ | |
1446 | if (co->index >= UART_NR) | |
1447 | co->index = 0; | |
1448 | port = &sunsu_ports[co->index].port; | |
1449 | ||
1450 | /* | |
1451 | * Temporary fix. | |
1452 | */ | |
1453 | spin_lock_init(&port->lock); | |
1454 | ||
1455 | if (options) | |
1456 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1457 | ||
1458 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1459 | } | |
1460 | ||
1461 | static struct console sunsu_cons = { | |
1462 | .name = "ttyS", | |
1463 | .write = sunsu_console_write, | |
1464 | .device = uart_console_device, | |
1465 | .setup = sunsu_console_setup, | |
1466 | .flags = CON_PRINTBUFFER, | |
1467 | .index = -1, | |
1468 | .data = &sunsu_reg, | |
1469 | }; | |
1470 | #define SUNSU_CONSOLE (&sunsu_cons) | |
1471 | ||
1472 | /* | |
1473 | * Register console. | |
1474 | */ | |
1475 | ||
1476 | static int __init sunsu_serial_console_init(void) | |
1477 | { | |
1478 | int i; | |
1479 | ||
1480 | if (con_is_present()) | |
1481 | return 0; | |
1482 | ||
1483 | for (i = 0; i < UART_NR; i++) { | |
1484 | int this_minor = sunsu_reg.minor + i; | |
1485 | ||
1486 | if ((this_minor - 64) == (serial_console - 1)) | |
1487 | break; | |
1488 | } | |
1489 | if (i == UART_NR) | |
1490 | return 0; | |
1491 | if (sunsu_ports[i].port_node == 0) | |
1492 | return 0; | |
1493 | ||
1494 | sunsu_cons.index = i; | |
1495 | register_console(&sunsu_cons); | |
1496 | return 0; | |
1497 | } | |
1498 | #else | |
1499 | #define SUNSU_CONSOLE (NULL) | |
1500 | #define sunsu_serial_console_init() do { } while (0) | |
1501 | #endif | |
1502 | ||
1503 | static int __init sunsu_serial_init(void) | |
1504 | { | |
1505 | int instance, ret, i; | |
1506 | ||
1507 | /* How many instances do we need? */ | |
1508 | instance = 0; | |
1509 | for (i = 0; i < UART_NR; i++) { | |
1510 | struct uart_sunsu_port *up = &sunsu_ports[i]; | |
1511 | ||
1512 | if (up->su_type == SU_PORT_MS || | |
1513 | up->su_type == SU_PORT_KBD) | |
1514 | continue; | |
1515 | ||
1516 | up->port.flags |= ASYNC_BOOT_AUTOCONF; | |
1517 | up->port.type = PORT_UNKNOWN; | |
1518 | up->port.uartclk = (SU_BASE_BAUD * 16); | |
1519 | ||
1520 | sunsu_autoconfig(up); | |
1521 | if (up->port.type == PORT_UNKNOWN) | |
1522 | continue; | |
1523 | ||
1524 | up->port.line = instance++; | |
1525 | up->port.ops = &sunsu_pops; | |
1526 | } | |
1527 | ||
1528 | sunsu_reg.minor = sunserial_current_minor; | |
1529 | sunserial_current_minor += instance; | |
1530 | ||
1531 | sunsu_reg.nr = instance; | |
1532 | sunsu_reg.cons = SUNSU_CONSOLE; | |
1533 | ||
1534 | ret = uart_register_driver(&sunsu_reg); | |
1535 | if (ret < 0) | |
1536 | return ret; | |
1537 | ||
1538 | sunsu_serial_console_init(); | |
1539 | for (i = 0; i < UART_NR; i++) { | |
1540 | struct uart_sunsu_port *up = &sunsu_ports[i]; | |
1541 | ||
1542 | /* Do not register Keyboard/Mouse lines with UART | |
1543 | * layer. | |
1544 | */ | |
1545 | if (up->su_type == SU_PORT_MS || | |
1546 | up->su_type == SU_PORT_KBD) | |
1547 | continue; | |
1548 | ||
1549 | if (up->port.type == PORT_UNKNOWN) | |
1550 | continue; | |
1551 | ||
1552 | uart_add_one_port(&sunsu_reg, &up->port); | |
1553 | } | |
1554 | ||
1555 | return 0; | |
1556 | } | |
1557 | ||
1558 | static int su_node_ok(int node, char *name, int namelen) | |
1559 | { | |
1560 | if (strncmp(name, "su", namelen) == 0 || | |
1561 | strncmp(name, "su_pnp", namelen) == 0) | |
1562 | return 1; | |
1563 | ||
1564 | if (strncmp(name, "serial", namelen) == 0) { | |
1565 | char compat[32]; | |
1566 | int clen; | |
1567 | ||
1568 | /* Is it _really_ a 'su' device? */ | |
1569 | clen = prom_getproperty(node, "compatible", compat, sizeof(compat)); | |
1570 | if (clen > 0) { | |
1571 | if (strncmp(compat, "sab82532", 8) == 0) { | |
1572 | /* Nope, Siemens serial, not for us. */ | |
1573 | return 0; | |
1574 | } | |
1575 | } | |
1576 | return 1; | |
1577 | } | |
1578 | ||
1579 | return 0; | |
1580 | } | |
1581 | ||
1582 | #define SU_PROPSIZE 128 | |
1583 | ||
1584 | /* | |
1585 | * Scan status structure. | |
1586 | * "prop" is a local variable but it eats stack to keep it in each | |
1587 | * stack frame of a recursive procedure. | |
1588 | */ | |
1589 | struct su_probe_scan { | |
1590 | int msnode, kbnode; /* PROM nodes for mouse and keyboard */ | |
1591 | int msx, kbx; /* minors for mouse and keyboard */ | |
1592 | int devices; /* scan index */ | |
1593 | char prop[SU_PROPSIZE]; | |
1594 | }; | |
1595 | ||
1596 | /* | |
1597 | * We have several platforms which present 'su' in different parts | |
1598 | * of the device tree. 'su' may be found under obio, ebus, isa and pci. | |
1599 | * We walk over the tree and find them wherever PROM hides them. | |
1600 | */ | |
1601 | static void __init su_probe_any(struct su_probe_scan *t, int sunode) | |
1602 | { | |
1603 | struct uart_sunsu_port *up; | |
1604 | int len; | |
1605 | ||
1606 | if (t->devices >= UART_NR) | |
1607 | return; | |
1608 | ||
1609 | for (; sunode != 0; sunode = prom_getsibling(sunode)) { | |
1610 | len = prom_getproperty(sunode, "name", t->prop, SU_PROPSIZE); | |
1611 | if (len <= 1) | |
1612 | continue; /* Broken PROM node */ | |
1613 | ||
1614 | if (su_node_ok(sunode, t->prop, len)) { | |
1615 | up = &sunsu_ports[t->devices]; | |
1616 | if (t->kbnode != 0 && sunode == t->kbnode) { | |
1617 | t->kbx = t->devices; | |
1618 | up->su_type = SU_PORT_KBD; | |
1619 | } else if (t->msnode != 0 && sunode == t->msnode) { | |
1620 | t->msx = t->devices; | |
1621 | up->su_type = SU_PORT_MS; | |
1622 | } else { | |
1623 | #ifdef CONFIG_SPARC64 | |
1624 | /* | |
1625 | * Do not attempt to use the truncated | |
1626 | * keyboard/mouse ports as serial ports | |
1627 | * on Ultras with PC keyboard attached. | |
1628 | */ | |
1629 | if (prom_getbool(sunode, "mouse")) | |
1630 | continue; | |
1631 | if (prom_getbool(sunode, "keyboard")) | |
1632 | continue; | |
1633 | #endif | |
1634 | up->su_type = SU_PORT_PORT; | |
1635 | } | |
1636 | up->port_node = sunode; | |
1637 | ++t->devices; | |
1638 | } else { | |
1639 | su_probe_any(t, prom_getchild(sunode)); | |
1640 | } | |
1641 | } | |
1642 | } | |
1643 | ||
1644 | static int __init sunsu_probe(void) | |
1645 | { | |
1646 | int node; | |
1647 | int len; | |
1648 | struct su_probe_scan scan; | |
1649 | ||
1650 | /* | |
1651 | * First, we scan the tree. | |
1652 | */ | |
1653 | scan.devices = 0; | |
1654 | scan.msx = -1; | |
1655 | scan.kbx = -1; | |
1656 | scan.kbnode = 0; | |
1657 | scan.msnode = 0; | |
1658 | ||
1659 | /* | |
1660 | * Get the nodes for keyboard and mouse from 'aliases'... | |
1661 | */ | |
1662 | node = prom_getchild(prom_root_node); | |
1663 | node = prom_searchsiblings(node, "aliases"); | |
1664 | if (node != 0) { | |
1665 | len = prom_getproperty(node, "keyboard", scan.prop, SU_PROPSIZE); | |
1666 | if (len > 0) { | |
1667 | scan.prop[len] = 0; | |
1668 | scan.kbnode = prom_finddevice(scan.prop); | |
1669 | } | |
1670 | ||
1671 | len = prom_getproperty(node, "mouse", scan.prop, SU_PROPSIZE); | |
1672 | if (len > 0) { | |
1673 | scan.prop[len] = 0; | |
1674 | scan.msnode = prom_finddevice(scan.prop); | |
1675 | } | |
1676 | } | |
1677 | ||
1678 | su_probe_any(&scan, prom_getchild(prom_root_node)); | |
1679 | ||
1680 | /* | |
1681 | * Second, we process the special case of keyboard and mouse. | |
1682 | * | |
1683 | * Currently if we got keyboard and mouse hooked to "su" ports | |
1684 | * we do not use any possible remaining "su" as a serial port. | |
1685 | * Thus, we ignore values of .msx and .kbx, then compact ports. | |
1686 | */ | |
1687 | if (scan.msx != -1 && scan.kbx != -1) { | |
1688 | sunsu_ports[0].su_type = SU_PORT_MS; | |
1689 | sunsu_ports[0].port_node = scan.msnode; | |
1690 | sunsu_kbd_ms_init(&sunsu_ports[0], 0); | |
1691 | ||
1692 | sunsu_ports[1].su_type = SU_PORT_KBD; | |
1693 | sunsu_ports[1].port_node = scan.kbnode; | |
1694 | sunsu_kbd_ms_init(&sunsu_ports[1], 1); | |
1695 | ||
1696 | return 0; | |
1697 | } | |
1698 | ||
1699 | if (scan.msx != -1 || scan.kbx != -1) { | |
1700 | printk("sunsu_probe: cannot match keyboard and mouse, confused\n"); | |
1701 | return -ENODEV; | |
1702 | } | |
1703 | ||
1704 | if (scan.devices == 0) | |
1705 | return -ENODEV; | |
1706 | ||
1707 | /* | |
1708 | * Console must be initiated after the generic initialization. | |
1709 | */ | |
1710 | sunsu_serial_init(); | |
1711 | ||
1712 | return 0; | |
1713 | } | |
1714 | ||
1715 | static void __exit sunsu_exit(void) | |
1716 | { | |
1717 | int i, saw_uart; | |
1718 | ||
1719 | saw_uart = 0; | |
1720 | for (i = 0; i < UART_NR; i++) { | |
1721 | struct uart_sunsu_port *up = &sunsu_ports[i]; | |
1722 | ||
1723 | if (up->su_type == SU_PORT_MS || | |
1724 | up->su_type == SU_PORT_KBD) { | |
1725 | #ifdef CONFIG_SERIO | |
1726 | if (up->serio) { | |
1727 | serio_unregister_port(up->serio); | |
1728 | up->serio = NULL; | |
1729 | } | |
1730 | #endif | |
1731 | } else if (up->port.type != PORT_UNKNOWN) { | |
1732 | uart_remove_one_port(&sunsu_reg, &up->port); | |
1733 | saw_uart++; | |
1734 | } | |
1735 | } | |
1736 | ||
1737 | if (saw_uart) | |
1738 | uart_unregister_driver(&sunsu_reg); | |
1739 | } | |
1740 | ||
1741 | module_init(sunsu_probe); | |
1742 | module_exit(sunsu_exit); |