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e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
a0d2642e | 3 | * Copyright (C) 2013, Intel Corporation |
e0c9905e SS |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/errno.h> | |
cbfd6a21 | 25 | #include <linux/err.h> |
e0c9905e SS |
26 | #include <linux/interrupt.h> |
27 | #include <linux/platform_device.h> | |
8348c259 | 28 | #include <linux/spi/pxa2xx_spi.h> |
e0c9905e SS |
29 | #include <linux/spi/spi.h> |
30 | #include <linux/workqueue.h> | |
e0c9905e | 31 | #include <linux/delay.h> |
a7bb3909 | 32 | #include <linux/gpio.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
3343b7a6 | 34 | #include <linux/clk.h> |
7d94a505 | 35 | #include <linux/pm_runtime.h> |
a3496855 | 36 | #include <linux/acpi.h> |
e0c9905e SS |
37 | |
38 | #include <asm/io.h> | |
39 | #include <asm/irq.h> | |
e0c9905e | 40 | #include <asm/delay.h> |
e0c9905e | 41 | |
cd7bed00 | 42 | #include "spi-pxa2xx.h" |
e0c9905e SS |
43 | |
44 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 45 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 46 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 47 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e SS |
48 | |
49 | #define MAX_BUSES 3 | |
50 | ||
f1f640a9 VS |
51 | #define TIMOUT_DFLT 1000 |
52 | ||
b97c74bd NF |
53 | /* |
54 | * for testing SSCR1 changes that require SSP restart, basically | |
55 | * everything except the service and interrupt enables, the pxa270 developer | |
56 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
57 | * list, but the PXA255 dev man says all bits without really meaning the | |
58 | * service and interrupt enables | |
59 | */ | |
60 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 61 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
62 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
63 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
64 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
65 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 66 | |
a0d2642e MW |
67 | #define LPSS_RX_THRESH_DFLT 64 |
68 | #define LPSS_TX_LOTHRESH_DFLT 160 | |
69 | #define LPSS_TX_HITHRESH_DFLT 224 | |
70 | ||
71 | /* Offset from drv_data->lpss_base */ | |
1de70612 MW |
72 | #define GENERAL_REG 0x08 |
73 | #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) | |
0054e28d | 74 | #define SSP_REG 0x0c |
a0d2642e MW |
75 | #define SPI_CS_CONTROL 0x18 |
76 | #define SPI_CS_CONTROL_SW_MODE BIT(0) | |
77 | #define SPI_CS_CONTROL_CS_HIGH BIT(1) | |
78 | ||
79 | static bool is_lpss_ssp(const struct driver_data *drv_data) | |
80 | { | |
81 | return drv_data->ssp_type == LPSS_SSP; | |
82 | } | |
83 | ||
84 | /* | |
85 | * Read and write LPSS SSP private registers. Caller must first check that | |
86 | * is_lpss_ssp() returns true before these can be called. | |
87 | */ | |
88 | static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) | |
89 | { | |
90 | WARN_ON(!drv_data->lpss_base); | |
91 | return readl(drv_data->lpss_base + offset); | |
92 | } | |
93 | ||
94 | static void __lpss_ssp_write_priv(struct driver_data *drv_data, | |
95 | unsigned offset, u32 value) | |
96 | { | |
97 | WARN_ON(!drv_data->lpss_base); | |
98 | writel(value, drv_data->lpss_base + offset); | |
99 | } | |
100 | ||
101 | /* | |
102 | * lpss_ssp_setup - perform LPSS SSP specific setup | |
103 | * @drv_data: pointer to the driver private data | |
104 | * | |
105 | * Perform LPSS SSP specific setup. This function must be called first if | |
106 | * one is going to use LPSS SSP private registers. | |
107 | */ | |
108 | static void lpss_ssp_setup(struct driver_data *drv_data) | |
109 | { | |
110 | unsigned offset = 0x400; | |
111 | u32 value, orig; | |
112 | ||
113 | if (!is_lpss_ssp(drv_data)) | |
114 | return; | |
115 | ||
116 | /* | |
117 | * Perform auto-detection of the LPSS SSP private registers. They | |
118 | * can be either at 1k or 2k offset from the base address. | |
119 | */ | |
120 | orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
121 | ||
122 | value = orig | SPI_CS_CONTROL_SW_MODE; | |
123 | writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
124 | value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
125 | if (value != (orig | SPI_CS_CONTROL_SW_MODE)) { | |
126 | offset = 0x800; | |
127 | goto detection_done; | |
128 | } | |
129 | ||
130 | value &= ~SPI_CS_CONTROL_SW_MODE; | |
131 | writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
132 | value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
133 | if (value != orig) { | |
134 | offset = 0x800; | |
135 | goto detection_done; | |
136 | } | |
137 | ||
138 | detection_done: | |
139 | /* Now set the LPSS base */ | |
140 | drv_data->lpss_base = drv_data->ioaddr + offset; | |
141 | ||
142 | /* Enable software chip select control */ | |
143 | value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; | |
144 | __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); | |
0054e28d MW |
145 | |
146 | /* Enable multiblock DMA transfers */ | |
1de70612 | 147 | if (drv_data->master_info->enable_dma) { |
0054e28d | 148 | __lpss_ssp_write_priv(drv_data, SSP_REG, 1); |
1de70612 MW |
149 | |
150 | value = __lpss_ssp_read_priv(drv_data, GENERAL_REG); | |
151 | value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE; | |
152 | __lpss_ssp_write_priv(drv_data, GENERAL_REG, value); | |
153 | } | |
a0d2642e MW |
154 | } |
155 | ||
156 | static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) | |
157 | { | |
158 | u32 value; | |
159 | ||
160 | if (!is_lpss_ssp(drv_data)) | |
161 | return; | |
162 | ||
163 | value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL); | |
164 | if (enable) | |
165 | value &= ~SPI_CS_CONTROL_CS_HIGH; | |
166 | else | |
167 | value |= SPI_CS_CONTROL_CS_HIGH; | |
168 | __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); | |
169 | } | |
170 | ||
a7bb3909 EM |
171 | static void cs_assert(struct driver_data *drv_data) |
172 | { | |
173 | struct chip_data *chip = drv_data->cur_chip; | |
174 | ||
2a8626a9 SAS |
175 | if (drv_data->ssp_type == CE4100_SSP) { |
176 | write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr); | |
177 | return; | |
178 | } | |
179 | ||
a7bb3909 EM |
180 | if (chip->cs_control) { |
181 | chip->cs_control(PXA2XX_CS_ASSERT); | |
182 | return; | |
183 | } | |
184 | ||
a0d2642e | 185 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 186 | gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); |
a0d2642e MW |
187 | return; |
188 | } | |
189 | ||
190 | lpss_ssp_cs_control(drv_data, true); | |
a7bb3909 EM |
191 | } |
192 | ||
193 | static void cs_deassert(struct driver_data *drv_data) | |
194 | { | |
195 | struct chip_data *chip = drv_data->cur_chip; | |
196 | ||
2a8626a9 SAS |
197 | if (drv_data->ssp_type == CE4100_SSP) |
198 | return; | |
199 | ||
a7bb3909 | 200 | if (chip->cs_control) { |
2b2562d3 | 201 | chip->cs_control(PXA2XX_CS_DEASSERT); |
a7bb3909 EM |
202 | return; |
203 | } | |
204 | ||
a0d2642e | 205 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 206 | gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); |
a0d2642e MW |
207 | return; |
208 | } | |
209 | ||
210 | lpss_ssp_cs_control(drv_data, false); | |
a7bb3909 EM |
211 | } |
212 | ||
cd7bed00 | 213 | int pxa2xx_spi_flush(struct driver_data *drv_data) |
e0c9905e SS |
214 | { |
215 | unsigned long limit = loops_per_jiffy << 1; | |
216 | ||
cf43369d | 217 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
218 | |
219 | do { | |
220 | while (read_SSSR(reg) & SSSR_RNE) { | |
221 | read_SSDR(reg); | |
222 | } | |
306c68aa | 223 | } while ((read_SSSR(reg) & SSSR_BSY) && --limit); |
2a8626a9 | 224 | write_SSSR_CS(drv_data, SSSR_ROR); |
e0c9905e SS |
225 | |
226 | return limit; | |
227 | } | |
228 | ||
8d94cc50 | 229 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 230 | { |
cf43369d | 231 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 232 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 233 | |
4a25605f | 234 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
235 | || (drv_data->tx == drv_data->tx_end)) |
236 | return 0; | |
237 | ||
238 | write_SSDR(0, reg); | |
239 | drv_data->tx += n_bytes; | |
240 | ||
241 | return 1; | |
e0c9905e SS |
242 | } |
243 | ||
8d94cc50 | 244 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 245 | { |
cf43369d | 246 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 247 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e SS |
248 | |
249 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 250 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
251 | read_SSDR(reg); |
252 | drv_data->rx += n_bytes; | |
253 | } | |
8d94cc50 SS |
254 | |
255 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
256 | } |
257 | ||
8d94cc50 | 258 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 259 | { |
cf43369d | 260 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 261 | |
4a25605f | 262 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
263 | || (drv_data->tx == drv_data->tx_end)) |
264 | return 0; | |
265 | ||
266 | write_SSDR(*(u8 *)(drv_data->tx), reg); | |
267 | ++drv_data->tx; | |
268 | ||
269 | return 1; | |
e0c9905e SS |
270 | } |
271 | ||
8d94cc50 | 272 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 273 | { |
cf43369d | 274 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
275 | |
276 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 277 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
278 | *(u8 *)(drv_data->rx) = read_SSDR(reg); |
279 | ++drv_data->rx; | |
280 | } | |
8d94cc50 SS |
281 | |
282 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
283 | } |
284 | ||
8d94cc50 | 285 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 286 | { |
cf43369d | 287 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 288 | |
4a25605f | 289 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
290 | || (drv_data->tx == drv_data->tx_end)) |
291 | return 0; | |
292 | ||
293 | write_SSDR(*(u16 *)(drv_data->tx), reg); | |
294 | drv_data->tx += 2; | |
295 | ||
296 | return 1; | |
e0c9905e SS |
297 | } |
298 | ||
8d94cc50 | 299 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 300 | { |
cf43369d | 301 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
302 | |
303 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 304 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
305 | *(u16 *)(drv_data->rx) = read_SSDR(reg); |
306 | drv_data->rx += 2; | |
307 | } | |
8d94cc50 SS |
308 | |
309 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 310 | } |
8d94cc50 SS |
311 | |
312 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 313 | { |
cf43369d | 314 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 315 | |
4a25605f | 316 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
317 | || (drv_data->tx == drv_data->tx_end)) |
318 | return 0; | |
319 | ||
320 | write_SSDR(*(u32 *)(drv_data->tx), reg); | |
321 | drv_data->tx += 4; | |
322 | ||
323 | return 1; | |
e0c9905e SS |
324 | } |
325 | ||
8d94cc50 | 326 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 327 | { |
cf43369d | 328 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
329 | |
330 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 331 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
332 | *(u32 *)(drv_data->rx) = read_SSDR(reg); |
333 | drv_data->rx += 4; | |
334 | } | |
8d94cc50 SS |
335 | |
336 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
337 | } |
338 | ||
cd7bed00 | 339 | void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) |
e0c9905e SS |
340 | { |
341 | struct spi_message *msg = drv_data->cur_msg; | |
342 | struct spi_transfer *trans = drv_data->cur_transfer; | |
343 | ||
344 | /* Move to next transfer */ | |
345 | if (trans->transfer_list.next != &msg->transfers) { | |
346 | drv_data->cur_transfer = | |
347 | list_entry(trans->transfer_list.next, | |
348 | struct spi_transfer, | |
349 | transfer_list); | |
350 | return RUNNING_STATE; | |
351 | } else | |
352 | return DONE_STATE; | |
353 | } | |
354 | ||
e0c9905e | 355 | /* caller already set message->status; dma and pio irqs are blocked */ |
5daa3ba0 | 356 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
357 | { |
358 | struct spi_transfer* last_transfer; | |
5daa3ba0 | 359 | struct spi_message *msg; |
e0c9905e | 360 | |
5daa3ba0 SS |
361 | msg = drv_data->cur_msg; |
362 | drv_data->cur_msg = NULL; | |
363 | drv_data->cur_transfer = NULL; | |
5daa3ba0 SS |
364 | |
365 | last_transfer = list_entry(msg->transfers.prev, | |
e0c9905e SS |
366 | struct spi_transfer, |
367 | transfer_list); | |
368 | ||
8423597d NF |
369 | /* Delay if requested before any change in chip select */ |
370 | if (last_transfer->delay_usecs) | |
371 | udelay(last_transfer->delay_usecs); | |
372 | ||
373 | /* Drop chip select UNLESS cs_change is true or we are returning | |
374 | * a message with an error, or next message is for another chip | |
375 | */ | |
e0c9905e | 376 | if (!last_transfer->cs_change) |
a7bb3909 | 377 | cs_deassert(drv_data); |
8423597d NF |
378 | else { |
379 | struct spi_message *next_msg; | |
380 | ||
381 | /* Holding of cs was hinted, but we need to make sure | |
382 | * the next message is for the same chip. Don't waste | |
383 | * time with the following tests unless this was hinted. | |
384 | * | |
385 | * We cannot postpone this until pump_messages, because | |
386 | * after calling msg->complete (below) the driver that | |
387 | * sent the current message could be unloaded, which | |
388 | * could invalidate the cs_control() callback... | |
389 | */ | |
390 | ||
391 | /* get a pointer to the next message, if any */ | |
7f86bde9 | 392 | next_msg = spi_get_next_queued_message(drv_data->master); |
8423597d NF |
393 | |
394 | /* see if the next and current messages point | |
395 | * to the same chip | |
396 | */ | |
397 | if (next_msg && next_msg->spi != msg->spi) | |
398 | next_msg = NULL; | |
399 | if (!next_msg || msg->state == ERROR_STATE) | |
a7bb3909 | 400 | cs_deassert(drv_data); |
8423597d | 401 | } |
e0c9905e | 402 | |
7f86bde9 | 403 | spi_finalize_current_message(drv_data->master); |
a7bb3909 | 404 | drv_data->cur_chip = NULL; |
e0c9905e SS |
405 | } |
406 | ||
579d3bb2 SAS |
407 | static void reset_sccr1(struct driver_data *drv_data) |
408 | { | |
409 | void __iomem *reg = drv_data->ioaddr; | |
410 | struct chip_data *chip = drv_data->cur_chip; | |
411 | u32 sccr1_reg; | |
412 | ||
413 | sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1; | |
414 | sccr1_reg &= ~SSCR1_RFT; | |
415 | sccr1_reg |= chip->threshold; | |
416 | write_SSCR1(sccr1_reg, reg); | |
417 | } | |
418 | ||
8d94cc50 | 419 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 420 | { |
cf43369d | 421 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 422 | |
8d94cc50 | 423 | /* Stop and reset SSP */ |
2a8626a9 | 424 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 425 | reset_sccr1(drv_data); |
2a8626a9 | 426 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 427 | write_SSTO(0, reg); |
cd7bed00 | 428 | pxa2xx_spi_flush(drv_data); |
8d94cc50 | 429 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); |
e0c9905e | 430 | |
8d94cc50 | 431 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 432 | |
8d94cc50 SS |
433 | drv_data->cur_msg->state = ERROR_STATE; |
434 | tasklet_schedule(&drv_data->pump_transfers); | |
435 | } | |
5daa3ba0 | 436 | |
8d94cc50 SS |
437 | static void int_transfer_complete(struct driver_data *drv_data) |
438 | { | |
cf43369d | 439 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 440 | |
8d94cc50 | 441 | /* Stop SSP */ |
2a8626a9 | 442 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 443 | reset_sccr1(drv_data); |
2a8626a9 | 444 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 445 | write_SSTO(0, reg); |
e0c9905e | 446 | |
25985edc | 447 | /* Update total byte transferred return count actual bytes read */ |
8d94cc50 SS |
448 | drv_data->cur_msg->actual_length += drv_data->len - |
449 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 450 | |
8423597d NF |
451 | /* Transfer delays and chip select release are |
452 | * handled in pump_transfers or giveback | |
453 | */ | |
e0c9905e | 454 | |
8d94cc50 | 455 | /* Move to next transfer */ |
cd7bed00 | 456 | drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); |
e0c9905e | 457 | |
8d94cc50 SS |
458 | /* Schedule transfer tasklet */ |
459 | tasklet_schedule(&drv_data->pump_transfers); | |
460 | } | |
e0c9905e | 461 | |
8d94cc50 SS |
462 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
463 | { | |
cf43369d | 464 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 465 | |
8d94cc50 SS |
466 | u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? |
467 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 468 | |
8d94cc50 | 469 | u32 irq_status = read_SSSR(reg) & irq_mask; |
e0c9905e | 470 | |
8d94cc50 SS |
471 | if (irq_status & SSSR_ROR) { |
472 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
473 | return IRQ_HANDLED; | |
474 | } | |
e0c9905e | 475 | |
8d94cc50 SS |
476 | if (irq_status & SSSR_TINT) { |
477 | write_SSSR(SSSR_TINT, reg); | |
478 | if (drv_data->read(drv_data)) { | |
479 | int_transfer_complete(drv_data); | |
480 | return IRQ_HANDLED; | |
481 | } | |
482 | } | |
e0c9905e | 483 | |
8d94cc50 SS |
484 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
485 | do { | |
486 | if (drv_data->read(drv_data)) { | |
487 | int_transfer_complete(drv_data); | |
488 | return IRQ_HANDLED; | |
489 | } | |
490 | } while (drv_data->write(drv_data)); | |
e0c9905e | 491 | |
8d94cc50 SS |
492 | if (drv_data->read(drv_data)) { |
493 | int_transfer_complete(drv_data); | |
494 | return IRQ_HANDLED; | |
495 | } | |
e0c9905e | 496 | |
8d94cc50 | 497 | if (drv_data->tx == drv_data->tx_end) { |
579d3bb2 SAS |
498 | u32 bytes_left; |
499 | u32 sccr1_reg; | |
500 | ||
501 | sccr1_reg = read_SSCR1(reg); | |
502 | sccr1_reg &= ~SSCR1_TIE; | |
503 | ||
504 | /* | |
505 | * PXA25x_SSP has no timeout, set up rx threshould for the | |
25985edc | 506 | * remaining RX bytes. |
579d3bb2 | 507 | */ |
2a8626a9 | 508 | if (pxa25x_ssp_comp(drv_data)) { |
579d3bb2 SAS |
509 | |
510 | sccr1_reg &= ~SSCR1_RFT; | |
511 | ||
512 | bytes_left = drv_data->rx_end - drv_data->rx; | |
513 | switch (drv_data->n_bytes) { | |
514 | case 4: | |
515 | bytes_left >>= 1; | |
516 | case 2: | |
517 | bytes_left >>= 1; | |
8d94cc50 | 518 | } |
579d3bb2 SAS |
519 | |
520 | if (bytes_left > RX_THRESH_DFLT) | |
521 | bytes_left = RX_THRESH_DFLT; | |
522 | ||
523 | sccr1_reg |= SSCR1_RxTresh(bytes_left); | |
e0c9905e | 524 | } |
579d3bb2 | 525 | write_SSCR1(sccr1_reg, reg); |
e0c9905e SS |
526 | } |
527 | ||
5daa3ba0 SS |
528 | /* We did something */ |
529 | return IRQ_HANDLED; | |
e0c9905e SS |
530 | } |
531 | ||
7d12e780 | 532 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 533 | { |
c7bec5ab | 534 | struct driver_data *drv_data = dev_id; |
cf43369d | 535 | void __iomem *reg = drv_data->ioaddr; |
7d94a505 | 536 | u32 sccr1_reg; |
49cbb1e0 SAS |
537 | u32 mask = drv_data->mask_sr; |
538 | u32 status; | |
539 | ||
7d94a505 MW |
540 | /* |
541 | * The IRQ might be shared with other peripherals so we must first | |
542 | * check that are we RPM suspended or not. If we are we assume that | |
543 | * the IRQ was not for us (we shouldn't be RPM suspended when the | |
544 | * interrupt is enabled). | |
545 | */ | |
546 | if (pm_runtime_suspended(&drv_data->pdev->dev)) | |
547 | return IRQ_NONE; | |
548 | ||
269e4a41 MW |
549 | /* |
550 | * If the device is not yet in RPM suspended state and we get an | |
551 | * interrupt that is meant for another device, check if status bits | |
552 | * are all set to one. That means that the device is already | |
553 | * powered off. | |
554 | */ | |
49cbb1e0 | 555 | status = read_SSSR(reg); |
269e4a41 MW |
556 | if (status == ~0) |
557 | return IRQ_NONE; | |
558 | ||
559 | sccr1_reg = read_SSCR1(reg); | |
49cbb1e0 SAS |
560 | |
561 | /* Ignore possible writes if we don't need to write */ | |
562 | if (!(sccr1_reg & SSCR1_TIE)) | |
563 | mask &= ~SSSR_TFS; | |
564 | ||
565 | if (!(status & mask)) | |
566 | return IRQ_NONE; | |
e0c9905e SS |
567 | |
568 | if (!drv_data->cur_msg) { | |
5daa3ba0 SS |
569 | |
570 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
571 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
2a8626a9 | 572 | if (!pxa25x_ssp_comp(drv_data)) |
5daa3ba0 | 573 | write_SSTO(0, reg); |
2a8626a9 | 574 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
5daa3ba0 | 575 | |
f6bd03a7 JN |
576 | dev_err(&drv_data->pdev->dev, |
577 | "bad message state in interrupt handler\n"); | |
5daa3ba0 | 578 | |
e0c9905e SS |
579 | /* Never fail */ |
580 | return IRQ_HANDLED; | |
581 | } | |
582 | ||
583 | return drv_data->transfer_handler(drv_data); | |
584 | } | |
585 | ||
3343b7a6 | 586 | static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) |
2f1a74e5 | 587 | { |
3343b7a6 MW |
588 | unsigned long ssp_clk = drv_data->max_clk_rate; |
589 | const struct ssp_device *ssp = drv_data->ssp; | |
590 | ||
591 | rate = min_t(int, ssp_clk, rate); | |
2f1a74e5 | 592 | |
2a8626a9 | 593 | if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) |
2f1a74e5 | 594 | return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; |
595 | else | |
596 | return ((ssp_clk / rate - 1) & 0xfff) << 8; | |
597 | } | |
598 | ||
e0c9905e SS |
599 | static void pump_transfers(unsigned long data) |
600 | { | |
601 | struct driver_data *drv_data = (struct driver_data *)data; | |
602 | struct spi_message *message = NULL; | |
603 | struct spi_transfer *transfer = NULL; | |
604 | struct spi_transfer *previous = NULL; | |
605 | struct chip_data *chip = NULL; | |
cf43369d | 606 | void __iomem *reg = drv_data->ioaddr; |
9708c121 SS |
607 | u32 clk_div = 0; |
608 | u8 bits = 0; | |
609 | u32 speed = 0; | |
610 | u32 cr0; | |
8d94cc50 SS |
611 | u32 cr1; |
612 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
613 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
e0c9905e SS |
614 | |
615 | /* Get current state information */ | |
616 | message = drv_data->cur_msg; | |
617 | transfer = drv_data->cur_transfer; | |
618 | chip = drv_data->cur_chip; | |
619 | ||
620 | /* Handle for abort */ | |
621 | if (message->state == ERROR_STATE) { | |
622 | message->status = -EIO; | |
5daa3ba0 | 623 | giveback(drv_data); |
e0c9905e SS |
624 | return; |
625 | } | |
626 | ||
627 | /* Handle end of message */ | |
628 | if (message->state == DONE_STATE) { | |
629 | message->status = 0; | |
5daa3ba0 | 630 | giveback(drv_data); |
e0c9905e SS |
631 | return; |
632 | } | |
633 | ||
8423597d | 634 | /* Delay if requested at end of transfer before CS change */ |
e0c9905e SS |
635 | if (message->state == RUNNING_STATE) { |
636 | previous = list_entry(transfer->transfer_list.prev, | |
637 | struct spi_transfer, | |
638 | transfer_list); | |
639 | if (previous->delay_usecs) | |
640 | udelay(previous->delay_usecs); | |
8423597d NF |
641 | |
642 | /* Drop chip select only if cs_change is requested */ | |
643 | if (previous->cs_change) | |
a7bb3909 | 644 | cs_deassert(drv_data); |
e0c9905e SS |
645 | } |
646 | ||
cd7bed00 MW |
647 | /* Check if we can DMA this transfer */ |
648 | if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { | |
7e964455 NF |
649 | |
650 | /* reject already-mapped transfers; PIO won't always work */ | |
651 | if (message->is_dma_mapped | |
652 | || transfer->rx_dma || transfer->tx_dma) { | |
653 | dev_err(&drv_data->pdev->dev, | |
f6bd03a7 JN |
654 | "pump_transfers: mapped transfer length of " |
655 | "%u is greater than %d\n", | |
7e964455 NF |
656 | transfer->len, MAX_DMA_LEN); |
657 | message->status = -EINVAL; | |
658 | giveback(drv_data); | |
659 | return; | |
660 | } | |
661 | ||
662 | /* warn ... we force this to PIO mode */ | |
f6bd03a7 JN |
663 | dev_warn_ratelimited(&message->spi->dev, |
664 | "pump_transfers: DMA disabled for transfer length %ld " | |
665 | "greater than %d\n", | |
666 | (long)drv_data->len, MAX_DMA_LEN); | |
8d94cc50 SS |
667 | } |
668 | ||
e0c9905e | 669 | /* Setup the transfer state based on the type of transfer */ |
cd7bed00 | 670 | if (pxa2xx_spi_flush(drv_data) == 0) { |
e0c9905e SS |
671 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
672 | message->status = -EIO; | |
5daa3ba0 | 673 | giveback(drv_data); |
e0c9905e SS |
674 | return; |
675 | } | |
9708c121 | 676 | drv_data->n_bytes = chip->n_bytes; |
e0c9905e SS |
677 | drv_data->tx = (void *)transfer->tx_buf; |
678 | drv_data->tx_end = drv_data->tx + transfer->len; | |
679 | drv_data->rx = transfer->rx_buf; | |
680 | drv_data->rx_end = drv_data->rx + transfer->len; | |
681 | drv_data->rx_dma = transfer->rx_dma; | |
682 | drv_data->tx_dma = transfer->tx_dma; | |
cd7bed00 | 683 | drv_data->len = transfer->len; |
e0c9905e SS |
684 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
685 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
686 | |
687 | /* Change speed and bit per word on a per transfer */ | |
8d94cc50 | 688 | cr0 = chip->cr0; |
9708c121 SS |
689 | if (transfer->speed_hz || transfer->bits_per_word) { |
690 | ||
9708c121 SS |
691 | bits = chip->bits_per_word; |
692 | speed = chip->speed_hz; | |
693 | ||
694 | if (transfer->speed_hz) | |
695 | speed = transfer->speed_hz; | |
696 | ||
697 | if (transfer->bits_per_word) | |
698 | bits = transfer->bits_per_word; | |
699 | ||
3343b7a6 | 700 | clk_div = ssp_get_clk_div(drv_data, speed); |
9708c121 SS |
701 | |
702 | if (bits <= 8) { | |
703 | drv_data->n_bytes = 1; | |
9708c121 SS |
704 | drv_data->read = drv_data->read != null_reader ? |
705 | u8_reader : null_reader; | |
706 | drv_data->write = drv_data->write != null_writer ? | |
707 | u8_writer : null_writer; | |
708 | } else if (bits <= 16) { | |
709 | drv_data->n_bytes = 2; | |
9708c121 SS |
710 | drv_data->read = drv_data->read != null_reader ? |
711 | u16_reader : null_reader; | |
712 | drv_data->write = drv_data->write != null_writer ? | |
713 | u16_writer : null_writer; | |
714 | } else if (bits <= 32) { | |
715 | drv_data->n_bytes = 4; | |
9708c121 SS |
716 | drv_data->read = drv_data->read != null_reader ? |
717 | u32_reader : null_reader; | |
718 | drv_data->write = drv_data->write != null_writer ? | |
719 | u32_writer : null_writer; | |
720 | } | |
8d94cc50 SS |
721 | /* if bits/word is changed in dma mode, then must check the |
722 | * thresholds and burst also */ | |
723 | if (chip->enable_dma) { | |
cd7bed00 MW |
724 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, |
725 | message->spi, | |
8d94cc50 SS |
726 | bits, &dma_burst, |
727 | &dma_thresh)) | |
f6bd03a7 JN |
728 | dev_warn_ratelimited(&message->spi->dev, |
729 | "pump_transfers: DMA burst size reduced to match bits_per_word\n"); | |
8d94cc50 | 730 | } |
9708c121 SS |
731 | |
732 | cr0 = clk_div | |
733 | | SSCR0_Motorola | |
5daa3ba0 | 734 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) |
9708c121 SS |
735 | | SSCR0_SSE |
736 | | (bits > 16 ? SSCR0_EDSS : 0); | |
9708c121 SS |
737 | } |
738 | ||
e0c9905e SS |
739 | message->state = RUNNING_STATE; |
740 | ||
7e964455 | 741 | drv_data->dma_mapped = 0; |
cd7bed00 MW |
742 | if (pxa2xx_spi_dma_is_possible(drv_data->len)) |
743 | drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); | |
7e964455 | 744 | if (drv_data->dma_mapped) { |
e0c9905e SS |
745 | |
746 | /* Ensure we have the correct interrupt handler */ | |
cd7bed00 MW |
747 | drv_data->transfer_handler = pxa2xx_spi_dma_transfer; |
748 | ||
749 | pxa2xx_spi_dma_prepare(drv_data, dma_burst); | |
e0c9905e | 750 | |
8d94cc50 SS |
751 | /* Clear status and start DMA engine */ |
752 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
e0c9905e | 753 | write_SSSR(drv_data->clear_sr, reg); |
cd7bed00 MW |
754 | |
755 | pxa2xx_spi_dma_start(drv_data); | |
e0c9905e SS |
756 | } else { |
757 | /* Ensure we have the correct interrupt handler */ | |
758 | drv_data->transfer_handler = interrupt_transfer; | |
759 | ||
8d94cc50 SS |
760 | /* Clear status */ |
761 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
2a8626a9 | 762 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
8d94cc50 SS |
763 | } |
764 | ||
a0d2642e MW |
765 | if (is_lpss_ssp(drv_data)) { |
766 | if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold) | |
767 | write_SSIRF(chip->lpss_rx_threshold, reg); | |
768 | if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold) | |
769 | write_SSITF(chip->lpss_tx_threshold, reg); | |
770 | } | |
771 | ||
8d94cc50 SS |
772 | /* see if we need to reload the config registers */ |
773 | if ((read_SSCR0(reg) != cr0) | |
774 | || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != | |
775 | (cr1 & SSCR1_CHANGE_MASK)) { | |
776 | ||
b97c74bd | 777 | /* stop the SSP, and update the other bits */ |
8d94cc50 | 778 | write_SSCR0(cr0 & ~SSCR0_SSE, reg); |
2a8626a9 | 779 | if (!pxa25x_ssp_comp(drv_data)) |
e0c9905e | 780 | write_SSTO(chip->timeout, reg); |
b97c74bd NF |
781 | /* first set CR1 without interrupt and service enables */ |
782 | write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); | |
783 | /* restart the SSP */ | |
8d94cc50 | 784 | write_SSCR0(cr0, reg); |
b97c74bd | 785 | |
8d94cc50 | 786 | } else { |
2a8626a9 | 787 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 788 | write_SSTO(chip->timeout, reg); |
e0c9905e | 789 | } |
b97c74bd | 790 | |
a7bb3909 | 791 | cs_assert(drv_data); |
b97c74bd NF |
792 | |
793 | /* after chip select, release the data by enabling service | |
794 | * requests and interrupts, without changing any mode bits */ | |
795 | write_SSCR1(cr1, reg); | |
e0c9905e SS |
796 | } |
797 | ||
7f86bde9 MW |
798 | static int pxa2xx_spi_transfer_one_message(struct spi_master *master, |
799 | struct spi_message *msg) | |
e0c9905e | 800 | { |
7f86bde9 | 801 | struct driver_data *drv_data = spi_master_get_devdata(master); |
e0c9905e | 802 | |
7f86bde9 | 803 | drv_data->cur_msg = msg; |
e0c9905e SS |
804 | /* Initial message state*/ |
805 | drv_data->cur_msg->state = START_STATE; | |
806 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
807 | struct spi_transfer, | |
808 | transfer_list); | |
809 | ||
8d94cc50 SS |
810 | /* prepare to setup the SSP, in pump_transfers, using the per |
811 | * chip configuration */ | |
e0c9905e | 812 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
813 | |
814 | /* Mark as busy and launch transfers */ | |
815 | tasklet_schedule(&drv_data->pump_transfers); | |
e0c9905e SS |
816 | return 0; |
817 | } | |
818 | ||
7d94a505 MW |
819 | static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) |
820 | { | |
821 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
822 | ||
823 | /* Disable the SSP now */ | |
824 | write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE, | |
825 | drv_data->ioaddr); | |
826 | ||
7d94a505 MW |
827 | return 0; |
828 | } | |
829 | ||
a7bb3909 EM |
830 | static int setup_cs(struct spi_device *spi, struct chip_data *chip, |
831 | struct pxa2xx_spi_chip *chip_info) | |
832 | { | |
833 | int err = 0; | |
834 | ||
835 | if (chip == NULL || chip_info == NULL) | |
836 | return 0; | |
837 | ||
838 | /* NOTE: setup() can be called multiple times, possibly with | |
839 | * different chip_info, release previously requested GPIO | |
840 | */ | |
841 | if (gpio_is_valid(chip->gpio_cs)) | |
842 | gpio_free(chip->gpio_cs); | |
843 | ||
844 | /* If (*cs_control) is provided, ignore GPIO chip select */ | |
845 | if (chip_info->cs_control) { | |
846 | chip->cs_control = chip_info->cs_control; | |
847 | return 0; | |
848 | } | |
849 | ||
850 | if (gpio_is_valid(chip_info->gpio_cs)) { | |
851 | err = gpio_request(chip_info->gpio_cs, "SPI_CS"); | |
852 | if (err) { | |
f6bd03a7 JN |
853 | dev_err(&spi->dev, "failed to request chip select GPIO%d\n", |
854 | chip_info->gpio_cs); | |
a7bb3909 EM |
855 | return err; |
856 | } | |
857 | ||
858 | chip->gpio_cs = chip_info->gpio_cs; | |
859 | chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; | |
860 | ||
861 | err = gpio_direction_output(chip->gpio_cs, | |
862 | !chip->gpio_cs_inverted); | |
863 | } | |
864 | ||
865 | return err; | |
866 | } | |
867 | ||
e0c9905e SS |
868 | static int setup(struct spi_device *spi) |
869 | { | |
870 | struct pxa2xx_spi_chip *chip_info = NULL; | |
871 | struct chip_data *chip; | |
872 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
873 | unsigned int clk_div; | |
a0d2642e MW |
874 | uint tx_thres, tx_hi_thres, rx_thres; |
875 | ||
876 | if (is_lpss_ssp(drv_data)) { | |
877 | tx_thres = LPSS_TX_LOTHRESH_DFLT; | |
878 | tx_hi_thres = LPSS_TX_HITHRESH_DFLT; | |
879 | rx_thres = LPSS_RX_THRESH_DFLT; | |
880 | } else { | |
881 | tx_thres = TX_THRESH_DFLT; | |
882 | tx_hi_thres = 0; | |
883 | rx_thres = RX_THRESH_DFLT; | |
884 | } | |
e0c9905e | 885 | |
8d94cc50 | 886 | /* Only alloc on first setup */ |
e0c9905e | 887 | chip = spi_get_ctldata(spi); |
8d94cc50 | 888 | if (!chip) { |
e0c9905e | 889 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
8d94cc50 SS |
890 | if (!chip) { |
891 | dev_err(&spi->dev, | |
892 | "failed setup: can't allocate chip data\n"); | |
e0c9905e | 893 | return -ENOMEM; |
8d94cc50 | 894 | } |
e0c9905e | 895 | |
2a8626a9 SAS |
896 | if (drv_data->ssp_type == CE4100_SSP) { |
897 | if (spi->chip_select > 4) { | |
f6bd03a7 JN |
898 | dev_err(&spi->dev, |
899 | "failed setup: cs number must not be > 4.\n"); | |
2a8626a9 SAS |
900 | kfree(chip); |
901 | return -EINVAL; | |
902 | } | |
903 | ||
904 | chip->frm = spi->chip_select; | |
905 | } else | |
906 | chip->gpio_cs = -1; | |
e0c9905e | 907 | chip->enable_dma = 0; |
f1f640a9 | 908 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
909 | } |
910 | ||
8d94cc50 SS |
911 | /* protocol drivers may change the chip settings, so... |
912 | * if chip_info exists, use it */ | |
913 | chip_info = spi->controller_data; | |
914 | ||
e0c9905e | 915 | /* chip_info isn't always needed */ |
8d94cc50 | 916 | chip->cr1 = 0; |
e0c9905e | 917 | if (chip_info) { |
f1f640a9 VS |
918 | if (chip_info->timeout) |
919 | chip->timeout = chip_info->timeout; | |
920 | if (chip_info->tx_threshold) | |
921 | tx_thres = chip_info->tx_threshold; | |
a0d2642e MW |
922 | if (chip_info->tx_hi_threshold) |
923 | tx_hi_thres = chip_info->tx_hi_threshold; | |
f1f640a9 VS |
924 | if (chip_info->rx_threshold) |
925 | rx_thres = chip_info->rx_threshold; | |
926 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e | 927 | chip->dma_threshold = 0; |
e0c9905e SS |
928 | if (chip_info->enable_loopback) |
929 | chip->cr1 = SSCR1_LBM; | |
a3496855 MW |
930 | } else if (ACPI_HANDLE(&spi->dev)) { |
931 | /* | |
932 | * Slave devices enumerated from ACPI namespace don't | |
933 | * usually have chip_info but we still might want to use | |
934 | * DMA with them. | |
935 | */ | |
936 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e SS |
937 | } |
938 | ||
f1f640a9 VS |
939 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | |
940 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
941 | ||
a0d2642e MW |
942 | chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); |
943 | chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | |
944 | | SSITF_TxHiThresh(tx_hi_thres); | |
945 | ||
8d94cc50 SS |
946 | /* set dma burst and threshold outside of chip_info path so that if |
947 | * chip_info goes away after setting chip->enable_dma, the | |
948 | * burst and threshold can still respond to changes in bits_per_word */ | |
949 | if (chip->enable_dma) { | |
950 | /* set up legal burst and threshold for dma */ | |
cd7bed00 MW |
951 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, |
952 | spi->bits_per_word, | |
8d94cc50 SS |
953 | &chip->dma_burst_size, |
954 | &chip->dma_threshold)) { | |
f6bd03a7 JN |
955 | dev_warn(&spi->dev, |
956 | "in setup: DMA burst size reduced to match bits_per_word\n"); | |
8d94cc50 SS |
957 | } |
958 | } | |
959 | ||
3343b7a6 | 960 | clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz); |
9708c121 | 961 | chip->speed_hz = spi->max_speed_hz; |
e0c9905e SS |
962 | |
963 | chip->cr0 = clk_div | |
964 | | SSCR0_Motorola | |
5daa3ba0 SS |
965 | | SSCR0_DataSize(spi->bits_per_word > 16 ? |
966 | spi->bits_per_word - 16 : spi->bits_per_word) | |
e0c9905e SS |
967 | | SSCR0_SSE |
968 | | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); | |
7f6ee1ad JC |
969 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
970 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
971 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e | 972 | |
b833172f MW |
973 | if (spi->mode & SPI_LOOP) |
974 | chip->cr1 |= SSCR1_LBM; | |
975 | ||
e0c9905e | 976 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ |
2a8626a9 | 977 | if (!pxa25x_ssp_comp(drv_data)) |
7d077197 | 978 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 979 | drv_data->max_clk_rate |
c9840daa EM |
980 | / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), |
981 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e | 982 | else |
7d077197 | 983 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 984 | drv_data->max_clk_rate / 2 |
c9840daa EM |
985 | / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), |
986 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e SS |
987 | |
988 | if (spi->bits_per_word <= 8) { | |
989 | chip->n_bytes = 1; | |
e0c9905e SS |
990 | chip->read = u8_reader; |
991 | chip->write = u8_writer; | |
992 | } else if (spi->bits_per_word <= 16) { | |
993 | chip->n_bytes = 2; | |
e0c9905e SS |
994 | chip->read = u16_reader; |
995 | chip->write = u16_writer; | |
996 | } else if (spi->bits_per_word <= 32) { | |
997 | chip->cr0 |= SSCR0_EDSS; | |
998 | chip->n_bytes = 4; | |
e0c9905e SS |
999 | chip->read = u32_reader; |
1000 | chip->write = u32_writer; | |
e0c9905e | 1001 | } |
9708c121 | 1002 | chip->bits_per_word = spi->bits_per_word; |
e0c9905e SS |
1003 | |
1004 | spi_set_ctldata(spi, chip); | |
1005 | ||
2a8626a9 SAS |
1006 | if (drv_data->ssp_type == CE4100_SSP) |
1007 | return 0; | |
1008 | ||
a7bb3909 | 1009 | return setup_cs(spi, chip, chip_info); |
e0c9905e SS |
1010 | } |
1011 | ||
0ffa0285 | 1012 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1013 | { |
0ffa0285 | 1014 | struct chip_data *chip = spi_get_ctldata(spi); |
2a8626a9 | 1015 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
e0c9905e | 1016 | |
7348d82a DR |
1017 | if (!chip) |
1018 | return; | |
1019 | ||
2a8626a9 | 1020 | if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) |
a7bb3909 EM |
1021 | gpio_free(chip->gpio_cs); |
1022 | ||
e0c9905e SS |
1023 | kfree(chip); |
1024 | } | |
1025 | ||
a3496855 | 1026 | #ifdef CONFIG_ACPI |
a3496855 MW |
1027 | static struct pxa2xx_spi_master * |
1028 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | |
1029 | { | |
1030 | struct pxa2xx_spi_master *pdata; | |
a3496855 MW |
1031 | struct acpi_device *adev; |
1032 | struct ssp_device *ssp; | |
1033 | struct resource *res; | |
1034 | int devid; | |
1035 | ||
1036 | if (!ACPI_HANDLE(&pdev->dev) || | |
1037 | acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
1038 | return NULL; | |
1039 | ||
cc0ee987 | 1040 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
a3496855 MW |
1041 | if (!pdata) { |
1042 | dev_err(&pdev->dev, | |
1043 | "failed to allocate memory for platform data\n"); | |
1044 | return NULL; | |
1045 | } | |
1046 | ||
1047 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1048 | if (!res) | |
1049 | return NULL; | |
1050 | ||
1051 | ssp = &pdata->ssp; | |
1052 | ||
1053 | ssp->phys_base = res->start; | |
cbfd6a21 SK |
1054 | ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); |
1055 | if (IS_ERR(ssp->mmio_base)) | |
6dc81f6f | 1056 | return NULL; |
a3496855 MW |
1057 | |
1058 | ssp->clk = devm_clk_get(&pdev->dev, NULL); | |
1059 | ssp->irq = platform_get_irq(pdev, 0); | |
1060 | ssp->type = LPSS_SSP; | |
1061 | ssp->pdev = pdev; | |
1062 | ||
1063 | ssp->port_id = -1; | |
1064 | if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid)) | |
1065 | ssp->port_id = devid; | |
1066 | ||
1067 | pdata->num_chipselect = 1; | |
cddb339b | 1068 | pdata->enable_dma = true; |
483c3191 MW |
1069 | pdata->tx_chan_id = -1; |
1070 | pdata->rx_chan_id = -1; | |
a3496855 MW |
1071 | |
1072 | return pdata; | |
1073 | } | |
1074 | ||
1075 | static struct acpi_device_id pxa2xx_spi_acpi_match[] = { | |
1076 | { "INT33C0", 0 }, | |
1077 | { "INT33C1", 0 }, | |
54acbd96 MW |
1078 | { "INT3430", 0 }, |
1079 | { "INT3431", 0 }, | |
4b30f2a1 | 1080 | { "80860F0E", 0 }, |
a3496855 MW |
1081 | { }, |
1082 | }; | |
1083 | MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); | |
1084 | #else | |
1085 | static inline struct pxa2xx_spi_master * | |
1086 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | |
1087 | { | |
1088 | return NULL; | |
1089 | } | |
1090 | #endif | |
1091 | ||
fd4a319b | 1092 | static int pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1093 | { |
1094 | struct device *dev = &pdev->dev; | |
1095 | struct pxa2xx_spi_master *platform_info; | |
1096 | struct spi_master *master; | |
65a00a20 | 1097 | struct driver_data *drv_data; |
2f1a74e5 | 1098 | struct ssp_device *ssp; |
65a00a20 | 1099 | int status; |
e0c9905e | 1100 | |
851bacf5 MW |
1101 | platform_info = dev_get_platdata(dev); |
1102 | if (!platform_info) { | |
a3496855 MW |
1103 | platform_info = pxa2xx_spi_acpi_get_pdata(pdev); |
1104 | if (!platform_info) { | |
1105 | dev_err(&pdev->dev, "missing platform data\n"); | |
1106 | return -ENODEV; | |
1107 | } | |
851bacf5 | 1108 | } |
e0c9905e | 1109 | |
baffe169 | 1110 | ssp = pxa_ssp_request(pdev->id, pdev->name); |
851bacf5 MW |
1111 | if (!ssp) |
1112 | ssp = &platform_info->ssp; | |
1113 | ||
1114 | if (!ssp->mmio_base) { | |
1115 | dev_err(&pdev->dev, "failed to get ssp\n"); | |
e0c9905e SS |
1116 | return -ENODEV; |
1117 | } | |
1118 | ||
1119 | /* Allocate master with space for drv_data and null dma buffer */ | |
1120 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1121 | if (!master) { | |
65a00a20 | 1122 | dev_err(&pdev->dev, "cannot alloc spi_master\n"); |
baffe169 | 1123 | pxa_ssp_free(ssp); |
e0c9905e SS |
1124 | return -ENOMEM; |
1125 | } | |
1126 | drv_data = spi_master_get_devdata(master); | |
1127 | drv_data->master = master; | |
1128 | drv_data->master_info = platform_info; | |
1129 | drv_data->pdev = pdev; | |
2f1a74e5 | 1130 | drv_data->ssp = ssp; |
e0c9905e | 1131 | |
21486af0 | 1132 | master->dev.parent = &pdev->dev; |
21486af0 | 1133 | master->dev.of_node = pdev->dev.of_node; |
e7db06b5 | 1134 | /* the spi->mode bits understood by this driver: */ |
b833172f | 1135 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
e7db06b5 | 1136 | |
851bacf5 | 1137 | master->bus_num = ssp->port_id; |
e0c9905e | 1138 | master->num_chipselect = platform_info->num_chipselect; |
7ad0ba91 | 1139 | master->dma_alignment = DMA_ALIGNMENT; |
e0c9905e SS |
1140 | master->cleanup = cleanup; |
1141 | master->setup = setup; | |
7f86bde9 | 1142 | master->transfer_one_message = pxa2xx_spi_transfer_one_message; |
7d94a505 | 1143 | master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; |
7dd62787 | 1144 | master->auto_runtime_pm = true; |
e0c9905e | 1145 | |
2f1a74e5 | 1146 | drv_data->ssp_type = ssp->type; |
2b9b84f4 | 1147 | drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); |
e0c9905e | 1148 | |
2f1a74e5 | 1149 | drv_data->ioaddr = ssp->mmio_base; |
1150 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
2a8626a9 | 1151 | if (pxa25x_ssp_comp(drv_data)) { |
24778be2 | 1152 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
e0c9905e SS |
1153 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1154 | drv_data->dma_cr1 = 0; | |
1155 | drv_data->clear_sr = SSSR_ROR; | |
1156 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1157 | } else { | |
24778be2 | 1158 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
e0c9905e | 1159 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; |
5928808e | 1160 | drv_data->dma_cr1 = DEFAULT_DMA_CR1; |
e0c9905e SS |
1161 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; |
1162 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1163 | } | |
1164 | ||
49cbb1e0 SAS |
1165 | status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), |
1166 | drv_data); | |
e0c9905e | 1167 | if (status < 0) { |
65a00a20 | 1168 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
e0c9905e SS |
1169 | goto out_error_master_alloc; |
1170 | } | |
1171 | ||
1172 | /* Setup DMA if requested */ | |
1173 | drv_data->tx_channel = -1; | |
1174 | drv_data->rx_channel = -1; | |
1175 | if (platform_info->enable_dma) { | |
cd7bed00 MW |
1176 | status = pxa2xx_spi_dma_setup(drv_data); |
1177 | if (status) { | |
cddb339b | 1178 | dev_dbg(dev, "no DMA channels available, using PIO\n"); |
cd7bed00 | 1179 | platform_info->enable_dma = false; |
e0c9905e | 1180 | } |
e0c9905e SS |
1181 | } |
1182 | ||
1183 | /* Enable SOC clock */ | |
3343b7a6 MW |
1184 | clk_prepare_enable(ssp->clk); |
1185 | ||
1186 | drv_data->max_clk_rate = clk_get_rate(ssp->clk); | |
e0c9905e SS |
1187 | |
1188 | /* Load default SSP configuration */ | |
1189 | write_SSCR0(0, drv_data->ioaddr); | |
f1f640a9 VS |
1190 | write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | |
1191 | SSCR1_TxTresh(TX_THRESH_DFLT), | |
1192 | drv_data->ioaddr); | |
c9840daa | 1193 | write_SSCR0(SSCR0_SCR(2) |
e0c9905e SS |
1194 | | SSCR0_Motorola |
1195 | | SSCR0_DataSize(8), | |
1196 | drv_data->ioaddr); | |
2a8626a9 | 1197 | if (!pxa25x_ssp_comp(drv_data)) |
e0c9905e SS |
1198 | write_SSTO(0, drv_data->ioaddr); |
1199 | write_SSPSP(0, drv_data->ioaddr); | |
1200 | ||
a0d2642e MW |
1201 | lpss_ssp_setup(drv_data); |
1202 | ||
7f86bde9 MW |
1203 | tasklet_init(&drv_data->pump_transfers, pump_transfers, |
1204 | (unsigned long)drv_data); | |
e0c9905e SS |
1205 | |
1206 | /* Register with the SPI framework */ | |
1207 | platform_set_drvdata(pdev, drv_data); | |
a807fcd0 | 1208 | status = devm_spi_register_master(&pdev->dev, master); |
e0c9905e SS |
1209 | if (status != 0) { |
1210 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
7f86bde9 | 1211 | goto out_error_clock_enabled; |
e0c9905e SS |
1212 | } |
1213 | ||
7d94a505 MW |
1214 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1215 | pm_runtime_use_autosuspend(&pdev->dev); | |
1216 | pm_runtime_set_active(&pdev->dev); | |
1217 | pm_runtime_enable(&pdev->dev); | |
1218 | ||
e0c9905e SS |
1219 | return status; |
1220 | ||
e0c9905e | 1221 | out_error_clock_enabled: |
3343b7a6 | 1222 | clk_disable_unprepare(ssp->clk); |
cd7bed00 | 1223 | pxa2xx_spi_dma_release(drv_data); |
2f1a74e5 | 1224 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1225 | |
1226 | out_error_master_alloc: | |
1227 | spi_master_put(master); | |
baffe169 | 1228 | pxa_ssp_free(ssp); |
e0c9905e SS |
1229 | return status; |
1230 | } | |
1231 | ||
1232 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1233 | { | |
1234 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
51e911e2 | 1235 | struct ssp_device *ssp; |
e0c9905e SS |
1236 | |
1237 | if (!drv_data) | |
1238 | return 0; | |
51e911e2 | 1239 | ssp = drv_data->ssp; |
e0c9905e | 1240 | |
7d94a505 MW |
1241 | pm_runtime_get_sync(&pdev->dev); |
1242 | ||
e0c9905e SS |
1243 | /* Disable the SSP at the peripheral and SOC level */ |
1244 | write_SSCR0(0, drv_data->ioaddr); | |
3343b7a6 | 1245 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1246 | |
1247 | /* Release DMA */ | |
cd7bed00 MW |
1248 | if (drv_data->master_info->enable_dma) |
1249 | pxa2xx_spi_dma_release(drv_data); | |
e0c9905e | 1250 | |
7d94a505 MW |
1251 | pm_runtime_put_noidle(&pdev->dev); |
1252 | pm_runtime_disable(&pdev->dev); | |
1253 | ||
e0c9905e | 1254 | /* Release IRQ */ |
2f1a74e5 | 1255 | free_irq(ssp->irq, drv_data); |
1256 | ||
1257 | /* Release SSP */ | |
baffe169 | 1258 | pxa_ssp_free(ssp); |
e0c9905e | 1259 | |
e0c9905e SS |
1260 | return 0; |
1261 | } | |
1262 | ||
1263 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1264 | { | |
1265 | int status = 0; | |
1266 | ||
1267 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1268 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1269 | } | |
1270 | ||
382cebb0 | 1271 | #ifdef CONFIG_PM_SLEEP |
86d2593a | 1272 | static int pxa2xx_spi_suspend(struct device *dev) |
e0c9905e | 1273 | { |
86d2593a | 1274 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1275 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1276 | int status = 0; |
1277 | ||
7f86bde9 | 1278 | status = spi_master_suspend(drv_data->master); |
e0c9905e SS |
1279 | if (status != 0) |
1280 | return status; | |
1281 | write_SSCR0(0, drv_data->ioaddr); | |
3343b7a6 | 1282 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1283 | |
1284 | return 0; | |
1285 | } | |
1286 | ||
86d2593a | 1287 | static int pxa2xx_spi_resume(struct device *dev) |
e0c9905e | 1288 | { |
86d2593a | 1289 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1290 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1291 | int status = 0; |
1292 | ||
cd7bed00 | 1293 | pxa2xx_spi_dma_resume(drv_data); |
148da331 | 1294 | |
e0c9905e | 1295 | /* Enable the SSP clock */ |
3343b7a6 | 1296 | clk_prepare_enable(ssp->clk); |
e0c9905e | 1297 | |
c50325f7 CCE |
1298 | /* Restore LPSS private register bits */ |
1299 | lpss_ssp_setup(drv_data); | |
1300 | ||
e0c9905e | 1301 | /* Start the queue running */ |
7f86bde9 | 1302 | status = spi_master_resume(drv_data->master); |
e0c9905e | 1303 | if (status != 0) { |
86d2593a | 1304 | dev_err(dev, "problem starting queue (%d)\n", status); |
e0c9905e SS |
1305 | return status; |
1306 | } | |
1307 | ||
1308 | return 0; | |
1309 | } | |
7d94a505 MW |
1310 | #endif |
1311 | ||
1312 | #ifdef CONFIG_PM_RUNTIME | |
1313 | static int pxa2xx_spi_runtime_suspend(struct device *dev) | |
1314 | { | |
1315 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1316 | ||
1317 | clk_disable_unprepare(drv_data->ssp->clk); | |
1318 | return 0; | |
1319 | } | |
1320 | ||
1321 | static int pxa2xx_spi_runtime_resume(struct device *dev) | |
1322 | { | |
1323 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1324 | ||
1325 | clk_prepare_enable(drv_data->ssp->clk); | |
1326 | return 0; | |
1327 | } | |
1328 | #endif | |
86d2593a | 1329 | |
47145210 | 1330 | static const struct dev_pm_ops pxa2xx_spi_pm_ops = { |
7d94a505 MW |
1331 | SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) |
1332 | SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, | |
1333 | pxa2xx_spi_runtime_resume, NULL) | |
86d2593a | 1334 | }; |
e0c9905e SS |
1335 | |
1336 | static struct platform_driver driver = { | |
1337 | .driver = { | |
86d2593a MR |
1338 | .name = "pxa2xx-spi", |
1339 | .owner = THIS_MODULE, | |
86d2593a | 1340 | .pm = &pxa2xx_spi_pm_ops, |
a3496855 | 1341 | .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), |
e0c9905e | 1342 | }, |
fbd29a14 | 1343 | .probe = pxa2xx_spi_probe, |
d1e44d9c | 1344 | .remove = pxa2xx_spi_remove, |
e0c9905e | 1345 | .shutdown = pxa2xx_spi_shutdown, |
e0c9905e SS |
1346 | }; |
1347 | ||
1348 | static int __init pxa2xx_spi_init(void) | |
1349 | { | |
fbd29a14 | 1350 | return platform_driver_register(&driver); |
e0c9905e | 1351 | } |
5b61a749 | 1352 | subsys_initcall(pxa2xx_spi_init); |
e0c9905e SS |
1353 | |
1354 | static void __exit pxa2xx_spi_exit(void) | |
1355 | { | |
1356 | platform_driver_unregister(&driver); | |
1357 | } | |
1358 | module_exit(pxa2xx_spi_exit); |