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e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
a0d2642e | 3 | * Copyright (C) 2013, Intel Corporation |
e0c9905e SS |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
e0c9905e SS |
14 | */ |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/errno.h> | |
cbfd6a21 | 21 | #include <linux/err.h> |
e0c9905e | 22 | #include <linux/interrupt.h> |
9df461ec | 23 | #include <linux/kernel.h> |
34cadd9c | 24 | #include <linux/pci.h> |
e0c9905e | 25 | #include <linux/platform_device.h> |
8348c259 | 26 | #include <linux/spi/pxa2xx_spi.h> |
e0c9905e | 27 | #include <linux/spi/spi.h> |
e0c9905e | 28 | #include <linux/delay.h> |
a7bb3909 | 29 | #include <linux/gpio.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
3343b7a6 | 31 | #include <linux/clk.h> |
7d94a505 | 32 | #include <linux/pm_runtime.h> |
a3496855 | 33 | #include <linux/acpi.h> |
e0c9905e | 34 | |
cd7bed00 | 35 | #include "spi-pxa2xx.h" |
e0c9905e SS |
36 | |
37 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 38 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 39 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 40 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e | 41 | |
f1f640a9 VS |
42 | #define TIMOUT_DFLT 1000 |
43 | ||
b97c74bd NF |
44 | /* |
45 | * for testing SSCR1 changes that require SSP restart, basically | |
46 | * everything except the service and interrupt enables, the pxa270 developer | |
47 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
48 | * list, but the PXA255 dev man says all bits without really meaning the | |
49 | * service and interrupt enables | |
50 | */ | |
51 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 52 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
53 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
54 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
55 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
56 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 57 | |
e5262d05 WC |
58 | #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \ |
59 | | QUARK_X1000_SSCR1_EFWR \ | |
60 | | QUARK_X1000_SSCR1_RFT \ | |
61 | | QUARK_X1000_SSCR1_TFT \ | |
62 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
63 | ||
1de70612 | 64 | #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) |
a0d2642e MW |
65 | #define SPI_CS_CONTROL_SW_MODE BIT(0) |
66 | #define SPI_CS_CONTROL_CS_HIGH BIT(1) | |
67 | ||
dccf7369 JN |
68 | struct lpss_config { |
69 | /* LPSS offset from drv_data->ioaddr */ | |
70 | unsigned offset; | |
71 | /* Register offsets from drv_data->lpss_base or -1 */ | |
72 | int reg_general; | |
73 | int reg_ssp; | |
74 | int reg_cs_ctrl; | |
75 | /* FIFO thresholds */ | |
76 | u32 rx_threshold; | |
77 | u32 tx_threshold_lo; | |
78 | u32 tx_threshold_hi; | |
79 | }; | |
80 | ||
81 | /* Keep these sorted with enum pxa_ssp_type */ | |
82 | static const struct lpss_config lpss_platforms[] = { | |
83 | { /* LPSS_LPT_SSP */ | |
84 | .offset = 0x800, | |
85 | .reg_general = 0x08, | |
86 | .reg_ssp = 0x0c, | |
87 | .reg_cs_ctrl = 0x18, | |
88 | .rx_threshold = 64, | |
89 | .tx_threshold_lo = 160, | |
90 | .tx_threshold_hi = 224, | |
91 | }, | |
92 | { /* LPSS_BYT_SSP */ | |
93 | .offset = 0x400, | |
94 | .reg_general = 0x08, | |
95 | .reg_ssp = 0x0c, | |
96 | .reg_cs_ctrl = 0x18, | |
97 | .rx_threshold = 64, | |
98 | .tx_threshold_lo = 160, | |
99 | .tx_threshold_hi = 224, | |
100 | }, | |
34cadd9c JN |
101 | { /* LPSS_SPT_SSP */ |
102 | .offset = 0x200, | |
103 | .reg_general = -1, | |
104 | .reg_ssp = 0x20, | |
105 | .reg_cs_ctrl = 0x24, | |
106 | .rx_threshold = 1, | |
107 | .tx_threshold_lo = 32, | |
108 | .tx_threshold_hi = 56, | |
109 | }, | |
dccf7369 JN |
110 | }; |
111 | ||
112 | static inline const struct lpss_config | |
113 | *lpss_get_config(const struct driver_data *drv_data) | |
114 | { | |
115 | return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; | |
116 | } | |
117 | ||
a0d2642e MW |
118 | static bool is_lpss_ssp(const struct driver_data *drv_data) |
119 | { | |
03fbf488 JN |
120 | switch (drv_data->ssp_type) { |
121 | case LPSS_LPT_SSP: | |
122 | case LPSS_BYT_SSP: | |
34cadd9c | 123 | case LPSS_SPT_SSP: |
03fbf488 JN |
124 | return true; |
125 | default: | |
126 | return false; | |
127 | } | |
a0d2642e MW |
128 | } |
129 | ||
e5262d05 WC |
130 | static bool is_quark_x1000_ssp(const struct driver_data *drv_data) |
131 | { | |
132 | return drv_data->ssp_type == QUARK_X1000_SSP; | |
133 | } | |
134 | ||
4fdb2424 WC |
135 | static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) |
136 | { | |
137 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
138 | case QUARK_X1000_SSP: |
139 | return QUARK_X1000_SSCR1_CHANGE_MASK; | |
4fdb2424 WC |
140 | default: |
141 | return SSCR1_CHANGE_MASK; | |
142 | } | |
143 | } | |
144 | ||
145 | static u32 | |
146 | pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) | |
147 | { | |
148 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
149 | case QUARK_X1000_SSP: |
150 | return RX_THRESH_QUARK_X1000_DFLT; | |
4fdb2424 WC |
151 | default: |
152 | return RX_THRESH_DFLT; | |
153 | } | |
154 | } | |
155 | ||
156 | static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) | |
157 | { | |
4fdb2424 WC |
158 | u32 mask; |
159 | ||
160 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
161 | case QUARK_X1000_SSP: |
162 | mask = QUARK_X1000_SSSR_TFL_MASK; | |
163 | break; | |
4fdb2424 WC |
164 | default: |
165 | mask = SSSR_TFL_MASK; | |
166 | break; | |
167 | } | |
168 | ||
c039dd27 | 169 | return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask; |
4fdb2424 WC |
170 | } |
171 | ||
172 | static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, | |
173 | u32 *sccr1_reg) | |
174 | { | |
175 | u32 mask; | |
176 | ||
177 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
178 | case QUARK_X1000_SSP: |
179 | mask = QUARK_X1000_SSCR1_RFT; | |
180 | break; | |
4fdb2424 WC |
181 | default: |
182 | mask = SSCR1_RFT; | |
183 | break; | |
184 | } | |
185 | *sccr1_reg &= ~mask; | |
186 | } | |
187 | ||
188 | static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, | |
189 | u32 *sccr1_reg, u32 threshold) | |
190 | { | |
191 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
192 | case QUARK_X1000_SSP: |
193 | *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); | |
194 | break; | |
4fdb2424 WC |
195 | default: |
196 | *sccr1_reg |= SSCR1_RxTresh(threshold); | |
197 | break; | |
198 | } | |
199 | } | |
200 | ||
201 | static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, | |
202 | u32 clk_div, u8 bits) | |
203 | { | |
204 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
205 | case QUARK_X1000_SSP: |
206 | return clk_div | |
207 | | QUARK_X1000_SSCR0_Motorola | |
208 | | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits) | |
209 | | SSCR0_SSE; | |
4fdb2424 WC |
210 | default: |
211 | return clk_div | |
212 | | SSCR0_Motorola | |
213 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) | |
214 | | SSCR0_SSE | |
215 | | (bits > 16 ? SSCR0_EDSS : 0); | |
216 | } | |
217 | } | |
218 | ||
a0d2642e MW |
219 | /* |
220 | * Read and write LPSS SSP private registers. Caller must first check that | |
221 | * is_lpss_ssp() returns true before these can be called. | |
222 | */ | |
223 | static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) | |
224 | { | |
225 | WARN_ON(!drv_data->lpss_base); | |
226 | return readl(drv_data->lpss_base + offset); | |
227 | } | |
228 | ||
229 | static void __lpss_ssp_write_priv(struct driver_data *drv_data, | |
230 | unsigned offset, u32 value) | |
231 | { | |
232 | WARN_ON(!drv_data->lpss_base); | |
233 | writel(value, drv_data->lpss_base + offset); | |
234 | } | |
235 | ||
236 | /* | |
237 | * lpss_ssp_setup - perform LPSS SSP specific setup | |
238 | * @drv_data: pointer to the driver private data | |
239 | * | |
240 | * Perform LPSS SSP specific setup. This function must be called first if | |
241 | * one is going to use LPSS SSP private registers. | |
242 | */ | |
243 | static void lpss_ssp_setup(struct driver_data *drv_data) | |
244 | { | |
dccf7369 JN |
245 | const struct lpss_config *config; |
246 | u32 value; | |
a0d2642e | 247 | |
dccf7369 JN |
248 | config = lpss_get_config(drv_data); |
249 | drv_data->lpss_base = drv_data->ioaddr + config->offset; | |
a0d2642e MW |
250 | |
251 | /* Enable software chip select control */ | |
252 | value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; | |
dccf7369 | 253 | __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); |
0054e28d MW |
254 | |
255 | /* Enable multiblock DMA transfers */ | |
1de70612 | 256 | if (drv_data->master_info->enable_dma) { |
dccf7369 | 257 | __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); |
1de70612 | 258 | |
82ba2c2a JN |
259 | if (config->reg_general >= 0) { |
260 | value = __lpss_ssp_read_priv(drv_data, | |
261 | config->reg_general); | |
262 | value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE; | |
263 | __lpss_ssp_write_priv(drv_data, | |
264 | config->reg_general, value); | |
265 | } | |
1de70612 | 266 | } |
a0d2642e MW |
267 | } |
268 | ||
269 | static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) | |
270 | { | |
dccf7369 | 271 | const struct lpss_config *config; |
a0d2642e MW |
272 | u32 value; |
273 | ||
dccf7369 JN |
274 | config = lpss_get_config(drv_data); |
275 | ||
276 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); | |
a0d2642e MW |
277 | if (enable) |
278 | value &= ~SPI_CS_CONTROL_CS_HIGH; | |
279 | else | |
280 | value |= SPI_CS_CONTROL_CS_HIGH; | |
dccf7369 | 281 | __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); |
a0d2642e MW |
282 | } |
283 | ||
a7bb3909 EM |
284 | static void cs_assert(struct driver_data *drv_data) |
285 | { | |
286 | struct chip_data *chip = drv_data->cur_chip; | |
287 | ||
2a8626a9 | 288 | if (drv_data->ssp_type == CE4100_SSP) { |
c039dd27 | 289 | pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm); |
2a8626a9 SAS |
290 | return; |
291 | } | |
292 | ||
a7bb3909 EM |
293 | if (chip->cs_control) { |
294 | chip->cs_control(PXA2XX_CS_ASSERT); | |
295 | return; | |
296 | } | |
297 | ||
a0d2642e | 298 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 299 | gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); |
a0d2642e MW |
300 | return; |
301 | } | |
302 | ||
7566bcc7 JN |
303 | if (is_lpss_ssp(drv_data)) |
304 | lpss_ssp_cs_control(drv_data, true); | |
a7bb3909 EM |
305 | } |
306 | ||
307 | static void cs_deassert(struct driver_data *drv_data) | |
308 | { | |
309 | struct chip_data *chip = drv_data->cur_chip; | |
310 | ||
2a8626a9 SAS |
311 | if (drv_data->ssp_type == CE4100_SSP) |
312 | return; | |
313 | ||
a7bb3909 | 314 | if (chip->cs_control) { |
2b2562d3 | 315 | chip->cs_control(PXA2XX_CS_DEASSERT); |
a7bb3909 EM |
316 | return; |
317 | } | |
318 | ||
a0d2642e | 319 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 320 | gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); |
a0d2642e MW |
321 | return; |
322 | } | |
323 | ||
7566bcc7 JN |
324 | if (is_lpss_ssp(drv_data)) |
325 | lpss_ssp_cs_control(drv_data, false); | |
a7bb3909 EM |
326 | } |
327 | ||
cd7bed00 | 328 | int pxa2xx_spi_flush(struct driver_data *drv_data) |
e0c9905e SS |
329 | { |
330 | unsigned long limit = loops_per_jiffy << 1; | |
331 | ||
e0c9905e | 332 | do { |
c039dd27 JN |
333 | while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
334 | pxa2xx_spi_read(drv_data, SSDR); | |
335 | } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); | |
2a8626a9 | 336 | write_SSSR_CS(drv_data, SSSR_ROR); |
e0c9905e SS |
337 | |
338 | return limit; | |
339 | } | |
340 | ||
8d94cc50 | 341 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 342 | { |
9708c121 | 343 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 344 | |
4fdb2424 | 345 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
346 | || (drv_data->tx == drv_data->tx_end)) |
347 | return 0; | |
348 | ||
c039dd27 | 349 | pxa2xx_spi_write(drv_data, SSDR, 0); |
8d94cc50 SS |
350 | drv_data->tx += n_bytes; |
351 | ||
352 | return 1; | |
e0c9905e SS |
353 | } |
354 | ||
8d94cc50 | 355 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 356 | { |
9708c121 | 357 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 358 | |
c039dd27 JN |
359 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
360 | && (drv_data->rx < drv_data->rx_end)) { | |
361 | pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
362 | drv_data->rx += n_bytes; |
363 | } | |
8d94cc50 SS |
364 | |
365 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
366 | } |
367 | ||
8d94cc50 | 368 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 369 | { |
4fdb2424 | 370 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
371 | || (drv_data->tx == drv_data->tx_end)) |
372 | return 0; | |
373 | ||
c039dd27 | 374 | pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); |
8d94cc50 SS |
375 | ++drv_data->tx; |
376 | ||
377 | return 1; | |
e0c9905e SS |
378 | } |
379 | ||
8d94cc50 | 380 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 381 | { |
c039dd27 JN |
382 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
383 | && (drv_data->rx < drv_data->rx_end)) { | |
384 | *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
385 | ++drv_data->rx; |
386 | } | |
8d94cc50 SS |
387 | |
388 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
389 | } |
390 | ||
8d94cc50 | 391 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 392 | { |
4fdb2424 | 393 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
394 | || (drv_data->tx == drv_data->tx_end)) |
395 | return 0; | |
396 | ||
c039dd27 | 397 | pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); |
8d94cc50 SS |
398 | drv_data->tx += 2; |
399 | ||
400 | return 1; | |
e0c9905e SS |
401 | } |
402 | ||
8d94cc50 | 403 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 404 | { |
c039dd27 JN |
405 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
406 | && (drv_data->rx < drv_data->rx_end)) { | |
407 | *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
408 | drv_data->rx += 2; |
409 | } | |
8d94cc50 SS |
410 | |
411 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 412 | } |
8d94cc50 SS |
413 | |
414 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 415 | { |
4fdb2424 | 416 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
417 | || (drv_data->tx == drv_data->tx_end)) |
418 | return 0; | |
419 | ||
c039dd27 | 420 | pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); |
8d94cc50 SS |
421 | drv_data->tx += 4; |
422 | ||
423 | return 1; | |
e0c9905e SS |
424 | } |
425 | ||
8d94cc50 | 426 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 427 | { |
c039dd27 JN |
428 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
429 | && (drv_data->rx < drv_data->rx_end)) { | |
430 | *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
431 | drv_data->rx += 4; |
432 | } | |
8d94cc50 SS |
433 | |
434 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
435 | } |
436 | ||
cd7bed00 | 437 | void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) |
e0c9905e SS |
438 | { |
439 | struct spi_message *msg = drv_data->cur_msg; | |
440 | struct spi_transfer *trans = drv_data->cur_transfer; | |
441 | ||
442 | /* Move to next transfer */ | |
443 | if (trans->transfer_list.next != &msg->transfers) { | |
444 | drv_data->cur_transfer = | |
445 | list_entry(trans->transfer_list.next, | |
446 | struct spi_transfer, | |
447 | transfer_list); | |
448 | return RUNNING_STATE; | |
449 | } else | |
450 | return DONE_STATE; | |
451 | } | |
452 | ||
e0c9905e | 453 | /* caller already set message->status; dma and pio irqs are blocked */ |
5daa3ba0 | 454 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
455 | { |
456 | struct spi_transfer* last_transfer; | |
5daa3ba0 | 457 | struct spi_message *msg; |
e0c9905e | 458 | |
5daa3ba0 SS |
459 | msg = drv_data->cur_msg; |
460 | drv_data->cur_msg = NULL; | |
461 | drv_data->cur_transfer = NULL; | |
5daa3ba0 | 462 | |
23e2c2aa | 463 | last_transfer = list_last_entry(&msg->transfers, struct spi_transfer, |
e0c9905e SS |
464 | transfer_list); |
465 | ||
8423597d NF |
466 | /* Delay if requested before any change in chip select */ |
467 | if (last_transfer->delay_usecs) | |
468 | udelay(last_transfer->delay_usecs); | |
469 | ||
470 | /* Drop chip select UNLESS cs_change is true or we are returning | |
471 | * a message with an error, or next message is for another chip | |
472 | */ | |
e0c9905e | 473 | if (!last_transfer->cs_change) |
a7bb3909 | 474 | cs_deassert(drv_data); |
8423597d NF |
475 | else { |
476 | struct spi_message *next_msg; | |
477 | ||
478 | /* Holding of cs was hinted, but we need to make sure | |
479 | * the next message is for the same chip. Don't waste | |
480 | * time with the following tests unless this was hinted. | |
481 | * | |
482 | * We cannot postpone this until pump_messages, because | |
483 | * after calling msg->complete (below) the driver that | |
484 | * sent the current message could be unloaded, which | |
485 | * could invalidate the cs_control() callback... | |
486 | */ | |
487 | ||
488 | /* get a pointer to the next message, if any */ | |
7f86bde9 | 489 | next_msg = spi_get_next_queued_message(drv_data->master); |
8423597d NF |
490 | |
491 | /* see if the next and current messages point | |
492 | * to the same chip | |
493 | */ | |
494 | if (next_msg && next_msg->spi != msg->spi) | |
495 | next_msg = NULL; | |
496 | if (!next_msg || msg->state == ERROR_STATE) | |
a7bb3909 | 497 | cs_deassert(drv_data); |
8423597d | 498 | } |
e0c9905e | 499 | |
a7bb3909 | 500 | drv_data->cur_chip = NULL; |
c957e8f0 | 501 | spi_finalize_current_message(drv_data->master); |
e0c9905e SS |
502 | } |
503 | ||
579d3bb2 SAS |
504 | static void reset_sccr1(struct driver_data *drv_data) |
505 | { | |
579d3bb2 SAS |
506 | struct chip_data *chip = drv_data->cur_chip; |
507 | u32 sccr1_reg; | |
508 | ||
c039dd27 | 509 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1; |
579d3bb2 SAS |
510 | sccr1_reg &= ~SSCR1_RFT; |
511 | sccr1_reg |= chip->threshold; | |
c039dd27 | 512 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); |
579d3bb2 SAS |
513 | } |
514 | ||
8d94cc50 | 515 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 516 | { |
8d94cc50 | 517 | /* Stop and reset SSP */ |
2a8626a9 | 518 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 519 | reset_sccr1(drv_data); |
2a8626a9 | 520 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 521 | pxa2xx_spi_write(drv_data, SSTO, 0); |
cd7bed00 | 522 | pxa2xx_spi_flush(drv_data); |
c039dd27 JN |
523 | pxa2xx_spi_write(drv_data, SSCR0, |
524 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
e0c9905e | 525 | |
8d94cc50 | 526 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 527 | |
8d94cc50 SS |
528 | drv_data->cur_msg->state = ERROR_STATE; |
529 | tasklet_schedule(&drv_data->pump_transfers); | |
530 | } | |
5daa3ba0 | 531 | |
8d94cc50 SS |
532 | static void int_transfer_complete(struct driver_data *drv_data) |
533 | { | |
8d94cc50 | 534 | /* Stop SSP */ |
2a8626a9 | 535 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 536 | reset_sccr1(drv_data); |
2a8626a9 | 537 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 538 | pxa2xx_spi_write(drv_data, SSTO, 0); |
e0c9905e | 539 | |
25985edc | 540 | /* Update total byte transferred return count actual bytes read */ |
8d94cc50 SS |
541 | drv_data->cur_msg->actual_length += drv_data->len - |
542 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 543 | |
8423597d NF |
544 | /* Transfer delays and chip select release are |
545 | * handled in pump_transfers or giveback | |
546 | */ | |
e0c9905e | 547 | |
8d94cc50 | 548 | /* Move to next transfer */ |
cd7bed00 | 549 | drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); |
e0c9905e | 550 | |
8d94cc50 SS |
551 | /* Schedule transfer tasklet */ |
552 | tasklet_schedule(&drv_data->pump_transfers); | |
553 | } | |
e0c9905e | 554 | |
8d94cc50 SS |
555 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
556 | { | |
c039dd27 JN |
557 | u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ? |
558 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 559 | |
c039dd27 | 560 | u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask; |
e0c9905e | 561 | |
8d94cc50 SS |
562 | if (irq_status & SSSR_ROR) { |
563 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
564 | return IRQ_HANDLED; | |
565 | } | |
e0c9905e | 566 | |
8d94cc50 | 567 | if (irq_status & SSSR_TINT) { |
c039dd27 | 568 | pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT); |
8d94cc50 SS |
569 | if (drv_data->read(drv_data)) { |
570 | int_transfer_complete(drv_data); | |
571 | return IRQ_HANDLED; | |
572 | } | |
573 | } | |
e0c9905e | 574 | |
8d94cc50 SS |
575 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
576 | do { | |
577 | if (drv_data->read(drv_data)) { | |
578 | int_transfer_complete(drv_data); | |
579 | return IRQ_HANDLED; | |
580 | } | |
581 | } while (drv_data->write(drv_data)); | |
e0c9905e | 582 | |
8d94cc50 SS |
583 | if (drv_data->read(drv_data)) { |
584 | int_transfer_complete(drv_data); | |
585 | return IRQ_HANDLED; | |
586 | } | |
e0c9905e | 587 | |
8d94cc50 | 588 | if (drv_data->tx == drv_data->tx_end) { |
579d3bb2 SAS |
589 | u32 bytes_left; |
590 | u32 sccr1_reg; | |
591 | ||
c039dd27 | 592 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); |
579d3bb2 SAS |
593 | sccr1_reg &= ~SSCR1_TIE; |
594 | ||
595 | /* | |
596 | * PXA25x_SSP has no timeout, set up rx threshould for the | |
25985edc | 597 | * remaining RX bytes. |
579d3bb2 | 598 | */ |
2a8626a9 | 599 | if (pxa25x_ssp_comp(drv_data)) { |
4fdb2424 | 600 | u32 rx_thre; |
579d3bb2 | 601 | |
4fdb2424 | 602 | pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); |
579d3bb2 SAS |
603 | |
604 | bytes_left = drv_data->rx_end - drv_data->rx; | |
605 | switch (drv_data->n_bytes) { | |
606 | case 4: | |
607 | bytes_left >>= 1; | |
608 | case 2: | |
609 | bytes_left >>= 1; | |
8d94cc50 | 610 | } |
579d3bb2 | 611 | |
4fdb2424 WC |
612 | rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); |
613 | if (rx_thre > bytes_left) | |
614 | rx_thre = bytes_left; | |
579d3bb2 | 615 | |
4fdb2424 | 616 | pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); |
e0c9905e | 617 | } |
c039dd27 | 618 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); |
e0c9905e SS |
619 | } |
620 | ||
5daa3ba0 SS |
621 | /* We did something */ |
622 | return IRQ_HANDLED; | |
e0c9905e SS |
623 | } |
624 | ||
7d12e780 | 625 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 626 | { |
c7bec5ab | 627 | struct driver_data *drv_data = dev_id; |
7d94a505 | 628 | u32 sccr1_reg; |
49cbb1e0 SAS |
629 | u32 mask = drv_data->mask_sr; |
630 | u32 status; | |
631 | ||
7d94a505 MW |
632 | /* |
633 | * The IRQ might be shared with other peripherals so we must first | |
634 | * check that are we RPM suspended or not. If we are we assume that | |
635 | * the IRQ was not for us (we shouldn't be RPM suspended when the | |
636 | * interrupt is enabled). | |
637 | */ | |
638 | if (pm_runtime_suspended(&drv_data->pdev->dev)) | |
639 | return IRQ_NONE; | |
640 | ||
269e4a41 MW |
641 | /* |
642 | * If the device is not yet in RPM suspended state and we get an | |
643 | * interrupt that is meant for another device, check if status bits | |
644 | * are all set to one. That means that the device is already | |
645 | * powered off. | |
646 | */ | |
c039dd27 | 647 | status = pxa2xx_spi_read(drv_data, SSSR); |
269e4a41 MW |
648 | if (status == ~0) |
649 | return IRQ_NONE; | |
650 | ||
c039dd27 | 651 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); |
49cbb1e0 SAS |
652 | |
653 | /* Ignore possible writes if we don't need to write */ | |
654 | if (!(sccr1_reg & SSCR1_TIE)) | |
655 | mask &= ~SSSR_TFS; | |
656 | ||
657 | if (!(status & mask)) | |
658 | return IRQ_NONE; | |
e0c9905e SS |
659 | |
660 | if (!drv_data->cur_msg) { | |
5daa3ba0 | 661 | |
c039dd27 JN |
662 | pxa2xx_spi_write(drv_data, SSCR0, |
663 | pxa2xx_spi_read(drv_data, SSCR0) | |
664 | & ~SSCR0_SSE); | |
665 | pxa2xx_spi_write(drv_data, SSCR1, | |
666 | pxa2xx_spi_read(drv_data, SSCR1) | |
667 | & ~drv_data->int_cr1); | |
2a8626a9 | 668 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 669 | pxa2xx_spi_write(drv_data, SSTO, 0); |
2a8626a9 | 670 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
5daa3ba0 | 671 | |
f6bd03a7 JN |
672 | dev_err(&drv_data->pdev->dev, |
673 | "bad message state in interrupt handler\n"); | |
5daa3ba0 | 674 | |
e0c9905e SS |
675 | /* Never fail */ |
676 | return IRQ_HANDLED; | |
677 | } | |
678 | ||
679 | return drv_data->transfer_handler(drv_data); | |
680 | } | |
681 | ||
e5262d05 | 682 | /* |
9df461ec AS |
683 | * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply |
684 | * input frequency by fractions of 2^24. It also has a divider by 5. | |
685 | * | |
686 | * There are formulas to get baud rate value for given input frequency and | |
687 | * divider parameters, such as DDS_CLK_RATE and SCR: | |
688 | * | |
689 | * Fsys = 200MHz | |
690 | * | |
691 | * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1) | |
692 | * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2) | |
693 | * | |
694 | * DDS_CLK_RATE either 2^n or 2^n / 5. | |
695 | * SCR is in range 0 .. 255 | |
696 | * | |
697 | * Divisor = 5^i * 2^j * 2 * k | |
698 | * i = [0, 1] i = 1 iff j = 0 or j > 3 | |
699 | * j = [0, 23] j = 0 iff i = 1 | |
700 | * k = [1, 256] | |
701 | * Special case: j = 0, i = 1: Divisor = 2 / 5 | |
702 | * | |
703 | * Accordingly to the specification the recommended values for DDS_CLK_RATE | |
704 | * are: | |
705 | * Case 1: 2^n, n = [0, 23] | |
706 | * Case 2: 2^24 * 2 / 5 (0x666666) | |
707 | * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333) | |
708 | * | |
709 | * In all cases the lowest possible value is better. | |
710 | * | |
711 | * The function calculates parameters for all cases and chooses the one closest | |
712 | * to the asked baud rate. | |
e5262d05 | 713 | */ |
9df461ec AS |
714 | static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) |
715 | { | |
716 | unsigned long xtal = 200000000; | |
717 | unsigned long fref = xtal / 2; /* mandatory division by 2, | |
718 | see (2) */ | |
719 | /* case 3 */ | |
720 | unsigned long fref1 = fref / 2; /* case 1 */ | |
721 | unsigned long fref2 = fref * 2 / 5; /* case 2 */ | |
722 | unsigned long scale; | |
723 | unsigned long q, q1, q2; | |
724 | long r, r1, r2; | |
725 | u32 mul; | |
726 | ||
727 | /* Case 1 */ | |
728 | ||
729 | /* Set initial value for DDS_CLK_RATE */ | |
730 | mul = (1 << 24) >> 1; | |
731 | ||
732 | /* Calculate initial quot */ | |
733 | q1 = DIV_ROUND_CLOSEST(fref1, rate); | |
734 | ||
735 | /* Scale q1 if it's too big */ | |
736 | if (q1 > 256) { | |
737 | /* Scale q1 to range [1, 512] */ | |
738 | scale = fls_long(q1 - 1); | |
739 | if (scale > 9) { | |
740 | q1 >>= scale - 9; | |
741 | mul >>= scale - 9; | |
e5262d05 | 742 | } |
9df461ec AS |
743 | |
744 | /* Round the result if we have a remainder */ | |
745 | q1 += q1 & 1; | |
746 | } | |
747 | ||
748 | /* Decrease DDS_CLK_RATE as much as we can without loss in precision */ | |
749 | scale = __ffs(q1); | |
750 | q1 >>= scale; | |
751 | mul >>= scale; | |
752 | ||
753 | /* Get the remainder */ | |
754 | r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); | |
755 | ||
756 | /* Case 2 */ | |
757 | ||
758 | q2 = DIV_ROUND_CLOSEST(fref2, rate); | |
759 | r2 = abs(fref2 / q2 - rate); | |
760 | ||
761 | /* | |
762 | * Choose the best between two: less remainder we have the better. We | |
763 | * can't go case 2 if q2 is greater than 256 since SCR register can | |
764 | * hold only values 0 .. 255. | |
765 | */ | |
766 | if (r2 >= r1 || q2 > 256) { | |
767 | /* case 1 is better */ | |
768 | r = r1; | |
769 | q = q1; | |
770 | } else { | |
771 | /* case 2 is better */ | |
772 | r = r2; | |
773 | q = q2; | |
774 | mul = (1 << 24) * 2 / 5; | |
e5262d05 WC |
775 | } |
776 | ||
9df461ec AS |
777 | /* Check case 3 only If the divisor is big enough */ |
778 | if (fref / rate >= 80) { | |
779 | u64 fssp; | |
780 | u32 m; | |
781 | ||
782 | /* Calculate initial quot */ | |
783 | q1 = DIV_ROUND_CLOSEST(fref, rate); | |
784 | m = (1 << 24) / q1; | |
785 | ||
786 | /* Get the remainder */ | |
787 | fssp = (u64)fref * m; | |
788 | do_div(fssp, 1 << 24); | |
789 | r1 = abs(fssp - rate); | |
790 | ||
791 | /* Choose this one if it suits better */ | |
792 | if (r1 < r) { | |
793 | /* case 3 is better */ | |
794 | q = 1; | |
795 | mul = m; | |
796 | } | |
797 | } | |
e5262d05 | 798 | |
9df461ec AS |
799 | *dds = mul; |
800 | return q - 1; | |
e5262d05 WC |
801 | } |
802 | ||
3343b7a6 | 803 | static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) |
2f1a74e5 | 804 | { |
3343b7a6 MW |
805 | unsigned long ssp_clk = drv_data->max_clk_rate; |
806 | const struct ssp_device *ssp = drv_data->ssp; | |
807 | ||
808 | rate = min_t(int, ssp_clk, rate); | |
2f1a74e5 | 809 | |
2a8626a9 | 810 | if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) |
025ffe88 | 811 | return (ssp_clk / (2 * rate) - 1) & 0xff; |
2f1a74e5 | 812 | else |
025ffe88 | 813 | return (ssp_clk / rate - 1) & 0xfff; |
2f1a74e5 | 814 | } |
815 | ||
e5262d05 WC |
816 | static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, |
817 | struct chip_data *chip, int rate) | |
818 | { | |
025ffe88 | 819 | unsigned int clk_div; |
e5262d05 WC |
820 | |
821 | switch (drv_data->ssp_type) { | |
822 | case QUARK_X1000_SSP: | |
9df461ec | 823 | clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); |
eecacf73 | 824 | break; |
e5262d05 | 825 | default: |
025ffe88 | 826 | clk_div = ssp_get_clk_div(drv_data, rate); |
eecacf73 | 827 | break; |
e5262d05 | 828 | } |
025ffe88 | 829 | return clk_div << 8; |
e5262d05 WC |
830 | } |
831 | ||
e0c9905e SS |
832 | static void pump_transfers(unsigned long data) |
833 | { | |
834 | struct driver_data *drv_data = (struct driver_data *)data; | |
835 | struct spi_message *message = NULL; | |
836 | struct spi_transfer *transfer = NULL; | |
837 | struct spi_transfer *previous = NULL; | |
838 | struct chip_data *chip = NULL; | |
9708c121 SS |
839 | u32 clk_div = 0; |
840 | u8 bits = 0; | |
841 | u32 speed = 0; | |
842 | u32 cr0; | |
8d94cc50 SS |
843 | u32 cr1; |
844 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
845 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
4fdb2424 | 846 | u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); |
e0c9905e SS |
847 | |
848 | /* Get current state information */ | |
849 | message = drv_data->cur_msg; | |
850 | transfer = drv_data->cur_transfer; | |
851 | chip = drv_data->cur_chip; | |
852 | ||
853 | /* Handle for abort */ | |
854 | if (message->state == ERROR_STATE) { | |
855 | message->status = -EIO; | |
5daa3ba0 | 856 | giveback(drv_data); |
e0c9905e SS |
857 | return; |
858 | } | |
859 | ||
860 | /* Handle end of message */ | |
861 | if (message->state == DONE_STATE) { | |
862 | message->status = 0; | |
5daa3ba0 | 863 | giveback(drv_data); |
e0c9905e SS |
864 | return; |
865 | } | |
866 | ||
8423597d | 867 | /* Delay if requested at end of transfer before CS change */ |
e0c9905e SS |
868 | if (message->state == RUNNING_STATE) { |
869 | previous = list_entry(transfer->transfer_list.prev, | |
870 | struct spi_transfer, | |
871 | transfer_list); | |
872 | if (previous->delay_usecs) | |
873 | udelay(previous->delay_usecs); | |
8423597d NF |
874 | |
875 | /* Drop chip select only if cs_change is requested */ | |
876 | if (previous->cs_change) | |
a7bb3909 | 877 | cs_deassert(drv_data); |
e0c9905e SS |
878 | } |
879 | ||
cd7bed00 MW |
880 | /* Check if we can DMA this transfer */ |
881 | if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { | |
7e964455 NF |
882 | |
883 | /* reject already-mapped transfers; PIO won't always work */ | |
884 | if (message->is_dma_mapped | |
885 | || transfer->rx_dma || transfer->tx_dma) { | |
886 | dev_err(&drv_data->pdev->dev, | |
f6bd03a7 JN |
887 | "pump_transfers: mapped transfer length of " |
888 | "%u is greater than %d\n", | |
7e964455 NF |
889 | transfer->len, MAX_DMA_LEN); |
890 | message->status = -EINVAL; | |
891 | giveback(drv_data); | |
892 | return; | |
893 | } | |
894 | ||
895 | /* warn ... we force this to PIO mode */ | |
f6bd03a7 JN |
896 | dev_warn_ratelimited(&message->spi->dev, |
897 | "pump_transfers: DMA disabled for transfer length %ld " | |
898 | "greater than %d\n", | |
899 | (long)drv_data->len, MAX_DMA_LEN); | |
8d94cc50 SS |
900 | } |
901 | ||
e0c9905e | 902 | /* Setup the transfer state based on the type of transfer */ |
cd7bed00 | 903 | if (pxa2xx_spi_flush(drv_data) == 0) { |
e0c9905e SS |
904 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
905 | message->status = -EIO; | |
5daa3ba0 | 906 | giveback(drv_data); |
e0c9905e SS |
907 | return; |
908 | } | |
9708c121 | 909 | drv_data->n_bytes = chip->n_bytes; |
e0c9905e SS |
910 | drv_data->tx = (void *)transfer->tx_buf; |
911 | drv_data->tx_end = drv_data->tx + transfer->len; | |
912 | drv_data->rx = transfer->rx_buf; | |
913 | drv_data->rx_end = drv_data->rx + transfer->len; | |
914 | drv_data->rx_dma = transfer->rx_dma; | |
915 | drv_data->tx_dma = transfer->tx_dma; | |
cd7bed00 | 916 | drv_data->len = transfer->len; |
e0c9905e SS |
917 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
918 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
919 | |
920 | /* Change speed and bit per word on a per transfer */ | |
8d94cc50 | 921 | cr0 = chip->cr0; |
9708c121 SS |
922 | if (transfer->speed_hz || transfer->bits_per_word) { |
923 | ||
9708c121 SS |
924 | bits = chip->bits_per_word; |
925 | speed = chip->speed_hz; | |
926 | ||
927 | if (transfer->speed_hz) | |
928 | speed = transfer->speed_hz; | |
929 | ||
930 | if (transfer->bits_per_word) | |
931 | bits = transfer->bits_per_word; | |
932 | ||
e5262d05 | 933 | clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, speed); |
9708c121 SS |
934 | |
935 | if (bits <= 8) { | |
936 | drv_data->n_bytes = 1; | |
9708c121 SS |
937 | drv_data->read = drv_data->read != null_reader ? |
938 | u8_reader : null_reader; | |
939 | drv_data->write = drv_data->write != null_writer ? | |
940 | u8_writer : null_writer; | |
941 | } else if (bits <= 16) { | |
942 | drv_data->n_bytes = 2; | |
9708c121 SS |
943 | drv_data->read = drv_data->read != null_reader ? |
944 | u16_reader : null_reader; | |
945 | drv_data->write = drv_data->write != null_writer ? | |
946 | u16_writer : null_writer; | |
947 | } else if (bits <= 32) { | |
948 | drv_data->n_bytes = 4; | |
9708c121 SS |
949 | drv_data->read = drv_data->read != null_reader ? |
950 | u32_reader : null_reader; | |
951 | drv_data->write = drv_data->write != null_writer ? | |
952 | u32_writer : null_writer; | |
953 | } | |
8d94cc50 SS |
954 | /* if bits/word is changed in dma mode, then must check the |
955 | * thresholds and burst also */ | |
956 | if (chip->enable_dma) { | |
cd7bed00 MW |
957 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, |
958 | message->spi, | |
8d94cc50 SS |
959 | bits, &dma_burst, |
960 | &dma_thresh)) | |
f6bd03a7 JN |
961 | dev_warn_ratelimited(&message->spi->dev, |
962 | "pump_transfers: DMA burst size reduced to match bits_per_word\n"); | |
8d94cc50 | 963 | } |
9708c121 | 964 | |
4fdb2424 | 965 | cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); |
9708c121 SS |
966 | } |
967 | ||
e0c9905e SS |
968 | message->state = RUNNING_STATE; |
969 | ||
7e964455 | 970 | drv_data->dma_mapped = 0; |
cd7bed00 MW |
971 | if (pxa2xx_spi_dma_is_possible(drv_data->len)) |
972 | drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); | |
7e964455 | 973 | if (drv_data->dma_mapped) { |
e0c9905e SS |
974 | |
975 | /* Ensure we have the correct interrupt handler */ | |
cd7bed00 MW |
976 | drv_data->transfer_handler = pxa2xx_spi_dma_transfer; |
977 | ||
978 | pxa2xx_spi_dma_prepare(drv_data, dma_burst); | |
e0c9905e | 979 | |
8d94cc50 SS |
980 | /* Clear status and start DMA engine */ |
981 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
c039dd27 | 982 | pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); |
cd7bed00 MW |
983 | |
984 | pxa2xx_spi_dma_start(drv_data); | |
e0c9905e SS |
985 | } else { |
986 | /* Ensure we have the correct interrupt handler */ | |
987 | drv_data->transfer_handler = interrupt_transfer; | |
988 | ||
8d94cc50 SS |
989 | /* Clear status */ |
990 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
2a8626a9 | 991 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
8d94cc50 SS |
992 | } |
993 | ||
a0d2642e | 994 | if (is_lpss_ssp(drv_data)) { |
c039dd27 JN |
995 | if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff) |
996 | != chip->lpss_rx_threshold) | |
997 | pxa2xx_spi_write(drv_data, SSIRF, | |
998 | chip->lpss_rx_threshold); | |
999 | if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff) | |
1000 | != chip->lpss_tx_threshold) | |
1001 | pxa2xx_spi_write(drv_data, SSITF, | |
1002 | chip->lpss_tx_threshold); | |
a0d2642e MW |
1003 | } |
1004 | ||
e5262d05 | 1005 | if (is_quark_x1000_ssp(drv_data) && |
c039dd27 JN |
1006 | (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate)) |
1007 | pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate); | |
e5262d05 | 1008 | |
8d94cc50 | 1009 | /* see if we need to reload the config registers */ |
c039dd27 JN |
1010 | if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0) |
1011 | || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask) | |
1012 | != (cr1 & change_mask)) { | |
b97c74bd | 1013 | /* stop the SSP, and update the other bits */ |
c039dd27 | 1014 | pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE); |
2a8626a9 | 1015 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1016 | pxa2xx_spi_write(drv_data, SSTO, chip->timeout); |
b97c74bd | 1017 | /* first set CR1 without interrupt and service enables */ |
c039dd27 | 1018 | pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask); |
b97c74bd | 1019 | /* restart the SSP */ |
c039dd27 | 1020 | pxa2xx_spi_write(drv_data, SSCR0, cr0); |
b97c74bd | 1021 | |
8d94cc50 | 1022 | } else { |
2a8626a9 | 1023 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1024 | pxa2xx_spi_write(drv_data, SSTO, chip->timeout); |
e0c9905e | 1025 | } |
b97c74bd | 1026 | |
a7bb3909 | 1027 | cs_assert(drv_data); |
b97c74bd NF |
1028 | |
1029 | /* after chip select, release the data by enabling service | |
1030 | * requests and interrupts, without changing any mode bits */ | |
c039dd27 | 1031 | pxa2xx_spi_write(drv_data, SSCR1, cr1); |
e0c9905e SS |
1032 | } |
1033 | ||
7f86bde9 MW |
1034 | static int pxa2xx_spi_transfer_one_message(struct spi_master *master, |
1035 | struct spi_message *msg) | |
e0c9905e | 1036 | { |
7f86bde9 | 1037 | struct driver_data *drv_data = spi_master_get_devdata(master); |
e0c9905e | 1038 | |
7f86bde9 | 1039 | drv_data->cur_msg = msg; |
e0c9905e SS |
1040 | /* Initial message state*/ |
1041 | drv_data->cur_msg->state = START_STATE; | |
1042 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
1043 | struct spi_transfer, | |
1044 | transfer_list); | |
1045 | ||
8d94cc50 SS |
1046 | /* prepare to setup the SSP, in pump_transfers, using the per |
1047 | * chip configuration */ | |
e0c9905e | 1048 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
1049 | |
1050 | /* Mark as busy and launch transfers */ | |
1051 | tasklet_schedule(&drv_data->pump_transfers); | |
e0c9905e SS |
1052 | return 0; |
1053 | } | |
1054 | ||
7d94a505 MW |
1055 | static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) |
1056 | { | |
1057 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
1058 | ||
1059 | /* Disable the SSP now */ | |
c039dd27 JN |
1060 | pxa2xx_spi_write(drv_data, SSCR0, |
1061 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
7d94a505 | 1062 | |
7d94a505 MW |
1063 | return 0; |
1064 | } | |
1065 | ||
a7bb3909 EM |
1066 | static int setup_cs(struct spi_device *spi, struct chip_data *chip, |
1067 | struct pxa2xx_spi_chip *chip_info) | |
1068 | { | |
1069 | int err = 0; | |
1070 | ||
1071 | if (chip == NULL || chip_info == NULL) | |
1072 | return 0; | |
1073 | ||
1074 | /* NOTE: setup() can be called multiple times, possibly with | |
1075 | * different chip_info, release previously requested GPIO | |
1076 | */ | |
1077 | if (gpio_is_valid(chip->gpio_cs)) | |
1078 | gpio_free(chip->gpio_cs); | |
1079 | ||
1080 | /* If (*cs_control) is provided, ignore GPIO chip select */ | |
1081 | if (chip_info->cs_control) { | |
1082 | chip->cs_control = chip_info->cs_control; | |
1083 | return 0; | |
1084 | } | |
1085 | ||
1086 | if (gpio_is_valid(chip_info->gpio_cs)) { | |
1087 | err = gpio_request(chip_info->gpio_cs, "SPI_CS"); | |
1088 | if (err) { | |
f6bd03a7 JN |
1089 | dev_err(&spi->dev, "failed to request chip select GPIO%d\n", |
1090 | chip_info->gpio_cs); | |
a7bb3909 EM |
1091 | return err; |
1092 | } | |
1093 | ||
1094 | chip->gpio_cs = chip_info->gpio_cs; | |
1095 | chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; | |
1096 | ||
1097 | err = gpio_direction_output(chip->gpio_cs, | |
1098 | !chip->gpio_cs_inverted); | |
1099 | } | |
1100 | ||
1101 | return err; | |
1102 | } | |
1103 | ||
e0c9905e SS |
1104 | static int setup(struct spi_device *spi) |
1105 | { | |
1106 | struct pxa2xx_spi_chip *chip_info = NULL; | |
1107 | struct chip_data *chip; | |
dccf7369 | 1108 | const struct lpss_config *config; |
e0c9905e SS |
1109 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
1110 | unsigned int clk_div; | |
a0d2642e MW |
1111 | uint tx_thres, tx_hi_thres, rx_thres; |
1112 | ||
e5262d05 WC |
1113 | switch (drv_data->ssp_type) { |
1114 | case QUARK_X1000_SSP: | |
1115 | tx_thres = TX_THRESH_QUARK_X1000_DFLT; | |
1116 | tx_hi_thres = 0; | |
1117 | rx_thres = RX_THRESH_QUARK_X1000_DFLT; | |
1118 | break; | |
03fbf488 JN |
1119 | case LPSS_LPT_SSP: |
1120 | case LPSS_BYT_SSP: | |
34cadd9c | 1121 | case LPSS_SPT_SSP: |
dccf7369 JN |
1122 | config = lpss_get_config(drv_data); |
1123 | tx_thres = config->tx_threshold_lo; | |
1124 | tx_hi_thres = config->tx_threshold_hi; | |
1125 | rx_thres = config->rx_threshold; | |
e5262d05 WC |
1126 | break; |
1127 | default: | |
a0d2642e MW |
1128 | tx_thres = TX_THRESH_DFLT; |
1129 | tx_hi_thres = 0; | |
1130 | rx_thres = RX_THRESH_DFLT; | |
e5262d05 | 1131 | break; |
a0d2642e | 1132 | } |
e0c9905e | 1133 | |
8d94cc50 | 1134 | /* Only alloc on first setup */ |
e0c9905e | 1135 | chip = spi_get_ctldata(spi); |
8d94cc50 | 1136 | if (!chip) { |
e0c9905e | 1137 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
9deae459 | 1138 | if (!chip) |
e0c9905e SS |
1139 | return -ENOMEM; |
1140 | ||
2a8626a9 SAS |
1141 | if (drv_data->ssp_type == CE4100_SSP) { |
1142 | if (spi->chip_select > 4) { | |
f6bd03a7 JN |
1143 | dev_err(&spi->dev, |
1144 | "failed setup: cs number must not be > 4.\n"); | |
2a8626a9 SAS |
1145 | kfree(chip); |
1146 | return -EINVAL; | |
1147 | } | |
1148 | ||
1149 | chip->frm = spi->chip_select; | |
1150 | } else | |
1151 | chip->gpio_cs = -1; | |
e0c9905e | 1152 | chip->enable_dma = 0; |
f1f640a9 | 1153 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
1154 | } |
1155 | ||
8d94cc50 SS |
1156 | /* protocol drivers may change the chip settings, so... |
1157 | * if chip_info exists, use it */ | |
1158 | chip_info = spi->controller_data; | |
1159 | ||
e0c9905e | 1160 | /* chip_info isn't always needed */ |
8d94cc50 | 1161 | chip->cr1 = 0; |
e0c9905e | 1162 | if (chip_info) { |
f1f640a9 VS |
1163 | if (chip_info->timeout) |
1164 | chip->timeout = chip_info->timeout; | |
1165 | if (chip_info->tx_threshold) | |
1166 | tx_thres = chip_info->tx_threshold; | |
a0d2642e MW |
1167 | if (chip_info->tx_hi_threshold) |
1168 | tx_hi_thres = chip_info->tx_hi_threshold; | |
f1f640a9 VS |
1169 | if (chip_info->rx_threshold) |
1170 | rx_thres = chip_info->rx_threshold; | |
1171 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e | 1172 | chip->dma_threshold = 0; |
e0c9905e SS |
1173 | if (chip_info->enable_loopback) |
1174 | chip->cr1 = SSCR1_LBM; | |
a3496855 MW |
1175 | } else if (ACPI_HANDLE(&spi->dev)) { |
1176 | /* | |
1177 | * Slave devices enumerated from ACPI namespace don't | |
1178 | * usually have chip_info but we still might want to use | |
1179 | * DMA with them. | |
1180 | */ | |
1181 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e SS |
1182 | } |
1183 | ||
a0d2642e MW |
1184 | chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); |
1185 | chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | |
1186 | | SSITF_TxHiThresh(tx_hi_thres); | |
1187 | ||
8d94cc50 SS |
1188 | /* set dma burst and threshold outside of chip_info path so that if |
1189 | * chip_info goes away after setting chip->enable_dma, the | |
1190 | * burst and threshold can still respond to changes in bits_per_word */ | |
1191 | if (chip->enable_dma) { | |
1192 | /* set up legal burst and threshold for dma */ | |
cd7bed00 MW |
1193 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, |
1194 | spi->bits_per_word, | |
8d94cc50 SS |
1195 | &chip->dma_burst_size, |
1196 | &chip->dma_threshold)) { | |
f6bd03a7 JN |
1197 | dev_warn(&spi->dev, |
1198 | "in setup: DMA burst size reduced to match bits_per_word\n"); | |
8d94cc50 SS |
1199 | } |
1200 | } | |
1201 | ||
e5262d05 | 1202 | clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, spi->max_speed_hz); |
9708c121 | 1203 | chip->speed_hz = spi->max_speed_hz; |
e0c9905e | 1204 | |
4fdb2424 WC |
1205 | chip->cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, |
1206 | spi->bits_per_word); | |
e5262d05 WC |
1207 | switch (drv_data->ssp_type) { |
1208 | case QUARK_X1000_SSP: | |
1209 | chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) | |
1210 | & QUARK_X1000_SSCR1_RFT) | |
1211 | | (QUARK_X1000_SSCR1_TxTresh(tx_thres) | |
1212 | & QUARK_X1000_SSCR1_TFT); | |
1213 | break; | |
1214 | default: | |
1215 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | | |
1216 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
1217 | break; | |
1218 | } | |
1219 | ||
7f6ee1ad JC |
1220 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
1221 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
1222 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e | 1223 | |
b833172f MW |
1224 | if (spi->mode & SPI_LOOP) |
1225 | chip->cr1 |= SSCR1_LBM; | |
1226 | ||
e0c9905e | 1227 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ |
2a8626a9 | 1228 | if (!pxa25x_ssp_comp(drv_data)) |
7d077197 | 1229 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 1230 | drv_data->max_clk_rate |
c9840daa EM |
1231 | / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), |
1232 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e | 1233 | else |
7d077197 | 1234 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 1235 | drv_data->max_clk_rate / 2 |
c9840daa EM |
1236 | / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), |
1237 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e SS |
1238 | |
1239 | if (spi->bits_per_word <= 8) { | |
1240 | chip->n_bytes = 1; | |
e0c9905e SS |
1241 | chip->read = u8_reader; |
1242 | chip->write = u8_writer; | |
1243 | } else if (spi->bits_per_word <= 16) { | |
1244 | chip->n_bytes = 2; | |
e0c9905e SS |
1245 | chip->read = u16_reader; |
1246 | chip->write = u16_writer; | |
1247 | } else if (spi->bits_per_word <= 32) { | |
e5262d05 WC |
1248 | if (!is_quark_x1000_ssp(drv_data)) |
1249 | chip->cr0 |= SSCR0_EDSS; | |
e0c9905e | 1250 | chip->n_bytes = 4; |
e0c9905e SS |
1251 | chip->read = u32_reader; |
1252 | chip->write = u32_writer; | |
e0c9905e | 1253 | } |
9708c121 | 1254 | chip->bits_per_word = spi->bits_per_word; |
e0c9905e SS |
1255 | |
1256 | spi_set_ctldata(spi, chip); | |
1257 | ||
2a8626a9 SAS |
1258 | if (drv_data->ssp_type == CE4100_SSP) |
1259 | return 0; | |
1260 | ||
a7bb3909 | 1261 | return setup_cs(spi, chip, chip_info); |
e0c9905e SS |
1262 | } |
1263 | ||
0ffa0285 | 1264 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1265 | { |
0ffa0285 | 1266 | struct chip_data *chip = spi_get_ctldata(spi); |
2a8626a9 | 1267 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
e0c9905e | 1268 | |
7348d82a DR |
1269 | if (!chip) |
1270 | return; | |
1271 | ||
2a8626a9 | 1272 | if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) |
a7bb3909 EM |
1273 | gpio_free(chip->gpio_cs); |
1274 | ||
e0c9905e SS |
1275 | kfree(chip); |
1276 | } | |
1277 | ||
a3496855 | 1278 | #ifdef CONFIG_ACPI |
03fbf488 | 1279 | |
8422ddf7 | 1280 | static const struct acpi_device_id pxa2xx_spi_acpi_match[] = { |
03fbf488 JN |
1281 | { "INT33C0", LPSS_LPT_SSP }, |
1282 | { "INT33C1", LPSS_LPT_SSP }, | |
1283 | { "INT3430", LPSS_LPT_SSP }, | |
1284 | { "INT3431", LPSS_LPT_SSP }, | |
1285 | { "80860F0E", LPSS_BYT_SSP }, | |
1286 | { "8086228E", LPSS_BYT_SSP }, | |
1287 | { }, | |
1288 | }; | |
1289 | MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); | |
1290 | ||
34cadd9c JN |
1291 | /* |
1292 | * PCI IDs of compound devices that integrate both host controller and private | |
1293 | * integrated DMA engine. Please note these are not used in module | |
1294 | * autoloading and probing in this module but matching the LPSS SSP type. | |
1295 | */ | |
1296 | static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = { | |
1297 | /* SPT-LP */ | |
1298 | { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP }, | |
1299 | { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP }, | |
1300 | /* SPT-H */ | |
1301 | { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP }, | |
1302 | { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP }, | |
94e5c23d | 1303 | { }, |
34cadd9c JN |
1304 | }; |
1305 | ||
1306 | static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param) | |
1307 | { | |
1308 | struct device *dev = param; | |
1309 | ||
1310 | if (dev != chan->device->dev->parent) | |
1311 | return false; | |
1312 | ||
1313 | return true; | |
1314 | } | |
1315 | ||
a3496855 MW |
1316 | static struct pxa2xx_spi_master * |
1317 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | |
1318 | { | |
1319 | struct pxa2xx_spi_master *pdata; | |
a3496855 MW |
1320 | struct acpi_device *adev; |
1321 | struct ssp_device *ssp; | |
1322 | struct resource *res; | |
34cadd9c JN |
1323 | const struct acpi_device_id *adev_id = NULL; |
1324 | const struct pci_device_id *pcidev_id = NULL; | |
03fbf488 | 1325 | int devid, type; |
a3496855 MW |
1326 | |
1327 | if (!ACPI_HANDLE(&pdev->dev) || | |
1328 | acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
1329 | return NULL; | |
1330 | ||
34cadd9c JN |
1331 | if (dev_is_pci(pdev->dev.parent)) |
1332 | pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, | |
1333 | to_pci_dev(pdev->dev.parent)); | |
1334 | else | |
1335 | adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table, | |
1336 | &pdev->dev); | |
1337 | ||
1338 | if (adev_id) | |
1339 | type = (int)adev_id->driver_data; | |
1340 | else if (pcidev_id) | |
1341 | type = (int)pcidev_id->driver_data; | |
03fbf488 JN |
1342 | else |
1343 | return NULL; | |
1344 | ||
cc0ee987 | 1345 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
9deae459 | 1346 | if (!pdata) |
a3496855 | 1347 | return NULL; |
a3496855 MW |
1348 | |
1349 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1350 | if (!res) | |
1351 | return NULL; | |
1352 | ||
1353 | ssp = &pdata->ssp; | |
1354 | ||
1355 | ssp->phys_base = res->start; | |
cbfd6a21 SK |
1356 | ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); |
1357 | if (IS_ERR(ssp->mmio_base)) | |
6dc81f6f | 1358 | return NULL; |
a3496855 | 1359 | |
34cadd9c JN |
1360 | if (pcidev_id) { |
1361 | pdata->tx_param = pdev->dev.parent; | |
1362 | pdata->rx_param = pdev->dev.parent; | |
1363 | pdata->dma_filter = pxa2xx_spi_idma_filter; | |
1364 | } | |
1365 | ||
a3496855 MW |
1366 | ssp->clk = devm_clk_get(&pdev->dev, NULL); |
1367 | ssp->irq = platform_get_irq(pdev, 0); | |
03fbf488 | 1368 | ssp->type = type; |
a3496855 MW |
1369 | ssp->pdev = pdev; |
1370 | ||
1371 | ssp->port_id = -1; | |
1372 | if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid)) | |
1373 | ssp->port_id = devid; | |
1374 | ||
1375 | pdata->num_chipselect = 1; | |
cddb339b | 1376 | pdata->enable_dma = true; |
a3496855 MW |
1377 | |
1378 | return pdata; | |
1379 | } | |
1380 | ||
a3496855 MW |
1381 | #else |
1382 | static inline struct pxa2xx_spi_master * | |
1383 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | |
1384 | { | |
1385 | return NULL; | |
1386 | } | |
1387 | #endif | |
1388 | ||
fd4a319b | 1389 | static int pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1390 | { |
1391 | struct device *dev = &pdev->dev; | |
1392 | struct pxa2xx_spi_master *platform_info; | |
1393 | struct spi_master *master; | |
65a00a20 | 1394 | struct driver_data *drv_data; |
2f1a74e5 | 1395 | struct ssp_device *ssp; |
65a00a20 | 1396 | int status; |
c039dd27 | 1397 | u32 tmp; |
e0c9905e | 1398 | |
851bacf5 MW |
1399 | platform_info = dev_get_platdata(dev); |
1400 | if (!platform_info) { | |
a3496855 MW |
1401 | platform_info = pxa2xx_spi_acpi_get_pdata(pdev); |
1402 | if (!platform_info) { | |
1403 | dev_err(&pdev->dev, "missing platform data\n"); | |
1404 | return -ENODEV; | |
1405 | } | |
851bacf5 | 1406 | } |
e0c9905e | 1407 | |
baffe169 | 1408 | ssp = pxa_ssp_request(pdev->id, pdev->name); |
851bacf5 MW |
1409 | if (!ssp) |
1410 | ssp = &platform_info->ssp; | |
1411 | ||
1412 | if (!ssp->mmio_base) { | |
1413 | dev_err(&pdev->dev, "failed to get ssp\n"); | |
e0c9905e SS |
1414 | return -ENODEV; |
1415 | } | |
1416 | ||
757fe8d5 | 1417 | master = spi_alloc_master(dev, sizeof(struct driver_data)); |
e0c9905e | 1418 | if (!master) { |
65a00a20 | 1419 | dev_err(&pdev->dev, "cannot alloc spi_master\n"); |
baffe169 | 1420 | pxa_ssp_free(ssp); |
e0c9905e SS |
1421 | return -ENOMEM; |
1422 | } | |
1423 | drv_data = spi_master_get_devdata(master); | |
1424 | drv_data->master = master; | |
1425 | drv_data->master_info = platform_info; | |
1426 | drv_data->pdev = pdev; | |
2f1a74e5 | 1427 | drv_data->ssp = ssp; |
e0c9905e | 1428 | |
21486af0 | 1429 | master->dev.parent = &pdev->dev; |
21486af0 | 1430 | master->dev.of_node = pdev->dev.of_node; |
e7db06b5 | 1431 | /* the spi->mode bits understood by this driver: */ |
b833172f | 1432 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
e7db06b5 | 1433 | |
851bacf5 | 1434 | master->bus_num = ssp->port_id; |
e0c9905e | 1435 | master->num_chipselect = platform_info->num_chipselect; |
7ad0ba91 | 1436 | master->dma_alignment = DMA_ALIGNMENT; |
e0c9905e SS |
1437 | master->cleanup = cleanup; |
1438 | master->setup = setup; | |
7f86bde9 | 1439 | master->transfer_one_message = pxa2xx_spi_transfer_one_message; |
7d94a505 | 1440 | master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; |
7dd62787 | 1441 | master->auto_runtime_pm = true; |
e0c9905e | 1442 | |
2f1a74e5 | 1443 | drv_data->ssp_type = ssp->type; |
e0c9905e | 1444 | |
2f1a74e5 | 1445 | drv_data->ioaddr = ssp->mmio_base; |
1446 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
2a8626a9 | 1447 | if (pxa25x_ssp_comp(drv_data)) { |
e5262d05 WC |
1448 | switch (drv_data->ssp_type) { |
1449 | case QUARK_X1000_SSP: | |
1450 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); | |
1451 | break; | |
1452 | default: | |
1453 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); | |
1454 | break; | |
1455 | } | |
1456 | ||
e0c9905e SS |
1457 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1458 | drv_data->dma_cr1 = 0; | |
1459 | drv_data->clear_sr = SSSR_ROR; | |
1460 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1461 | } else { | |
24778be2 | 1462 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
e0c9905e | 1463 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; |
5928808e | 1464 | drv_data->dma_cr1 = DEFAULT_DMA_CR1; |
e0c9905e SS |
1465 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; |
1466 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1467 | } | |
1468 | ||
49cbb1e0 SAS |
1469 | status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), |
1470 | drv_data); | |
e0c9905e | 1471 | if (status < 0) { |
65a00a20 | 1472 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
e0c9905e SS |
1473 | goto out_error_master_alloc; |
1474 | } | |
1475 | ||
1476 | /* Setup DMA if requested */ | |
e0c9905e | 1477 | if (platform_info->enable_dma) { |
cd7bed00 MW |
1478 | status = pxa2xx_spi_dma_setup(drv_data); |
1479 | if (status) { | |
cddb339b | 1480 | dev_dbg(dev, "no DMA channels available, using PIO\n"); |
cd7bed00 | 1481 | platform_info->enable_dma = false; |
e0c9905e | 1482 | } |
e0c9905e SS |
1483 | } |
1484 | ||
1485 | /* Enable SOC clock */ | |
3343b7a6 MW |
1486 | clk_prepare_enable(ssp->clk); |
1487 | ||
1488 | drv_data->max_clk_rate = clk_get_rate(ssp->clk); | |
e0c9905e SS |
1489 | |
1490 | /* Load default SSP configuration */ | |
c039dd27 | 1491 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
e5262d05 WC |
1492 | switch (drv_data->ssp_type) { |
1493 | case QUARK_X1000_SSP: | |
c039dd27 JN |
1494 | tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1495 | | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT); | |
1496 | pxa2xx_spi_write(drv_data, SSCR1, tmp); | |
e5262d05 WC |
1497 | |
1498 | /* using the Motorola SPI protocol and use 8 bit frame */ | |
c039dd27 JN |
1499 | pxa2xx_spi_write(drv_data, SSCR0, |
1500 | QUARK_X1000_SSCR0_Motorola | |
1501 | | QUARK_X1000_SSCR0_DataSize(8)); | |
e5262d05 WC |
1502 | break; |
1503 | default: | |
c039dd27 JN |
1504 | tmp = SSCR1_RxTresh(RX_THRESH_DFLT) | |
1505 | SSCR1_TxTresh(TX_THRESH_DFLT); | |
1506 | pxa2xx_spi_write(drv_data, SSCR1, tmp); | |
1507 | tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); | |
1508 | pxa2xx_spi_write(drv_data, SSCR0, tmp); | |
e5262d05 WC |
1509 | break; |
1510 | } | |
1511 | ||
2a8626a9 | 1512 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1513 | pxa2xx_spi_write(drv_data, SSTO, 0); |
e5262d05 WC |
1514 | |
1515 | if (!is_quark_x1000_ssp(drv_data)) | |
c039dd27 | 1516 | pxa2xx_spi_write(drv_data, SSPSP, 0); |
e0c9905e | 1517 | |
7566bcc7 JN |
1518 | if (is_lpss_ssp(drv_data)) |
1519 | lpss_ssp_setup(drv_data); | |
a0d2642e | 1520 | |
7f86bde9 MW |
1521 | tasklet_init(&drv_data->pump_transfers, pump_transfers, |
1522 | (unsigned long)drv_data); | |
e0c9905e | 1523 | |
836d1a22 AO |
1524 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1525 | pm_runtime_use_autosuspend(&pdev->dev); | |
1526 | pm_runtime_set_active(&pdev->dev); | |
1527 | pm_runtime_enable(&pdev->dev); | |
1528 | ||
e0c9905e SS |
1529 | /* Register with the SPI framework */ |
1530 | platform_set_drvdata(pdev, drv_data); | |
a807fcd0 | 1531 | status = devm_spi_register_master(&pdev->dev, master); |
e0c9905e SS |
1532 | if (status != 0) { |
1533 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
7f86bde9 | 1534 | goto out_error_clock_enabled; |
e0c9905e SS |
1535 | } |
1536 | ||
1537 | return status; | |
1538 | ||
e0c9905e | 1539 | out_error_clock_enabled: |
3343b7a6 | 1540 | clk_disable_unprepare(ssp->clk); |
cd7bed00 | 1541 | pxa2xx_spi_dma_release(drv_data); |
2f1a74e5 | 1542 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1543 | |
1544 | out_error_master_alloc: | |
1545 | spi_master_put(master); | |
baffe169 | 1546 | pxa_ssp_free(ssp); |
e0c9905e SS |
1547 | return status; |
1548 | } | |
1549 | ||
1550 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1551 | { | |
1552 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
51e911e2 | 1553 | struct ssp_device *ssp; |
e0c9905e SS |
1554 | |
1555 | if (!drv_data) | |
1556 | return 0; | |
51e911e2 | 1557 | ssp = drv_data->ssp; |
e0c9905e | 1558 | |
7d94a505 MW |
1559 | pm_runtime_get_sync(&pdev->dev); |
1560 | ||
e0c9905e | 1561 | /* Disable the SSP at the peripheral and SOC level */ |
c039dd27 | 1562 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
3343b7a6 | 1563 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1564 | |
1565 | /* Release DMA */ | |
cd7bed00 MW |
1566 | if (drv_data->master_info->enable_dma) |
1567 | pxa2xx_spi_dma_release(drv_data); | |
e0c9905e | 1568 | |
7d94a505 MW |
1569 | pm_runtime_put_noidle(&pdev->dev); |
1570 | pm_runtime_disable(&pdev->dev); | |
1571 | ||
e0c9905e | 1572 | /* Release IRQ */ |
2f1a74e5 | 1573 | free_irq(ssp->irq, drv_data); |
1574 | ||
1575 | /* Release SSP */ | |
baffe169 | 1576 | pxa_ssp_free(ssp); |
e0c9905e | 1577 | |
e0c9905e SS |
1578 | return 0; |
1579 | } | |
1580 | ||
1581 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1582 | { | |
1583 | int status = 0; | |
1584 | ||
1585 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1586 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1587 | } | |
1588 | ||
382cebb0 | 1589 | #ifdef CONFIG_PM_SLEEP |
86d2593a | 1590 | static int pxa2xx_spi_suspend(struct device *dev) |
e0c9905e | 1591 | { |
86d2593a | 1592 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1593 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1594 | int status = 0; |
1595 | ||
7f86bde9 | 1596 | status = spi_master_suspend(drv_data->master); |
e0c9905e SS |
1597 | if (status != 0) |
1598 | return status; | |
c039dd27 | 1599 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
2b9375b9 DES |
1600 | |
1601 | if (!pm_runtime_suspended(dev)) | |
1602 | clk_disable_unprepare(ssp->clk); | |
e0c9905e SS |
1603 | |
1604 | return 0; | |
1605 | } | |
1606 | ||
86d2593a | 1607 | static int pxa2xx_spi_resume(struct device *dev) |
e0c9905e | 1608 | { |
86d2593a | 1609 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1610 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1611 | int status = 0; |
1612 | ||
cd7bed00 | 1613 | pxa2xx_spi_dma_resume(drv_data); |
148da331 | 1614 | |
e0c9905e | 1615 | /* Enable the SSP clock */ |
2b9375b9 DES |
1616 | if (!pm_runtime_suspended(dev)) |
1617 | clk_prepare_enable(ssp->clk); | |
e0c9905e | 1618 | |
c50325f7 | 1619 | /* Restore LPSS private register bits */ |
48421adf JN |
1620 | if (is_lpss_ssp(drv_data)) |
1621 | lpss_ssp_setup(drv_data); | |
c50325f7 | 1622 | |
e0c9905e | 1623 | /* Start the queue running */ |
7f86bde9 | 1624 | status = spi_master_resume(drv_data->master); |
e0c9905e | 1625 | if (status != 0) { |
86d2593a | 1626 | dev_err(dev, "problem starting queue (%d)\n", status); |
e0c9905e SS |
1627 | return status; |
1628 | } | |
1629 | ||
1630 | return 0; | |
1631 | } | |
7d94a505 MW |
1632 | #endif |
1633 | ||
ec833050 | 1634 | #ifdef CONFIG_PM |
7d94a505 MW |
1635 | static int pxa2xx_spi_runtime_suspend(struct device *dev) |
1636 | { | |
1637 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1638 | ||
1639 | clk_disable_unprepare(drv_data->ssp->clk); | |
1640 | return 0; | |
1641 | } | |
1642 | ||
1643 | static int pxa2xx_spi_runtime_resume(struct device *dev) | |
1644 | { | |
1645 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1646 | ||
1647 | clk_prepare_enable(drv_data->ssp->clk); | |
1648 | return 0; | |
1649 | } | |
1650 | #endif | |
86d2593a | 1651 | |
47145210 | 1652 | static const struct dev_pm_ops pxa2xx_spi_pm_ops = { |
7d94a505 MW |
1653 | SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) |
1654 | SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, | |
1655 | pxa2xx_spi_runtime_resume, NULL) | |
86d2593a | 1656 | }; |
e0c9905e SS |
1657 | |
1658 | static struct platform_driver driver = { | |
1659 | .driver = { | |
86d2593a | 1660 | .name = "pxa2xx-spi", |
86d2593a | 1661 | .pm = &pxa2xx_spi_pm_ops, |
a3496855 | 1662 | .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), |
e0c9905e | 1663 | }, |
fbd29a14 | 1664 | .probe = pxa2xx_spi_probe, |
d1e44d9c | 1665 | .remove = pxa2xx_spi_remove, |
e0c9905e | 1666 | .shutdown = pxa2xx_spi_shutdown, |
e0c9905e SS |
1667 | }; |
1668 | ||
1669 | static int __init pxa2xx_spi_init(void) | |
1670 | { | |
fbd29a14 | 1671 | return platform_driver_register(&driver); |
e0c9905e | 1672 | } |
5b61a749 | 1673 | subsys_initcall(pxa2xx_spi_init); |
e0c9905e SS |
1674 | |
1675 | static void __exit pxa2xx_spi_exit(void) | |
1676 | { | |
1677 | platform_driver_unregister(&driver); | |
1678 | } | |
1679 | module_exit(pxa2xx_spi_exit); |