Commit | Line | Data |
---|---|---|
0b2182dd SY |
1 | /* |
2 | * SH RSPI driver | |
3 | * | |
93722206 | 4 | * Copyright (C) 2012, 2013 Renesas Solutions Corp. |
880c6d11 | 5 | * Copyright (C) 2014 Glider bvba |
0b2182dd SY |
6 | * |
7 | * Based on spi-sh.c: | |
8 | * Copyright (C) 2011 Renesas Solutions Corp. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
22 | * | |
23 | */ | |
24 | ||
25 | #include <linux/module.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/sched.h> | |
28 | #include <linux/errno.h> | |
0b2182dd SY |
29 | #include <linux/interrupt.h> |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/io.h> | |
32 | #include <linux/clk.h> | |
a3633fe7 SY |
33 | #include <linux/dmaengine.h> |
34 | #include <linux/dma-mapping.h> | |
426ef76d | 35 | #include <linux/of_device.h> |
a3633fe7 | 36 | #include <linux/sh_dma.h> |
0b2182dd | 37 | #include <linux/spi/spi.h> |
a3633fe7 | 38 | #include <linux/spi/rspi.h> |
0b2182dd | 39 | |
6ab4865b GU |
40 | #define RSPI_SPCR 0x00 /* Control Register */ |
41 | #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */ | |
42 | #define RSPI_SPPCR 0x02 /* Pin Control Register */ | |
43 | #define RSPI_SPSR 0x03 /* Status Register */ | |
44 | #define RSPI_SPDR 0x04 /* Data Register */ | |
45 | #define RSPI_SPSCR 0x08 /* Sequence Control Register */ | |
46 | #define RSPI_SPSSR 0x09 /* Sequence Status Register */ | |
47 | #define RSPI_SPBR 0x0a /* Bit Rate Register */ | |
48 | #define RSPI_SPDCR 0x0b /* Data Control Register */ | |
49 | #define RSPI_SPCKD 0x0c /* Clock Delay Register */ | |
50 | #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */ | |
51 | #define RSPI_SPND 0x0e /* Next-Access Delay Register */ | |
862d357f | 52 | #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */ |
6ab4865b GU |
53 | #define RSPI_SPCMD0 0x10 /* Command Register 0 */ |
54 | #define RSPI_SPCMD1 0x12 /* Command Register 1 */ | |
55 | #define RSPI_SPCMD2 0x14 /* Command Register 2 */ | |
56 | #define RSPI_SPCMD3 0x16 /* Command Register 3 */ | |
57 | #define RSPI_SPCMD4 0x18 /* Command Register 4 */ | |
58 | #define RSPI_SPCMD5 0x1a /* Command Register 5 */ | |
59 | #define RSPI_SPCMD6 0x1c /* Command Register 6 */ | |
60 | #define RSPI_SPCMD7 0x1e /* Command Register 7 */ | |
880c6d11 GU |
61 | #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2) |
62 | #define RSPI_NUM_SPCMD 8 | |
63 | #define RSPI_RZ_NUM_SPCMD 4 | |
64 | #define QSPI_NUM_SPCMD 4 | |
862d357f GU |
65 | |
66 | /* RSPI on RZ only */ | |
6ab4865b GU |
67 | #define RSPI_SPBFCR 0x20 /* Buffer Control Register */ |
68 | #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ | |
0b2182dd | 69 | |
862d357f | 70 | /* QSPI only */ |
fbe5072b GU |
71 | #define QSPI_SPBFCR 0x18 /* Buffer Control Register */ |
72 | #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ | |
73 | #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ | |
74 | #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ | |
75 | #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ | |
76 | #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ | |
880c6d11 | 77 | #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4) |
5ce0ba88 | 78 | |
6ab4865b GU |
79 | /* SPCR - Control Register */ |
80 | #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ | |
81 | #define SPCR_SPE 0x40 /* Function Enable */ | |
82 | #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */ | |
83 | #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */ | |
84 | #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */ | |
85 | #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */ | |
86 | /* RSPI on SH only */ | |
87 | #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */ | |
88 | #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */ | |
fbe5072b GU |
89 | /* QSPI on R-Car M2 only */ |
90 | #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */ | |
91 | #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */ | |
6ab4865b GU |
92 | |
93 | /* SSLP - Slave Select Polarity Register */ | |
94 | #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */ | |
95 | #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */ | |
96 | ||
97 | /* SPPCR - Pin Control Register */ | |
98 | #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */ | |
99 | #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */ | |
0b2182dd | 100 | #define SPPCR_SPOM 0x04 |
6ab4865b GU |
101 | #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */ |
102 | #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */ | |
103 | ||
fbe5072b GU |
104 | #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */ |
105 | #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */ | |
106 | ||
6ab4865b GU |
107 | /* SPSR - Status Register */ |
108 | #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */ | |
109 | #define SPSR_TEND 0x40 /* Transmit End */ | |
110 | #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */ | |
111 | #define SPSR_PERF 0x08 /* Parity Error Flag */ | |
112 | #define SPSR_MODF 0x04 /* Mode Fault Error Flag */ | |
113 | #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */ | |
862d357f | 114 | #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */ |
6ab4865b GU |
115 | |
116 | /* SPSCR - Sequence Control Register */ | |
117 | #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */ | |
118 | ||
119 | /* SPSSR - Sequence Status Register */ | |
120 | #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */ | |
121 | #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */ | |
122 | ||
123 | /* SPDCR - Data Control Register */ | |
124 | #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */ | |
125 | #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */ | |
126 | #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */ | |
127 | #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0) | |
128 | #define SPDCR_SPLWORD SPDCR_SPLW1 | |
129 | #define SPDCR_SPLBYTE SPDCR_SPLW0 | |
130 | #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */ | |
862d357f | 131 | #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */ |
0b2182dd SY |
132 | #define SPDCR_SLSEL1 0x08 |
133 | #define SPDCR_SLSEL0 0x04 | |
862d357f | 134 | #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */ |
0b2182dd SY |
135 | #define SPDCR_SPFC1 0x02 |
136 | #define SPDCR_SPFC0 0x01 | |
862d357f | 137 | #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */ |
0b2182dd | 138 | |
6ab4865b GU |
139 | /* SPCKD - Clock Delay Register */ |
140 | #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */ | |
0b2182dd | 141 | |
6ab4865b GU |
142 | /* SSLND - Slave Select Negation Delay Register */ |
143 | #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */ | |
0b2182dd | 144 | |
6ab4865b GU |
145 | /* SPND - Next-Access Delay Register */ |
146 | #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */ | |
0b2182dd | 147 | |
6ab4865b GU |
148 | /* SPCR2 - Control Register 2 */ |
149 | #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */ | |
150 | #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */ | |
151 | #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */ | |
152 | #define SPCR2_SPPE 0x01 /* Parity Enable */ | |
0b2182dd | 153 | |
6ab4865b GU |
154 | /* SPCMDn - Command Registers */ |
155 | #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */ | |
156 | #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */ | |
157 | #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */ | |
158 | #define SPCMD_LSBF 0x1000 /* LSB First */ | |
159 | #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */ | |
0b2182dd | 160 | #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) |
880c6d11 | 161 | #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */ |
5ce0ba88 | 162 | #define SPCMD_SPB_16BIT 0x0100 |
0b2182dd SY |
163 | #define SPCMD_SPB_20BIT 0x0000 |
164 | #define SPCMD_SPB_24BIT 0x0100 | |
165 | #define SPCMD_SPB_32BIT 0x0200 | |
6ab4865b | 166 | #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */ |
fbe5072b GU |
167 | #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */ |
168 | #define SPCMD_SPIMOD1 0x0040 | |
169 | #define SPCMD_SPIMOD0 0x0020 | |
170 | #define SPCMD_SPIMOD_SINGLE 0 | |
171 | #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0 | |
172 | #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1 | |
173 | #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */ | |
6ab4865b GU |
174 | #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */ |
175 | #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */ | |
176 | #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */ | |
177 | #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ | |
178 | ||
179 | /* SPBFCR - Buffer Control Register */ | |
862d357f GU |
180 | #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */ |
181 | #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */ | |
6ab4865b GU |
182 | #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ |
183 | #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ | |
5ce0ba88 | 184 | |
2aae80b2 GU |
185 | #define DUMMY_DATA 0x00 |
186 | ||
0b2182dd SY |
187 | struct rspi_data { |
188 | void __iomem *addr; | |
189 | u32 max_speed_hz; | |
190 | struct spi_master *master; | |
0b2182dd | 191 | wait_queue_head_t wait; |
0b2182dd | 192 | struct clk *clk; |
348e5153 | 193 | u16 spcmd; |
06a7a3cf GU |
194 | u8 spsr; |
195 | u8 sppcr; | |
93722206 | 196 | int rx_irq, tx_irq; |
5ce0ba88 | 197 | const struct spi_ops *ops; |
a3633fe7 SY |
198 | |
199 | /* for dmaengine */ | |
a3633fe7 SY |
200 | struct dma_chan *chan_tx; |
201 | struct dma_chan *chan_rx; | |
a3633fe7 SY |
202 | |
203 | unsigned dma_width_16bit:1; | |
204 | unsigned dma_callbacked:1; | |
74da7686 | 205 | unsigned byte_access:1; |
0b2182dd SY |
206 | }; |
207 | ||
baf588f4 | 208 | static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset) |
0b2182dd SY |
209 | { |
210 | iowrite8(data, rspi->addr + offset); | |
211 | } | |
212 | ||
baf588f4 | 213 | static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset) |
0b2182dd SY |
214 | { |
215 | iowrite16(data, rspi->addr + offset); | |
216 | } | |
217 | ||
baf588f4 | 218 | static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset) |
5ce0ba88 HCM |
219 | { |
220 | iowrite32(data, rspi->addr + offset); | |
221 | } | |
222 | ||
baf588f4 | 223 | static u8 rspi_read8(const struct rspi_data *rspi, u16 offset) |
0b2182dd SY |
224 | { |
225 | return ioread8(rspi->addr + offset); | |
226 | } | |
227 | ||
baf588f4 | 228 | static u16 rspi_read16(const struct rspi_data *rspi, u16 offset) |
0b2182dd SY |
229 | { |
230 | return ioread16(rspi->addr + offset); | |
231 | } | |
232 | ||
74da7686 GU |
233 | static void rspi_write_data(const struct rspi_data *rspi, u16 data) |
234 | { | |
235 | if (rspi->byte_access) | |
236 | rspi_write8(rspi, data, RSPI_SPDR); | |
237 | else /* 16 bit */ | |
238 | rspi_write16(rspi, data, RSPI_SPDR); | |
239 | } | |
240 | ||
241 | static u16 rspi_read_data(const struct rspi_data *rspi) | |
242 | { | |
243 | if (rspi->byte_access) | |
244 | return rspi_read8(rspi, RSPI_SPDR); | |
245 | else /* 16 bit */ | |
246 | return rspi_read16(rspi, RSPI_SPDR); | |
247 | } | |
248 | ||
5ce0ba88 HCM |
249 | /* optional functions */ |
250 | struct spi_ops { | |
74da7686 | 251 | int (*set_config_register)(struct rspi_data *rspi, int access_size); |
eb557f75 GU |
252 | int (*transfer_one)(struct spi_master *master, struct spi_device *spi, |
253 | struct spi_transfer *xfer); | |
880c6d11 | 254 | u16 mode_bits; |
5ce0ba88 HCM |
255 | }; |
256 | ||
257 | /* | |
862d357f | 258 | * functions for RSPI on legacy SH |
5ce0ba88 | 259 | */ |
74da7686 | 260 | static int rspi_set_config_register(struct rspi_data *rspi, int access_size) |
0b2182dd | 261 | { |
5ce0ba88 HCM |
262 | int spbr; |
263 | ||
06a7a3cf GU |
264 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
265 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
0b2182dd | 266 | |
5ce0ba88 HCM |
267 | /* Sets transfer bit rate */ |
268 | spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1; | |
269 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); | |
270 | ||
74da7686 GU |
271 | /* Disable dummy transmission, set 16-bit word access, 1 frame */ |
272 | rspi_write8(rspi, 0, RSPI_SPDCR); | |
273 | rspi->byte_access = 0; | |
0b2182dd | 274 | |
5ce0ba88 HCM |
275 | /* Sets RSPCK, SSL, next-access delay value */ |
276 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
277 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
278 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
279 | ||
280 | /* Sets parity, interrupt mask */ | |
281 | rspi_write8(rspi, 0x00, RSPI_SPCR2); | |
282 | ||
283 | /* Sets SPCMD */ | |
880c6d11 GU |
284 | rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); |
285 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); | |
5ce0ba88 HCM |
286 | |
287 | /* Sets RSPI mode */ | |
288 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); | |
289 | ||
290 | return 0; | |
0b2182dd SY |
291 | } |
292 | ||
862d357f GU |
293 | /* |
294 | * functions for RSPI on RZ | |
295 | */ | |
296 | static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size) | |
297 | { | |
298 | int spbr; | |
299 | ||
06a7a3cf GU |
300 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
301 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
862d357f GU |
302 | |
303 | /* Sets transfer bit rate */ | |
304 | spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1; | |
305 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); | |
306 | ||
307 | /* Disable dummy transmission, set byte access */ | |
308 | rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR); | |
309 | rspi->byte_access = 1; | |
310 | ||
311 | /* Sets RSPCK, SSL, next-access delay value */ | |
312 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
313 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
314 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
315 | ||
316 | /* Sets SPCMD */ | |
317 | rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); | |
318 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); | |
319 | ||
320 | /* Sets RSPI mode */ | |
321 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
5ce0ba88 HCM |
326 | /* |
327 | * functions for QSPI | |
328 | */ | |
74da7686 | 329 | static int qspi_set_config_register(struct rspi_data *rspi, int access_size) |
5ce0ba88 | 330 | { |
5ce0ba88 HCM |
331 | int spbr; |
332 | ||
06a7a3cf GU |
333 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
334 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
5ce0ba88 HCM |
335 | |
336 | /* Sets transfer bit rate */ | |
337 | spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz); | |
338 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); | |
339 | ||
74da7686 GU |
340 | /* Disable dummy transmission, set byte access */ |
341 | rspi_write8(rspi, 0, RSPI_SPDCR); | |
342 | rspi->byte_access = 1; | |
5ce0ba88 HCM |
343 | |
344 | /* Sets RSPCK, SSL, next-access delay value */ | |
345 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
346 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
347 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
348 | ||
349 | /* Data Length Setting */ | |
350 | if (access_size == 8) | |
880c6d11 | 351 | rspi->spcmd |= SPCMD_SPB_8BIT; |
5ce0ba88 | 352 | else if (access_size == 16) |
880c6d11 | 353 | rspi->spcmd |= SPCMD_SPB_16BIT; |
8e1c8096 | 354 | else |
880c6d11 | 355 | rspi->spcmd |= SPCMD_SPB_32BIT; |
5ce0ba88 | 356 | |
880c6d11 | 357 | rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN; |
5ce0ba88 HCM |
358 | |
359 | /* Resets transfer data length */ | |
360 | rspi_write32(rspi, 0, QSPI_SPBMUL0); | |
361 | ||
362 | /* Resets transmit and receive buffer */ | |
363 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); | |
364 | /* Sets buffer to allow normal operation */ | |
365 | rspi_write8(rspi, 0x00, QSPI_SPBFCR); | |
366 | ||
367 | /* Sets SPCMD */ | |
880c6d11 | 368 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); |
5ce0ba88 | 369 | |
880c6d11 | 370 | /* Enables SPI function in master mode */ |
5ce0ba88 HCM |
371 | rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR); |
372 | ||
373 | return 0; | |
374 | } | |
375 | ||
376 | #define set_config_register(spi, n) spi->ops->set_config_register(spi, n) | |
377 | ||
baf588f4 | 378 | static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable) |
0b2182dd SY |
379 | { |
380 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); | |
381 | } | |
382 | ||
baf588f4 | 383 | static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable) |
0b2182dd SY |
384 | { |
385 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); | |
386 | } | |
387 | ||
388 | static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask, | |
389 | u8 enable_bit) | |
390 | { | |
391 | int ret; | |
392 | ||
393 | rspi->spsr = rspi_read8(rspi, RSPI_SPSR); | |
5dd1ad23 GU |
394 | if (rspi->spsr & wait_mask) |
395 | return 0; | |
396 | ||
0b2182dd SY |
397 | rspi_enable_irq(rspi, enable_bit); |
398 | ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); | |
399 | if (ret == 0 && !(rspi->spsr & wait_mask)) | |
400 | return -ETIMEDOUT; | |
401 | ||
402 | return 0; | |
403 | } | |
404 | ||
35301c99 GU |
405 | static int rspi_data_out(struct rspi_data *rspi, u8 data) |
406 | { | |
407 | if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { | |
408 | dev_err(&rspi->master->dev, "transmit timeout\n"); | |
409 | return -ETIMEDOUT; | |
410 | } | |
411 | rspi_write_data(rspi, data); | |
412 | return 0; | |
413 | } | |
414 | ||
415 | static int rspi_data_in(struct rspi_data *rspi) | |
416 | { | |
417 | u8 data; | |
418 | ||
419 | if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) { | |
420 | dev_err(&rspi->master->dev, "receive timeout\n"); | |
421 | return -ETIMEDOUT; | |
422 | } | |
423 | data = rspi_read_data(rspi); | |
424 | return data; | |
425 | } | |
426 | ||
427 | static int rspi_data_out_in(struct rspi_data *rspi, u8 data) | |
428 | { | |
429 | int ret; | |
430 | ||
431 | ret = rspi_data_out(rspi, data); | |
432 | if (ret < 0) | |
433 | return ret; | |
434 | ||
435 | return rspi_data_in(rspi); | |
436 | } | |
437 | ||
a3633fe7 SY |
438 | static void rspi_dma_complete(void *arg) |
439 | { | |
440 | struct rspi_data *rspi = arg; | |
441 | ||
442 | rspi->dma_callbacked = 1; | |
443 | wake_up_interruptible(&rspi->wait); | |
444 | } | |
445 | ||
c132f094 GU |
446 | static int rspi_dma_map_sg(struct scatterlist *sg, const void *buf, |
447 | unsigned len, struct dma_chan *chan, | |
a3633fe7 SY |
448 | enum dma_transfer_direction dir) |
449 | { | |
450 | sg_init_table(sg, 1); | |
451 | sg_set_buf(sg, buf, len); | |
452 | sg_dma_len(sg) = len; | |
453 | return dma_map_sg(chan->device->dev, sg, 1, dir); | |
454 | } | |
455 | ||
456 | static void rspi_dma_unmap_sg(struct scatterlist *sg, struct dma_chan *chan, | |
457 | enum dma_transfer_direction dir) | |
458 | { | |
459 | dma_unmap_sg(chan->device->dev, sg, 1, dir); | |
460 | } | |
461 | ||
462 | static void rspi_memory_to_8bit(void *buf, const void *data, unsigned len) | |
463 | { | |
464 | u16 *dst = buf; | |
465 | const u8 *src = data; | |
466 | ||
467 | while (len) { | |
468 | *dst++ = (u16)(*src++); | |
469 | len--; | |
470 | } | |
471 | } | |
472 | ||
473 | static void rspi_memory_from_8bit(void *buf, const void *data, unsigned len) | |
474 | { | |
475 | u8 *dst = buf; | |
476 | const u16 *src = data; | |
477 | ||
478 | while (len) { | |
479 | *dst++ = (u8)*src++; | |
480 | len--; | |
481 | } | |
482 | } | |
483 | ||
484 | static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t) | |
485 | { | |
486 | struct scatterlist sg; | |
c132f094 | 487 | const void *buf = NULL; |
a3633fe7 | 488 | struct dma_async_tx_descriptor *desc; |
93722206 | 489 | unsigned int len; |
a3633fe7 SY |
490 | int ret = 0; |
491 | ||
492 | if (rspi->dma_width_16bit) { | |
c132f094 | 493 | void *tmp; |
a3633fe7 SY |
494 | /* |
495 | * If DMAC bus width is 16-bit, the driver allocates a dummy | |
496 | * buffer. And, the driver converts original data into the | |
497 | * DMAC data as the following format: | |
498 | * original data: 1st byte, 2nd byte ... | |
499 | * DMAC data: 1st byte, dummy, 2nd byte, dummy ... | |
500 | */ | |
501 | len = t->len * 2; | |
c132f094 GU |
502 | tmp = kmalloc(len, GFP_KERNEL); |
503 | if (!tmp) | |
a3633fe7 | 504 | return -ENOMEM; |
c132f094 GU |
505 | rspi_memory_to_8bit(tmp, t->tx_buf, t->len); |
506 | buf = tmp; | |
a3633fe7 SY |
507 | } else { |
508 | len = t->len; | |
c132f094 | 509 | buf = t->tx_buf; |
a3633fe7 SY |
510 | } |
511 | ||
512 | if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) { | |
513 | ret = -EFAULT; | |
514 | goto end_nomap; | |
515 | } | |
516 | desc = dmaengine_prep_slave_sg(rspi->chan_tx, &sg, 1, DMA_TO_DEVICE, | |
517 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
518 | if (!desc) { | |
519 | ret = -EIO; | |
520 | goto end; | |
521 | } | |
522 | ||
523 | /* | |
524 | * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be | |
525 | * called. So, this driver disables the IRQ while DMA transfer. | |
526 | */ | |
93722206 | 527 | disable_irq(rspi->tx_irq); |
a3633fe7 SY |
528 | |
529 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR); | |
530 | rspi_enable_irq(rspi, SPCR_SPTIE); | |
531 | rspi->dma_callbacked = 0; | |
532 | ||
533 | desc->callback = rspi_dma_complete; | |
534 | desc->callback_param = rspi; | |
535 | dmaengine_submit(desc); | |
536 | dma_async_issue_pending(rspi->chan_tx); | |
537 | ||
538 | ret = wait_event_interruptible_timeout(rspi->wait, | |
539 | rspi->dma_callbacked, HZ); | |
540 | if (ret > 0 && rspi->dma_callbacked) | |
541 | ret = 0; | |
542 | else if (!ret) | |
543 | ret = -ETIMEDOUT; | |
544 | rspi_disable_irq(rspi, SPCR_SPTIE); | |
545 | ||
93722206 | 546 | enable_irq(rspi->tx_irq); |
a3633fe7 SY |
547 | |
548 | end: | |
549 | rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE); | |
550 | end_nomap: | |
551 | if (rspi->dma_width_16bit) | |
552 | kfree(buf); | |
553 | ||
554 | return ret; | |
555 | } | |
556 | ||
baf588f4 | 557 | static void rspi_receive_init(const struct rspi_data *rspi) |
0b2182dd | 558 | { |
97b95c11 | 559 | u8 spsr; |
0b2182dd SY |
560 | |
561 | spsr = rspi_read8(rspi, RSPI_SPSR); | |
562 | if (spsr & SPSR_SPRF) | |
74da7686 | 563 | rspi_read_data(rspi); /* dummy read */ |
0b2182dd SY |
564 | if (spsr & SPSR_OVRF) |
565 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, | |
df900e67 | 566 | RSPI_SPSR); |
a3633fe7 SY |
567 | } |
568 | ||
862d357f GU |
569 | static void rspi_rz_receive_init(const struct rspi_data *rspi) |
570 | { | |
571 | rspi_receive_init(rspi); | |
572 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR); | |
573 | rspi_write8(rspi, 0, RSPI_SPBFCR); | |
574 | } | |
575 | ||
baf588f4 | 576 | static void qspi_receive_init(const struct rspi_data *rspi) |
cb52c673 | 577 | { |
97b95c11 | 578 | u8 spsr; |
cb52c673 HCM |
579 | |
580 | spsr = rspi_read8(rspi, RSPI_SPSR); | |
581 | if (spsr & SPSR_SPRF) | |
74da7686 | 582 | rspi_read_data(rspi); /* dummy read */ |
cb52c673 | 583 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); |
340a15e6 | 584 | rspi_write8(rspi, 0, QSPI_SPBFCR); |
cb52c673 HCM |
585 | } |
586 | ||
a3633fe7 SY |
587 | static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t) |
588 | { | |
589 | struct scatterlist sg, sg_dummy; | |
590 | void *dummy = NULL, *rx_buf = NULL; | |
591 | struct dma_async_tx_descriptor *desc, *desc_dummy; | |
93722206 | 592 | unsigned int len; |
a3633fe7 SY |
593 | int ret = 0; |
594 | ||
595 | if (rspi->dma_width_16bit) { | |
596 | /* | |
597 | * If DMAC bus width is 16-bit, the driver allocates a dummy | |
598 | * buffer. And, finally the driver converts the DMAC data into | |
599 | * actual data as the following format: | |
600 | * DMAC data: 1st byte, dummy, 2nd byte, dummy ... | |
601 | * actual data: 1st byte, 2nd byte ... | |
602 | */ | |
603 | len = t->len * 2; | |
604 | rx_buf = kmalloc(len, GFP_KERNEL); | |
605 | if (!rx_buf) | |
606 | return -ENOMEM; | |
607 | } else { | |
608 | len = t->len; | |
609 | rx_buf = t->rx_buf; | |
610 | } | |
611 | ||
612 | /* prepare dummy transfer to generate SPI clocks */ | |
613 | dummy = kzalloc(len, GFP_KERNEL); | |
614 | if (!dummy) { | |
615 | ret = -ENOMEM; | |
616 | goto end_nomap; | |
617 | } | |
618 | if (!rspi_dma_map_sg(&sg_dummy, dummy, len, rspi->chan_tx, | |
619 | DMA_TO_DEVICE)) { | |
620 | ret = -EFAULT; | |
621 | goto end_nomap; | |
622 | } | |
623 | desc_dummy = dmaengine_prep_slave_sg(rspi->chan_tx, &sg_dummy, 1, | |
624 | DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
625 | if (!desc_dummy) { | |
626 | ret = -EIO; | |
627 | goto end_dummy_mapped; | |
628 | } | |
629 | ||
630 | /* prepare receive transfer */ | |
631 | if (!rspi_dma_map_sg(&sg, rx_buf, len, rspi->chan_rx, | |
632 | DMA_FROM_DEVICE)) { | |
633 | ret = -EFAULT; | |
634 | goto end_dummy_mapped; | |
635 | ||
636 | } | |
637 | desc = dmaengine_prep_slave_sg(rspi->chan_rx, &sg, 1, DMA_FROM_DEVICE, | |
638 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
639 | if (!desc) { | |
640 | ret = -EIO; | |
641 | goto end; | |
642 | } | |
643 | ||
644 | rspi_receive_init(rspi); | |
645 | ||
646 | /* | |
647 | * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be | |
648 | * called. So, this driver disables the IRQ while DMA transfer. | |
649 | */ | |
93722206 GU |
650 | disable_irq(rspi->tx_irq); |
651 | if (rspi->rx_irq != rspi->tx_irq) | |
652 | disable_irq(rspi->rx_irq); | |
a3633fe7 SY |
653 | |
654 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR); | |
655 | rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); | |
656 | rspi->dma_callbacked = 0; | |
657 | ||
658 | desc->callback = rspi_dma_complete; | |
659 | desc->callback_param = rspi; | |
660 | dmaengine_submit(desc); | |
661 | dma_async_issue_pending(rspi->chan_rx); | |
662 | ||
663 | desc_dummy->callback = NULL; /* No callback */ | |
664 | dmaengine_submit(desc_dummy); | |
665 | dma_async_issue_pending(rspi->chan_tx); | |
666 | ||
667 | ret = wait_event_interruptible_timeout(rspi->wait, | |
668 | rspi->dma_callbacked, HZ); | |
669 | if (ret > 0 && rspi->dma_callbacked) | |
670 | ret = 0; | |
671 | else if (!ret) | |
672 | ret = -ETIMEDOUT; | |
673 | rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); | |
674 | ||
93722206 GU |
675 | enable_irq(rspi->tx_irq); |
676 | if (rspi->rx_irq != rspi->tx_irq) | |
677 | enable_irq(rspi->rx_irq); | |
a3633fe7 SY |
678 | |
679 | end: | |
680 | rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE); | |
681 | end_dummy_mapped: | |
682 | rspi_dma_unmap_sg(&sg_dummy, rspi->chan_tx, DMA_TO_DEVICE); | |
683 | end_nomap: | |
684 | if (rspi->dma_width_16bit) { | |
685 | if (!ret) | |
686 | rspi_memory_from_8bit(t->rx_buf, rx_buf, t->len); | |
687 | kfree(rx_buf); | |
688 | } | |
689 | kfree(dummy); | |
690 | ||
691 | return ret; | |
692 | } | |
693 | ||
baf588f4 | 694 | static int rspi_is_dma(const struct rspi_data *rspi, struct spi_transfer *t) |
a3633fe7 SY |
695 | { |
696 | if (t->tx_buf && rspi->chan_tx) | |
697 | return 1; | |
698 | /* If the module receives data by DMAC, it also needs TX DMAC */ | |
699 | if (t->rx_buf && rspi->chan_tx && rspi->chan_rx) | |
700 | return 1; | |
701 | ||
702 | return 0; | |
703 | } | |
704 | ||
8449fd76 GU |
705 | static int rspi_transfer_out_in(struct rspi_data *rspi, |
706 | struct spi_transfer *xfer) | |
707 | { | |
708 | int remain = xfer->len, ret; | |
709 | const u8 *tx_buf = xfer->tx_buf; | |
710 | u8 *rx_buf = xfer->rx_buf; | |
711 | u8 spcr, data; | |
712 | ||
713 | rspi_receive_init(rspi); | |
714 | ||
715 | spcr = rspi_read8(rspi, RSPI_SPCR); | |
716 | if (rx_buf) | |
717 | spcr &= ~SPCR_TXMD; | |
718 | else | |
719 | spcr |= SPCR_TXMD; | |
720 | rspi_write8(rspi, spcr, RSPI_SPCR); | |
721 | ||
722 | while (remain > 0) { | |
723 | data = tx_buf ? *tx_buf++ : DUMMY_DATA; | |
724 | ret = rspi_data_out(rspi, data); | |
725 | if (ret < 0) | |
726 | return ret; | |
727 | if (rx_buf) { | |
728 | ret = rspi_data_in(rspi); | |
729 | if (ret < 0) | |
730 | return ret; | |
731 | *rx_buf++ = ret; | |
732 | } | |
733 | remain--; | |
734 | } | |
735 | ||
736 | /* Wait for the last transmission */ | |
737 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); | |
738 | ||
739 | return 0; | |
740 | } | |
741 | ||
79d23495 GU |
742 | static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi, |
743 | struct spi_transfer *xfer) | |
0b2182dd | 744 | { |
79d23495 | 745 | struct rspi_data *rspi = spi_master_get_devdata(master); |
8449fd76 GU |
746 | int ret; |
747 | ||
748 | if (!rspi_is_dma(rspi, xfer)) | |
749 | return rspi_transfer_out_in(rspi, xfer); | |
0b2182dd | 750 | |
79d23495 | 751 | if (xfer->tx_buf) { |
8449fd76 | 752 | ret = rspi_send_dma(rspi, xfer); |
79d23495 GU |
753 | if (ret < 0) |
754 | return ret; | |
0b2182dd | 755 | } |
8449fd76 GU |
756 | if (xfer->rx_buf) |
757 | return rspi_receive_dma(rspi, xfer); | |
758 | ||
759 | return 0; | |
eb557f75 GU |
760 | } |
761 | ||
862d357f GU |
762 | static int rspi_rz_transfer_out_in(struct rspi_data *rspi, |
763 | struct spi_transfer *xfer) | |
764 | { | |
765 | int remain = xfer->len, ret; | |
766 | const u8 *tx_buf = xfer->tx_buf; | |
767 | u8 *rx_buf = xfer->rx_buf; | |
768 | u8 data; | |
769 | ||
770 | rspi_rz_receive_init(rspi); | |
771 | ||
772 | while (remain > 0) { | |
773 | data = tx_buf ? *tx_buf++ : DUMMY_DATA; | |
774 | ret = rspi_data_out_in(rspi, data); | |
775 | if (ret < 0) | |
776 | return ret; | |
777 | if (rx_buf) | |
778 | *rx_buf++ = ret; | |
779 | remain--; | |
780 | } | |
781 | ||
782 | /* Wait for the last transmission */ | |
783 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); | |
784 | ||
785 | return 0; | |
786 | } | |
787 | ||
788 | static int rspi_rz_transfer_one(struct spi_master *master, | |
789 | struct spi_device *spi, | |
790 | struct spi_transfer *xfer) | |
791 | { | |
792 | struct rspi_data *rspi = spi_master_get_devdata(master); | |
793 | ||
794 | return rspi_rz_transfer_out_in(rspi, xfer); | |
795 | } | |
796 | ||
340a15e6 GU |
797 | static int qspi_transfer_out_in(struct rspi_data *rspi, |
798 | struct spi_transfer *xfer) | |
eb557f75 | 799 | { |
340a15e6 GU |
800 | int remain = xfer->len, ret; |
801 | const u8 *tx_buf = xfer->tx_buf; | |
802 | u8 *rx_buf = xfer->rx_buf; | |
803 | u8 data; | |
eb557f75 | 804 | |
340a15e6 GU |
805 | qspi_receive_init(rspi); |
806 | ||
807 | while (remain > 0) { | |
808 | data = tx_buf ? *tx_buf++ : DUMMY_DATA; | |
809 | ret = rspi_data_out_in(rspi, data); | |
eb557f75 GU |
810 | if (ret < 0) |
811 | return ret; | |
340a15e6 GU |
812 | if (rx_buf) |
813 | *rx_buf++ = ret; | |
814 | remain--; | |
79d23495 | 815 | } |
340a15e6 GU |
816 | |
817 | /* Wait for the last transmission */ | |
818 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); | |
819 | ||
820 | return 0; | |
821 | } | |
822 | ||
880c6d11 GU |
823 | static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer) |
824 | { | |
825 | const u8 *buf = xfer->tx_buf; | |
826 | unsigned int i; | |
827 | int ret; | |
828 | ||
829 | for (i = 0; i < xfer->len; i++) { | |
830 | ret = rspi_data_out(rspi, *buf++); | |
831 | if (ret < 0) | |
832 | return ret; | |
833 | } | |
834 | ||
835 | /* Wait for the last transmission */ | |
836 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); | |
837 | ||
838 | return 0; | |
839 | } | |
840 | ||
841 | static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer) | |
842 | { | |
843 | u8 *buf = xfer->rx_buf; | |
844 | unsigned int i; | |
845 | int ret; | |
846 | ||
847 | for (i = 0; i < xfer->len; i++) { | |
848 | ret = rspi_data_in(rspi); | |
849 | if (ret < 0) | |
850 | return ret; | |
851 | *buf++ = ret; | |
852 | } | |
853 | ||
854 | return 0; | |
855 | } | |
856 | ||
340a15e6 GU |
857 | static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi, |
858 | struct spi_transfer *xfer) | |
859 | { | |
860 | struct rspi_data *rspi = spi_master_get_devdata(master); | |
861 | ||
880c6d11 GU |
862 | if (xfer->tx_buf && xfer->tx_nbits > SPI_NBITS_SINGLE) { |
863 | /* Quad or Dual SPI Write */ | |
864 | return qspi_transfer_out(rspi, xfer); | |
865 | } else if (xfer->rx_buf && xfer->rx_nbits > SPI_NBITS_SINGLE) { | |
866 | /* Quad or Dual SPI Read */ | |
867 | return qspi_transfer_in(rspi, xfer); | |
868 | } else { | |
869 | /* Single SPI Transfer */ | |
870 | return qspi_transfer_out_in(rspi, xfer); | |
871 | } | |
0b2182dd SY |
872 | } |
873 | ||
874 | static int rspi_setup(struct spi_device *spi) | |
875 | { | |
876 | struct rspi_data *rspi = spi_master_get_devdata(spi->master); | |
877 | ||
0b2182dd SY |
878 | rspi->max_speed_hz = spi->max_speed_hz; |
879 | ||
348e5153 GU |
880 | rspi->spcmd = SPCMD_SSLKP; |
881 | if (spi->mode & SPI_CPOL) | |
882 | rspi->spcmd |= SPCMD_CPOL; | |
883 | if (spi->mode & SPI_CPHA) | |
884 | rspi->spcmd |= SPCMD_CPHA; | |
885 | ||
06a7a3cf GU |
886 | /* CMOS output mode and MOSI signal from previous transfer */ |
887 | rspi->sppcr = 0; | |
888 | if (spi->mode & SPI_LOOP) | |
889 | rspi->sppcr |= SPPCR_SPLP; | |
890 | ||
5ce0ba88 | 891 | set_config_register(rspi, 8); |
0b2182dd SY |
892 | |
893 | return 0; | |
894 | } | |
895 | ||
880c6d11 GU |
896 | static u16 qspi_transfer_mode(const struct spi_transfer *xfer) |
897 | { | |
898 | if (xfer->tx_buf) | |
899 | switch (xfer->tx_nbits) { | |
900 | case SPI_NBITS_QUAD: | |
901 | return SPCMD_SPIMOD_QUAD; | |
902 | case SPI_NBITS_DUAL: | |
903 | return SPCMD_SPIMOD_DUAL; | |
904 | default: | |
905 | return 0; | |
906 | } | |
907 | if (xfer->rx_buf) | |
908 | switch (xfer->rx_nbits) { | |
909 | case SPI_NBITS_QUAD: | |
910 | return SPCMD_SPIMOD_QUAD | SPCMD_SPRW; | |
911 | case SPI_NBITS_DUAL: | |
912 | return SPCMD_SPIMOD_DUAL | SPCMD_SPRW; | |
913 | default: | |
914 | return 0; | |
915 | } | |
916 | ||
917 | return 0; | |
918 | } | |
919 | ||
920 | static int qspi_setup_sequencer(struct rspi_data *rspi, | |
921 | const struct spi_message *msg) | |
922 | { | |
923 | const struct spi_transfer *xfer; | |
924 | unsigned int i = 0, len = 0; | |
925 | u16 current_mode = 0xffff, mode; | |
926 | ||
927 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
928 | mode = qspi_transfer_mode(xfer); | |
929 | if (mode == current_mode) { | |
930 | len += xfer->len; | |
931 | continue; | |
932 | } | |
933 | ||
934 | /* Transfer mode change */ | |
935 | if (i) { | |
936 | /* Set transfer data length of previous transfer */ | |
937 | rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); | |
938 | } | |
939 | ||
940 | if (i >= QSPI_NUM_SPCMD) { | |
941 | dev_err(&msg->spi->dev, | |
942 | "Too many different transfer modes"); | |
943 | return -EINVAL; | |
944 | } | |
945 | ||
946 | /* Program transfer mode for this transfer */ | |
947 | rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i)); | |
948 | current_mode = mode; | |
949 | len = xfer->len; | |
950 | i++; | |
951 | } | |
952 | if (i) { | |
953 | /* Set final transfer data length and sequence length */ | |
954 | rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); | |
955 | rspi_write8(rspi, i - 1, RSPI_SPSCR); | |
956 | } | |
957 | ||
958 | return 0; | |
959 | } | |
960 | ||
79d23495 | 961 | static int rspi_prepare_message(struct spi_master *master, |
880c6d11 | 962 | struct spi_message *msg) |
79d23495 GU |
963 | { |
964 | struct rspi_data *rspi = spi_master_get_devdata(master); | |
880c6d11 | 965 | int ret; |
0b2182dd | 966 | |
880c6d11 GU |
967 | if (msg->spi->mode & |
968 | (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) { | |
969 | /* Setup sequencer for messages with multiple transfer modes */ | |
970 | ret = qspi_setup_sequencer(rspi, msg); | |
971 | if (ret < 0) | |
972 | return ret; | |
973 | } | |
974 | ||
975 | /* Enable SPI function in master mode */ | |
79d23495 | 976 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); |
0b2182dd SY |
977 | return 0; |
978 | } | |
979 | ||
79d23495 | 980 | static int rspi_unprepare_message(struct spi_master *master, |
880c6d11 | 981 | struct spi_message *msg) |
0b2182dd | 982 | { |
79d23495 GU |
983 | struct rspi_data *rspi = spi_master_get_devdata(master); |
984 | ||
880c6d11 | 985 | /* Disable SPI function */ |
79d23495 | 986 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); |
880c6d11 GU |
987 | |
988 | /* Reset sequencer for Single SPI Transfers */ | |
989 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); | |
990 | rspi_write8(rspi, 0, RSPI_SPSCR); | |
79d23495 | 991 | return 0; |
0b2182dd SY |
992 | } |
993 | ||
93722206 | 994 | static irqreturn_t rspi_irq_mux(int irq, void *_sr) |
0b2182dd | 995 | { |
c132f094 | 996 | struct rspi_data *rspi = _sr; |
97b95c11 | 997 | u8 spsr; |
0b2182dd | 998 | irqreturn_t ret = IRQ_NONE; |
97b95c11 | 999 | u8 disable_irq = 0; |
0b2182dd SY |
1000 | |
1001 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
1002 | if (spsr & SPSR_SPRF) | |
1003 | disable_irq |= SPCR_SPRIE; | |
1004 | if (spsr & SPSR_SPTEF) | |
1005 | disable_irq |= SPCR_SPTIE; | |
1006 | ||
1007 | if (disable_irq) { | |
1008 | ret = IRQ_HANDLED; | |
1009 | rspi_disable_irq(rspi, disable_irq); | |
1010 | wake_up(&rspi->wait); | |
1011 | } | |
1012 | ||
1013 | return ret; | |
1014 | } | |
1015 | ||
93722206 GU |
1016 | static irqreturn_t rspi_irq_rx(int irq, void *_sr) |
1017 | { | |
1018 | struct rspi_data *rspi = _sr; | |
1019 | u8 spsr; | |
1020 | ||
1021 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
1022 | if (spsr & SPSR_SPRF) { | |
1023 | rspi_disable_irq(rspi, SPCR_SPRIE); | |
1024 | wake_up(&rspi->wait); | |
1025 | return IRQ_HANDLED; | |
1026 | } | |
1027 | ||
1028 | return 0; | |
1029 | } | |
1030 | ||
1031 | static irqreturn_t rspi_irq_tx(int irq, void *_sr) | |
1032 | { | |
1033 | struct rspi_data *rspi = _sr; | |
1034 | u8 spsr; | |
1035 | ||
1036 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
1037 | if (spsr & SPSR_SPTEF) { | |
1038 | rspi_disable_irq(rspi, SPCR_SPTIE); | |
1039 | wake_up(&rspi->wait); | |
1040 | return IRQ_HANDLED; | |
1041 | } | |
1042 | ||
1043 | return 0; | |
1044 | } | |
1045 | ||
fd4a319b | 1046 | static int rspi_request_dma(struct rspi_data *rspi, |
0243c536 | 1047 | struct platform_device *pdev) |
a3633fe7 | 1048 | { |
baf588f4 | 1049 | const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev); |
e2b05099 | 1050 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
a3633fe7 | 1051 | dma_cap_mask_t mask; |
0243c536 SY |
1052 | struct dma_slave_config cfg; |
1053 | int ret; | |
a3633fe7 | 1054 | |
e2b05099 | 1055 | if (!res || !rspi_pd) |
0243c536 | 1056 | return 0; /* The driver assumes no error. */ |
a3633fe7 SY |
1057 | |
1058 | rspi->dma_width_16bit = rspi_pd->dma_width_16bit; | |
1059 | ||
1060 | /* If the module receives data by DMAC, it also needs TX DMAC */ | |
1061 | if (rspi_pd->dma_rx_id && rspi_pd->dma_tx_id) { | |
1062 | dma_cap_zero(mask); | |
1063 | dma_cap_set(DMA_SLAVE, mask); | |
0243c536 SY |
1064 | rspi->chan_rx = dma_request_channel(mask, shdma_chan_filter, |
1065 | (void *)rspi_pd->dma_rx_id); | |
1066 | if (rspi->chan_rx) { | |
1067 | cfg.slave_id = rspi_pd->dma_rx_id; | |
1068 | cfg.direction = DMA_DEV_TO_MEM; | |
e2b05099 GL |
1069 | cfg.dst_addr = 0; |
1070 | cfg.src_addr = res->start + RSPI_SPDR; | |
0243c536 SY |
1071 | ret = dmaengine_slave_config(rspi->chan_rx, &cfg); |
1072 | if (!ret) | |
1073 | dev_info(&pdev->dev, "Use DMA when rx.\n"); | |
1074 | else | |
1075 | return ret; | |
1076 | } | |
a3633fe7 SY |
1077 | } |
1078 | if (rspi_pd->dma_tx_id) { | |
1079 | dma_cap_zero(mask); | |
1080 | dma_cap_set(DMA_SLAVE, mask); | |
0243c536 SY |
1081 | rspi->chan_tx = dma_request_channel(mask, shdma_chan_filter, |
1082 | (void *)rspi_pd->dma_tx_id); | |
1083 | if (rspi->chan_tx) { | |
1084 | cfg.slave_id = rspi_pd->dma_tx_id; | |
1085 | cfg.direction = DMA_MEM_TO_DEV; | |
e2b05099 GL |
1086 | cfg.dst_addr = res->start + RSPI_SPDR; |
1087 | cfg.src_addr = 0; | |
0243c536 SY |
1088 | ret = dmaengine_slave_config(rspi->chan_tx, &cfg); |
1089 | if (!ret) | |
1090 | dev_info(&pdev->dev, "Use DMA when tx\n"); | |
1091 | else | |
1092 | return ret; | |
1093 | } | |
a3633fe7 | 1094 | } |
0243c536 SY |
1095 | |
1096 | return 0; | |
a3633fe7 SY |
1097 | } |
1098 | ||
fd4a319b | 1099 | static void rspi_release_dma(struct rspi_data *rspi) |
a3633fe7 SY |
1100 | { |
1101 | if (rspi->chan_tx) | |
1102 | dma_release_channel(rspi->chan_tx); | |
1103 | if (rspi->chan_rx) | |
1104 | dma_release_channel(rspi->chan_rx); | |
1105 | } | |
1106 | ||
fd4a319b | 1107 | static int rspi_remove(struct platform_device *pdev) |
0b2182dd | 1108 | { |
5ffbe2d9 | 1109 | struct rspi_data *rspi = platform_get_drvdata(pdev); |
0b2182dd | 1110 | |
a3633fe7 | 1111 | rspi_release_dma(rspi); |
17fe0d9a | 1112 | clk_disable_unprepare(rspi->clk); |
0b2182dd SY |
1113 | |
1114 | return 0; | |
1115 | } | |
1116 | ||
426ef76d GU |
1117 | static const struct spi_ops rspi_ops = { |
1118 | .set_config_register = rspi_set_config_register, | |
1119 | .transfer_one = rspi_transfer_one, | |
880c6d11 | 1120 | .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, |
426ef76d GU |
1121 | }; |
1122 | ||
1123 | static const struct spi_ops rspi_rz_ops = { | |
1124 | .set_config_register = rspi_rz_set_config_register, | |
1125 | .transfer_one = rspi_rz_transfer_one, | |
880c6d11 | 1126 | .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, |
426ef76d GU |
1127 | }; |
1128 | ||
1129 | static const struct spi_ops qspi_ops = { | |
1130 | .set_config_register = qspi_set_config_register, | |
1131 | .transfer_one = qspi_transfer_one, | |
880c6d11 GU |
1132 | .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP | |
1133 | SPI_TX_DUAL | SPI_TX_QUAD | | |
1134 | SPI_RX_DUAL | SPI_RX_QUAD, | |
426ef76d GU |
1135 | }; |
1136 | ||
1137 | #ifdef CONFIG_OF | |
1138 | static const struct of_device_id rspi_of_match[] = { | |
1139 | /* RSPI on legacy SH */ | |
1140 | { .compatible = "renesas,rspi", .data = &rspi_ops }, | |
1141 | /* RSPI on RZ/A1H */ | |
1142 | { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops }, | |
1143 | /* QSPI on R-Car Gen2 */ | |
1144 | { .compatible = "renesas,qspi", .data = &qspi_ops }, | |
1145 | { /* sentinel */ } | |
1146 | }; | |
1147 | ||
1148 | MODULE_DEVICE_TABLE(of, rspi_of_match); | |
1149 | ||
1150 | static int rspi_parse_dt(struct device *dev, struct spi_master *master) | |
1151 | { | |
1152 | u32 num_cs; | |
1153 | int error; | |
1154 | ||
1155 | /* Parse DT properties */ | |
1156 | error = of_property_read_u32(dev->of_node, "num-cs", &num_cs); | |
1157 | if (error) { | |
1158 | dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error); | |
1159 | return error; | |
1160 | } | |
1161 | ||
1162 | master->num_chipselect = num_cs; | |
1163 | return 0; | |
1164 | } | |
1165 | #else | |
64b67def | 1166 | #define rspi_of_match NULL |
426ef76d GU |
1167 | static inline int rspi_parse_dt(struct device *dev, struct spi_master *master) |
1168 | { | |
1169 | return -EINVAL; | |
1170 | } | |
1171 | #endif /* CONFIG_OF */ | |
1172 | ||
93722206 GU |
1173 | static int rspi_request_irq(struct device *dev, unsigned int irq, |
1174 | irq_handler_t handler, const char *suffix, | |
1175 | void *dev_id) | |
1176 | { | |
1177 | const char *base = dev_name(dev); | |
1178 | size_t len = strlen(base) + strlen(suffix) + 2; | |
1179 | char *name = devm_kzalloc(dev, len, GFP_KERNEL); | |
1180 | if (!name) | |
1181 | return -ENOMEM; | |
1182 | snprintf(name, len, "%s:%s", base, suffix); | |
1183 | return devm_request_irq(dev, irq, handler, 0, name, dev_id); | |
1184 | } | |
1185 | ||
fd4a319b | 1186 | static int rspi_probe(struct platform_device *pdev) |
0b2182dd SY |
1187 | { |
1188 | struct resource *res; | |
1189 | struct spi_master *master; | |
1190 | struct rspi_data *rspi; | |
93722206 | 1191 | int ret; |
426ef76d GU |
1192 | const struct of_device_id *of_id; |
1193 | const struct rspi_plat_data *rspi_pd; | |
5ce0ba88 | 1194 | const struct spi_ops *ops; |
0b2182dd | 1195 | |
0b2182dd SY |
1196 | master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); |
1197 | if (master == NULL) { | |
1198 | dev_err(&pdev->dev, "spi_alloc_master error.\n"); | |
1199 | return -ENOMEM; | |
1200 | } | |
1201 | ||
426ef76d GU |
1202 | of_id = of_match_device(rspi_of_match, &pdev->dev); |
1203 | if (of_id) { | |
1204 | ops = of_id->data; | |
1205 | ret = rspi_parse_dt(&pdev->dev, master); | |
1206 | if (ret) | |
1207 | goto error1; | |
1208 | } else { | |
1209 | ops = (struct spi_ops *)pdev->id_entry->driver_data; | |
1210 | rspi_pd = dev_get_platdata(&pdev->dev); | |
1211 | if (rspi_pd && rspi_pd->num_chipselect) | |
1212 | master->num_chipselect = rspi_pd->num_chipselect; | |
1213 | else | |
1214 | master->num_chipselect = 2; /* default */ | |
1215 | }; | |
1216 | ||
1217 | /* ops parameter check */ | |
1218 | if (!ops->set_config_register) { | |
1219 | dev_err(&pdev->dev, "there is no set_config_register\n"); | |
1220 | ret = -ENODEV; | |
1221 | goto error1; | |
1222 | } | |
1223 | ||
0b2182dd | 1224 | rspi = spi_master_get_devdata(master); |
24b5a82c | 1225 | platform_set_drvdata(pdev, rspi); |
5ce0ba88 | 1226 | rspi->ops = ops; |
0b2182dd | 1227 | rspi->master = master; |
5d79e9ac LP |
1228 | |
1229 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1230 | rspi->addr = devm_ioremap_resource(&pdev->dev, res); | |
1231 | if (IS_ERR(rspi->addr)) { | |
1232 | ret = PTR_ERR(rspi->addr); | |
0b2182dd SY |
1233 | goto error1; |
1234 | } | |
1235 | ||
29f397b7 | 1236 | rspi->clk = devm_clk_get(&pdev->dev, NULL); |
0b2182dd SY |
1237 | if (IS_ERR(rspi->clk)) { |
1238 | dev_err(&pdev->dev, "cannot get clock\n"); | |
1239 | ret = PTR_ERR(rspi->clk); | |
5d79e9ac | 1240 | goto error1; |
0b2182dd | 1241 | } |
17fe0d9a GU |
1242 | |
1243 | ret = clk_prepare_enable(rspi->clk); | |
1244 | if (ret < 0) { | |
1245 | dev_err(&pdev->dev, "unable to prepare/enable clock\n"); | |
1246 | goto error1; | |
1247 | } | |
0b2182dd | 1248 | |
0b2182dd SY |
1249 | init_waitqueue_head(&rspi->wait); |
1250 | ||
0b2182dd SY |
1251 | master->bus_num = pdev->id; |
1252 | master->setup = rspi_setup; | |
eb557f75 | 1253 | master->transfer_one = ops->transfer_one; |
79d23495 GU |
1254 | master->prepare_message = rspi_prepare_message; |
1255 | master->unprepare_message = rspi_unprepare_message; | |
880c6d11 | 1256 | master->mode_bits = ops->mode_bits; |
426ef76d | 1257 | master->dev.of_node = pdev->dev.of_node; |
0b2182dd | 1258 | |
93722206 GU |
1259 | ret = platform_get_irq_byname(pdev, "rx"); |
1260 | if (ret < 0) { | |
1261 | ret = platform_get_irq_byname(pdev, "mux"); | |
1262 | if (ret < 0) | |
1263 | ret = platform_get_irq(pdev, 0); | |
1264 | if (ret >= 0) | |
1265 | rspi->rx_irq = rspi->tx_irq = ret; | |
1266 | } else { | |
1267 | rspi->rx_irq = ret; | |
1268 | ret = platform_get_irq_byname(pdev, "tx"); | |
1269 | if (ret >= 0) | |
1270 | rspi->tx_irq = ret; | |
1271 | } | |
1272 | if (ret < 0) { | |
1273 | dev_err(&pdev->dev, "platform_get_irq error\n"); | |
1274 | goto error2; | |
1275 | } | |
1276 | ||
1277 | if (rspi->rx_irq == rspi->tx_irq) { | |
1278 | /* Single multiplexed interrupt */ | |
1279 | ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux, | |
1280 | "mux", rspi); | |
1281 | } else { | |
1282 | /* Multi-interrupt mode, only SPRI and SPTI are used */ | |
1283 | ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx, | |
1284 | "rx", rspi); | |
1285 | if (!ret) | |
1286 | ret = rspi_request_irq(&pdev->dev, rspi->tx_irq, | |
1287 | rspi_irq_tx, "tx", rspi); | |
1288 | } | |
0b2182dd SY |
1289 | if (ret < 0) { |
1290 | dev_err(&pdev->dev, "request_irq error\n"); | |
fcb4ed74 | 1291 | goto error2; |
0b2182dd SY |
1292 | } |
1293 | ||
0243c536 SY |
1294 | ret = rspi_request_dma(rspi, pdev); |
1295 | if (ret < 0) { | |
1296 | dev_err(&pdev->dev, "rspi_request_dma failed.\n"); | |
fcb4ed74 | 1297 | goto error3; |
0243c536 | 1298 | } |
a3633fe7 | 1299 | |
9e03d05e | 1300 | ret = devm_spi_register_master(&pdev->dev, master); |
0b2182dd SY |
1301 | if (ret < 0) { |
1302 | dev_err(&pdev->dev, "spi_register_master error.\n"); | |
fcb4ed74 | 1303 | goto error3; |
0b2182dd SY |
1304 | } |
1305 | ||
1306 | dev_info(&pdev->dev, "probed\n"); | |
1307 | ||
1308 | return 0; | |
1309 | ||
fcb4ed74 | 1310 | error3: |
5d79e9ac | 1311 | rspi_release_dma(rspi); |
fcb4ed74 | 1312 | error2: |
17fe0d9a | 1313 | clk_disable_unprepare(rspi->clk); |
0b2182dd SY |
1314 | error1: |
1315 | spi_master_put(master); | |
1316 | ||
1317 | return ret; | |
1318 | } | |
1319 | ||
5ce0ba88 HCM |
1320 | static struct platform_device_id spi_driver_ids[] = { |
1321 | { "rspi", (kernel_ulong_t)&rspi_ops }, | |
862d357f | 1322 | { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops }, |
5ce0ba88 HCM |
1323 | { "qspi", (kernel_ulong_t)&qspi_ops }, |
1324 | {}, | |
1325 | }; | |
1326 | ||
1327 | MODULE_DEVICE_TABLE(platform, spi_driver_ids); | |
1328 | ||
0b2182dd SY |
1329 | static struct platform_driver rspi_driver = { |
1330 | .probe = rspi_probe, | |
fd4a319b | 1331 | .remove = rspi_remove, |
5ce0ba88 | 1332 | .id_table = spi_driver_ids, |
0b2182dd | 1333 | .driver = { |
5ce0ba88 | 1334 | .name = "renesas_spi", |
0b2182dd | 1335 | .owner = THIS_MODULE, |
426ef76d | 1336 | .of_match_table = of_match_ptr(rspi_of_match), |
0b2182dd SY |
1337 | }, |
1338 | }; | |
1339 | module_platform_driver(rspi_driver); | |
1340 | ||
1341 | MODULE_DESCRIPTION("Renesas RSPI bus driver"); | |
1342 | MODULE_LICENSE("GPL v2"); | |
1343 | MODULE_AUTHOR("Yoshihiro Shimoda"); | |
1344 | MODULE_ALIAS("platform:rspi"); |