Commit | Line | Data |
---|---|---|
a5f6abd4 | 1 | /* |
26fdc1f0 | 2 | * Blackfin On-Chip SPI Driver |
a5f6abd4 | 3 | * |
9c0a788b | 4 | * Copyright 2004-2010 Analog Devices Inc. |
a5f6abd4 | 5 | * |
26fdc1f0 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
a5f6abd4 | 7 | * |
26fdc1f0 | 8 | * Licensed under the GPL-2 or later. |
a5f6abd4 WB |
9 | */ |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
131b17d4 | 13 | #include <linux/delay.h> |
a5f6abd4 | 14 | #include <linux/device.h> |
5a0e3ad6 | 15 | #include <linux/slab.h> |
131b17d4 | 16 | #include <linux/io.h> |
a5f6abd4 | 17 | #include <linux/ioport.h> |
131b17d4 | 18 | #include <linux/irq.h> |
a5f6abd4 WB |
19 | #include <linux/errno.h> |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/dma-mapping.h> | |
23 | #include <linux/spi/spi.h> | |
24 | #include <linux/workqueue.h> | |
a5f6abd4 | 25 | |
a5f6abd4 | 26 | #include <asm/dma.h> |
131b17d4 | 27 | #include <asm/portmux.h> |
a5f6abd4 | 28 | #include <asm/bfin5xx_spi.h> |
8cf5858c VM |
29 | #include <asm/cacheflush.h> |
30 | ||
a32c691d BW |
31 | #define DRV_NAME "bfin-spi" |
32 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" | |
138f97cd | 33 | #define DRV_DESC "Blackfin on-chip SPI Controller Driver" |
a32c691d BW |
34 | #define DRV_VERSION "1.0" |
35 | ||
36 | MODULE_AUTHOR(DRV_AUTHOR); | |
37 | MODULE_DESCRIPTION(DRV_DESC); | |
a5f6abd4 WB |
38 | MODULE_LICENSE("GPL"); |
39 | ||
bb90eb00 BW |
40 | #define START_STATE ((void *)0) |
41 | #define RUNNING_STATE ((void *)1) | |
42 | #define DONE_STATE ((void *)2) | |
43 | #define ERROR_STATE ((void *)-1) | |
a5f6abd4 | 44 | |
9c0a788b | 45 | struct bfin_spi_master_data; |
9c4542c7 | 46 | |
9c0a788b MF |
47 | struct bfin_spi_transfer_ops { |
48 | void (*write) (struct bfin_spi_master_data *); | |
49 | void (*read) (struct bfin_spi_master_data *); | |
50 | void (*duplex) (struct bfin_spi_master_data *); | |
9c4542c7 MF |
51 | }; |
52 | ||
9c0a788b | 53 | struct bfin_spi_master_data { |
a5f6abd4 WB |
54 | /* Driver model hookup */ |
55 | struct platform_device *pdev; | |
56 | ||
57 | /* SPI framework hookup */ | |
58 | struct spi_master *master; | |
59 | ||
bb90eb00 | 60 | /* Regs base of SPI controller */ |
f452126c | 61 | void __iomem *regs_base; |
bb90eb00 | 62 | |
003d9226 BW |
63 | /* Pin request list */ |
64 | u16 *pin_req; | |
65 | ||
a5f6abd4 WB |
66 | /* BFIN hookup */ |
67 | struct bfin5xx_spi_master *master_info; | |
68 | ||
69 | /* Driver message queue */ | |
70 | struct workqueue_struct *workqueue; | |
71 | struct work_struct pump_messages; | |
72 | spinlock_t lock; | |
73 | struct list_head queue; | |
74 | int busy; | |
f4f50c3f | 75 | bool running; |
a5f6abd4 WB |
76 | |
77 | /* Message Transfer pump */ | |
78 | struct tasklet_struct pump_transfers; | |
79 | ||
80 | /* Current message transfer state info */ | |
81 | struct spi_message *cur_msg; | |
82 | struct spi_transfer *cur_transfer; | |
9c0a788b | 83 | struct bfin_spi_slave_data *cur_chip; |
a5f6abd4 WB |
84 | size_t len_in_bytes; |
85 | size_t len; | |
86 | void *tx; | |
87 | void *tx_end; | |
88 | void *rx; | |
89 | void *rx_end; | |
bb90eb00 BW |
90 | |
91 | /* DMA stuffs */ | |
92 | int dma_channel; | |
a5f6abd4 | 93 | int dma_mapped; |
bb90eb00 | 94 | int dma_requested; |
a5f6abd4 WB |
95 | dma_addr_t rx_dma; |
96 | dma_addr_t tx_dma; | |
bb90eb00 | 97 | |
f6a6d966 YL |
98 | int irq_requested; |
99 | int spi_irq; | |
100 | ||
a5f6abd4 WB |
101 | size_t rx_map_len; |
102 | size_t tx_map_len; | |
103 | u8 n_bytes; | |
b052fd0a BS |
104 | u16 ctrl_reg; |
105 | u16 flag_reg; | |
106 | ||
fad91c89 | 107 | int cs_change; |
9c0a788b | 108 | const struct bfin_spi_transfer_ops *ops; |
a5f6abd4 WB |
109 | }; |
110 | ||
9c0a788b | 111 | struct bfin_spi_slave_data { |
a5f6abd4 WB |
112 | u16 ctl_reg; |
113 | u16 baud; | |
114 | u16 flag; | |
115 | ||
116 | u8 chip_select_num; | |
a5f6abd4 | 117 | u8 enable_dma; |
62310e51 | 118 | u16 cs_chg_udelay; /* Some devices require > 255usec delay */ |
42c78b2b | 119 | u32 cs_gpio; |
93b61bdd | 120 | u16 idle_tx_val; |
f6a6d966 | 121 | u8 pio_interrupt; /* use spi data irq */ |
9c0a788b | 122 | const struct bfin_spi_transfer_ops *ops; |
a5f6abd4 WB |
123 | }; |
124 | ||
bb90eb00 | 125 | #define DEFINE_SPI_REG(reg, off) \ |
9c0a788b | 126 | static inline u16 read_##reg(struct bfin_spi_master_data *drv_data) \ |
bb90eb00 | 127 | { return bfin_read16(drv_data->regs_base + off); } \ |
9c0a788b | 128 | static inline void write_##reg(struct bfin_spi_master_data *drv_data, u16 v) \ |
bb90eb00 BW |
129 | { bfin_write16(drv_data->regs_base + off, v); } |
130 | ||
131 | DEFINE_SPI_REG(CTRL, 0x00) | |
132 | DEFINE_SPI_REG(FLAG, 0x04) | |
133 | DEFINE_SPI_REG(STAT, 0x08) | |
134 | DEFINE_SPI_REG(TDBR, 0x0C) | |
135 | DEFINE_SPI_REG(RDBR, 0x10) | |
136 | DEFINE_SPI_REG(BAUD, 0x14) | |
137 | DEFINE_SPI_REG(SHAW, 0x18) | |
138 | ||
9c0a788b | 139 | static void bfin_spi_enable(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
140 | { |
141 | u16 cr; | |
142 | ||
bb90eb00 BW |
143 | cr = read_CTRL(drv_data); |
144 | write_CTRL(drv_data, (cr | BIT_CTL_ENABLE)); | |
a5f6abd4 WB |
145 | } |
146 | ||
9c0a788b | 147 | static void bfin_spi_disable(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
148 | { |
149 | u16 cr; | |
150 | ||
bb90eb00 BW |
151 | cr = read_CTRL(drv_data); |
152 | write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE))); | |
a5f6abd4 WB |
153 | } |
154 | ||
155 | /* Caculate the SPI_BAUD register value based on input HZ */ | |
156 | static u16 hz_to_spi_baud(u32 speed_hz) | |
157 | { | |
158 | u_long sclk = get_sclk(); | |
159 | u16 spi_baud = (sclk / (2 * speed_hz)); | |
160 | ||
161 | if ((sclk % (2 * speed_hz)) > 0) | |
162 | spi_baud++; | |
163 | ||
7513e006 MH |
164 | if (spi_baud < MIN_SPI_BAUD_VAL) |
165 | spi_baud = MIN_SPI_BAUD_VAL; | |
166 | ||
a5f6abd4 WB |
167 | return spi_baud; |
168 | } | |
169 | ||
9c0a788b | 170 | static int bfin_spi_flush(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
171 | { |
172 | unsigned long limit = loops_per_jiffy << 1; | |
173 | ||
174 | /* wait for stop and clear stat */ | |
b4bd2aba | 175 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit) |
d8c05008 | 176 | cpu_relax(); |
a5f6abd4 | 177 | |
bb90eb00 | 178 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 WB |
179 | |
180 | return limit; | |
181 | } | |
182 | ||
fad91c89 | 183 | /* Chip select operation functions for cs_change flag */ |
9c0a788b | 184 | static void bfin_spi_cs_active(struct bfin_spi_master_data *drv_data, struct bfin_spi_slave_data *chip) |
fad91c89 | 185 | { |
d3cc71f7 | 186 | if (likely(chip->chip_select_num < MAX_CTRL_CS)) { |
42c78b2b | 187 | u16 flag = read_FLAG(drv_data); |
fad91c89 | 188 | |
8221610e | 189 | flag &= ~chip->flag; |
fad91c89 | 190 | |
42c78b2b MH |
191 | write_FLAG(drv_data, flag); |
192 | } else { | |
193 | gpio_set_value(chip->cs_gpio, 0); | |
194 | } | |
fad91c89 BW |
195 | } |
196 | ||
9c0a788b MF |
197 | static void bfin_spi_cs_deactive(struct bfin_spi_master_data *drv_data, |
198 | struct bfin_spi_slave_data *chip) | |
fad91c89 | 199 | { |
d3cc71f7 | 200 | if (likely(chip->chip_select_num < MAX_CTRL_CS)) { |
42c78b2b | 201 | u16 flag = read_FLAG(drv_data); |
fad91c89 | 202 | |
8221610e | 203 | flag |= chip->flag; |
fad91c89 | 204 | |
42c78b2b MH |
205 | write_FLAG(drv_data, flag); |
206 | } else { | |
207 | gpio_set_value(chip->cs_gpio, 1); | |
208 | } | |
62310e51 BW |
209 | |
210 | /* Move delay here for consistency */ | |
211 | if (chip->cs_chg_udelay) | |
212 | udelay(chip->cs_chg_udelay); | |
fad91c89 BW |
213 | } |
214 | ||
8221610e | 215 | /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */ |
9c0a788b MF |
216 | static inline void bfin_spi_cs_enable(struct bfin_spi_master_data *drv_data, |
217 | struct bfin_spi_slave_data *chip) | |
8221610e | 218 | { |
d3cc71f7 BS |
219 | if (chip->chip_select_num < MAX_CTRL_CS) { |
220 | u16 flag = read_FLAG(drv_data); | |
8221610e | 221 | |
d3cc71f7 | 222 | flag |= (chip->flag >> 8); |
8221610e | 223 | |
d3cc71f7 BS |
224 | write_FLAG(drv_data, flag); |
225 | } | |
8221610e BS |
226 | } |
227 | ||
9c0a788b MF |
228 | static inline void bfin_spi_cs_disable(struct bfin_spi_master_data *drv_data, |
229 | struct bfin_spi_slave_data *chip) | |
8221610e | 230 | { |
d3cc71f7 BS |
231 | if (chip->chip_select_num < MAX_CTRL_CS) { |
232 | u16 flag = read_FLAG(drv_data); | |
8221610e | 233 | |
d3cc71f7 | 234 | flag &= ~(chip->flag >> 8); |
8221610e | 235 | |
d3cc71f7 BS |
236 | write_FLAG(drv_data, flag); |
237 | } | |
8221610e BS |
238 | } |
239 | ||
a5f6abd4 | 240 | /* stop controller and re-config current chip*/ |
9c0a788b | 241 | static void bfin_spi_restore_state(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 242 | { |
9c0a788b | 243 | struct bfin_spi_slave_data *chip = drv_data->cur_chip; |
12e17c42 | 244 | |
a5f6abd4 | 245 | /* Clear status and disable clock */ |
bb90eb00 | 246 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 | 247 | bfin_spi_disable(drv_data); |
88b40369 | 248 | dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); |
a5f6abd4 | 249 | |
9677b0de BS |
250 | SSYNC(); |
251 | ||
5fec5b5a | 252 | /* Load the registers */ |
bb90eb00 | 253 | write_CTRL(drv_data, chip->ctl_reg); |
092e1fda | 254 | write_BAUD(drv_data, chip->baud); |
cc487e73 SZ |
255 | |
256 | bfin_spi_enable(drv_data); | |
138f97cd | 257 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 WB |
258 | } |
259 | ||
93b61bdd | 260 | /* used to kick off transfer in rx mode and read unwanted RX data */ |
9c0a788b | 261 | static inline void bfin_spi_dummy_read(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 262 | { |
93b61bdd | 263 | (void) read_RDBR(drv_data); |
a5f6abd4 WB |
264 | } |
265 | ||
9c0a788b | 266 | static void bfin_spi_u8_writer(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 267 | { |
93b61bdd WM |
268 | /* clear RXS (we check for RXS inside the loop) */ |
269 | bfin_spi_dummy_read(drv_data); | |
cc487e73 | 270 | |
a5f6abd4 | 271 | while (drv_data->tx < drv_data->tx_end) { |
93b61bdd WM |
272 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
273 | /* wait until transfer finished. | |
274 | checking SPIF or TXS may not guarantee transfer completion */ | |
275 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
d8c05008 | 276 | cpu_relax(); |
93b61bdd WM |
277 | /* discard RX data and clear RXS */ |
278 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 279 | } |
a5f6abd4 WB |
280 | } |
281 | ||
9c0a788b | 282 | static void bfin_spi_u8_reader(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 283 | { |
93b61bdd | 284 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
a5f6abd4 | 285 | |
93b61bdd | 286 | /* discard old RX data and clear RXS */ |
138f97cd | 287 | bfin_spi_dummy_read(drv_data); |
cc487e73 | 288 | |
93b61bdd WM |
289 | while (drv_data->rx < drv_data->rx_end) { |
290 | write_TDBR(drv_data, tx_val); | |
bb90eb00 | 291 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 292 | cpu_relax(); |
93b61bdd | 293 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
a5f6abd4 | 294 | } |
a5f6abd4 WB |
295 | } |
296 | ||
9c0a788b | 297 | static void bfin_spi_u8_duplex(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 298 | { |
93b61bdd WM |
299 | /* discard old RX data and clear RXS */ |
300 | bfin_spi_dummy_read(drv_data); | |
301 | ||
a5f6abd4 | 302 | while (drv_data->rx < drv_data->rx_end) { |
93b61bdd | 303 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
bb90eb00 | 304 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 305 | cpu_relax(); |
93b61bdd | 306 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
a5f6abd4 WB |
307 | } |
308 | } | |
309 | ||
9c0a788b | 310 | static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u8 = { |
9c4542c7 MF |
311 | .write = bfin_spi_u8_writer, |
312 | .read = bfin_spi_u8_reader, | |
313 | .duplex = bfin_spi_u8_duplex, | |
314 | }; | |
315 | ||
9c0a788b | 316 | static void bfin_spi_u16_writer(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 317 | { |
93b61bdd WM |
318 | /* clear RXS (we check for RXS inside the loop) */ |
319 | bfin_spi_dummy_read(drv_data); | |
88b40369 | 320 | |
a5f6abd4 | 321 | while (drv_data->tx < drv_data->tx_end) { |
bb90eb00 | 322 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
a5f6abd4 | 323 | drv_data->tx += 2; |
93b61bdd WM |
324 | /* wait until transfer finished. |
325 | checking SPIF or TXS may not guarantee transfer completion */ | |
326 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
327 | cpu_relax(); | |
328 | /* discard RX data and clear RXS */ | |
329 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 330 | } |
a5f6abd4 WB |
331 | } |
332 | ||
9c0a788b | 333 | static void bfin_spi_u16_reader(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 334 | { |
93b61bdd | 335 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
cc487e73 | 336 | |
93b61bdd | 337 | /* discard old RX data and clear RXS */ |
138f97cd | 338 | bfin_spi_dummy_read(drv_data); |
a5f6abd4 | 339 | |
93b61bdd WM |
340 | while (drv_data->rx < drv_data->rx_end) { |
341 | write_TDBR(drv_data, tx_val); | |
bb90eb00 | 342 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 343 | cpu_relax(); |
bb90eb00 | 344 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 WB |
345 | drv_data->rx += 2; |
346 | } | |
a5f6abd4 WB |
347 | } |
348 | ||
9c0a788b | 349 | static void bfin_spi_u16_duplex(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 350 | { |
93b61bdd WM |
351 | /* discard old RX data and clear RXS */ |
352 | bfin_spi_dummy_read(drv_data); | |
353 | ||
354 | while (drv_data->rx < drv_data->rx_end) { | |
bb90eb00 | 355 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
93b61bdd | 356 | drv_data->tx += 2; |
bb90eb00 | 357 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 358 | cpu_relax(); |
bb90eb00 | 359 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 | 360 | drv_data->rx += 2; |
a5f6abd4 WB |
361 | } |
362 | } | |
363 | ||
9c0a788b | 364 | static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u16 = { |
9c4542c7 MF |
365 | .write = bfin_spi_u16_writer, |
366 | .read = bfin_spi_u16_reader, | |
367 | .duplex = bfin_spi_u16_duplex, | |
368 | }; | |
369 | ||
e3595405 | 370 | /* test if there is more transfer to be done */ |
9c0a788b | 371 | static void *bfin_spi_next_transfer(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
372 | { |
373 | struct spi_message *msg = drv_data->cur_msg; | |
374 | struct spi_transfer *trans = drv_data->cur_transfer; | |
375 | ||
376 | /* Move to next transfer */ | |
377 | if (trans->transfer_list.next != &msg->transfers) { | |
378 | drv_data->cur_transfer = | |
379 | list_entry(trans->transfer_list.next, | |
380 | struct spi_transfer, transfer_list); | |
381 | return RUNNING_STATE; | |
382 | } else | |
383 | return DONE_STATE; | |
384 | } | |
385 | ||
386 | /* | |
387 | * caller already set message->status; | |
388 | * dma and pio irqs are blocked give finished message back | |
389 | */ | |
9c0a788b | 390 | static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 391 | { |
9c0a788b | 392 | struct bfin_spi_slave_data *chip = drv_data->cur_chip; |
a5f6abd4 WB |
393 | struct spi_transfer *last_transfer; |
394 | unsigned long flags; | |
395 | struct spi_message *msg; | |
396 | ||
397 | spin_lock_irqsave(&drv_data->lock, flags); | |
398 | msg = drv_data->cur_msg; | |
399 | drv_data->cur_msg = NULL; | |
400 | drv_data->cur_transfer = NULL; | |
401 | drv_data->cur_chip = NULL; | |
402 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
403 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
404 | ||
405 | last_transfer = list_entry(msg->transfers.prev, | |
406 | struct spi_transfer, transfer_list); | |
407 | ||
408 | msg->state = NULL; | |
409 | ||
fad91c89 | 410 | if (!drv_data->cs_change) |
138f97cd | 411 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 412 | |
b9b2a76a YL |
413 | /* Not stop spi in autobuffer mode */ |
414 | if (drv_data->tx_dma != 0xFFFF) | |
415 | bfin_spi_disable(drv_data); | |
416 | ||
a5f6abd4 WB |
417 | if (msg->complete) |
418 | msg->complete(msg->context); | |
419 | } | |
420 | ||
f6a6d966 YL |
421 | /* spi data irq handler */ |
422 | static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id) | |
423 | { | |
9c0a788b MF |
424 | struct bfin_spi_master_data *drv_data = dev_id; |
425 | struct bfin_spi_slave_data *chip = drv_data->cur_chip; | |
f6a6d966 YL |
426 | struct spi_message *msg = drv_data->cur_msg; |
427 | int n_bytes = drv_data->n_bytes; | |
4d676fc5 | 428 | int loop = 0; |
f6a6d966 YL |
429 | |
430 | /* wait until transfer finished. */ | |
431 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
432 | cpu_relax(); | |
433 | ||
434 | if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) || | |
435 | (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) { | |
436 | /* last read */ | |
437 | if (drv_data->rx) { | |
438 | dev_dbg(&drv_data->pdev->dev, "last read\n"); | |
4d676fc5 BL |
439 | if (n_bytes % 2) { |
440 | u16 *buf = (u16 *)drv_data->rx; | |
441 | for (loop = 0; loop < n_bytes / 2; loop++) | |
442 | *buf++ = read_RDBR(drv_data); | |
443 | } else { | |
444 | u8 *buf = (u8 *)drv_data->rx; | |
445 | for (loop = 0; loop < n_bytes; loop++) | |
446 | *buf++ = read_RDBR(drv_data); | |
447 | } | |
f6a6d966 YL |
448 | drv_data->rx += n_bytes; |
449 | } | |
450 | ||
451 | msg->actual_length += drv_data->len_in_bytes; | |
452 | if (drv_data->cs_change) | |
453 | bfin_spi_cs_deactive(drv_data, chip); | |
454 | /* Move to next transfer */ | |
455 | msg->state = bfin_spi_next_transfer(drv_data); | |
456 | ||
7370ed6b | 457 | disable_irq_nosync(drv_data->spi_irq); |
f6a6d966 YL |
458 | |
459 | /* Schedule transfer tasklet */ | |
460 | tasklet_schedule(&drv_data->pump_transfers); | |
461 | return IRQ_HANDLED; | |
462 | } | |
463 | ||
464 | if (drv_data->rx && drv_data->tx) { | |
465 | /* duplex */ | |
466 | dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n"); | |
4d676fc5 BL |
467 | if (n_bytes % 2) { |
468 | u16 *buf = (u16 *)drv_data->rx; | |
469 | u16 *buf2 = (u16 *)drv_data->tx; | |
470 | for (loop = 0; loop < n_bytes / 2; loop++) { | |
471 | *buf++ = read_RDBR(drv_data); | |
472 | write_TDBR(drv_data, *buf2++); | |
473 | } | |
474 | } else { | |
475 | u8 *buf = (u8 *)drv_data->rx; | |
476 | u8 *buf2 = (u8 *)drv_data->tx; | |
477 | for (loop = 0; loop < n_bytes; loop++) { | |
478 | *buf++ = read_RDBR(drv_data); | |
479 | write_TDBR(drv_data, *buf2++); | |
480 | } | |
f6a6d966 YL |
481 | } |
482 | } else if (drv_data->rx) { | |
483 | /* read */ | |
484 | dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n"); | |
4d676fc5 BL |
485 | if (n_bytes % 2) { |
486 | u16 *buf = (u16 *)drv_data->rx; | |
487 | for (loop = 0; loop < n_bytes / 2; loop++) { | |
488 | *buf++ = read_RDBR(drv_data); | |
489 | write_TDBR(drv_data, chip->idle_tx_val); | |
490 | } | |
491 | } else { | |
492 | u8 *buf = (u8 *)drv_data->rx; | |
493 | for (loop = 0; loop < n_bytes; loop++) { | |
494 | *buf++ = read_RDBR(drv_data); | |
495 | write_TDBR(drv_data, chip->idle_tx_val); | |
496 | } | |
497 | } | |
f6a6d966 YL |
498 | } else if (drv_data->tx) { |
499 | /* write */ | |
500 | dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n"); | |
4d676fc5 BL |
501 | if (n_bytes % 2) { |
502 | u16 *buf = (u16 *)drv_data->tx; | |
503 | for (loop = 0; loop < n_bytes / 2; loop++) { | |
504 | read_RDBR(drv_data); | |
505 | write_TDBR(drv_data, *buf++); | |
506 | } | |
507 | } else { | |
508 | u8 *buf = (u8 *)drv_data->tx; | |
509 | for (loop = 0; loop < n_bytes; loop++) { | |
510 | read_RDBR(drv_data); | |
511 | write_TDBR(drv_data, *buf++); | |
512 | } | |
513 | } | |
f6a6d966 YL |
514 | } |
515 | ||
516 | if (drv_data->tx) | |
517 | drv_data->tx += n_bytes; | |
518 | if (drv_data->rx) | |
519 | drv_data->rx += n_bytes; | |
520 | ||
521 | return IRQ_HANDLED; | |
522 | } | |
523 | ||
138f97cd | 524 | static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id) |
a5f6abd4 | 525 | { |
9c0a788b MF |
526 | struct bfin_spi_master_data *drv_data = dev_id; |
527 | struct bfin_spi_slave_data *chip = drv_data->cur_chip; | |
bb90eb00 | 528 | struct spi_message *msg = drv_data->cur_msg; |
aaaf939c | 529 | unsigned long timeout; |
d24bd1d0 | 530 | unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel); |
04b95d2f | 531 | u16 spistat = read_STAT(drv_data); |
a5f6abd4 | 532 | |
d24bd1d0 MF |
533 | dev_dbg(&drv_data->pdev->dev, |
534 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
535 | dmastat, spistat); | |
536 | ||
782a8956 MH |
537 | if (drv_data->rx != NULL) { |
538 | u16 cr = read_CTRL(drv_data); | |
539 | /* discard old RX data and clear RXS */ | |
540 | bfin_spi_dummy_read(drv_data); | |
541 | write_CTRL(drv_data, cr & ~BIT_CTL_ENABLE); /* Disable SPI */ | |
542 | write_CTRL(drv_data, cr & ~BIT_CTL_TIMOD); /* Restore State */ | |
543 | write_STAT(drv_data, BIT_STAT_CLR); /* Clear Status */ | |
544 | } | |
545 | ||
bb90eb00 | 546 | clear_dma_irqstat(drv_data->dma_channel); |
a5f6abd4 WB |
547 | |
548 | /* | |
d6fe89b0 BW |
549 | * wait for the last transaction shifted out. HRM states: |
550 | * at this point there may still be data in the SPI DMA FIFO waiting | |
551 | * to be transmitted ... software needs to poll TXS in the SPI_STAT | |
552 | * register until it goes low for 2 successive reads | |
a5f6abd4 WB |
553 | */ |
554 | if (drv_data->tx != NULL) { | |
90008a64 MF |
555 | while ((read_STAT(drv_data) & BIT_STAT_TXS) || |
556 | (read_STAT(drv_data) & BIT_STAT_TXS)) | |
d8c05008 | 557 | cpu_relax(); |
a5f6abd4 WB |
558 | } |
559 | ||
aaaf939c MF |
560 | dev_dbg(&drv_data->pdev->dev, |
561 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
562 | dmastat, read_STAT(drv_data)); | |
563 | ||
564 | timeout = jiffies + HZ; | |
90008a64 | 565 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
aaaf939c MF |
566 | if (!time_before(jiffies, timeout)) { |
567 | dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF"); | |
568 | break; | |
569 | } else | |
570 | cpu_relax(); | |
a5f6abd4 | 571 | |
90008a64 | 572 | if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) { |
04b95d2f MF |
573 | msg->state = ERROR_STATE; |
574 | dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n"); | |
575 | } else { | |
576 | msg->actual_length += drv_data->len_in_bytes; | |
a5f6abd4 | 577 | |
04b95d2f | 578 | if (drv_data->cs_change) |
138f97cd | 579 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 580 | |
04b95d2f | 581 | /* Move to next transfer */ |
138f97cd | 582 | msg->state = bfin_spi_next_transfer(drv_data); |
04b95d2f | 583 | } |
a5f6abd4 WB |
584 | |
585 | /* Schedule transfer tasklet */ | |
586 | tasklet_schedule(&drv_data->pump_transfers); | |
587 | ||
588 | /* free the irq handler before next transfer */ | |
88b40369 BW |
589 | dev_dbg(&drv_data->pdev->dev, |
590 | "disable dma channel irq%d\n", | |
bb90eb00 | 591 | drv_data->dma_channel); |
a75bd65b | 592 | dma_disable_irq_nosync(drv_data->dma_channel); |
a5f6abd4 WB |
593 | |
594 | return IRQ_HANDLED; | |
595 | } | |
596 | ||
138f97cd | 597 | static void bfin_spi_pump_transfers(unsigned long data) |
a5f6abd4 | 598 | { |
9c0a788b | 599 | struct bfin_spi_master_data *drv_data = (struct bfin_spi_master_data *)data; |
a5f6abd4 WB |
600 | struct spi_message *message = NULL; |
601 | struct spi_transfer *transfer = NULL; | |
602 | struct spi_transfer *previous = NULL; | |
9c0a788b | 603 | struct bfin_spi_slave_data *chip = NULL; |
033f44bd | 604 | unsigned int bits_per_word; |
5e8592dc | 605 | u16 cr, cr_width, dma_width, dma_config; |
a5f6abd4 | 606 | u32 tranf_success = 1; |
8eeb12e5 | 607 | u8 full_duplex = 0; |
a5f6abd4 WB |
608 | |
609 | /* Get current state information */ | |
610 | message = drv_data->cur_msg; | |
611 | transfer = drv_data->cur_transfer; | |
612 | chip = drv_data->cur_chip; | |
092e1fda | 613 | |
a5f6abd4 WB |
614 | /* |
615 | * if msg is error or done, report it back using complete() callback | |
616 | */ | |
617 | ||
618 | /* Handle for abort */ | |
619 | if (message->state == ERROR_STATE) { | |
d24bd1d0 | 620 | dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n"); |
a5f6abd4 | 621 | message->status = -EIO; |
138f97cd | 622 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
623 | return; |
624 | } | |
625 | ||
626 | /* Handle end of message */ | |
627 | if (message->state == DONE_STATE) { | |
d24bd1d0 | 628 | dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n"); |
a5f6abd4 | 629 | message->status = 0; |
138f97cd | 630 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
631 | return; |
632 | } | |
633 | ||
634 | /* Delay if requested at end of transfer */ | |
635 | if (message->state == RUNNING_STATE) { | |
d24bd1d0 | 636 | dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n"); |
a5f6abd4 WB |
637 | previous = list_entry(transfer->transfer_list.prev, |
638 | struct spi_transfer, transfer_list); | |
639 | if (previous->delay_usecs) | |
640 | udelay(previous->delay_usecs); | |
641 | } | |
642 | ||
ab09e040 | 643 | /* Flush any existing transfers that may be sitting in the hardware */ |
138f97cd | 644 | if (bfin_spi_flush(drv_data) == 0) { |
a5f6abd4 WB |
645 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
646 | message->status = -EIO; | |
138f97cd | 647 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
648 | return; |
649 | } | |
650 | ||
93b61bdd WM |
651 | if (transfer->len == 0) { |
652 | /* Move to next transfer of this msg */ | |
653 | message->state = bfin_spi_next_transfer(drv_data); | |
654 | /* Schedule next transfer tasklet */ | |
655 | tasklet_schedule(&drv_data->pump_transfers); | |
1974eba6 | 656 | return; |
93b61bdd WM |
657 | } |
658 | ||
a5f6abd4 WB |
659 | if (transfer->tx_buf != NULL) { |
660 | drv_data->tx = (void *)transfer->tx_buf; | |
661 | drv_data->tx_end = drv_data->tx + transfer->len; | |
88b40369 BW |
662 | dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n", |
663 | transfer->tx_buf, drv_data->tx_end); | |
a5f6abd4 WB |
664 | } else { |
665 | drv_data->tx = NULL; | |
666 | } | |
667 | ||
668 | if (transfer->rx_buf != NULL) { | |
8eeb12e5 | 669 | full_duplex = transfer->tx_buf != NULL; |
a5f6abd4 WB |
670 | drv_data->rx = transfer->rx_buf; |
671 | drv_data->rx_end = drv_data->rx + transfer->len; | |
88b40369 BW |
672 | dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n", |
673 | transfer->rx_buf, drv_data->rx_end); | |
a5f6abd4 WB |
674 | } else { |
675 | drv_data->rx = NULL; | |
676 | } | |
677 | ||
678 | drv_data->rx_dma = transfer->rx_dma; | |
679 | drv_data->tx_dma = transfer->tx_dma; | |
680 | drv_data->len_in_bytes = transfer->len; | |
fad91c89 | 681 | drv_data->cs_change = transfer->cs_change; |
a5f6abd4 | 682 | |
092e1fda | 683 | /* Bits per word setup */ |
033f44bd | 684 | bits_per_word = transfer->bits_per_word ? : message->spi->bits_per_word; |
4d676fc5 BL |
685 | if ((bits_per_word > 0) && (bits_per_word % 16 == 0)) { |
686 | drv_data->n_bytes = bits_per_word/8; | |
5e8592dc MF |
687 | drv_data->len = (transfer->len) >> 1; |
688 | cr_width = BIT_CTL_WORDSIZE; | |
9c0a788b | 689 | drv_data->ops = &bfin_bfin_spi_transfer_ops_u16; |
4d676fc5 BL |
690 | } else if ((bits_per_word > 0) && (bits_per_word % 8 == 0)) { |
691 | drv_data->n_bytes = bits_per_word/8; | |
692 | drv_data->len = transfer->len; | |
693 | cr_width = 0; | |
694 | drv_data->ops = &bfin_bfin_spi_transfer_ops_u8; | |
2e768659 BL |
695 | } else { |
696 | dev_err(&drv_data->pdev->dev, "transfer: unsupported bits_per_word\n"); | |
697 | message->status = -EINVAL; | |
698 | bfin_spi_giveback(drv_data); | |
699 | return; | |
092e1fda | 700 | } |
5e8592dc MF |
701 | cr = read_CTRL(drv_data) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE); |
702 | cr |= cr_width; | |
092e1fda BW |
703 | write_CTRL(drv_data, cr); |
704 | ||
4fb98efa | 705 | dev_dbg(&drv_data->pdev->dev, |
9c4542c7 | 706 | "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n", |
9c0a788b | 707 | drv_data->ops, chip->ops, &bfin_bfin_spi_transfer_ops_u8); |
a5f6abd4 | 708 | |
a5f6abd4 WB |
709 | message->state = RUNNING_STATE; |
710 | dma_config = 0; | |
711 | ||
092e1fda BW |
712 | /* Speed setup (surely valid because already checked) */ |
713 | if (transfer->speed_hz) | |
714 | write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz)); | |
715 | else | |
716 | write_BAUD(drv_data, chip->baud); | |
717 | ||
bb90eb00 | 718 | write_STAT(drv_data, BIT_STAT_CLR); |
e72dcde7 | 719 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 | 720 | |
88b40369 BW |
721 | dev_dbg(&drv_data->pdev->dev, |
722 | "now pumping a transfer: width is %d, len is %d\n", | |
5e8592dc | 723 | cr_width, transfer->len); |
a5f6abd4 WB |
724 | |
725 | /* | |
8cf5858c VM |
726 | * Try to map dma buffer and do a dma transfer. If successful use, |
727 | * different way to r/w according to the enable_dma settings and if | |
728 | * we are not doing a full duplex transfer (since the hardware does | |
729 | * not support full duplex DMA transfers). | |
a5f6abd4 | 730 | */ |
8eeb12e5 VM |
731 | if (!full_duplex && drv_data->cur_chip->enable_dma |
732 | && drv_data->len > 6) { | |
a5f6abd4 | 733 | |
11d6f599 | 734 | unsigned long dma_start_addr, flags; |
7aec3566 | 735 | |
bb90eb00 BW |
736 | disable_dma(drv_data->dma_channel); |
737 | clear_dma_irqstat(drv_data->dma_channel); | |
a5f6abd4 WB |
738 | |
739 | /* config dma channel */ | |
88b40369 | 740 | dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); |
7aec3566 | 741 | set_dma_x_count(drv_data->dma_channel, drv_data->len); |
5e8592dc | 742 | if (cr_width == BIT_CTL_WORDSIZE) { |
bb90eb00 | 743 | set_dma_x_modify(drv_data->dma_channel, 2); |
a5f6abd4 WB |
744 | dma_width = WDSIZE_16; |
745 | } else { | |
bb90eb00 | 746 | set_dma_x_modify(drv_data->dma_channel, 1); |
a5f6abd4 WB |
747 | dma_width = WDSIZE_8; |
748 | } | |
749 | ||
3f479a65 | 750 | /* poll for SPI completion before start */ |
bb90eb00 | 751 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 752 | cpu_relax(); |
3f479a65 | 753 | |
a5f6abd4 WB |
754 | /* dirty hack for autobuffer DMA mode */ |
755 | if (drv_data->tx_dma == 0xFFFF) { | |
88b40369 BW |
756 | dev_dbg(&drv_data->pdev->dev, |
757 | "doing autobuffer DMA out.\n"); | |
a5f6abd4 WB |
758 | |
759 | /* no irq in autobuffer mode */ | |
760 | dma_config = | |
761 | (DMAFLOW_AUTO | RESTART | dma_width | DI_EN); | |
bb90eb00 BW |
762 | set_dma_config(drv_data->dma_channel, dma_config); |
763 | set_dma_start_addr(drv_data->dma_channel, | |
a32c691d | 764 | (unsigned long)drv_data->tx); |
bb90eb00 | 765 | enable_dma(drv_data->dma_channel); |
a5f6abd4 | 766 | |
07612e5f | 767 | /* start SPI transfer */ |
11d6f599 | 768 | write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX); |
07612e5f SZ |
769 | |
770 | /* just return here, there can only be one transfer | |
771 | * in this mode | |
772 | */ | |
a5f6abd4 | 773 | message->status = 0; |
138f97cd | 774 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
775 | return; |
776 | } | |
777 | ||
778 | /* In dma mode, rx or tx must be NULL in one transfer */ | |
7aec3566 | 779 | dma_config = (RESTART | dma_width | DI_EN); |
a5f6abd4 WB |
780 | if (drv_data->rx != NULL) { |
781 | /* set transfer mode, and enable SPI */ | |
d24bd1d0 MF |
782 | dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n", |
783 | drv_data->rx, drv_data->len_in_bytes); | |
a5f6abd4 | 784 | |
8cf5858c | 785 | /* invalidate caches, if needed */ |
67834fa9 | 786 | if (bfin_addr_dcacheable((unsigned long) drv_data->rx)) |
8cf5858c VM |
787 | invalidate_dcache_range((unsigned long) drv_data->rx, |
788 | (unsigned long) (drv_data->rx + | |
ace32865 | 789 | drv_data->len_in_bytes)); |
8cf5858c | 790 | |
7aec3566 MF |
791 | dma_config |= WNR; |
792 | dma_start_addr = (unsigned long)drv_data->rx; | |
b31e27a6 | 793 | cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT; |
07612e5f | 794 | |
a5f6abd4 | 795 | } else if (drv_data->tx != NULL) { |
88b40369 | 796 | dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n"); |
a5f6abd4 | 797 | |
8cf5858c | 798 | /* flush caches, if needed */ |
67834fa9 | 799 | if (bfin_addr_dcacheable((unsigned long) drv_data->tx)) |
8cf5858c VM |
800 | flush_dcache_range((unsigned long) drv_data->tx, |
801 | (unsigned long) (drv_data->tx + | |
ace32865 | 802 | drv_data->len_in_bytes)); |
8cf5858c | 803 | |
7aec3566 | 804 | dma_start_addr = (unsigned long)drv_data->tx; |
b31e27a6 | 805 | cr |= BIT_CTL_TIMOD_DMA_TX; |
7aec3566 MF |
806 | |
807 | } else | |
808 | BUG(); | |
809 | ||
11d6f599 MF |
810 | /* oh man, here there be monsters ... and i dont mean the |
811 | * fluffy cute ones from pixar, i mean the kind that'll eat | |
812 | * your data, kick your dog, and love it all. do *not* try | |
813 | * and change these lines unless you (1) heavily test DMA | |
814 | * with SPI flashes on a loaded system (e.g. ping floods), | |
815 | * (2) know just how broken the DMA engine interaction with | |
816 | * the SPI peripheral is, and (3) have someone else to blame | |
817 | * when you screw it all up anyways. | |
818 | */ | |
7aec3566 | 819 | set_dma_start_addr(drv_data->dma_channel, dma_start_addr); |
11d6f599 MF |
820 | set_dma_config(drv_data->dma_channel, dma_config); |
821 | local_irq_save(flags); | |
a963ea83 | 822 | SSYNC(); |
11d6f599 | 823 | write_CTRL(drv_data, cr); |
a963ea83 | 824 | enable_dma(drv_data->dma_channel); |
11d6f599 MF |
825 | dma_enable_irq(drv_data->dma_channel); |
826 | local_irq_restore(flags); | |
07612e5f | 827 | |
f6a6d966 YL |
828 | return; |
829 | } | |
a5f6abd4 | 830 | |
5e8592dc MF |
831 | /* |
832 | * We always use SPI_WRITE mode (transfer starts with TDBR write). | |
833 | * SPI_READ mode (transfer starts with RDBR read) seems to have | |
834 | * problems with setting up the output value in TDBR prior to the | |
835 | * start of the transfer. | |
836 | */ | |
837 | write_CTRL(drv_data, cr | BIT_CTL_TXMOD); | |
838 | ||
f6a6d966 | 839 | if (chip->pio_interrupt) { |
5e8592dc | 840 | /* SPI irq should have been disabled by now */ |
93b61bdd | 841 | |
f6a6d966 YL |
842 | /* discard old RX data and clear RXS */ |
843 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 844 | |
f6a6d966 YL |
845 | /* start transfer */ |
846 | if (drv_data->tx == NULL) | |
847 | write_TDBR(drv_data, chip->idle_tx_val); | |
848 | else { | |
4d676fc5 BL |
849 | int loop; |
850 | if (bits_per_word % 16 == 0) { | |
851 | u16 *buf = (u16 *)drv_data->tx; | |
852 | for (loop = 0; loop < bits_per_word / 16; | |
853 | loop++) { | |
854 | write_TDBR(drv_data, *buf++); | |
855 | } | |
856 | } else if (bits_per_word % 8 == 0) { | |
857 | u8 *buf = (u8 *)drv_data->tx; | |
858 | for (loop = 0; loop < bits_per_word / 8; loop++) | |
859 | write_TDBR(drv_data, *buf++); | |
860 | } | |
861 | ||
f6a6d966 YL |
862 | drv_data->tx += drv_data->n_bytes; |
863 | } | |
a5f6abd4 | 864 | |
f6a6d966 YL |
865 | /* once TDBR is empty, interrupt is triggered */ |
866 | enable_irq(drv_data->spi_irq); | |
867 | return; | |
868 | } | |
a5f6abd4 | 869 | |
f6a6d966 YL |
870 | /* IO mode */ |
871 | dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); | |
872 | ||
f6a6d966 YL |
873 | if (full_duplex) { |
874 | /* full duplex mode */ | |
875 | BUG_ON((drv_data->tx_end - drv_data->tx) != | |
876 | (drv_data->rx_end - drv_data->rx)); | |
877 | dev_dbg(&drv_data->pdev->dev, | |
878 | "IO duplex: cr is 0x%x\n", cr); | |
879 | ||
9c4542c7 | 880 | drv_data->ops->duplex(drv_data); |
f6a6d966 YL |
881 | |
882 | if (drv_data->tx != drv_data->tx_end) | |
883 | tranf_success = 0; | |
884 | } else if (drv_data->tx != NULL) { | |
885 | /* write only half duplex */ | |
886 | dev_dbg(&drv_data->pdev->dev, | |
887 | "IO write: cr is 0x%x\n", cr); | |
888 | ||
9c4542c7 | 889 | drv_data->ops->write(drv_data); |
f6a6d966 YL |
890 | |
891 | if (drv_data->tx != drv_data->tx_end) | |
892 | tranf_success = 0; | |
893 | } else if (drv_data->rx != NULL) { | |
894 | /* read only half duplex */ | |
895 | dev_dbg(&drv_data->pdev->dev, | |
896 | "IO read: cr is 0x%x\n", cr); | |
897 | ||
9c4542c7 | 898 | drv_data->ops->read(drv_data); |
f6a6d966 YL |
899 | if (drv_data->rx != drv_data->rx_end) |
900 | tranf_success = 0; | |
901 | } | |
a5f6abd4 | 902 | |
f6a6d966 YL |
903 | if (!tranf_success) { |
904 | dev_dbg(&drv_data->pdev->dev, | |
905 | "IO write error!\n"); | |
906 | message->state = ERROR_STATE; | |
907 | } else { | |
25985edc | 908 | /* Update total byte transferred */ |
f6a6d966 YL |
909 | message->actual_length += drv_data->len_in_bytes; |
910 | /* Move to next transfer of this msg */ | |
911 | message->state = bfin_spi_next_transfer(drv_data); | |
912 | if (drv_data->cs_change) | |
913 | bfin_spi_cs_deactive(drv_data, chip); | |
a5f6abd4 | 914 | } |
f6a6d966 YL |
915 | |
916 | /* Schedule next transfer tasklet */ | |
917 | tasklet_schedule(&drv_data->pump_transfers); | |
a5f6abd4 WB |
918 | } |
919 | ||
920 | /* pop a msg from queue and kick off real transfer */ | |
138f97cd | 921 | static void bfin_spi_pump_messages(struct work_struct *work) |
a5f6abd4 | 922 | { |
9c0a788b | 923 | struct bfin_spi_master_data *drv_data; |
a5f6abd4 WB |
924 | unsigned long flags; |
925 | ||
9c0a788b | 926 | drv_data = container_of(work, struct bfin_spi_master_data, pump_messages); |
131b17d4 | 927 | |
a5f6abd4 WB |
928 | /* Lock queue and check for queue work */ |
929 | spin_lock_irqsave(&drv_data->lock, flags); | |
f4f50c3f | 930 | if (list_empty(&drv_data->queue) || !drv_data->running) { |
a5f6abd4 WB |
931 | /* pumper kicked off but no work to do */ |
932 | drv_data->busy = 0; | |
933 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
934 | return; | |
935 | } | |
936 | ||
937 | /* Make sure we are not already running a message */ | |
938 | if (drv_data->cur_msg) { | |
939 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
940 | return; | |
941 | } | |
942 | ||
943 | /* Extract head of queue */ | |
944 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
945 | struct spi_message, queue); | |
5fec5b5a BW |
946 | |
947 | /* Setup the SSP using the per chip configuration */ | |
948 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); | |
138f97cd | 949 | bfin_spi_restore_state(drv_data); |
5fec5b5a | 950 | |
a5f6abd4 WB |
951 | list_del_init(&drv_data->cur_msg->queue); |
952 | ||
953 | /* Initial message state */ | |
954 | drv_data->cur_msg->state = START_STATE; | |
955 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
956 | struct spi_transfer, transfer_list); | |
957 | ||
5fec5b5a BW |
958 | dev_dbg(&drv_data->pdev->dev, "got a message to pump, " |
959 | "state is set to: baud %d, flag 0x%x, ctl 0x%x\n", | |
960 | drv_data->cur_chip->baud, drv_data->cur_chip->flag, | |
961 | drv_data->cur_chip->ctl_reg); | |
131b17d4 BW |
962 | |
963 | dev_dbg(&drv_data->pdev->dev, | |
88b40369 BW |
964 | "the first transfer len is %d\n", |
965 | drv_data->cur_transfer->len); | |
a5f6abd4 WB |
966 | |
967 | /* Mark as busy and launch transfers */ | |
968 | tasklet_schedule(&drv_data->pump_transfers); | |
969 | ||
970 | drv_data->busy = 1; | |
971 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
972 | } | |
973 | ||
974 | /* | |
975 | * got a msg to transfer, queue it in drv_data->queue. | |
976 | * And kick off message pumper | |
977 | */ | |
138f97cd | 978 | static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg) |
a5f6abd4 | 979 | { |
9c0a788b | 980 | struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master); |
a5f6abd4 WB |
981 | unsigned long flags; |
982 | ||
983 | spin_lock_irqsave(&drv_data->lock, flags); | |
984 | ||
f4f50c3f | 985 | if (!drv_data->running) { |
a5f6abd4 WB |
986 | spin_unlock_irqrestore(&drv_data->lock, flags); |
987 | return -ESHUTDOWN; | |
988 | } | |
989 | ||
990 | msg->actual_length = 0; | |
991 | msg->status = -EINPROGRESS; | |
992 | msg->state = START_STATE; | |
993 | ||
88b40369 | 994 | dev_dbg(&spi->dev, "adding an msg in transfer() \n"); |
a5f6abd4 WB |
995 | list_add_tail(&msg->queue, &drv_data->queue); |
996 | ||
f4f50c3f | 997 | if (drv_data->running && !drv_data->busy) |
a5f6abd4 WB |
998 | queue_work(drv_data->workqueue, &drv_data->pump_messages); |
999 | ||
1000 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1001 | ||
1002 | return 0; | |
1003 | } | |
1004 | ||
12e17c42 SZ |
1005 | #define MAX_SPI_SSEL 7 |
1006 | ||
4160bde2 | 1007 | static u16 ssel[][MAX_SPI_SSEL] = { |
12e17c42 SZ |
1008 | {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3, |
1009 | P_SPI0_SSEL4, P_SPI0_SSEL5, | |
1010 | P_SPI0_SSEL6, P_SPI0_SSEL7}, | |
1011 | ||
1012 | {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3, | |
1013 | P_SPI1_SSEL4, P_SPI1_SSEL5, | |
1014 | P_SPI1_SSEL6, P_SPI1_SSEL7}, | |
1015 | ||
1016 | {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3, | |
1017 | P_SPI2_SSEL4, P_SPI2_SSEL5, | |
1018 | P_SPI2_SSEL6, P_SPI2_SSEL7}, | |
1019 | }; | |
1020 | ||
ab09e040 | 1021 | /* setup for devices (may be called multiple times -- not just first setup) */ |
138f97cd | 1022 | static int bfin_spi_setup(struct spi_device *spi) |
a5f6abd4 | 1023 | { |
ac01e97d | 1024 | struct bfin5xx_spi_chip *chip_info; |
9c0a788b MF |
1025 | struct bfin_spi_slave_data *chip = NULL; |
1026 | struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master); | |
5b47bcd4 | 1027 | u16 bfin_ctl_reg; |
ac01e97d | 1028 | int ret = -EINVAL; |
a5f6abd4 | 1029 | |
a5f6abd4 | 1030 | /* Only alloc (or use chip_info) on first setup */ |
ac01e97d | 1031 | chip_info = NULL; |
a5f6abd4 WB |
1032 | chip = spi_get_ctldata(spi); |
1033 | if (chip == NULL) { | |
ac01e97d DM |
1034 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
1035 | if (!chip) { | |
1036 | dev_err(&spi->dev, "cannot allocate chip data\n"); | |
1037 | ret = -ENOMEM; | |
1038 | goto error; | |
1039 | } | |
a5f6abd4 WB |
1040 | |
1041 | chip->enable_dma = 0; | |
1042 | chip_info = spi->controller_data; | |
1043 | } | |
1044 | ||
5b47bcd4 MF |
1045 | /* Let people set non-standard bits directly */ |
1046 | bfin_ctl_reg = BIT_CTL_OPENDRAIN | BIT_CTL_EMISO | | |
1047 | BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ; | |
1048 | ||
a5f6abd4 WB |
1049 | /* chip_info isn't always needed */ |
1050 | if (chip_info) { | |
2ed35516 MF |
1051 | /* Make sure people stop trying to set fields via ctl_reg |
1052 | * when they should actually be using common SPI framework. | |
90008a64 | 1053 | * Currently we let through: WOM EMISO PSSE GM SZ. |
2ed35516 MF |
1054 | * Not sure if a user actually needs/uses any of these, |
1055 | * but let's assume (for now) they do. | |
1056 | */ | |
5b47bcd4 | 1057 | if (chip_info->ctl_reg & ~bfin_ctl_reg) { |
2ed35516 MF |
1058 | dev_err(&spi->dev, "do not set bits in ctl_reg " |
1059 | "that the SPI framework manages\n"); | |
ac01e97d | 1060 | goto error; |
2ed35516 | 1061 | } |
a5f6abd4 WB |
1062 | chip->enable_dma = chip_info->enable_dma != 0 |
1063 | && drv_data->master_info->enable_dma; | |
1064 | chip->ctl_reg = chip_info->ctl_reg; | |
a5f6abd4 | 1065 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; |
93b61bdd | 1066 | chip->idle_tx_val = chip_info->idle_tx_val; |
f6a6d966 | 1067 | chip->pio_interrupt = chip_info->pio_interrupt; |
033f44bd | 1068 | spi->bits_per_word = chip_info->bits_per_word; |
5b47bcd4 MF |
1069 | } else { |
1070 | /* force a default base state */ | |
1071 | chip->ctl_reg &= bfin_ctl_reg; | |
033f44bd MF |
1072 | } |
1073 | ||
4d676fc5 | 1074 | if (spi->bits_per_word % 8) { |
033f44bd MF |
1075 | dev_err(&spi->dev, "%d bits_per_word is not supported\n", |
1076 | spi->bits_per_word); | |
1077 | goto error; | |
a5f6abd4 WB |
1078 | } |
1079 | ||
1080 | /* translate common spi framework into our register */ | |
7715aad4 MF |
1081 | if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) { |
1082 | dev_err(&spi->dev, "unsupported spi modes detected\n"); | |
1083 | goto error; | |
1084 | } | |
a5f6abd4 | 1085 | if (spi->mode & SPI_CPOL) |
90008a64 | 1086 | chip->ctl_reg |= BIT_CTL_CPOL; |
a5f6abd4 | 1087 | if (spi->mode & SPI_CPHA) |
90008a64 | 1088 | chip->ctl_reg |= BIT_CTL_CPHA; |
a5f6abd4 | 1089 | if (spi->mode & SPI_LSB_FIRST) |
90008a64 | 1090 | chip->ctl_reg |= BIT_CTL_LSBF; |
a5f6abd4 | 1091 | /* we dont support running in slave mode (yet?) */ |
90008a64 | 1092 | chip->ctl_reg |= BIT_CTL_MASTER; |
a5f6abd4 | 1093 | |
a5f6abd4 WB |
1094 | /* |
1095 | * Notice: for blackfin, the speed_hz is the value of register | |
1096 | * SPI_BAUD, not the real baudrate | |
1097 | */ | |
1098 | chip->baud = hz_to_spi_baud(spi->max_speed_hz); | |
a5f6abd4 | 1099 | chip->chip_select_num = spi->chip_select; |
4190f6a5 BS |
1100 | if (chip->chip_select_num < MAX_CTRL_CS) { |
1101 | if (!(spi->mode & SPI_CPHA)) | |
1102 | dev_warn(&spi->dev, "Warning: SPI CPHA not set:" | |
1103 | " Slave Select not under software control!\n" | |
1104 | " See Documentation/blackfin/bfin-spi-notes.txt"); | |
1105 | ||
d3cc71f7 | 1106 | chip->flag = (1 << spi->chip_select) << 8; |
4190f6a5 | 1107 | } else |
d3cc71f7 | 1108 | chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS; |
a5f6abd4 | 1109 | |
f6a6d966 YL |
1110 | if (chip->enable_dma && chip->pio_interrupt) { |
1111 | dev_err(&spi->dev, "enable_dma is set, " | |
1112 | "do not set pio_interrupt\n"); | |
1113 | goto error; | |
1114 | } | |
ac01e97d DM |
1115 | /* |
1116 | * if any one SPI chip is registered and wants DMA, request the | |
1117 | * DMA channel for it | |
1118 | */ | |
1119 | if (chip->enable_dma && !drv_data->dma_requested) { | |
1120 | /* register dma irq handler */ | |
1121 | ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA"); | |
1122 | if (ret) { | |
1123 | dev_err(&spi->dev, | |
1124 | "Unable to request BlackFin SPI DMA channel\n"); | |
1125 | goto error; | |
1126 | } | |
1127 | drv_data->dma_requested = 1; | |
1128 | ||
1129 | ret = set_dma_callback(drv_data->dma_channel, | |
1130 | bfin_spi_dma_irq_handler, drv_data); | |
1131 | if (ret) { | |
1132 | dev_err(&spi->dev, "Unable to set dma callback\n"); | |
1133 | goto error; | |
1134 | } | |
1135 | dma_disable_irq(drv_data->dma_channel); | |
1136 | } | |
1137 | ||
f6a6d966 YL |
1138 | if (chip->pio_interrupt && !drv_data->irq_requested) { |
1139 | ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler, | |
1140 | IRQF_DISABLED, "BFIN_SPI", drv_data); | |
1141 | if (ret) { | |
1142 | dev_err(&spi->dev, "Unable to register spi IRQ\n"); | |
1143 | goto error; | |
1144 | } | |
1145 | drv_data->irq_requested = 1; | |
1146 | /* we use write mode, spi irq has to be disabled here */ | |
1147 | disable_irq(drv_data->spi_irq); | |
1148 | } | |
1149 | ||
d3cc71f7 | 1150 | if (chip->chip_select_num >= MAX_CTRL_CS) { |
73e1ac16 MH |
1151 | /* Only request on first setup */ |
1152 | if (spi_get_ctldata(spi) == NULL) { | |
1153 | ret = gpio_request(chip->cs_gpio, spi->modalias); | |
1154 | if (ret) { | |
1155 | dev_err(&spi->dev, "gpio_request() error\n"); | |
1156 | goto pin_error; | |
1157 | } | |
1158 | gpio_direction_output(chip->cs_gpio, 1); | |
ac01e97d | 1159 | } |
a5f6abd4 WB |
1160 | } |
1161 | ||
898eb71c | 1162 | dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n", |
033f44bd | 1163 | spi->modalias, spi->bits_per_word, chip->enable_dma); |
88b40369 | 1164 | dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n", |
a5f6abd4 WB |
1165 | chip->ctl_reg, chip->flag); |
1166 | ||
1167 | spi_set_ctldata(spi, chip); | |
1168 | ||
12e17c42 | 1169 | dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num); |
d3cc71f7 | 1170 | if (chip->chip_select_num < MAX_CTRL_CS) { |
ac01e97d DM |
1171 | ret = peripheral_request(ssel[spi->master->bus_num] |
1172 | [chip->chip_select_num-1], spi->modalias); | |
1173 | if (ret) { | |
1174 | dev_err(&spi->dev, "peripheral_request() error\n"); | |
1175 | goto pin_error; | |
1176 | } | |
1177 | } | |
12e17c42 | 1178 | |
8221610e | 1179 | bfin_spi_cs_enable(drv_data, chip); |
138f97cd | 1180 | bfin_spi_cs_deactive(drv_data, chip); |
07612e5f | 1181 | |
a5f6abd4 | 1182 | return 0; |
ac01e97d DM |
1183 | |
1184 | pin_error: | |
d3cc71f7 | 1185 | if (chip->chip_select_num >= MAX_CTRL_CS) |
ac01e97d DM |
1186 | gpio_free(chip->cs_gpio); |
1187 | else | |
1188 | peripheral_free(ssel[spi->master->bus_num] | |
1189 | [chip->chip_select_num - 1]); | |
1190 | error: | |
1191 | if (chip) { | |
1192 | if (drv_data->dma_requested) | |
1193 | free_dma(drv_data->dma_channel); | |
1194 | drv_data->dma_requested = 0; | |
1195 | ||
1196 | kfree(chip); | |
1197 | /* prevent free 'chip' twice */ | |
1198 | spi_set_ctldata(spi, NULL); | |
1199 | } | |
1200 | ||
1201 | return ret; | |
a5f6abd4 WB |
1202 | } |
1203 | ||
1204 | /* | |
1205 | * callback for spi framework. | |
1206 | * clean driver specific data | |
1207 | */ | |
138f97cd | 1208 | static void bfin_spi_cleanup(struct spi_device *spi) |
a5f6abd4 | 1209 | { |
9c0a788b MF |
1210 | struct bfin_spi_slave_data *chip = spi_get_ctldata(spi); |
1211 | struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master); | |
a5f6abd4 | 1212 | |
e7d02e3c MF |
1213 | if (!chip) |
1214 | return; | |
1215 | ||
d3cc71f7 | 1216 | if (chip->chip_select_num < MAX_CTRL_CS) { |
12e17c42 SZ |
1217 | peripheral_free(ssel[spi->master->bus_num] |
1218 | [chip->chip_select_num-1]); | |
8221610e | 1219 | bfin_spi_cs_disable(drv_data, chip); |
d3cc71f7 | 1220 | } else |
42c78b2b MH |
1221 | gpio_free(chip->cs_gpio); |
1222 | ||
a5f6abd4 | 1223 | kfree(chip); |
ac01e97d DM |
1224 | /* prevent free 'chip' twice */ |
1225 | spi_set_ctldata(spi, NULL); | |
a5f6abd4 WB |
1226 | } |
1227 | ||
9c0a788b | 1228 | static inline int bfin_spi_init_queue(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
1229 | { |
1230 | INIT_LIST_HEAD(&drv_data->queue); | |
1231 | spin_lock_init(&drv_data->lock); | |
1232 | ||
f4f50c3f | 1233 | drv_data->running = false; |
a5f6abd4 WB |
1234 | drv_data->busy = 0; |
1235 | ||
1236 | /* init transfer tasklet */ | |
1237 | tasklet_init(&drv_data->pump_transfers, | |
138f97cd | 1238 | bfin_spi_pump_transfers, (unsigned long)drv_data); |
a5f6abd4 WB |
1239 | |
1240 | /* init messages workqueue */ | |
138f97cd | 1241 | INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages); |
6c7377ab KS |
1242 | drv_data->workqueue = create_singlethread_workqueue( |
1243 | dev_name(drv_data->master->dev.parent)); | |
a5f6abd4 WB |
1244 | if (drv_data->workqueue == NULL) |
1245 | return -EBUSY; | |
1246 | ||
1247 | return 0; | |
1248 | } | |
1249 | ||
9c0a788b | 1250 | static inline int bfin_spi_start_queue(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
1251 | { |
1252 | unsigned long flags; | |
1253 | ||
1254 | spin_lock_irqsave(&drv_data->lock, flags); | |
1255 | ||
f4f50c3f | 1256 | if (drv_data->running || drv_data->busy) { |
a5f6abd4 WB |
1257 | spin_unlock_irqrestore(&drv_data->lock, flags); |
1258 | return -EBUSY; | |
1259 | } | |
1260 | ||
f4f50c3f | 1261 | drv_data->running = true; |
a5f6abd4 WB |
1262 | drv_data->cur_msg = NULL; |
1263 | drv_data->cur_transfer = NULL; | |
1264 | drv_data->cur_chip = NULL; | |
1265 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1266 | ||
1267 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1268 | ||
1269 | return 0; | |
1270 | } | |
1271 | ||
9c0a788b | 1272 | static inline int bfin_spi_stop_queue(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
1273 | { |
1274 | unsigned long flags; | |
1275 | unsigned limit = 500; | |
1276 | int status = 0; | |
1277 | ||
1278 | spin_lock_irqsave(&drv_data->lock, flags); | |
1279 | ||
1280 | /* | |
1281 | * This is a bit lame, but is optimized for the common execution path. | |
1282 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1283 | * execution path (pump_messages) would be required to call wake_up or | |
1284 | * friends on every SPI message. Do this instead | |
1285 | */ | |
f4f50c3f | 1286 | drv_data->running = false; |
850a28ec | 1287 | while ((!list_empty(&drv_data->queue) || drv_data->busy) && limit--) { |
a5f6abd4 WB |
1288 | spin_unlock_irqrestore(&drv_data->lock, flags); |
1289 | msleep(10); | |
1290 | spin_lock_irqsave(&drv_data->lock, flags); | |
1291 | } | |
1292 | ||
1293 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1294 | status = -EBUSY; | |
1295 | ||
1296 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1297 | ||
1298 | return status; | |
1299 | } | |
1300 | ||
9c0a788b | 1301 | static inline int bfin_spi_destroy_queue(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
1302 | { |
1303 | int status; | |
1304 | ||
138f97cd | 1305 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1306 | if (status != 0) |
1307 | return status; | |
1308 | ||
1309 | destroy_workqueue(drv_data->workqueue); | |
1310 | ||
1311 | return 0; | |
1312 | } | |
1313 | ||
138f97cd | 1314 | static int __init bfin_spi_probe(struct platform_device *pdev) |
a5f6abd4 WB |
1315 | { |
1316 | struct device *dev = &pdev->dev; | |
1317 | struct bfin5xx_spi_master *platform_info; | |
1318 | struct spi_master *master; | |
9c0a788b | 1319 | struct bfin_spi_master_data *drv_data; |
a32c691d | 1320 | struct resource *res; |
a5f6abd4 WB |
1321 | int status = 0; |
1322 | ||
1323 | platform_info = dev->platform_data; | |
1324 | ||
1325 | /* Allocate master with space for drv_data */ | |
2a045131 | 1326 | master = spi_alloc_master(dev, sizeof(*drv_data)); |
a5f6abd4 WB |
1327 | if (!master) { |
1328 | dev_err(&pdev->dev, "can not alloc spi_master\n"); | |
1329 | return -ENOMEM; | |
1330 | } | |
131b17d4 | 1331 | |
a5f6abd4 WB |
1332 | drv_data = spi_master_get_devdata(master); |
1333 | drv_data->master = master; | |
1334 | drv_data->master_info = platform_info; | |
1335 | drv_data->pdev = pdev; | |
003d9226 | 1336 | drv_data->pin_req = platform_info->pin_req; |
a5f6abd4 | 1337 | |
e7db06b5 DB |
1338 | /* the spi->mode bits supported by this driver: */ |
1339 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; | |
1340 | ||
a5f6abd4 WB |
1341 | master->bus_num = pdev->id; |
1342 | master->num_chipselect = platform_info->num_chipselect; | |
138f97cd MF |
1343 | master->cleanup = bfin_spi_cleanup; |
1344 | master->setup = bfin_spi_setup; | |
1345 | master->transfer = bfin_spi_transfer; | |
a5f6abd4 | 1346 | |
a32c691d BW |
1347 | /* Find and map our resources */ |
1348 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1349 | if (res == NULL) { | |
1350 | dev_err(dev, "Cannot get IORESOURCE_MEM\n"); | |
1351 | status = -ENOENT; | |
1352 | goto out_error_get_res; | |
1353 | } | |
1354 | ||
74947b89 | 1355 | drv_data->regs_base = ioremap(res->start, resource_size(res)); |
f452126c | 1356 | if (drv_data->regs_base == NULL) { |
a32c691d BW |
1357 | dev_err(dev, "Cannot map IO\n"); |
1358 | status = -ENXIO; | |
1359 | goto out_error_ioremap; | |
1360 | } | |
1361 | ||
f6a6d966 YL |
1362 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
1363 | if (res == NULL) { | |
a32c691d BW |
1364 | dev_err(dev, "No DMA channel specified\n"); |
1365 | status = -ENOENT; | |
f6a6d966 YL |
1366 | goto out_error_free_io; |
1367 | } | |
1368 | drv_data->dma_channel = res->start; | |
1369 | ||
1370 | drv_data->spi_irq = platform_get_irq(pdev, 0); | |
1371 | if (drv_data->spi_irq < 0) { | |
1372 | dev_err(dev, "No spi pio irq specified\n"); | |
1373 | status = -ENOENT; | |
1374 | goto out_error_free_io; | |
a32c691d BW |
1375 | } |
1376 | ||
a5f6abd4 | 1377 | /* Initial and start queue */ |
138f97cd | 1378 | status = bfin_spi_init_queue(drv_data); |
a5f6abd4 | 1379 | if (status != 0) { |
a32c691d | 1380 | dev_err(dev, "problem initializing queue\n"); |
a5f6abd4 WB |
1381 | goto out_error_queue_alloc; |
1382 | } | |
a32c691d | 1383 | |
138f97cd | 1384 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 | 1385 | if (status != 0) { |
a32c691d | 1386 | dev_err(dev, "problem starting queue\n"); |
a5f6abd4 WB |
1387 | goto out_error_queue_alloc; |
1388 | } | |
1389 | ||
f9e522ca VM |
1390 | status = peripheral_request_list(drv_data->pin_req, DRV_NAME); |
1391 | if (status != 0) { | |
1392 | dev_err(&pdev->dev, ": Requesting Peripherals failed\n"); | |
1393 | goto out_error_queue_alloc; | |
1394 | } | |
1395 | ||
bb8beecd WM |
1396 | /* Reset SPI registers. If these registers were used by the boot loader, |
1397 | * the sky may fall on your head if you enable the dma controller. | |
1398 | */ | |
1399 | write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER); | |
1400 | write_FLAG(drv_data, 0xFF00); | |
1401 | ||
a5f6abd4 WB |
1402 | /* Register with the SPI framework */ |
1403 | platform_set_drvdata(pdev, drv_data); | |
1404 | status = spi_register_master(master); | |
1405 | if (status != 0) { | |
a32c691d | 1406 | dev_err(dev, "problem registering spi master\n"); |
a5f6abd4 WB |
1407 | goto out_error_queue_alloc; |
1408 | } | |
a32c691d | 1409 | |
f452126c | 1410 | dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n", |
bb90eb00 BW |
1411 | DRV_DESC, DRV_VERSION, drv_data->regs_base, |
1412 | drv_data->dma_channel); | |
a5f6abd4 WB |
1413 | return status; |
1414 | ||
cc2f81a6 | 1415 | out_error_queue_alloc: |
138f97cd | 1416 | bfin_spi_destroy_queue(drv_data); |
f6a6d966 | 1417 | out_error_free_io: |
bb90eb00 | 1418 | iounmap((void *) drv_data->regs_base); |
a32c691d BW |
1419 | out_error_ioremap: |
1420 | out_error_get_res: | |
a5f6abd4 | 1421 | spi_master_put(master); |
cc2f81a6 | 1422 | |
a5f6abd4 WB |
1423 | return status; |
1424 | } | |
1425 | ||
1426 | /* stop hardware and remove the driver */ | |
138f97cd | 1427 | static int __devexit bfin_spi_remove(struct platform_device *pdev) |
a5f6abd4 | 1428 | { |
9c0a788b | 1429 | struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1430 | int status = 0; |
1431 | ||
1432 | if (!drv_data) | |
1433 | return 0; | |
1434 | ||
1435 | /* Remove the queue */ | |
138f97cd | 1436 | status = bfin_spi_destroy_queue(drv_data); |
a5f6abd4 WB |
1437 | if (status != 0) |
1438 | return status; | |
1439 | ||
1440 | /* Disable the SSP at the peripheral and SOC level */ | |
1441 | bfin_spi_disable(drv_data); | |
1442 | ||
1443 | /* Release DMA */ | |
1444 | if (drv_data->master_info->enable_dma) { | |
bb90eb00 BW |
1445 | if (dma_channel_active(drv_data->dma_channel)) |
1446 | free_dma(drv_data->dma_channel); | |
a5f6abd4 WB |
1447 | } |
1448 | ||
f6a6d966 YL |
1449 | if (drv_data->irq_requested) { |
1450 | free_irq(drv_data->spi_irq, drv_data); | |
1451 | drv_data->irq_requested = 0; | |
1452 | } | |
1453 | ||
a5f6abd4 WB |
1454 | /* Disconnect from the SPI framework */ |
1455 | spi_unregister_master(drv_data->master); | |
1456 | ||
003d9226 | 1457 | peripheral_free_list(drv_data->pin_req); |
cc2f81a6 | 1458 | |
a5f6abd4 WB |
1459 | /* Prevent double remove */ |
1460 | platform_set_drvdata(pdev, NULL); | |
1461 | ||
1462 | return 0; | |
1463 | } | |
1464 | ||
1465 | #ifdef CONFIG_PM | |
138f97cd | 1466 | static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state) |
a5f6abd4 | 1467 | { |
9c0a788b | 1468 | struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1469 | int status = 0; |
1470 | ||
138f97cd | 1471 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1472 | if (status != 0) |
1473 | return status; | |
1474 | ||
b052fd0a BS |
1475 | drv_data->ctrl_reg = read_CTRL(drv_data); |
1476 | drv_data->flag_reg = read_FLAG(drv_data); | |
1477 | ||
1478 | /* | |
1479 | * reset SPI_CTL and SPI_FLG registers | |
1480 | */ | |
1481 | write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER); | |
1482 | write_FLAG(drv_data, 0xFF00); | |
a5f6abd4 WB |
1483 | |
1484 | return 0; | |
1485 | } | |
1486 | ||
138f97cd | 1487 | static int bfin_spi_resume(struct platform_device *pdev) |
a5f6abd4 | 1488 | { |
9c0a788b | 1489 | struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1490 | int status = 0; |
1491 | ||
b052fd0a BS |
1492 | write_CTRL(drv_data, drv_data->ctrl_reg); |
1493 | write_FLAG(drv_data, drv_data->flag_reg); | |
a5f6abd4 WB |
1494 | |
1495 | /* Start the queue running */ | |
138f97cd | 1496 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 WB |
1497 | if (status != 0) { |
1498 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | |
1499 | return status; | |
1500 | } | |
1501 | ||
1502 | return 0; | |
1503 | } | |
1504 | #else | |
138f97cd MF |
1505 | #define bfin_spi_suspend NULL |
1506 | #define bfin_spi_resume NULL | |
a5f6abd4 WB |
1507 | #endif /* CONFIG_PM */ |
1508 | ||
7e38c3c4 | 1509 | MODULE_ALIAS("platform:bfin-spi"); |
138f97cd | 1510 | static struct platform_driver bfin_spi_driver = { |
fc3ba952 | 1511 | .driver = { |
a32c691d | 1512 | .name = DRV_NAME, |
88b40369 BW |
1513 | .owner = THIS_MODULE, |
1514 | }, | |
138f97cd MF |
1515 | .suspend = bfin_spi_suspend, |
1516 | .resume = bfin_spi_resume, | |
1517 | .remove = __devexit_p(bfin_spi_remove), | |
a5f6abd4 WB |
1518 | }; |
1519 | ||
138f97cd | 1520 | static int __init bfin_spi_init(void) |
a5f6abd4 | 1521 | { |
138f97cd | 1522 | return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe); |
a5f6abd4 | 1523 | } |
6f7c17f4 | 1524 | subsys_initcall(bfin_spi_init); |
a5f6abd4 | 1525 | |
138f97cd | 1526 | static void __exit bfin_spi_exit(void) |
a5f6abd4 | 1527 | { |
138f97cd | 1528 | platform_driver_unregister(&bfin_spi_driver); |
a5f6abd4 | 1529 | } |
138f97cd | 1530 | module_exit(bfin_spi_exit); |