projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
TTY: switch tty_flip_buffer_push
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
1da177e4
LT		 13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
1da177e4
LT		 18
19#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20#define SUPPORT_SYSRQ
21#endif
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
1da177e4 29#include <linux/delay.h>
d052d1be 30#include <linux/platform_device.h>
1da177e4 31#include <linux/tty.h>
cd3ecad1 32#include <linux/ratelimit.h>
1da177e4
LT		 33#include <linux/tty_flip.h>
34#include <linux/serial_reg.h>
35#include <linux/serial_core.h>
36#include <linux/serial.h>
37#include <linux/serial_8250.h>
78512ece 38#include <linux/nmi.h>
f392ecfa 39#include <linux/mutex.h>
5a0e3ad6 40#include <linux/slab.h>
6816383a
PG		 41#ifdef CONFIG_SPARC
42#include <linux/sunserialcore.h>
43#endif
1da177e4
LT		 44
45#include <asm/io.h>
46#include <asm/irq.h>
47
48#include "8250.h"
49
50/*
51 * Configuration:
40663cc7 52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 53 * is unsafe when used on edge-triggered interrupts.
54 */
408b664a 55static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 56
a61c2d78
DJ		 57static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
58
8440838b
DM		 59static struct uart_driver serial8250_reg;
60
61static int serial_index(struct uart_port *port)
62{
63 return (serial8250_reg.minor - 64) + port->line;
64}
65
d41a4b51
CE		 66static unsigned int skip_txen_test; /* force skip of txen test at init time */
67
1da177e4
LT		 68/*
69 * Debugging.
70 */
71#if 0
72#define DEBUG_AUTOCONF(fmt...) printk(fmt)
73#else
74#define DEBUG_AUTOCONF(fmt...) do { } while (0)
75#endif
76
77#if 0
78#define DEBUG_INTR(fmt...) printk(fmt)
79#else
80#define DEBUG_INTR(fmt...) do { } while (0)
81#endif
82
e7328ae1 83#define PASS_LIMIT 512
1da177e4 84
bca47613
DH		 85#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
86
87
1da177e4
LT		 88#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
89#define CONFIG_SERIAL_DETECT_IRQ 1
90#endif
1da177e4
LT		 91#ifdef CONFIG_SERIAL_8250_MANY_PORTS
92#define CONFIG_SERIAL_MANY_PORTS 1
93#endif
94
95/*
96 * HUB6 is always on. This will be removed once the header
97 * files have been cleaned.
98 */
99#define CONFIG_HUB6 1
100
a4ed1e41 101#include <asm/serial.h>
1da177e4
LT		 102/*
103 * SERIAL_PORT_DFNS tells us about built-in ports that have no
104 * standard enumeration mechanism. Platforms that can find all
105 * serial ports via mechanisms like ACPI or PCI need not supply it.
106 */
107#ifndef SERIAL_PORT_DFNS
108#define SERIAL_PORT_DFNS
109#endif
110
cb3592be 111static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 112 SERIAL_PORT_DFNS /* defined in asm/serial.h */
113};
114
026d02a2 115#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 116
117#ifdef CONFIG_SERIAL_8250_RSA
118
119#define PORT_RSA_MAX 4
120static unsigned long probe_rsa[PORT_RSA_MAX];
121static unsigned int probe_rsa_count;
122#endif /* CONFIG_SERIAL_8250_RSA */
123
1da177e4 124struct irq_info {
25db8ad5
AC		 125 struct hlist_node node;
126 int irq;
127 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 128 struct list_head *head;
129};
130
25db8ad5
AC		 131#define NR_IRQ_HASH 32 /* Can be adjusted later */
132static struct hlist_head irq_lists[NR_IRQ_HASH];
133static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 134
135/*
136 * Here we define the default xmit fifo size used for each type of UART.
137 */
138static const struct serial8250_config uart_config[] = {
139 [PORT_UNKNOWN] = {
140 .name = "unknown",
141 .fifo_size = 1,
142 .tx_loadsz = 1,
143 },
144 [PORT_8250] = {
145 .name = "8250",
146 .fifo_size = 1,
147 .tx_loadsz = 1,
148 },
149 [PORT_16450] = {
150 .name = "16450",
151 .fifo_size = 1,
152 .tx_loadsz = 1,
153 },
154 [PORT_16550] = {
155 .name = "16550",
156 .fifo_size = 1,
157 .tx_loadsz = 1,
158 },
159 [PORT_16550A] = {
160 .name = "16550A",
161 .fifo_size = 16,
162 .tx_loadsz = 16,
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO,
165 },
166 [PORT_CIRRUS] = {
167 .name = "Cirrus",
168 .fifo_size = 1,
169 .tx_loadsz = 1,
170 },
171 [PORT_16650] = {
172 .name = "ST16650",
173 .fifo_size = 1,
174 .tx_loadsz = 1,
175 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
176 },
177 [PORT_16650V2] = {
178 .name = "ST16650V2",
179 .fifo_size = 32,
180 .tx_loadsz = 16,
181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
182 UART_FCR_T_TRIG_00,
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
184 },
185 [PORT_16750] = {
186 .name = "TI16750",
187 .fifo_size = 64,
188 .tx_loadsz = 64,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
190 UART_FCR7_64BYTE,
191 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
192 },
193 [PORT_STARTECH] = {
194 .name = "Startech",
195 .fifo_size = 1,
196 .tx_loadsz = 1,
197 },
198 [PORT_16C950] = {
199 .name = "16C950/954",
200 .fifo_size = 128,
201 .tx_loadsz = 128,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
d0694e2a
PM		 203 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
1da177e4
LT		 205 },
206 [PORT_16654] = {
207 .name = "ST16654",
208 .fifo_size = 64,
209 .tx_loadsz = 32,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
211 UART_FCR_T_TRIG_10,
212 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
213 },
214 [PORT_16850] = {
215 .name = "XR16850",
216 .fifo_size = 128,
217 .tx_loadsz = 128,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
220 },
221 [PORT_RSA] = {
222 .name = "RSA",
223 .fifo_size = 2048,
224 .tx_loadsz = 2048,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
226 .flags = UART_CAP_FIFO,
227 },
228 [PORT_NS16550A] = {
229 .name = "NS16550A",
230 .fifo_size = 16,
231 .tx_loadsz = 16,
232 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
233 .flags = UART_CAP_FIFO | UART_NATSEMI,
234 },
235 [PORT_XSCALE] = {
236 .name = "XScale",
237 .fifo_size = 32,
238 .tx_loadsz = 32,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
4539c24f 240 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
1da177e4 241 },
6b06f191
DD		 242 [PORT_OCTEON] = {
243 .name = "OCTEON",
244 .fifo_size = 64,
245 .tx_loadsz = 64,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 247 .flags = UART_CAP_FIFO,
248 },
08e0992f
FF		 249 [PORT_AR7] = {
250 .name = "AR7",
251 .fifo_size = 16,
252 .tx_loadsz = 16,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
254 .flags = UART_CAP_FIFO | UART_CAP_AFE,
255 },
235dae5d
PL		 256 [PORT_U6_16550A] = {
257 .name = "U6_16550A",
258 .fifo_size = 64,
259 .tx_loadsz = 64,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
261 .flags = UART_CAP_FIFO | UART_CAP_AFE,
262 },
4539c24f
SW		 263 [PORT_TEGRA] = {
264 .name = "Tegra",
265 .fifo_size = 32,
266 .tx_loadsz = 8,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
268 UART_FCR_T_TRIG_01,
269 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
270 },
06315348
SH		 271 [PORT_XR17D15X] = {
272 .name = "XR17D15X",
273 .fifo_size = 64,
274 .tx_loadsz = 64,
275 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
81db0772
MS		 276 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
277 UART_CAP_SLEEP,
06315348 278 },
dc96efb7
MS		 279 [PORT_XR17V35X] = {
280 .name = "XR17V35X",
281 .fifo_size = 256,
282 .tx_loadsz = 256,
283 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
284 UART_FCR_T_TRIG_11,
285 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
286 UART_CAP_SLEEP,
287 },
7a514596
RS		 288 [PORT_LPC3220] = {
289 .name = "LPC3220",
290 .fifo_size = 64,
291 .tx_loadsz = 32,
292 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
293 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
294 .flags = UART_CAP_FIFO,
295 },
65ecc9c0
SY		 296 [PORT_8250_CIR] = {
297 .name = "CIR port"
298 }
1da177e4
LT		 299};
300
cc419fa0 301/* Uart divisor latch read */
e8155629 302static int default_serial_dl_read(struct uart_8250_port *up)
cc419fa0
MD		 303{
304 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
305}
306
307/* Uart divisor latch write */
e8155629 308static void default_serial_dl_write(struct uart_8250_port *up, int value)
cc419fa0
MD		 309{
310 serial_out(up, UART_DLL, value & 0xff);
311 serial_out(up, UART_DLM, value >> 8 & 0xff);
312}
313
6b416031 314#ifdef CONFIG_MIPS_ALCHEMY
21c614a7
PA		 315
316/* Au1x00 UART hardware has a weird register layout */
317static const u8 au_io_in_map[] = {
318 [UART_RX] = 0,
319 [UART_IER] = 2,
320 [UART_IIR] = 3,
321 [UART_LCR] = 5,
322 [UART_MCR] = 6,
323 [UART_LSR] = 7,
324 [UART_MSR] = 8,
325};
326
327static const u8 au_io_out_map[] = {
328 [UART_TX] = 1,
329 [UART_IER] = 2,
330 [UART_FCR] = 4,
331 [UART_LCR] = 5,
332 [UART_MCR] = 6,
333};
334
6b416031 335static unsigned int au_serial_in(struct uart_port *p, int offset)
21c614a7 336{
6b416031
MD		 337 offset = au_io_in_map[offset] << p->regshift;
338 return __raw_readl(p->membase + offset);
21c614a7
PA		 339}
340
6b416031 341static void au_serial_out(struct uart_port *p, int offset, int value)
21c614a7 342{
6b416031
MD		 343 offset = au_io_out_map[offset] << p->regshift;
344 __raw_writel(value, p->membase + offset);
345}
346
347/* Au1x00 haven't got a standard divisor latch */
348static int au_serial_dl_read(struct uart_8250_port *up)
349{
350 return __raw_readl(up->port.membase + 0x28);
351}
352
353static void au_serial_dl_write(struct uart_8250_port *up, int value)
354{
355 __raw_writel(value, up->port.membase + 0x28);
21c614a7
PA		 356}
357
6b416031
MD		 358#endif
359
7d6a07d1 360static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 361{
e8155629 362 offset = offset << p->regshift;
7d6a07d1
DD		 363 outb(p->hub6 - 1 + offset, p->iobase);
364 return inb(p->iobase + 1);
365}
1da177e4 366
7d6a07d1
DD		 367static void hub6_serial_out(struct uart_port *p, int offset, int value)
368{
e8155629 369 offset = offset << p->regshift;
7d6a07d1
DD		 370 outb(p->hub6 - 1 + offset, p->iobase);
371 outb(value, p->iobase + 1);
372}
1da177e4 373
7d6a07d1
DD		 374static unsigned int mem_serial_in(struct uart_port *p, int offset)
375{
e8155629 376 offset = offset << p->regshift;
7d6a07d1
DD		 377 return readb(p->membase + offset);
378}
1da177e4 379
7d6a07d1
DD		 380static void mem_serial_out(struct uart_port *p, int offset, int value)
381{
e8155629 382 offset = offset << p->regshift;
7d6a07d1
DD		 383 writeb(value, p->membase + offset);
384}
385
386static void mem32_serial_out(struct uart_port *p, int offset, int value)
387{
e8155629 388 offset = offset << p->regshift;
7d6a07d1
DD		 389 writel(value, p->membase + offset);
390}
391
392static unsigned int mem32_serial_in(struct uart_port *p, int offset)
393{
e8155629 394 offset = offset << p->regshift;
7d6a07d1
DD		 395 return readl(p->membase + offset);
396}
1da177e4 397
7d6a07d1
DD		 398static unsigned int io_serial_in(struct uart_port *p, int offset)
399{
e8155629 400 offset = offset << p->regshift;
7d6a07d1
DD		 401 return inb(p->iobase + offset);
402}
403
404static void io_serial_out(struct uart_port *p, int offset, int value)
405{
e8155629 406 offset = offset << p->regshift;
7d6a07d1
DD		 407 outb(value, p->iobase + offset);
408}
409
583d28e9 410static int serial8250_default_handle_irq(struct uart_port *port);
dc96efb7 411static int exar_handle_irq(struct uart_port *port);
583d28e9 412
7d6a07d1
DD		 413static void set_io_from_upio(struct uart_port *p)
414{
49d5741b
JI		 415 struct uart_8250_port *up =
416 container_of(p, struct uart_8250_port, port);
cc419fa0 417
e8155629
MD		 418 up->dl_read = default_serial_dl_read;
419 up->dl_write = default_serial_dl_write;
cc419fa0 420
7d6a07d1 421 switch (p->iotype) {
1da177e4 422 case UPIO_HUB6:
7d6a07d1
DD		 423 p->serial_in = hub6_serial_in;
424 p->serial_out = hub6_serial_out;
1da177e4
LT		 425 break;
426
427 case UPIO_MEM:
7d6a07d1
DD		 428 p->serial_in = mem_serial_in;
429 p->serial_out = mem_serial_out;
1da177e4
LT		 430 break;
431
432 case UPIO_MEM32:
7d6a07d1
DD		 433 p->serial_in = mem32_serial_in;
434 p->serial_out = mem32_serial_out;
1da177e4
LT		 435 break;
436
6b416031 437#ifdef CONFIG_MIPS_ALCHEMY
21c614a7 438 case UPIO_AU:
7d6a07d1
DD		 439 p->serial_in = au_serial_in;
440 p->serial_out = au_serial_out;
6b416031
MD		 441 up->dl_read = au_serial_dl_read;
442 up->dl_write = au_serial_dl_write;
21c614a7 443 break;
6b416031 444#endif
12bf3f24 445
1da177e4 446 default:
7d6a07d1
DD		 447 p->serial_in = io_serial_in;
448 p->serial_out = io_serial_out;
449 break;
1da177e4 450 }
b8e7e40a
AC		 451 /* Remember loaded iotype */
452 up->cur_iotype = p->iotype;
583d28e9 453 p->handle_irq = serial8250_default_handle_irq;
1da177e4
LT		 454}
455
40b36daa 456static void
55e4016d 457serial_port_out_sync(struct uart_port *p, int offset, int value)
40b36daa 458{
7d6a07d1 459 switch (p->iotype) {
40b36daa
AW		 460 case UPIO_MEM:
461 case UPIO_MEM32:
40b36daa 462 case UPIO_AU:
7d6a07d1
DD		 463 p->serial_out(p, offset, value);
464 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 465 break;
466 default:
7d6a07d1 467 p->serial_out(p, offset, value);
40b36daa
AW		 468 }
469}
470
1da177e4
LT		 471/*
472 * For the 16C950
473 */
474static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
475{
476 serial_out(up, UART_SCR, offset);
477 serial_out(up, UART_ICR, value);
478}
479
480static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
481{
482 unsigned int value;
483
484 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
485 serial_out(up, UART_SCR, offset);
486 value = serial_in(up, UART_ICR);
487 serial_icr_write(up, UART_ACR, up->acr);
488
489 return value;
490}
491
492/*
493 * FIFO support.
494 */
b5d674ab 495static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 496{
497 if (p->capabilities & UART_CAP_FIFO) {
0acf519f
PG		 498 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
499 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
1da177e4 500 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0acf519f 501 serial_out(p, UART_FCR, 0);
1da177e4
LT		 502 }
503}
504
0ad372b9
SM		 505void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
506{
507 unsigned char fcr;
508
509 serial8250_clear_fifos(p);
510 fcr = uart_config[p->port.type].fcr;
511 serial_out(p, UART_FCR, fcr);
512}
513EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
514
1da177e4
LT		 515/*
516 * IER sleep support. UARTs which have EFRs need the "extended
517 * capability" bit enabled. Note that on XR16C850s, we need to
518 * reset LCR to write to IER.
519 */
b5d674ab 520static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4 521{
dc96efb7
MS		 522 /*
523 * Exar UARTs have a SLEEP register that enables or disables
524 * each UART to enter sleep mode separately. On the XR17V35x the
525 * register is accessible to each UART at the UART_EXAR_SLEEP
526 * offset but the UART channel may only write to the corresponding
527 * bit.
528 */
81db0772
MS		 529 if ((p->port.type == PORT_XR17V35X) ||
530 (p->port.type == PORT_XR17D15X)) {
dc96efb7
MS		 531 serial_out(p, UART_EXAR_SLEEP, 0xff);
532 return;
533 }
534
1da177e4
LT		 535 if (p->capabilities & UART_CAP_SLEEP) {
536 if (p->capabilities & UART_CAP_EFR) {
0acf519f
PG		 537 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
538 serial_out(p, UART_EFR, UART_EFR_ECB);
539 serial_out(p, UART_LCR, 0);
1da177e4 540 }
0acf519f 541 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
1da177e4 542 if (p->capabilities & UART_CAP_EFR) {
0acf519f
PG		 543 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
544 serial_out(p, UART_EFR, 0);
545 serial_out(p, UART_LCR, 0);
1da177e4
LT		 546 }
547 }
548}
549
550#ifdef CONFIG_SERIAL_8250_RSA
551/*
552 * Attempts to turn on the RSA FIFO. Returns zero on failure.
553 * We set the port uart clock rate if we succeed.
554 */
555static int __enable_rsa(struct uart_8250_port *up)
556{
557 unsigned char mode;
558 int result;
559
0acf519f 560 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 561 result = mode & UART_RSA_MSR_FIFO;
562
563 if (!result) {
0acf519f
PG		 564 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
565 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 566 result = mode & UART_RSA_MSR_FIFO;
567 }
568
569 if (result)
570 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
571
572 return result;
573}
574
575static void enable_rsa(struct uart_8250_port *up)
576{
577 if (up->port.type == PORT_RSA) {
578 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
579 spin_lock_irq(&up->port.lock);
580 __enable_rsa(up);
581 spin_unlock_irq(&up->port.lock);
582 }
583 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
0acf519f 584 serial_out(up, UART_RSA_FRR, 0);
1da177e4
LT		 585 }
586}
587
588/*
589 * Attempts to turn off the RSA FIFO. Returns zero on failure.
590 * It is unknown why interrupts were disabled in here. However,
591 * the caller is expected to preserve this behaviour by grabbing
592 * the spinlock before calling this function.
593 */
594static void disable_rsa(struct uart_8250_port *up)
595{
596 unsigned char mode;
597 int result;
598
599 if (up->port.type == PORT_RSA &&
600 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
601 spin_lock_irq(&up->port.lock);
602
0acf519f 603 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 604 result = !(mode & UART_RSA_MSR_FIFO);
605
606 if (!result) {
0acf519f
PG		 607 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
608 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 609 result = !(mode & UART_RSA_MSR_FIFO);
610 }
611
612 if (result)
613 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
614 spin_unlock_irq(&up->port.lock);
615 }
616}
617#endif /* CONFIG_SERIAL_8250_RSA */
618
619/*
620 * This is a quickie test to see how big the FIFO is.
621 * It doesn't work at all the time, more's the pity.
622 */
623static int size_fifo(struct uart_8250_port *up)
624{
b32b19b8
JAH		 625 unsigned char old_fcr, old_mcr, old_lcr;
626 unsigned short old_dl;
1da177e4
LT		 627 int count;
628
0acf519f
PG		 629 old_lcr = serial_in(up, UART_LCR);
630 serial_out(up, UART_LCR, 0);
631 old_fcr = serial_in(up, UART_FCR);
632 old_mcr = serial_in(up, UART_MCR);
633 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1da177e4 634 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0acf519f
PG		 635 serial_out(up, UART_MCR, UART_MCR_LOOP);
636 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8
JAH		 637 old_dl = serial_dl_read(up);
638 serial_dl_write(up, 0x0001);
0acf519f 639 serial_out(up, UART_LCR, 0x03);
1da177e4 640 for (count = 0; count < 256; count++)
0acf519f 641 serial_out(up, UART_TX, count);
1da177e4 642 mdelay(20);/* FIXME - schedule_timeout */
0acf519f 643 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
1da177e4 644 (count < 256); count++)
0acf519f
PG		 645 serial_in(up, UART_RX);
646 serial_out(up, UART_FCR, old_fcr);
647 serial_out(up, UART_MCR, old_mcr);
648 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8 649 serial_dl_write(up, old_dl);
0acf519f 650 serial_out(up, UART_LCR, old_lcr);
1da177e4
LT		 651
652 return count;
653}
654
655/*
656 * Read UART ID using the divisor method - set DLL and DLM to zero
657 * and the revision will be in DLL and device type in DLM. We
658 * preserve the device state across this.
659 */
660static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
661{
662 unsigned char old_dll, old_dlm, old_lcr;
663 unsigned int id;
664
0acf519f
PG		 665 old_lcr = serial_in(p, UART_LCR);
666 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4 667
0acf519f
PG		 668 old_dll = serial_in(p, UART_DLL);
669 old_dlm = serial_in(p, UART_DLM);
1da177e4 670
0acf519f
PG		 671 serial_out(p, UART_DLL, 0);
672 serial_out(p, UART_DLM, 0);
1da177e4 673
0acf519f 674 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
1da177e4 675
0acf519f
PG		 676 serial_out(p, UART_DLL, old_dll);
677 serial_out(p, UART_DLM, old_dlm);
678 serial_out(p, UART_LCR, old_lcr);
1da177e4
LT		 679
680 return id;
681}
682
683/*
684 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
685 * When this function is called we know it is at least a StarTech
686 * 16650 V2, but it might be one of several StarTech UARTs, or one of
687 * its clones. (We treat the broken original StarTech 16650 V1 as a
688 * 16550, and why not? Startech doesn't seem to even acknowledge its
689 * existence.)
bd71c182 690 *
1da177e4
LT		 691 * What evil have men's minds wrought...
692 */
693static void autoconfig_has_efr(struct uart_8250_port *up)
694{
695 unsigned int id1, id2, id3, rev;
696
697 /*
698 * Everything with an EFR has SLEEP
699 */
700 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
701
702 /*
703 * First we check to see if it's an Oxford Semiconductor UART.
704 *
705 * If we have to do this here because some non-National
706 * Semiconductor clone chips lock up if you try writing to the
707 * LSR register (which serial_icr_read does)
708 */
709
710 /*
711 * Check for Oxford Semiconductor 16C950.
712 *
713 * EFR [4] must be set else this test fails.
714 *
715 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
716 * claims that it's needed for 952 dual UART's (which are not
717 * recommended for new designs).
718 */
719 up->acr = 0;
662b083a 720 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 721 serial_out(up, UART_EFR, UART_EFR_ECB);
722 serial_out(up, UART_LCR, 0x00);
723 id1 = serial_icr_read(up, UART_ID1);
724 id2 = serial_icr_read(up, UART_ID2);
725 id3 = serial_icr_read(up, UART_ID3);
726 rev = serial_icr_read(up, UART_REV);
727
728 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
729
730 if (id1 == 0x16 && id2 == 0xC9 &&
731 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
732 up->port.type = PORT_16C950;
4ba5e35d
RK		 733
734 /*
735 * Enable work around for the Oxford Semiconductor 952 rev B
736 * chip which causes it to seriously miscalculate baud rates
737 * when DLL is 0.
738 */
739 if (id3 == 0x52 && rev == 0x01)
740 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 741 return;
742 }
bd71c182 743
1da177e4
LT		 744 /*
745 * We check for a XR16C850 by setting DLL and DLM to 0, and then
746 * reading back DLL and DLM. The chip type depends on the DLM
747 * value read back:
748 * 0x10 - XR16C850 and the DLL contains the chip revision.
749 * 0x12 - XR16C2850.
750 * 0x14 - XR16C854.
751 */
752 id1 = autoconfig_read_divisor_id(up);
753 DEBUG_AUTOCONF("850id=%04x ", id1);
754
755 id2 = id1 >> 8;
756 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 757 up->port.type = PORT_16850;
758 return;
759 }
760
761 /*
762 * It wasn't an XR16C850.
763 *
764 * We distinguish between the '654 and the '650 by counting
765 * how many bytes are in the FIFO. I'm using this for now,
766 * since that's the technique that was sent to me in the
767 * serial driver update, but I'm not convinced this works.
768 * I've had problems doing this in the past. -TYT
769 */
770 if (size_fifo(up) == 64)
771 up->port.type = PORT_16654;
772 else
773 up->port.type = PORT_16650V2;
774}
775
776/*
777 * We detected a chip without a FIFO. Only two fall into
778 * this category - the original 8250 and the 16450. The
779 * 16450 has a scratch register (accessible with LCR=0)
780 */
781static void autoconfig_8250(struct uart_8250_port *up)
782{
783 unsigned char scratch, status1, status2;
784
785 up->port.type = PORT_8250;
786
787 scratch = serial_in(up, UART_SCR);
0acf519f 788 serial_out(up, UART_SCR, 0xa5);
1da177e4 789 status1 = serial_in(up, UART_SCR);
0acf519f 790 serial_out(up, UART_SCR, 0x5a);
1da177e4 791 status2 = serial_in(up, UART_SCR);
0acf519f 792 serial_out(up, UART_SCR, scratch);
1da177e4
LT		 793
794 if (status1 == 0xa5 && status2 == 0x5a)
795 up->port.type = PORT_16450;
796}
797
798static int broken_efr(struct uart_8250_port *up)
799{
800 /*
801 * Exar ST16C2550 "A2" devices incorrectly detect as
802 * having an EFR, and report an ID of 0x0201. See
631dd1a8 803 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1da177e4
LT		 804 */
805 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
806 return 1;
807
808 return 0;
809}
810
0d0389e5
YK		 811static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
812{
813 unsigned char status;
814
815 status = serial_in(up, 0x04); /* EXCR2 */
816#define PRESL(x) ((x) & 0x30)
817 if (PRESL(status) == 0x10) {
818 /* already in high speed mode */
819 return 0;
820 } else {
821 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
822 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
0acf519f 823 serial_out(up, 0x04, status);
0d0389e5
YK		 824 }
825 return 1;
826}
827
1da177e4
LT		 828/*
829 * We know that the chip has FIFOs. Does it have an EFR? The
830 * EFR is located in the same register position as the IIR and
831 * we know the top two bits of the IIR are currently set. The
832 * EFR should contain zero. Try to read the EFR.
833 */
834static void autoconfig_16550a(struct uart_8250_port *up)
835{
836 unsigned char status1, status2;
837 unsigned int iersave;
838
839 up->port.type = PORT_16550A;
840 up->capabilities |= UART_CAP_FIFO;
841
dc96efb7
MS		 842 /*
843 * XR17V35x UARTs have an extra divisor register, DLD
844 * that gets enabled with when DLAB is set which will
845 * cause the device to incorrectly match and assign
846 * port type to PORT_16650. The EFR for this UART is
847 * found at offset 0x09. Instead check the Deice ID (DVID)
848 * register for a 2, 4 or 8 port UART.
849 */
b7a7e14f
MS		 850 if (up->port.flags & UPF_EXAR_EFR) {
851 status1 = serial_in(up, UART_EXAR_DVID);
852 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
dc96efb7
MS		 853 DEBUG_AUTOCONF("Exar XR17V35x ");
854 up->port.type = PORT_XR17V35X;
855 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
856 UART_CAP_SLEEP;
857
858 return;
859 }
860
861 }
862
1da177e4
LT		 863 /*
864 * Check for presence of the EFR when DLAB is set.
865 * Only ST16C650V1 UARTs pass this test.
866 */
0acf519f 867 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4 868 if (serial_in(up, UART_EFR) == 0) {
0acf519f 869 serial_out(up, UART_EFR, 0xA8);
1da177e4
LT		 870 if (serial_in(up, UART_EFR) != 0) {
871 DEBUG_AUTOCONF("EFRv1 ");
872 up->port.type = PORT_16650;
873 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
874 } else {
875 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
876 }
0acf519f 877 serial_out(up, UART_EFR, 0);
1da177e4
LT		 878 return;
879 }
880
881 /*
882 * Maybe it requires 0xbf to be written to the LCR.
883 * (other ST16C650V2 UARTs, TI16C752A, etc)
884 */
0acf519f 885 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 886 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
887 DEBUG_AUTOCONF("EFRv2 ");
888 autoconfig_has_efr(up);
889 return;
890 }
891
892 /*
893 * Check for a National Semiconductor SuperIO chip.
894 * Attempt to switch to bank 2, read the value of the LOOP bit
895 * from EXCR1. Switch back to bank 0, change it in MCR. Then
896 * switch back to bank 2, read it from EXCR1 again and check
897 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4 898 */
0acf519f 899 serial_out(up, UART_LCR, 0);
1da177e4 900 status1 = serial_in(up, UART_MCR);
0acf519f 901 serial_out(up, UART_LCR, 0xE0);
1da177e4
LT		 902 status2 = serial_in(up, 0x02); /* EXCR1 */
903
904 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
0acf519f
PG		 905 serial_out(up, UART_LCR, 0);
906 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
907 serial_out(up, UART_LCR, 0xE0);
1da177e4 908 status2 = serial_in(up, 0x02); /* EXCR1 */
0acf519f
PG		 909 serial_out(up, UART_LCR, 0);
910 serial_out(up, UART_MCR, status1);
1da177e4
LT		 911
912 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 913 unsigned short quot;
914
0acf519f 915 serial_out(up, UART_LCR, 0xE0);
857dde2e 916
b32b19b8 917 quot = serial_dl_read(up);
857dde2e
DW		 918 quot <<= 3;
919
0d0389e5
YK		 920 if (ns16550a_goto_highspeed(up))
921 serial_dl_write(up, quot);
857dde2e 922
0acf519f 923 serial_out(up, UART_LCR, 0);
1da177e4 924
857dde2e 925 up->port.uartclk = 921600*16;
1da177e4
LT		 926 up->port.type = PORT_NS16550A;
927 up->capabilities |= UART_NATSEMI;
928 return;
929 }
930 }
931
932 /*
933 * No EFR. Try to detect a TI16750, which only sets bit 5 of
934 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
935 * Try setting it with and without DLAB set. Cheap clones
936 * set bit 5 without DLAB set.
937 */
0acf519f
PG		 938 serial_out(up, UART_LCR, 0);
939 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1da177e4 940 status1 = serial_in(up, UART_IIR) >> 5;
0acf519f
PG		 941 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
942 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
943 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1da177e4 944 status2 = serial_in(up, UART_IIR) >> 5;
0acf519f
PG		 945 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
946 serial_out(up, UART_LCR, 0);
1da177e4
LT		 947
948 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
949
950 if (status1 == 6 && status2 == 7) {
951 up->port.type = PORT_16750;
952 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
953 return;
954 }
955
956 /*
957 * Try writing and reading the UART_IER_UUE bit (b6).
958 * If it works, this is probably one of the Xscale platform's
959 * internal UARTs.
960 * We're going to explicitly set the UUE bit to 0 before
961 * trying to write and read a 1 just to make sure it's not
962 * already a 1 and maybe locked there before we even start start.
963 */
964 iersave = serial_in(up, UART_IER);
0acf519f 965 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1da177e4
LT		 966 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
967 /*
968 * OK it's in a known zero state, try writing and reading
969 * without disturbing the current state of the other bits.
970 */
0acf519f 971 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1da177e4
LT		 972 if (serial_in(up, UART_IER) & UART_IER_UUE) {
973 /*
974 * It's an Xscale.
975 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
976 */
977 DEBUG_AUTOCONF("Xscale ");
978 up->port.type = PORT_XSCALE;
5568181f 979 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1da177e4
LT		 980 return;
981 }
982 } else {
983 /*
984 * If we got here we couldn't force the IER_UUE bit to 0.
985 * Log it and continue.
986 */
987 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
988 }
0acf519f 989 serial_out(up, UART_IER, iersave);
235dae5d 990
06315348
SH		 991 /*
992 * Exar uarts have EFR in a weird location
993 */
994 if (up->port.flags & UPF_EXAR_EFR) {
81db0772 995 DEBUG_AUTOCONF("Exar XR17D15x ");
06315348 996 up->port.type = PORT_XR17D15X;
81db0772
MS		 997 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
998 UART_CAP_SLEEP;
999
1000 return;
06315348
SH		 1001 }
1002
235dae5d
PL		 1003 /*
1004 * We distinguish between 16550A and U6 16550A by counting
1005 * how many bytes are in the FIFO.
1006 */
1007 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1008 up->port.type = PORT_U6_16550A;
1009 up->capabilities |= UART_CAP_AFE;
1010 }
1da177e4
LT		 1011}
1012
1013/*
1014 * This routine is called by rs_init() to initialize a specific serial
1015 * port. It determines what type of UART chip this serial port is
1016 * using: 8250, 16450, 16550, 16550A. The important question is
1017 * whether or not this UART is a 16550A or not, since this will
1018 * determine whether or not we can use its FIFO features or not.
1019 */
1020static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1021{
1022 unsigned char status1, scratch, scratch2, scratch3;
1023 unsigned char save_lcr, save_mcr;
dfe42443 1024 struct uart_port *port = &up->port;
1da177e4 1025 unsigned long flags;
bd21f551 1026 unsigned int old_capabilities;
1da177e4 1027
dfe42443 1028 if (!port->iobase && !port->mapbase && !port->membase)
1da177e4
LT		 1029 return;
1030
80647b95 1031 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
dfe42443 1032 serial_index(port), port->iobase, port->membase);
1da177e4
LT		 1033
1034 /*
1035 * We really do need global IRQs disabled here - we're going to
1036 * be frobbing the chips IRQ enable register to see if it exists.
1037 */
dfe42443 1038 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 1039
1040 up->capabilities = 0;
4ba5e35d 1041 up->bugs = 0;
1da177e4 1042
dfe42443 1043 if (!(port->flags & UPF_BUGGY_UART)) {
1da177e4
LT		 1044 /*
1045 * Do a simple existence test first; if we fail this,
1046 * there's no point trying anything else.
bd71c182 1047 *
1da177e4
LT		 1048 * 0x80 is used as a nonsense port to prevent against
1049 * false positives due to ISA bus float. The
1050 * assumption is that 0x80 is a non-existent port;
1051 * which should be safe since include/asm/io.h also
1052 * makes this assumption.
1053 *
1054 * Note: this is safe as long as MCR bit 4 is clear
1055 * and the device is in "PC" mode.
1056 */
0acf519f
PG		 1057 scratch = serial_in(up, UART_IER);
1058 serial_out(up, UART_IER, 0);
1da177e4
LT		 1059#ifdef __i386__
1060 outb(0xff, 0x080);
1061#endif
48212008
TH		 1062 /*
1063 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1064 * 16C754B) allow only to modify them if an EFR bit is set.
1065 */
0acf519f
PG		 1066 scratch2 = serial_in(up, UART_IER) & 0x0f;
1067 serial_out(up, UART_IER, 0x0F);
1da177e4
LT		 1068#ifdef __i386__
1069 outb(0, 0x080);
1070#endif
0acf519f
PG		 1071 scratch3 = serial_in(up, UART_IER) & 0x0f;
1072 serial_out(up, UART_IER, scratch);
1da177e4
LT		 1073 if (scratch2 != 0 || scratch3 != 0x0F) {
1074 /*
1075 * We failed; there's nothing here
1076 */
bd21f551 1077 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1078 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1079 scratch2, scratch3);
1080 goto out;
1081 }
1082 }
1083
1084 save_mcr = serial_in(up, UART_MCR);
1085 save_lcr = serial_in(up, UART_LCR);
1086
bd71c182 1087 /*
1da177e4
LT		 1088 * Check to see if a UART is really there. Certain broken
1089 * internal modems based on the Rockwell chipset fail this
1090 * test, because they apparently don't implement the loopback
1091 * test mode. So this test is skipped on the COM 1 through
1092 * COM 4 ports. This *should* be safe, since no board
1093 * manufacturer would be stupid enough to design a board
1094 * that conflicts with COM 1-4 --- we hope!
1095 */
dfe42443 1096 if (!(port->flags & UPF_SKIP_TEST)) {
0acf519f
PG		 1097 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1098 status1 = serial_in(up, UART_MSR) & 0xF0;
1099 serial_out(up, UART_MCR, save_mcr);
1da177e4 1100 if (status1 != 0x90) {
bd21f551 1101 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1102 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1103 status1);
1104 goto out;
1105 }
1106 }
1107
1108 /*
1109 * We're pretty sure there's a port here. Lets find out what
1110 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1111 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1112 * determines what we test for next.
1113 *
1114 * We also initialise the EFR (if any) to zero for later. The
1115 * EFR occupies the same register location as the FCR and IIR.
1116 */
0acf519f
PG		 1117 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1118 serial_out(up, UART_EFR, 0);
1119 serial_out(up, UART_LCR, 0);
1da177e4 1120
0acf519f 1121 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1da177e4
LT		 1122 scratch = serial_in(up, UART_IIR) >> 6;
1123
1da177e4
LT		 1124 switch (scratch) {
1125 case 0:
1126 autoconfig_8250(up);
1127 break;
1128 case 1:
dfe42443 1129 port->type = PORT_UNKNOWN;
1da177e4
LT		 1130 break;
1131 case 2:
dfe42443 1132 port->type = PORT_16550;
1da177e4
LT		 1133 break;
1134 case 3:
1135 autoconfig_16550a(up);
1136 break;
1137 }
1138
1139#ifdef CONFIG_SERIAL_8250_RSA
1140 /*
1141 * Only probe for RSA ports if we got the region.
1142 */
dfe42443 1143 if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1da177e4
LT		 1144 int i;
1145
1146 for (i = 0 ; i < probe_rsa_count; ++i) {
dfe42443
PG		 1147 if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1148 port->type = PORT_RSA;
1da177e4
LT		 1149 break;
1150 }
1151 }
1152 }
1153#endif
21c614a7 1154
0acf519f 1155 serial_out(up, UART_LCR, save_lcr);
1da177e4 1156
dfe42443 1157 port->fifosize = uart_config[up->port.type].fifo_size;
bd21f551 1158 old_capabilities = up->capabilities;
dfe42443
PG		 1159 up->capabilities = uart_config[port->type].flags;
1160 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1da177e4 1161
dfe42443 1162 if (port->type == PORT_UNKNOWN)
bd21f551 1163 goto out_lock;
1da177e4
LT		 1164
1165 /*
1166 * Reset the UART.
1167 */
1168#ifdef CONFIG_SERIAL_8250_RSA
dfe42443 1169 if (port->type == PORT_RSA)
0acf519f 1170 serial_out(up, UART_RSA_FRR, 0);
1da177e4 1171#endif
0acf519f 1172 serial_out(up, UART_MCR, save_mcr);
1da177e4 1173 serial8250_clear_fifos(up);
40b36daa 1174 serial_in(up, UART_RX);
5c8c755c 1175 if (up->capabilities & UART_CAP_UUE)
0acf519f 1176 serial_out(up, UART_IER, UART_IER_UUE);
5c8c755c 1177 else
0acf519f 1178 serial_out(up, UART_IER, 0);
1da177e4 1179
bd21f551 1180out_lock:
dfe42443 1181 spin_unlock_irqrestore(&port->lock, flags);
bd21f551
FL		 1182 if (up->capabilities != old_capabilities) {
1183 printk(KERN_WARNING
1184 "ttyS%d: detected caps %08x should be %08x\n",
1185 serial_index(port), old_capabilities,
1186 up->capabilities);
1187 }
1188out:
1189 DEBUG_AUTOCONF("iir=%d ", scratch);
dfe42443 1190 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1da177e4
LT		 1191}
1192
1193static void autoconfig_irq(struct uart_8250_port *up)
1194{
dfe42443 1195 struct uart_port *port = &up->port;
1da177e4
LT		 1196 unsigned char save_mcr, save_ier;
1197 unsigned char save_ICP = 0;
1198 unsigned int ICP = 0;
1199 unsigned long irqs;
1200 int irq;
1201
dfe42443
PG		 1202 if (port->flags & UPF_FOURPORT) {
1203 ICP = (port->iobase & 0xfe0) | 0x1f;
1da177e4
LT		 1204 save_ICP = inb_p(ICP);
1205 outb_p(0x80, ICP);
0d263a26 1206 inb_p(ICP);
1da177e4
LT		 1207 }
1208
1209 /* forget possible initially masked and pending IRQ */
1210 probe_irq_off(probe_irq_on());
0acf519f
PG		 1211 save_mcr = serial_in(up, UART_MCR);
1212 save_ier = serial_in(up, UART_IER);
1213 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1214
1da177e4 1215 irqs = probe_irq_on();
0acf519f 1216 serial_out(up, UART_MCR, 0);
6f803cd0 1217 udelay(10);
dfe42443 1218 if (port->flags & UPF_FOURPORT) {
0acf519f 1219 serial_out(up, UART_MCR,
1da177e4
LT		 1220 UART_MCR_DTR | UART_MCR_RTS);
1221 } else {
0acf519f 1222 serial_out(up, UART_MCR,
1da177e4
LT		 1223 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1224 }
0acf519f 1225 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
0d263a26
PG		 1226 serial_in(up, UART_LSR);
1227 serial_in(up, UART_RX);
1228 serial_in(up, UART_IIR);
1229 serial_in(up, UART_MSR);
0acf519f 1230 serial_out(up, UART_TX, 0xFF);
6f803cd0 1231 udelay(20);
1da177e4
LT		 1232 irq = probe_irq_off(irqs);
1233
0acf519f
PG		 1234 serial_out(up, UART_MCR, save_mcr);
1235 serial_out(up, UART_IER, save_ier);
1da177e4 1236
dfe42443 1237 if (port->flags & UPF_FOURPORT)
1da177e4
LT		 1238 outb_p(save_ICP, ICP);
1239
dfe42443 1240 port->irq = (irq > 0) ? irq : 0;
1da177e4
LT		 1241}
1242
e763b90c
RK		 1243static inline void __stop_tx(struct uart_8250_port *p)
1244{
1245 if (p->ier & UART_IER_THRI) {
1246 p->ier &= ~UART_IER_THRI;
1247 serial_out(p, UART_IER, p->ier);
1248 }
1249}
1250
b129a8cc 1251static void serial8250_stop_tx(struct uart_port *port)
1da177e4 1252{
49d5741b
JI		 1253 struct uart_8250_port *up =
1254 container_of(port, struct uart_8250_port, port);
1da177e4 1255
e763b90c 1256 __stop_tx(up);
1da177e4
LT		 1257
1258 /*
e763b90c 1259 * We really want to stop the transmitter from sending.
1da177e4 1260 */
dfe42443 1261 if (port->type == PORT_16C950) {
1da177e4
LT		 1262 up->acr |= UART_ACR_TXDIS;
1263 serial_icr_write(up, UART_ACR, up->acr);
1264 }
1265}
1266
b129a8cc 1267static void serial8250_start_tx(struct uart_port *port)
1da177e4 1268{
49d5741b
JI		 1269 struct uart_8250_port *up =
1270 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1271
1272 if (!(up->ier & UART_IER_THRI)) {
1273 up->ier |= UART_IER_THRI;
4fd996a1 1274 serial_port_out(port, UART_IER, up->ier);
55d3b282 1275
67f7654e 1276 if (up->bugs & UART_BUG_TXEN) {
68cb4f8e 1277 unsigned char lsr;
55d3b282 1278 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1279 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
a205a56d 1280 if (lsr & UART_LSR_TEMT)
3986fb2b 1281 serial8250_tx_chars(up);
55d3b282 1282 }
1da177e4 1283 }
e763b90c 1284
1da177e4 1285 /*
e763b90c 1286 * Re-enable the transmitter if we disabled it.
1da177e4 1287 */
dfe42443 1288 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1289 up->acr &= ~UART_ACR_TXDIS;
1290 serial_icr_write(up, UART_ACR, up->acr);
1291 }
1292}
1293
1294static void serial8250_stop_rx(struct uart_port *port)
1295{
49d5741b
JI		 1296 struct uart_8250_port *up =
1297 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1298
1299 up->ier &= ~UART_IER_RLSI;
1300 up->port.read_status_mask &= ~UART_LSR_DR;
4fd996a1 1301 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 1302}
1303
1304static void serial8250_enable_ms(struct uart_port *port)
1305{
49d5741b
JI		 1306 struct uart_8250_port *up =
1307 container_of(port, struct uart_8250_port, port);
1da177e4 1308
21c614a7
PA		 1309 /* no MSR capabilities */
1310 if (up->bugs & UART_BUG_NOMSR)
1311 return;
1312
1da177e4 1313 up->ier |= UART_IER_MSI;
4fd996a1 1314 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 1315}
1316
0690f41f 1317/*
3986fb2b 1318 * serial8250_rx_chars: processes according to the passed in LSR
0690f41f
PG		 1319 * value, and returns the remaining LSR bits not handled
1320 * by this Rx routine.
1321 */
3986fb2b
PG		 1322unsigned char
1323serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1da177e4 1324{
dfe42443 1325 struct uart_port *port = &up->port;
0690f41f 1326 unsigned char ch;
1da177e4
LT		 1327 int max_count = 256;
1328 char flag;
1329
1330 do {
7500b1f6 1331 if (likely(lsr & UART_LSR_DR))
0acf519f 1332 ch = serial_in(up, UART_RX);
7500b1f6
AR		 1333 else
1334 /*
1335 * Intel 82571 has a Serial Over Lan device that will
1336 * set UART_LSR_BI without setting UART_LSR_DR when
1337 * it receives a break. To avoid reading from the
1338 * receive buffer without UART_LSR_DR bit set, we
1339 * just force the read character to be 0
1340 */
1341 ch = 0;
1342
1da177e4 1343 flag = TTY_NORMAL;
dfe42443 1344 port->icount.rx++;
1da177e4 1345
ad4c2aa6
CM		 1346 lsr |= up->lsr_saved_flags;
1347 up->lsr_saved_flags = 0;
1da177e4 1348
ad4c2aa6 1349 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1350 if (lsr & UART_LSR_BI) {
1351 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
dfe42443 1352 port->icount.brk++;
1da177e4
LT		 1353 /*
1354 * We do the SysRQ and SAK checking
1355 * here because otherwise the break
1356 * may get masked by ignore_status_mask
1357 * or read_status_mask.
1358 */
dfe42443 1359 if (uart_handle_break(port))
1da177e4
LT		 1360 goto ignore_char;
1361 } else if (lsr & UART_LSR_PE)
dfe42443 1362 port->icount.parity++;
1da177e4 1363 else if (lsr & UART_LSR_FE)
dfe42443 1364 port->icount.frame++;
1da177e4 1365 if (lsr & UART_LSR_OE)
dfe42443 1366 port->icount.overrun++;
1da177e4
LT		 1367
1368 /*
23907eb8 1369 * Mask off conditions which should be ignored.
1da177e4 1370 */
dfe42443 1371 lsr &= port->read_status_mask;
1da177e4
LT		 1372
1373 if (lsr & UART_LSR_BI) {
1374 DEBUG_INTR("handling break....");
1375 flag = TTY_BREAK;
1376 } else if (lsr & UART_LSR_PE)
1377 flag = TTY_PARITY;
1378 else if (lsr & UART_LSR_FE)
1379 flag = TTY_FRAME;
1380 }
dfe42443 1381 if (uart_handle_sysrq_char(port, ch))
1da177e4 1382 goto ignore_char;
05ab3014 1383
dfe42443 1384 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
05ab3014 1385
6f803cd0 1386ignore_char:
0acf519f 1387 lsr = serial_in(up, UART_LSR);
7500b1f6 1388 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
dfe42443 1389 spin_unlock(&port->lock);
2e124b4a 1390 tty_flip_buffer_push(&port->state->port);
dfe42443 1391 spin_lock(&port->lock);
0690f41f 1392 return lsr;
1da177e4 1393}
3986fb2b 1394EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1da177e4 1395
3986fb2b 1396void serial8250_tx_chars(struct uart_8250_port *up)
1da177e4 1397{
dfe42443
PG		 1398 struct uart_port *port = &up->port;
1399 struct circ_buf *xmit = &port->state->xmit;
1da177e4
LT		 1400 int count;
1401
dfe42443
PG		 1402 if (port->x_char) {
1403 serial_out(up, UART_TX, port->x_char);
1404 port->icount.tx++;
1405 port->x_char = 0;
1da177e4
LT		 1406 return;
1407 }
dfe42443
PG		 1408 if (uart_tx_stopped(port)) {
1409 serial8250_stop_tx(port);
b129a8cc
RK		 1410 return;
1411 }
1412 if (uart_circ_empty(xmit)) {
e763b90c 1413 __stop_tx(up);
1da177e4
LT		 1414 return;
1415 }
1416
1417 count = up->tx_loadsz;
1418 do {
1419 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1420 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
dfe42443 1421 port->icount.tx++;
1da177e4
LT		 1422 if (uart_circ_empty(xmit))
1423 break;
1424 } while (--count > 0);
1425
1426 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
dfe42443 1427 uart_write_wakeup(port);
1da177e4
LT		 1428
1429 DEBUG_INTR("THRE...");
1430
1431 if (uart_circ_empty(xmit))
e763b90c 1432 __stop_tx(up);
1da177e4 1433}
3986fb2b 1434EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1da177e4 1435
3986fb2b 1436unsigned int serial8250_modem_status(struct uart_8250_port *up)
1da177e4 1437{
dfe42443 1438 struct uart_port *port = &up->port;
2af7cd68
RK		 1439 unsigned int status = serial_in(up, UART_MSR);
1440
ad4c2aa6
CM		 1441 status |= up->msr_saved_flags;
1442 up->msr_saved_flags = 0;
fdc30b3d 1443 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
dfe42443 1444 port->state != NULL) {
2af7cd68 1445 if (status & UART_MSR_TERI)
dfe42443 1446 port->icount.rng++;
2af7cd68 1447 if (status & UART_MSR_DDSR)
dfe42443 1448 port->icount.dsr++;
2af7cd68 1449 if (status & UART_MSR_DDCD)
dfe42443 1450 uart_handle_dcd_change(port, status & UART_MSR_DCD);
2af7cd68 1451 if (status & UART_MSR_DCTS)
dfe42443 1452 uart_handle_cts_change(port, status & UART_MSR_CTS);
2af7cd68 1453
dfe42443 1454 wake_up_interruptible(&port->state->port.delta_msr_wait);
2af7cd68 1455 }
1da177e4 1456
2af7cd68 1457 return status;
1da177e4 1458}
3986fb2b 1459EXPORT_SYMBOL_GPL(serial8250_modem_status);
1da177e4
LT		 1460
1461/*
1462 * This handles the interrupt from one port.
1463 */
86b21199 1464int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1da177e4 1465{
0690f41f 1466 unsigned char status;
4bf3631c 1467 unsigned long flags;
86b21199
PG		 1468 struct uart_8250_port *up =
1469 container_of(port, struct uart_8250_port, port);
1470
1471 if (iir & UART_IIR_NO_INT)
1472 return 0;
45e24601 1473
dfe42443 1474 spin_lock_irqsave(&port->lock, flags);
45e24601 1475
4fd996a1 1476 status = serial_port_in(port, UART_LSR);
1da177e4
LT		 1477
1478 DEBUG_INTR("status = %x...", status);
1479
7500b1f6 1480 if (status & (UART_LSR_DR | UART_LSR_BI))
3986fb2b
PG		 1481 status = serial8250_rx_chars(up, status);
1482 serial8250_modem_status(up);
1da177e4 1483 if (status & UART_LSR_THRE)
3986fb2b 1484 serial8250_tx_chars(up);
45e24601 1485
dfe42443 1486 spin_unlock_irqrestore(&port->lock, flags);
86b21199 1487 return 1;
583d28e9 1488}
c7a1bdc5 1489EXPORT_SYMBOL_GPL(serial8250_handle_irq);
583d28e9
JI		 1490
1491static int serial8250_default_handle_irq(struct uart_port *port)
1492{
4fd996a1 1493 unsigned int iir = serial_port_in(port, UART_IIR);
583d28e9
JI		 1494
1495 return serial8250_handle_irq(port, iir);
1496}
1497
dc96efb7
MS		 1498/*
1499 * These Exar UARTs have an extra interrupt indicator that could
1500 * fire for a few unimplemented interrupts. One of which is a
1501 * wakeup event when coming out of sleep. Put this here just
1502 * to be on the safe side that these interrupts don't go unhandled.
1503 */
1504static int exar_handle_irq(struct uart_port *port)
1505{
1506 unsigned char int0, int1, int2, int3;
1507 unsigned int iir = serial_port_in(port, UART_IIR);
1508 int ret;
1509
1510 ret = serial8250_handle_irq(port, iir);
1511
30fa96a3
MS		 1512 if ((port->type == PORT_XR17V35X) ||
1513 (port->type == PORT_XR17D15X)) {
dc96efb7
MS		 1514 int0 = serial_port_in(port, 0x80);
1515 int1 = serial_port_in(port, 0x81);
1516 int2 = serial_port_in(port, 0x82);
1517 int3 = serial_port_in(port, 0x83);
1518 }
1519
1520 return ret;
1521}
1522
1da177e4
LT		 1523/*
1524 * This is the serial driver's interrupt routine.
1525 *
1526 * Arjan thinks the old way was overly complex, so it got simplified.
1527 * Alan disagrees, saying that need the complexity to handle the weird
1528 * nature of ISA shared interrupts. (This is a special exception.)
1529 *
1530 * In order to handle ISA shared interrupts properly, we need to check
1531 * that all ports have been serviced, and therefore the ISA interrupt
1532 * line has been de-asserted.
1533 *
1534 * This means we need to loop through all ports. checking that they
1535 * don't have an interrupt pending.
1536 */
7d12e780 1537static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1538{
1539 struct irq_info *i = dev_id;
1540 struct list_head *l, *end = NULL;
1541 int pass_counter = 0, handled = 0;
1542
1543 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1544
1545 spin_lock(&i->lock);
1546
1547 l = i->head;
1548 do {
1549 struct uart_8250_port *up;
583d28e9 1550 struct uart_port *port;
1da177e4
LT		 1551
1552 up = list_entry(l, struct uart_8250_port, list);
583d28e9 1553 port = &up->port;
1da177e4 1554
49b532f9 1555 if (port->handle_irq(port)) {
1da177e4 1556 handled = 1;
1da177e4
LT		 1557 end = NULL;
1558 } else if (end == NULL)
1559 end = l;
1560
1561 l = l->next;
1562
1563 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1564 /* If we hit this, we're dead. */
cd3ecad1
DD		 1565 printk_ratelimited(KERN_ERR
1566 "serial8250: too much work for irq%d\n", irq);
1da177e4
LT		 1567 break;
1568 }
1569 } while (l != end);
1570
1571 spin_unlock(&i->lock);
1572
1573 DEBUG_INTR("end.\n");
1574
1575 return IRQ_RETVAL(handled);
1576}
1577
1578/*
1579 * To support ISA shared interrupts, we need to have one interrupt
1580 * handler that ensures that the IRQ line has been deasserted
1581 * before returning. Failing to do this will result in the IRQ
1582 * line being stuck active, and, since ISA irqs are edge triggered,
1583 * no more IRQs will be seen.
1584 */
1585static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1586{
1587 spin_lock_irq(&i->lock);
1588
1589 if (!list_empty(i->head)) {
1590 if (i->head == &up->list)
1591 i->head = i->head->next;
1592 list_del(&up->list);
1593 } else {
1594 BUG_ON(i->head != &up->list);
1595 i->head = NULL;
1596 }
1da177e4 1597 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1598 /* List empty so throw away the hash node */
1599 if (i->head == NULL) {
1600 hlist_del(&i->node);
1601 kfree(i);
1602 }
1da177e4
LT		 1603}
1604
1605static int serial_link_irq_chain(struct uart_8250_port *up)
1606{
25db8ad5
AC		 1607 struct hlist_head *h;
1608 struct hlist_node *n;
1609 struct irq_info *i;
40663cc7 1610 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1611
25db8ad5
AC		 1612 mutex_lock(&hash_mutex);
1613
1614 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1615
1616 hlist_for_each(n, h) {
1617 i = hlist_entry(n, struct irq_info, node);
1618 if (i->irq == up->port.irq)
1619 break;
1620 }
1621
1622 if (n == NULL) {
1623 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1624 if (i == NULL) {
1625 mutex_unlock(&hash_mutex);
1626 return -ENOMEM;
1627 }
1628 spin_lock_init(&i->lock);
1629 i->irq = up->port.irq;
1630 hlist_add_head(&i->node, h);
1631 }
1632 mutex_unlock(&hash_mutex);
1633
1da177e4
LT		 1634 spin_lock_irq(&i->lock);
1635
1636 if (i->head) {
1637 list_add(&up->list, i->head);
1638 spin_unlock_irq(&i->lock);
1639
1640 ret = 0;
1641 } else {
1642 INIT_LIST_HEAD(&up->list);
1643 i->head = &up->list;
1644 spin_unlock_irq(&i->lock);
1c2f0493 1645 irq_flags |= up->port.irqflags;
1da177e4
LT		 1646 ret = request_irq(up->port.irq, serial8250_interrupt,
1647 irq_flags, "serial", i);
1648 if (ret < 0)
1649 serial_do_unlink(i, up);
1650 }
1651
1652 return ret;
1653}
1654
1655static void serial_unlink_irq_chain(struct uart_8250_port *up)
1656{
25db8ad5
AC		 1657 struct irq_info *i;
1658 struct hlist_node *n;
1659 struct hlist_head *h;
1da177e4 1660
25db8ad5
AC		 1661 mutex_lock(&hash_mutex);
1662
1663 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1664
1665 hlist_for_each(n, h) {
1666 i = hlist_entry(n, struct irq_info, node);
1667 if (i->irq == up->port.irq)
1668 break;
1669 }
1670
1671 BUG_ON(n == NULL);
1da177e4
LT		 1672 BUG_ON(i->head == NULL);
1673
1674 if (list_empty(i->head))
1675 free_irq(up->port.irq, i);
1676
1677 serial_do_unlink(i, up);
25db8ad5 1678 mutex_unlock(&hash_mutex);
1da177e4
LT		 1679}
1680
1681/*
1682 * This function is used to handle ports that do not have an
1683 * interrupt. This doesn't work very well for 16450's, but gives
1684 * barely passable results for a 16550A. (Although at the expense
1685 * of much CPU overhead).
1686 */
1687static void serial8250_timeout(unsigned long data)
1688{
1689 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4 1690
a0431476 1691 up->port.handle_irq(&up->port);
54381067 1692 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
40b36daa
AW		 1693}
1694
1695static void serial8250_backup_timeout(unsigned long data)
1696{
1697 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1698 unsigned int iir, ier = 0, lsr;
1699 unsigned long flags;
40b36daa 1700
dbb3b1ca
AC		 1701 spin_lock_irqsave(&up->port.lock, flags);
1702
40b36daa
AW		 1703 /*
1704 * Must disable interrupts or else we risk racing with the interrupt
1705 * based handler.
1706 */
d4e33fac 1707 if (up->port.irq) {
40b36daa
AW		 1708 ier = serial_in(up, UART_IER);
1709 serial_out(up, UART_IER, 0);
1710 }
1da177e4 1711
40b36daa
AW		 1712 iir = serial_in(up, UART_IIR);
1713
1714 /*
1715 * This should be a safe test for anyone who doesn't trust the
1716 * IIR bits on their UART, but it's specifically designed for
1717 * the "Diva" UART used on the management processor on many HP
1718 * ia64 and parisc boxes.
1719 */
ad4c2aa6
CM		 1720 lsr = serial_in(up, UART_LSR);
1721 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
40b36daa 1722 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
ebd2c8f6 1723 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
ad4c2aa6 1724 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1725 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1726 iir |= UART_IIR_THRI;
1727 }
1728
1729 if (!(iir & UART_IIR_NO_INT))
3986fb2b 1730 serial8250_tx_chars(up);
40b36daa 1731
d4e33fac 1732 if (up->port.irq)
40b36daa
AW		 1733 serial_out(up, UART_IER, ier);
1734
dbb3b1ca
AC		 1735 spin_unlock_irqrestore(&up->port.lock, flags);
1736
40b36daa 1737 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0 1738 mod_timer(&up->timer,
54381067 1739 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1da177e4
LT		 1740}
1741
1742static unsigned int serial8250_tx_empty(struct uart_port *port)
1743{
49d5741b
JI		 1744 struct uart_8250_port *up =
1745 container_of(port, struct uart_8250_port, port);
1da177e4 1746 unsigned long flags;
ad4c2aa6 1747 unsigned int lsr;
1da177e4 1748
dfe42443 1749 spin_lock_irqsave(&port->lock, flags);
4fd996a1 1750 lsr = serial_port_in(port, UART_LSR);
ad4c2aa6 1751 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
dfe42443 1752 spin_unlock_irqrestore(&port->lock, flags);
1da177e4 1753
bca47613 1754 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1da177e4
LT		 1755}
1756
1757static unsigned int serial8250_get_mctrl(struct uart_port *port)
1758{
49d5741b
JI		 1759 struct uart_8250_port *up =
1760 container_of(port, struct uart_8250_port, port);
2af7cd68 1761 unsigned int status;
1da177e4
LT		 1762 unsigned int ret;
1763
3986fb2b 1764 status = serial8250_modem_status(up);
1da177e4
LT		 1765
1766 ret = 0;
1767 if (status & UART_MSR_DCD)
1768 ret |= TIOCM_CAR;
1769 if (status & UART_MSR_RI)
1770 ret |= TIOCM_RNG;
1771 if (status & UART_MSR_DSR)
1772 ret |= TIOCM_DSR;
1773 if (status & UART_MSR_CTS)
1774 ret |= TIOCM_CTS;
1775 return ret;
1776}
1777
1778static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1779{
49d5741b
JI		 1780 struct uart_8250_port *up =
1781 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1782 unsigned char mcr = 0;
1783
1784 if (mctrl & TIOCM_RTS)
1785 mcr |= UART_MCR_RTS;
1786 if (mctrl & TIOCM_DTR)
1787 mcr |= UART_MCR_DTR;
1788 if (mctrl & TIOCM_OUT1)
1789 mcr |= UART_MCR_OUT1;
1790 if (mctrl & TIOCM_OUT2)
1791 mcr |= UART_MCR_OUT2;
1792 if (mctrl & TIOCM_LOOP)
1793 mcr |= UART_MCR_LOOP;
1794
1795 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1796
4fd996a1 1797 serial_port_out(port, UART_MCR, mcr);
1da177e4
LT		 1798}
1799
1800static void serial8250_break_ctl(struct uart_port *port, int break_state)
1801{
49d5741b
JI		 1802 struct uart_8250_port *up =
1803 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1804 unsigned long flags;
1805
dfe42443 1806 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 1807 if (break_state == -1)
1808 up->lcr |= UART_LCR_SBC;
1809 else
1810 up->lcr &= ~UART_LCR_SBC;
4fd996a1 1811 serial_port_out(port, UART_LCR, up->lcr);
dfe42443 1812 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1813}
1814
40b36daa
AW		 1815/*
1816 * Wait for transmitter & holding register to empty
1817 */
b5d674ab 1818static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 1819{
1820 unsigned int status, tmout = 10000;
1821
1822 /* Wait up to 10ms for the character(s) to be sent. */
97d303b7 1823 for (;;) {
40b36daa
AW		 1824 status = serial_in(up, UART_LSR);
1825
ad4c2aa6 1826 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa 1827
97d303b7
DD		 1828 if ((status & bits) == bits)
1829 break;
40b36daa
AW		 1830 if (--tmout == 0)
1831 break;
1832 udelay(1);
97d303b7 1833 }
40b36daa
AW		 1834
1835 /* Wait up to 1s for flow control if necessary */
1836 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1837 unsigned int tmout;
1838 for (tmout = 1000000; tmout; tmout--) {
1839 unsigned int msr = serial_in(up, UART_MSR);
1840 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1841 if (msr & UART_MSR_CTS)
1842 break;
40b36daa
AW		 1843 udelay(1);
1844 touch_nmi_watchdog();
1845 }
1846 }
1847}
1848
f2d937f3
JW		 1849#ifdef CONFIG_CONSOLE_POLL
1850/*
1851 * Console polling routines for writing and reading from the uart while
1852 * in an interrupt or debug context.
1853 */
1854
1855static int serial8250_get_poll_char(struct uart_port *port)
1856{
4fd996a1 1857 unsigned char lsr = serial_port_in(port, UART_LSR);
f2d937f3 1858
f5316b4a
JW		 1859 if (!(lsr & UART_LSR_DR))
1860 return NO_POLL_CHAR;
f2d937f3 1861
4fd996a1 1862 return serial_port_in(port, UART_RX);
f2d937f3
JW		 1863}
1864
1865
1866static void serial8250_put_poll_char(struct uart_port *port,
1867 unsigned char c)
1868{
1869 unsigned int ier;
49d5741b
JI		 1870 struct uart_8250_port *up =
1871 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1872
1873 /*
1874 * First save the IER then disable the interrupts
1875 */
4fd996a1 1876 ier = serial_port_in(port, UART_IER);
f2d937f3 1877 if (up->capabilities & UART_CAP_UUE)
4fd996a1 1878 serial_port_out(port, UART_IER, UART_IER_UUE);
f2d937f3 1879 else
4fd996a1 1880 serial_port_out(port, UART_IER, 0);
f2d937f3
JW		 1881
1882 wait_for_xmitr(up, BOTH_EMPTY);
1883 /*
1884 * Send the character out.
1885 * If a LF, also do CR...
1886 */
4fd996a1 1887 serial_port_out(port, UART_TX, c);
f2d937f3
JW		 1888 if (c == 10) {
1889 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 1890 serial_port_out(port, UART_TX, 13);
f2d937f3
JW		 1891 }
1892
1893 /*
1894 * Finally, wait for transmitter to become empty
1895 * and restore the IER
1896 */
1897 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 1898 serial_port_out(port, UART_IER, ier);
f2d937f3
JW		 1899}
1900
1901#endif /* CONFIG_CONSOLE_POLL */
1902
1da177e4
LT		 1903static int serial8250_startup(struct uart_port *port)
1904{
49d5741b
JI		 1905 struct uart_8250_port *up =
1906 container_of(port, struct uart_8250_port, port);
1da177e4 1907 unsigned long flags;
55d3b282 1908 unsigned char lsr, iir;
1da177e4
LT		 1909 int retval;
1910
65ecc9c0
SY		 1911 if (port->type == PORT_8250_CIR)
1912 return -ENODEV;
1913
dfe42443 1914 port->fifosize = uart_config[up->port.type].fifo_size;
e4f05af1 1915 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1da177e4
LT		 1916 up->capabilities = uart_config[up->port.type].flags;
1917 up->mcr = 0;
1918
dfe42443 1919 if (port->iotype != up->cur_iotype)
b8e7e40a
AC		 1920 set_io_from_upio(port);
1921
dfe42443 1922 if (port->type == PORT_16C950) {
1da177e4
LT		 1923 /* Wake up and initialize UART */
1924 up->acr = 0;
4fd996a1
PG		 1925 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1926 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1927 serial_port_out(port, UART_IER, 0);
1928 serial_port_out(port, UART_LCR, 0);
1da177e4 1929 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
4fd996a1
PG		 1930 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1931 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1932 serial_port_out(port, UART_LCR, 0);
1da177e4
LT		 1933 }
1934
1935#ifdef CONFIG_SERIAL_8250_RSA
1936 /*
1937 * If this is an RSA port, see if we can kick it up to the
1938 * higher speed clock.
1939 */
1940 enable_rsa(up);
1941#endif
1942
1943 /*
1944 * Clear the FIFO buffers and disable them.
7f927fcc 1945 * (they will be reenabled in set_termios())
1da177e4
LT		 1946 */
1947 serial8250_clear_fifos(up);
1948
1949 /*
1950 * Clear the interrupt registers.
1951 */
4fd996a1
PG		 1952 serial_port_in(port, UART_LSR);
1953 serial_port_in(port, UART_RX);
1954 serial_port_in(port, UART_IIR);
1955 serial_port_in(port, UART_MSR);
1da177e4
LT		 1956
1957 /*
1958 * At this point, there's no way the LSR could still be 0xff;
1959 * if it is, then bail out, because there's likely no UART
1960 * here.
1961 */
dfe42443 1962 if (!(port->flags & UPF_BUGGY_UART) &&
4fd996a1 1963 (serial_port_in(port, UART_LSR) == 0xff)) {
7808a4c4 1964 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
dfe42443 1965 serial_index(port));
1da177e4
LT		 1966 return -ENODEV;
1967 }
1968
1969 /*
1970 * For a XR16C850, we need to set the trigger levels
1971 */
dfe42443 1972 if (port->type == PORT_16850) {
1da177e4
LT		 1973 unsigned char fctr;
1974
0acf519f 1975 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4 1976
0acf519f 1977 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
4fd996a1
PG		 1978 serial_port_out(port, UART_FCTR,
1979 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1980 serial_port_out(port, UART_TRG, UART_TRG_96);
1981 serial_port_out(port, UART_FCTR,
1982 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1983 serial_port_out(port, UART_TRG, UART_TRG_96);
1da177e4 1984
4fd996a1 1985 serial_port_out(port, UART_LCR, 0);
1da177e4
LT		 1986 }
1987
dfe42443 1988 if (port->irq) {
01c194d9 1989 unsigned char iir1;
40b36daa
AW		 1990 /*
1991 * Test for UARTs that do not reassert THRE when the
1992 * transmitter is idle and the interrupt has already
1993 * been cleared. Real 16550s should always reassert
1994 * this interrupt whenever the transmitter is idle and
1995 * the interrupt is enabled. Delays are necessary to
1996 * allow register changes to become visible.
1997 */
dfe42443 1998 spin_lock_irqsave(&port->lock, flags);
1c2f0493 1999 if (up->port.irqflags & IRQF_SHARED)
dfe42443 2000 disable_irq_nosync(port->irq);
40b36daa
AW		 2001
2002 wait_for_xmitr(up, UART_LSR_THRE);
55e4016d 2003 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
40b36daa 2004 udelay(1); /* allow THRE to set */
4fd996a1
PG		 2005 iir1 = serial_port_in(port, UART_IIR);
2006 serial_port_out(port, UART_IER, 0);
55e4016d 2007 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
40b36daa 2008 udelay(1); /* allow a working UART time to re-assert THRE */
4fd996a1
PG		 2009 iir = serial_port_in(port, UART_IIR);
2010 serial_port_out(port, UART_IER, 0);
40b36daa 2011
dfe42443
PG		 2012 if (port->irqflags & IRQF_SHARED)
2013 enable_irq(port->irq);
2014 spin_unlock_irqrestore(&port->lock, flags);
40b36daa
AW		 2015
2016 /*
bc02d15a
DW		 2017 * If the interrupt is not reasserted, or we otherwise
2018 * don't trust the iir, setup a timer to kick the UART
2019 * on a regular basis.
40b36daa 2020 */
bc02d15a
DW		 2021 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2022 up->port.flags & UPF_BUG_THRE) {
363f66fe 2023 up->bugs |= UART_BUG_THRE;
8440838b
DM		 2024 pr_debug("ttyS%d - using backup timer\n",
2025 serial_index(port));
40b36daa
AW		 2026 }
2027 }
2028
363f66fe
WN		 2029 /*
2030 * The above check will only give an accurate result the first time
2031 * the port is opened so this value needs to be preserved.
2032 */
2033 if (up->bugs & UART_BUG_THRE) {
2034 up->timer.function = serial8250_backup_timeout;
2035 up->timer.data = (unsigned long)up;
2036 mod_timer(&up->timer, jiffies +
54381067 2037 uart_poll_timeout(port) + HZ / 5);
363f66fe
WN		 2038 }
2039
1da177e4
LT		 2040 /*
2041 * If the "interrupt" for this port doesn't correspond with any
2042 * hardware interrupt, we use a timer-based system. The original
2043 * driver used to do this with IRQ0.
2044 */
dfe42443 2045 if (!port->irq) {
1da177e4 2046 up->timer.data = (unsigned long)up;
54381067 2047 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
1da177e4
LT		 2048 } else {
2049 retval = serial_link_irq_chain(up);
2050 if (retval)
2051 return retval;
2052 }
2053
2054 /*
2055 * Now, initialize the UART
2056 */
4fd996a1 2057 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
1da177e4 2058
dfe42443 2059 spin_lock_irqsave(&port->lock, flags);
1da177e4 2060 if (up->port.flags & UPF_FOURPORT) {
d4e33fac 2061 if (!up->port.irq)
1da177e4
LT		 2062 up->port.mctrl |= TIOCM_OUT1;
2063 } else
2064 /*
2065 * Most PC uarts need OUT2 raised to enable interrupts.
2066 */
dfe42443 2067 if (port->irq)
1da177e4
LT		 2068 up->port.mctrl |= TIOCM_OUT2;
2069
dfe42443 2070 serial8250_set_mctrl(port, port->mctrl);
55d3b282 2071
b6adea33
MCC		 2072 /* Serial over Lan (SoL) hack:
2073 Intel 8257x Gigabit ethernet chips have a
2074 16550 emulation, to be used for Serial Over Lan.
2075 Those chips take a longer time than a normal
2076 serial device to signalize that a transmission
2077 data was queued. Due to that, the above test generally
2078 fails. One solution would be to delay the reading of
2079 iir. However, this is not reliable, since the timeout
2080 is variable. So, let's just don't test if we receive
2081 TX irq. This way, we'll never enable UART_BUG_TXEN.
2082 */
d41a4b51 2083 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
b6adea33
MCC		 2084 goto dont_test_tx_en;
2085
55d3b282
RK		 2086 /*
2087 * Do a quick test to see if we receive an
2088 * interrupt when we enable the TX irq.
2089 */
4fd996a1
PG		 2090 serial_port_out(port, UART_IER, UART_IER_THRI);
2091 lsr = serial_port_in(port, UART_LSR);
2092 iir = serial_port_in(port, UART_IIR);
2093 serial_port_out(port, UART_IER, 0);
55d3b282
RK		 2094
2095 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2096 if (!(up->bugs & UART_BUG_TXEN)) {
2097 up->bugs |= UART_BUG_TXEN;
55d3b282 2098 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2099 serial_index(port));
55d3b282
RK		 2100 }
2101 } else {
67f7654e 2102 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2103 }
2104
b6adea33 2105dont_test_tx_en:
dfe42443 2106 spin_unlock_irqrestore(&port->lock, flags);
1da177e4 2107
ad4c2aa6
CM		 2108 /*
2109 * Clear the interrupt registers again for luck, and clear the
2110 * saved flags to avoid getting false values from polling
2111 * routines or the previous session.
2112 */
4fd996a1
PG		 2113 serial_port_in(port, UART_LSR);
2114 serial_port_in(port, UART_RX);
2115 serial_port_in(port, UART_IIR);
2116 serial_port_in(port, UART_MSR);
ad4c2aa6
CM		 2117 up->lsr_saved_flags = 0;
2118 up->msr_saved_flags = 0;
2119
1da177e4
LT		 2120 /*
2121 * Finally, enable interrupts. Note: Modem status interrupts
2122 * are set via set_termios(), which will be occurring imminently
2123 * anyway, so we don't enable them here.
2124 */
2125 up->ier = UART_IER_RLSI | UART_IER_RDI;
4fd996a1 2126 serial_port_out(port, UART_IER, up->ier);
1da177e4 2127
dfe42443 2128 if (port->flags & UPF_FOURPORT) {
1da177e4
LT		 2129 unsigned int icp;
2130 /*
2131 * Enable interrupts on the AST Fourport board
2132 */
dfe42443 2133 icp = (port->iobase & 0xfe0) | 0x01f;
1da177e4 2134 outb_p(0x80, icp);
0d263a26 2135 inb_p(icp);
1da177e4
LT		 2136 }
2137
1da177e4
LT		 2138 return 0;
2139}
2140
2141static void serial8250_shutdown(struct uart_port *port)
2142{
49d5741b
JI		 2143 struct uart_8250_port *up =
2144 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2145 unsigned long flags;
2146
2147 /*
2148 * Disable interrupts from this port
2149 */
2150 up->ier = 0;
4fd996a1 2151 serial_port_out(port, UART_IER, 0);
1da177e4 2152
dfe42443
PG		 2153 spin_lock_irqsave(&port->lock, flags);
2154 if (port->flags & UPF_FOURPORT) {
1da177e4 2155 /* reset interrupts on the AST Fourport board */
dfe42443
PG		 2156 inb((port->iobase & 0xfe0) | 0x1f);
2157 port->mctrl |= TIOCM_OUT1;
1da177e4 2158 } else
dfe42443 2159 port->mctrl &= ~TIOCM_OUT2;
1da177e4 2160
dfe42443
PG		 2161 serial8250_set_mctrl(port, port->mctrl);
2162 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 2163
2164 /*
2165 * Disable break condition and FIFOs
2166 */
4fd996a1
PG		 2167 serial_port_out(port, UART_LCR,
2168 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
1da177e4
LT		 2169 serial8250_clear_fifos(up);
2170
2171#ifdef CONFIG_SERIAL_8250_RSA
2172 /*
2173 * Reset the RSA board back to 115kbps compat mode.
2174 */
2175 disable_rsa(up);
2176#endif
2177
2178 /*
2179 * Read data port to reset things, and then unlink from
2180 * the IRQ chain.
2181 */
4fd996a1 2182 serial_port_in(port, UART_RX);
1da177e4 2183
40b36daa
AW		 2184 del_timer_sync(&up->timer);
2185 up->timer.function = serial8250_timeout;
dfe42443 2186 if (port->irq)
1da177e4
LT		 2187 serial_unlink_irq_chain(up);
2188}
2189
2190static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2191{
2192 unsigned int quot;
2193
2194 /*
2195 * Handle magic divisors for baud rates above baud_base on
2196 * SMSC SuperIO chips.
2197 */
2198 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2199 baud == (port->uartclk/4))
2200 quot = 0x8001;
2201 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2202 baud == (port->uartclk/8))
2203 quot = 0x8002;
2204 else
2205 quot = uart_get_divisor(port, baud);
2206
2207 return quot;
2208}
2209
235dae5d
PL		 2210void
2211serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2212 struct ktermios *old)
1da177e4 2213{
49d5741b
JI		 2214 struct uart_8250_port *up =
2215 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2216 unsigned char cval, fcr = 0;
2217 unsigned long flags;
2218 unsigned int baud, quot;
eb26dfe8 2219 int fifo_bug = 0;
1da177e4
LT		 2220
2221 switch (termios->c_cflag & CSIZE) {
2222 case CS5:
0a8b80c5 2223 cval = UART_LCR_WLEN5;
1da177e4
LT		 2224 break;
2225 case CS6:
0a8b80c5 2226 cval = UART_LCR_WLEN6;
1da177e4
LT		 2227 break;
2228 case CS7:
0a8b80c5 2229 cval = UART_LCR_WLEN7;
1da177e4
LT		 2230 break;
2231 default:
2232 case CS8:
0a8b80c5 2233 cval = UART_LCR_WLEN8;
1da177e4
LT		 2234 break;
2235 }
2236
2237 if (termios->c_cflag & CSTOPB)
0a8b80c5 2238 cval |= UART_LCR_STOP;
eb26dfe8 2239 if (termios->c_cflag & PARENB) {
1da177e4 2240 cval |= UART_LCR_PARITY;
eb26dfe8
AC		 2241 if (up->bugs & UART_BUG_PARITY)
2242 fifo_bug = 1;
2243 }
1da177e4
LT		 2244 if (!(termios->c_cflag & PARODD))
2245 cval |= UART_LCR_EPAR;
2246#ifdef CMSPAR
2247 if (termios->c_cflag & CMSPAR)
2248 cval |= UART_LCR_SPAR;
2249#endif
2250
2251 /*
2252 * Ask the core to calculate the divisor for us.
2253 */
24d481ec
AV		 2254 baud = uart_get_baud_rate(port, termios, old,
2255 port->uartclk / 16 / 0xffff,
2256 port->uartclk / 16);
1da177e4
LT		 2257 quot = serial8250_get_divisor(port, baud);
2258
2259 /*
4ba5e35d 2260 * Oxford Semi 952 rev B workaround
1da177e4 2261 */
4ba5e35d 2262 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2263 quot++;
1da177e4 2264
dfe42443 2265 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
f9a9111b 2266 fcr = uart_config[port->type].fcr;
eb26dfe8 2267 if (baud < 2400 || fifo_bug) {
f9a9111b
CM		 2268 fcr &= ~UART_FCR_TRIGGER_MASK;
2269 fcr |= UART_FCR_TRIGGER_1;
2270 }
1da177e4
LT		 2271 }
2272
2273 /*
2274 * MCR-based auto flow control. When AFE is enabled, RTS will be
2275 * deasserted when the receive FIFO contains more characters than
2276 * the trigger, or the MCR RTS bit is cleared. In the case where
2277 * the remote UART is not using CTS auto flow control, we must
2278 * have sufficient FIFO entries for the latency of the remote
2279 * UART to respond. IOW, at least 32 bytes of FIFO.
2280 */
dfe42443 2281 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
1da177e4
LT		 2282 up->mcr &= ~UART_MCR_AFE;
2283 if (termios->c_cflag & CRTSCTS)
2284 up->mcr |= UART_MCR_AFE;
2285 }
2286
2287 /*
2288 * Ok, we're now changing the port state. Do it with
2289 * interrupts disabled.
2290 */
dfe42443 2291 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 2292
2293 /*
2294 * Update the per-port timeout.
2295 */
2296 uart_update_timeout(port, termios->c_cflag, baud);
2297
dfe42443 2298 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1da177e4 2299 if (termios->c_iflag & INPCK)
dfe42443 2300 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1da177e4 2301 if (termios->c_iflag & (BRKINT | PARMRK))
dfe42443 2302 port->read_status_mask |= UART_LSR_BI;
1da177e4
LT		 2303
2304 /*
2305 * Characteres to ignore
2306 */
dfe42443 2307 port->ignore_status_mask = 0;
1da177e4 2308 if (termios->c_iflag & IGNPAR)
dfe42443 2309 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1da177e4 2310 if (termios->c_iflag & IGNBRK) {
dfe42443 2311 port->ignore_status_mask |= UART_LSR_BI;
1da177e4
LT		 2312 /*
2313 * If we're ignoring parity and break indicators,
2314 * ignore overruns too (for real raw support).
2315 */
2316 if (termios->c_iflag & IGNPAR)
dfe42443 2317 port->ignore_status_mask |= UART_LSR_OE;
1da177e4
LT		 2318 }
2319
2320 /*
2321 * ignore all characters if CREAD is not set
2322 */
2323 if ((termios->c_cflag & CREAD) == 0)
dfe42443 2324 port->ignore_status_mask |= UART_LSR_DR;
1da177e4
LT		 2325
2326 /*
2327 * CTS flow control flag and modem status interrupts
2328 */
f8b372a1 2329 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2330 if (!(up->bugs & UART_BUG_NOMSR) &&
2331 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2332 up->ier |= UART_IER_MSI;
2333 if (up->capabilities & UART_CAP_UUE)
4539c24f
SW		 2334 up->ier |= UART_IER_UUE;
2335 if (up->capabilities & UART_CAP_RTOIE)
2336 up->ier |= UART_IER_RTOIE;
1da177e4 2337
4fd996a1 2338 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 2339
2340 if (up->capabilities & UART_CAP_EFR) {
2341 unsigned char efr = 0;
2342 /*
2343 * TI16C752/Startech hardware flow control. FIXME:
2344 * - TI16C752 requires control thresholds to be set.
2345 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2346 */
2347 if (termios->c_cflag & CRTSCTS)
2348 efr |= UART_EFR_CTS;
2349
4fd996a1 2350 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
dfe42443 2351 if (port->flags & UPF_EXAR_EFR)
4fd996a1 2352 serial_port_out(port, UART_XR_EFR, efr);
06315348 2353 else
4fd996a1 2354 serial_port_out(port, UART_EFR, efr);
1da177e4
LT		 2355 }
2356
255341c6 2357 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
54ec52b6 2358 if (is_omap1510_8250(up)) {
255341c6
JM		 2359 if (baud == 115200) {
2360 quot = 1;
4fd996a1 2361 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
255341c6 2362 } else
4fd996a1 2363 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
255341c6 2364 }
255341c6 2365
4fd996a1
PG		 2366 /*
2367 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2368 * otherwise just set DLAB
2369 */
2370 if (up->capabilities & UART_NATSEMI)
2371 serial_port_out(port, UART_LCR, 0xe0);
2372 else
2373 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
1da177e4 2374
b32b19b8 2375 serial_dl_write(up, quot);
1da177e4
LT		 2376
2377 /*
2378 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2379 * is written without DLAB set, this mode will be disabled.
2380 */
dfe42443 2381 if (port->type == PORT_16750)
4fd996a1 2382 serial_port_out(port, UART_FCR, fcr);
1da177e4 2383
4fd996a1 2384 serial_port_out(port, UART_LCR, cval); /* reset DLAB */
1da177e4 2385 up->lcr = cval; /* Save LCR */
dfe42443 2386 if (port->type != PORT_16750) {
4fd996a1
PG		 2387 /* emulated UARTs (Lucent Venus 167x) need two steps */
2388 if (fcr & UART_FCR_ENABLE_FIFO)
2389 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2390 serial_port_out(port, UART_FCR, fcr); /* set fcr */
1da177e4 2391 }
dfe42443
PG		 2392 serial8250_set_mctrl(port, port->mctrl);
2393 spin_unlock_irqrestore(&port->lock, flags);
e991a2bd
AC		 2394 /* Don't rewrite B0 */
2395 if (tty_termios_baud_rate(termios))
2396 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4 2397}
235dae5d
PL		 2398EXPORT_SYMBOL(serial8250_do_set_termios);
2399
2400static void
2401serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2402 struct ktermios *old)
2403{
2404 if (port->set_termios)
2405 port->set_termios(port, termios, old);
2406 else
2407 serial8250_do_set_termios(port, termios, old);
2408}
1da177e4 2409
dc77f161 2410static void
a0821df6 2411serial8250_set_ldisc(struct uart_port *port, int new)
dc77f161 2412{
a0821df6 2413 if (new == N_PPS) {
dc77f161
RG		 2414 port->flags |= UPF_HARDPPS_CD;
2415 serial8250_enable_ms(port);
2416 } else
2417 port->flags &= ~UPF_HARDPPS_CD;
2418}
2419
c161afe9
ML		 2420
2421void serial8250_do_pm(struct uart_port *port, unsigned int state,
2422 unsigned int oldstate)
1da177e4 2423{
49d5741b
JI		 2424 struct uart_8250_port *p =
2425 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2426
2427 serial8250_set_sleep(p, state != 0);
c161afe9
ML		 2428}
2429EXPORT_SYMBOL(serial8250_do_pm);
1da177e4 2430
c161afe9
ML		 2431static void
2432serial8250_pm(struct uart_port *port, unsigned int state,
2433 unsigned int oldstate)
2434{
2435 if (port->pm)
2436 port->pm(port, state, oldstate);
2437 else
2438 serial8250_do_pm(port, state, oldstate);
1da177e4
LT		 2439}
2440
f2eda27d
RK		 2441static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2442{
2443 if (pt->port.iotype == UPIO_AU)
b2b13cdf 2444 return 0x1000;
54ec52b6 2445 if (is_omap1_8250(pt))
f2eda27d 2446 return 0x16 << pt->port.regshift;
54ec52b6 2447
f2eda27d
RK		 2448 return 8 << pt->port.regshift;
2449}
2450
1da177e4
LT		 2451/*
2452 * Resource handling.
2453 */
2454static int serial8250_request_std_resource(struct uart_8250_port *up)
2455{
f2eda27d 2456 unsigned int size = serial8250_port_size(up);
dfe42443 2457 struct uart_port *port = &up->port;
1da177e4
LT		 2458 int ret = 0;
2459
dfe42443 2460 switch (port->iotype) {
85835f44 2461 case UPIO_AU:
0b30d668
SS		 2462 case UPIO_TSI:
2463 case UPIO_MEM32:
1da177e4 2464 case UPIO_MEM:
dfe42443 2465 if (!port->mapbase)
1da177e4
LT		 2466 break;
2467
dfe42443 2468 if (!request_mem_region(port->mapbase, size, "serial")) {
1da177e4
LT		 2469 ret = -EBUSY;
2470 break;
2471 }
2472
dfe42443
PG		 2473 if (port->flags & UPF_IOREMAP) {
2474 port->membase = ioremap_nocache(port->mapbase, size);
2475 if (!port->membase) {
2476 release_mem_region(port->mapbase, size);
1da177e4
LT		 2477 ret = -ENOMEM;
2478 }
2479 }
2480 break;
2481
2482 case UPIO_HUB6:
2483 case UPIO_PORT:
dfe42443 2484 if (!request_region(port->iobase, size, "serial"))
1da177e4
LT		 2485 ret = -EBUSY;
2486 break;
2487 }
2488 return ret;
2489}
2490
2491static void serial8250_release_std_resource(struct uart_8250_port *up)
2492{
f2eda27d 2493 unsigned int size = serial8250_port_size(up);
dfe42443 2494 struct uart_port *port = &up->port;
1da177e4 2495
dfe42443 2496 switch (port->iotype) {
85835f44 2497 case UPIO_AU:
0b30d668
SS		 2498 case UPIO_TSI:
2499 case UPIO_MEM32:
1da177e4 2500 case UPIO_MEM:
dfe42443 2501 if (!port->mapbase)
1da177e4
LT		 2502 break;
2503
dfe42443
PG		 2504 if (port->flags & UPF_IOREMAP) {
2505 iounmap(port->membase);
2506 port->membase = NULL;
1da177e4
LT		 2507 }
2508
dfe42443 2509 release_mem_region(port->mapbase, size);
1da177e4
LT		 2510 break;
2511
2512 case UPIO_HUB6:
2513 case UPIO_PORT:
dfe42443 2514 release_region(port->iobase, size);
1da177e4
LT		 2515 break;
2516 }
2517}
2518
2519static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2520{
2521 unsigned long start = UART_RSA_BASE << up->port.regshift;
2522 unsigned int size = 8 << up->port.regshift;
dfe42443 2523 struct uart_port *port = &up->port;
0b30d668 2524 int ret = -EINVAL;
1da177e4 2525
dfe42443 2526 switch (port->iotype) {
1da177e4
LT		 2527 case UPIO_HUB6:
2528 case UPIO_PORT:
dfe42443 2529 start += port->iobase;
0b30d668
SS		 2530 if (request_region(start, size, "serial-rsa"))
2531 ret = 0;
2532 else
1da177e4
LT		 2533 ret = -EBUSY;
2534 break;
2535 }
2536
2537 return ret;
2538}
2539
2540static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2541{
2542 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2543 unsigned int size = 8 << up->port.regshift;
dfe42443 2544 struct uart_port *port = &up->port;
1da177e4 2545
dfe42443 2546 switch (port->iotype) {
1da177e4
LT		 2547 case UPIO_HUB6:
2548 case UPIO_PORT:
dfe42443 2549 release_region(port->iobase + offset, size);
1da177e4
LT		 2550 break;
2551 }
2552}
2553
2554static void serial8250_release_port(struct uart_port *port)
2555{
49d5741b
JI		 2556 struct uart_8250_port *up =
2557 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2558
2559 serial8250_release_std_resource(up);
dfe42443 2560 if (port->type == PORT_RSA)
1da177e4
LT		 2561 serial8250_release_rsa_resource(up);
2562}
2563
2564static int serial8250_request_port(struct uart_port *port)
2565{
49d5741b
JI		 2566 struct uart_8250_port *up =
2567 container_of(port, struct uart_8250_port, port);
65ecc9c0
SY		 2568 int ret;
2569
2570 if (port->type == PORT_8250_CIR)
2571 return -ENODEV;
1da177e4
LT		 2572
2573 ret = serial8250_request_std_resource(up);
dfe42443 2574 if (ret == 0 && port->type == PORT_RSA) {
1da177e4
LT		 2575 ret = serial8250_request_rsa_resource(up);
2576 if (ret < 0)
2577 serial8250_release_std_resource(up);
2578 }
2579
2580 return ret;
2581}
2582
2583static void serial8250_config_port(struct uart_port *port, int flags)
2584{
49d5741b
JI		 2585 struct uart_8250_port *up =
2586 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2587 int probeflags = PROBE_ANY;
2588 int ret;
2589
65ecc9c0
SY		 2590 if (port->type == PORT_8250_CIR)
2591 return;
2592
1da177e4
LT		 2593 /*
2594 * Find the region that we can probe for. This in turn
2595 * tells us whether we can probe for the type of port.
2596 */
2597 ret = serial8250_request_std_resource(up);
2598 if (ret < 0)
2599 return;
2600
2601 ret = serial8250_request_rsa_resource(up);
2602 if (ret < 0)
2603 probeflags &= ~PROBE_RSA;
2604
dfe42443 2605 if (port->iotype != up->cur_iotype)
b8e7e40a
AC		 2606 set_io_from_upio(port);
2607
1da177e4
LT		 2608 if (flags & UART_CONFIG_TYPE)
2609 autoconfig(up, probeflags);
b2b13cdf 2610
b2b13cdf 2611 /* if access method is AU, it is a 16550 with a quirk */
dfe42443 2612 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
b2b13cdf 2613 up->bugs |= UART_BUG_NOMSR;
b2b13cdf 2614
dfe42443 2615 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
1da177e4
LT		 2616 autoconfig_irq(up);
2617
dfe42443 2618 if (port->type != PORT_RSA && probeflags & PROBE_RSA)
1da177e4 2619 serial8250_release_rsa_resource(up);
dfe42443 2620 if (port->type == PORT_UNKNOWN)
1da177e4 2621 serial8250_release_std_resource(up);
dc96efb7
MS		 2622
2623 /* Fixme: probably not the best place for this */
30fa96a3
MS		 2624 if ((port->type == PORT_XR17V35X) ||
2625 (port->type == PORT_XR17D15X))
dc96efb7 2626 port->handle_irq = exar_handle_irq;
1da177e4
LT		 2627}
2628
2629static int
2630serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2631{
a62c4133 2632 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 2633 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2634 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2635 ser->type == PORT_STARTECH)
2636 return -EINVAL;
2637 return 0;
2638}
2639
2640static const char *
2641serial8250_type(struct uart_port *port)
2642{
2643 int type = port->type;
2644
2645 if (type >= ARRAY_SIZE(uart_config))
2646 type = 0;
2647 return uart_config[type].name;
2648}
2649
2650static struct uart_ops serial8250_pops = {
2651 .tx_empty = serial8250_tx_empty,
2652 .set_mctrl = serial8250_set_mctrl,
2653 .get_mctrl = serial8250_get_mctrl,
2654 .stop_tx = serial8250_stop_tx,
2655 .start_tx = serial8250_start_tx,
2656 .stop_rx = serial8250_stop_rx,
2657 .enable_ms = serial8250_enable_ms,
2658 .break_ctl = serial8250_break_ctl,
2659 .startup = serial8250_startup,
2660 .shutdown = serial8250_shutdown,
2661 .set_termios = serial8250_set_termios,
dc77f161 2662 .set_ldisc = serial8250_set_ldisc,
1da177e4
LT		 2663 .pm = serial8250_pm,
2664 .type = serial8250_type,
2665 .release_port = serial8250_release_port,
2666 .request_port = serial8250_request_port,
2667 .config_port = serial8250_config_port,
2668 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2669#ifdef CONFIG_CONSOLE_POLL
2670 .poll_get_char = serial8250_get_poll_char,
2671 .poll_put_char = serial8250_put_poll_char,
2672#endif
1da177e4
LT		 2673};
2674
2675static struct uart_8250_port serial8250_ports[UART_NR];
2676
af7f3743
AC		 2677static void (*serial8250_isa_config)(int port, struct uart_port *up,
2678 unsigned short *capabilities);
2679
2680void serial8250_set_isa_configurator(
2681 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2682{
2683 serial8250_isa_config = v;
2684}
2685EXPORT_SYMBOL(serial8250_set_isa_configurator);
2686
1da177e4
LT		 2687static void __init serial8250_isa_init_ports(void)
2688{
2689 struct uart_8250_port *up;
2690 static int first = 1;
4c0ebb80 2691 int i, irqflag = 0;
1da177e4
LT		 2692
2693 if (!first)
2694 return;
2695 first = 0;
2696
835d844d
SY		 2697 if (nr_uarts > UART_NR)
2698 nr_uarts = UART_NR;
2699
a61c2d78 2700 for (i = 0; i < nr_uarts; i++) {
1da177e4 2701 struct uart_8250_port *up = &serial8250_ports[i];
dfe42443 2702 struct uart_port *port = &up->port;
1da177e4 2703
dfe42443
PG		 2704 port->line = i;
2705 spin_lock_init(&port->lock);
1da177e4
LT		 2706
2707 init_timer(&up->timer);
2708 up->timer.function = serial8250_timeout;
835d844d 2709 up->cur_iotype = 0xFF;
1da177e4
LT		 2710
2711 /*
2712 * ALPHA_KLUDGE_MCR needs to be killed.
2713 */
2714 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2715 up->mcr_force = ALPHA_KLUDGE_MCR;
2716
dfe42443 2717 port->ops = &serial8250_pops;
1da177e4
LT		 2718 }
2719
4c0ebb80
AGR		 2720 if (share_irqs)
2721 irqflag = IRQF_SHARED;
2722
44454bcd 2723 for (i = 0, up = serial8250_ports;
a61c2d78 2724 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4 2725 i++, up++) {
dfe42443
PG		 2726 struct uart_port *port = &up->port;
2727
2728 port->iobase = old_serial_port[i].port;
2729 port->irq = irq_canonicalize(old_serial_port[i].irq);
2730 port->irqflags = old_serial_port[i].irqflags;
2731 port->uartclk = old_serial_port[i].baud_base * 16;
2732 port->flags = old_serial_port[i].flags;
2733 port->hub6 = old_serial_port[i].hub6;
2734 port->membase = old_serial_port[i].iomem_base;
2735 port->iotype = old_serial_port[i].io_type;
2736 port->regshift = old_serial_port[i].iomem_reg_shift;
2737 set_io_from_upio(port);
2738 port->irqflags |= irqflag;
af7f3743
AC		 2739 if (serial8250_isa_config != NULL)
2740 serial8250_isa_config(i, &up->port, &up->capabilities);
2741
1da177e4
LT		 2742 }
2743}
2744
b5d228cc
SL		 2745static void
2746serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2747{
2748 up->port.type = type;
2749 up->port.fifosize = uart_config[type].fifo_size;
2750 up->capabilities = uart_config[type].flags;
2751 up->tx_loadsz = uart_config[type].tx_loadsz;
2752}
2753
1da177e4
LT		 2754static void __init
2755serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2756{
2757 int i;
2758
b8e7e40a
AC		 2759 for (i = 0; i < nr_uarts; i++) {
2760 struct uart_8250_port *up = &serial8250_ports[i];
b8e7e40a 2761
835d844d
SY		 2762 if (up->port.dev)
2763 continue;
1da177e4
LT		 2764
2765 up->port.dev = dev;
b5d228cc
SL		 2766
2767 if (up->port.flags & UPF_FIXED_TYPE)
2768 serial8250_init_fixed_type_port(up, up->port.type);
2769
1da177e4
LT		 2770 uart_add_one_port(drv, &up->port);
2771 }
2772}
2773
2774#ifdef CONFIG_SERIAL_8250_CONSOLE
2775
d358788f
RK		 2776static void serial8250_console_putchar(struct uart_port *port, int ch)
2777{
49d5741b
JI		 2778 struct uart_8250_port *up =
2779 container_of(port, struct uart_8250_port, port);
d358788f
RK		 2780
2781 wait_for_xmitr(up, UART_LSR_THRE);
4fd996a1 2782 serial_port_out(port, UART_TX, ch);
d358788f
RK		 2783}
2784
1da177e4
LT		 2785/*
2786 * Print a string to the serial port trying not to disturb
2787 * any possible real use of the port...
2788 *
2789 * The console_lock must be held when we get here.
2790 */
2791static void
2792serial8250_console_write(struct console *co, const char *s, unsigned int count)
2793{
2794 struct uart_8250_port *up = &serial8250_ports[co->index];
dfe42443 2795 struct uart_port *port = &up->port;
d8a5a8d7 2796 unsigned long flags;
1da177e4 2797 unsigned int ier;
d8a5a8d7 2798 int locked = 1;
1da177e4 2799
78512ece
AM		 2800 touch_nmi_watchdog();
2801
68aa2c0d 2802 local_irq_save(flags);
dfe42443 2803 if (port->sysrq) {
86b21199 2804 /* serial8250_handle_irq() already took the lock */
68aa2c0d
AM		 2805 locked = 0;
2806 } else if (oops_in_progress) {
dfe42443 2807 locked = spin_trylock(&port->lock);
d8a5a8d7 2808 } else
dfe42443 2809 spin_lock(&port->lock);
d8a5a8d7 2810
1da177e4 2811 /*
dc7bf130 2812 * First save the IER then disable the interrupts
1da177e4 2813 */
4fd996a1 2814 ier = serial_port_in(port, UART_IER);
1da177e4
LT		 2815
2816 if (up->capabilities & UART_CAP_UUE)
4fd996a1 2817 serial_port_out(port, UART_IER, UART_IER_UUE);
1da177e4 2818 else
4fd996a1 2819 serial_port_out(port, UART_IER, 0);
1da177e4 2820
dfe42443 2821 uart_console_write(port, s, count, serial8250_console_putchar);
1da177e4
LT		 2822
2823 /*
2824 * Finally, wait for transmitter to become empty
2825 * and restore the IER
2826 */
f91a3715 2827 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 2828 serial_port_out(port, UART_IER, ier);
d8a5a8d7 2829
ad4c2aa6
CM		 2830 /*
2831 * The receive handling will happen properly because the
2832 * receive ready bit will still be set; it is not cleared
2833 * on read. However, modem control will not, we must
2834 * call it if we have saved something in the saved flags
2835 * while processing with interrupts off.
2836 */
2837 if (up->msr_saved_flags)
3986fb2b 2838 serial8250_modem_status(up);
ad4c2aa6 2839
d8a5a8d7 2840 if (locked)
dfe42443 2841 spin_unlock(&port->lock);
68aa2c0d 2842 local_irq_restore(flags);
1da177e4
LT		 2843}
2844
118c0ace 2845static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2846{
2847 struct uart_port *port;
2848 int baud = 9600;
2849 int bits = 8;
2850 int parity = 'n';
2851 int flow = 'n';
2852
2853 /*
2854 * Check whether an invalid uart number has been specified, and
2855 * if so, search for the first available port that does have
2856 * console support.
2857 */
a61c2d78 2858 if (co->index >= nr_uarts)
1da177e4
LT		 2859 co->index = 0;
2860 port = &serial8250_ports[co->index].port;
2861 if (!port->iobase && !port->membase)
2862 return -ENODEV;
2863
2864 if (options)
2865 uart_parse_options(options, &baud, &parity, &bits, &flow);
2866
2867 return uart_set_options(port, co, baud, parity, bits, flow);
2868}
2869
b6b1d877 2870static int serial8250_console_early_setup(void)
18a8bd94
YL		 2871{
2872 return serial8250_find_port_for_earlycon();
2873}
2874
1da177e4
LT		 2875static struct console serial8250_console = {
2876 .name = "ttyS",
2877 .write = serial8250_console_write,
2878 .device = uart_console_device,
2879 .setup = serial8250_console_setup,
18a8bd94 2880 .early_setup = serial8250_console_early_setup,
a80c49db 2881 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1da177e4
LT		 2882 .index = -1,
2883 .data = &serial8250_reg,
2884};
2885
2886static int __init serial8250_console_init(void)
2887{
2888 serial8250_isa_init_ports();
2889 register_console(&serial8250_console);
2890 return 0;
2891}
2892console_initcall(serial8250_console_init);
2893
18a8bd94 2894int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2895{
2896 int line;
2897 struct uart_port *port;
2898
a61c2d78 2899 for (line = 0; line < nr_uarts; line++) {
1da177e4 2900 port = &serial8250_ports[line].port;
50aec3b5 2901 if (uart_match_port(p, port))
1da177e4
LT		 2902 return line;
2903 }
2904 return -ENODEV;
2905}
2906
1da177e4
LT		 2907#define SERIAL8250_CONSOLE &serial8250_console
2908#else
2909#define SERIAL8250_CONSOLE NULL
2910#endif
2911
2912static struct uart_driver serial8250_reg = {
2913 .owner = THIS_MODULE,
2914 .driver_name = "serial",
1da177e4
LT		 2915 .dev_name = "ttyS",
2916 .major = TTY_MAJOR,
2917 .minor = 64,
1da177e4
LT		 2918 .cons = SERIAL8250_CONSOLE,
2919};
2920
d856c666
RK		 2921/*
2922 * early_serial_setup - early registration for 8250 ports
2923 *
2924 * Setup an 8250 port structure prior to console initialisation. Use
2925 * after console initialisation will cause undefined behaviour.
2926 */
1da177e4
LT		 2927int __init early_serial_setup(struct uart_port *port)
2928{
b430428a
DD		 2929 struct uart_port *p;
2930
1da177e4
LT		 2931 if (port->line >= ARRAY_SIZE(serial8250_ports))
2932 return -ENODEV;
2933
2934 serial8250_isa_init_ports();
b430428a
DD		 2935 p = &serial8250_ports[port->line].port;
2936 p->iobase = port->iobase;
2937 p->membase = port->membase;
2938 p->irq = port->irq;
1c2f0493 2939 p->irqflags = port->irqflags;
b430428a
DD		 2940 p->uartclk = port->uartclk;
2941 p->fifosize = port->fifosize;
2942 p->regshift = port->regshift;
2943 p->iotype = port->iotype;
2944 p->flags = port->flags;
2945 p->mapbase = port->mapbase;
2946 p->private_data = port->private_data;
125c97d8
HD		 2947 p->type = port->type;
2948 p->line = port->line;
7d6a07d1
DD		 2949
2950 set_io_from_upio(p);
2951 if (port->serial_in)
2952 p->serial_in = port->serial_in;
2953 if (port->serial_out)
2954 p->serial_out = port->serial_out;
583d28e9
JI		 2955 if (port->handle_irq)
2956 p->handle_irq = port->handle_irq;
2957 else
2958 p->handle_irq = serial8250_default_handle_irq;
7d6a07d1 2959
1da177e4
LT		 2960 return 0;
2961}
2962
2963/**
2964 * serial8250_suspend_port - suspend one serial port
2965 * @line: serial line number
1da177e4
LT		 2966 *
2967 * Suspend one serial port.
2968 */
2969void serial8250_suspend_port(int line)
2970{
2971 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2972}
2973
2974/**
2975 * serial8250_resume_port - resume one serial port
2976 * @line: serial line number
1da177e4
LT		 2977 *
2978 * Resume one serial port.
2979 */
2980void serial8250_resume_port(int line)
2981{
b5b82df6 2982 struct uart_8250_port *up = &serial8250_ports[line];
dfe42443 2983 struct uart_port *port = &up->port;
b5b82df6
DW		 2984
2985 if (up->capabilities & UART_NATSEMI) {
b5b82df6 2986 /* Ensure it's still in high speed mode */
4fd996a1 2987 serial_port_out(port, UART_LCR, 0xE0);
b5b82df6 2988
0d0389e5 2989 ns16550a_goto_highspeed(up);
b5b82df6 2990
4fd996a1 2991 serial_port_out(port, UART_LCR, 0);
dfe42443 2992 port->uartclk = 921600*16;
b5b82df6 2993 }
dfe42443 2994 uart_resume_port(&serial8250_reg, port);
1da177e4
LT		 2995}
2996
2997/*
2998 * Register a set of serial devices attached to a platform device. The
2999 * list is terminated with a zero flags entry, which means we expect
3000 * all entries to have at least UPF_BOOT_AUTOCONF set.
3001 */
9671f099 3002static int serial8250_probe(struct platform_device *dev)
1da177e4 3003{
3ae5eaec 3004 struct plat_serial8250_port *p = dev->dev.platform_data;
2655a2c7 3005 struct uart_8250_port uart;
4c0ebb80 3006 int ret, i, irqflag = 0;
1da177e4 3007
2655a2c7 3008 memset(&uart, 0, sizeof(uart));
1da177e4 3009
4c0ebb80
AGR		 3010 if (share_irqs)
3011 irqflag = IRQF_SHARED;
3012
ec9f47cd 3013 for (i = 0; p && p->flags != 0; p++, i++) {
2655a2c7
AC		 3014 uart.port.iobase = p->iobase;
3015 uart.port.membase = p->membase;
3016 uart.port.irq = p->irq;
3017 uart.port.irqflags = p->irqflags;
3018 uart.port.uartclk = p->uartclk;
3019 uart.port.regshift = p->regshift;
3020 uart.port.iotype = p->iotype;
3021 uart.port.flags = p->flags;
3022 uart.port.mapbase = p->mapbase;
3023 uart.port.hub6 = p->hub6;
3024 uart.port.private_data = p->private_data;
3025 uart.port.type = p->type;
3026 uart.port.serial_in = p->serial_in;
3027 uart.port.serial_out = p->serial_out;
3028 uart.port.handle_irq = p->handle_irq;
3029 uart.port.handle_break = p->handle_break;
3030 uart.port.set_termios = p->set_termios;
3031 uart.port.pm = p->pm;
3032 uart.port.dev = &dev->dev;
3033 uart.port.irqflags |= irqflag;
3034 ret = serial8250_register_8250_port(&uart);
ec9f47cd 3035 if (ret < 0) {
3ae5eaec 3036 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 3037 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3038 p->iobase, (unsigned long long)p->mapbase,
3039 p->irq, ret);
ec9f47cd 3040 }
1da177e4
LT		 3041 }
3042 return 0;
3043}
3044
3045/*
3046 * Remove serial ports registered against a platform device.
3047 */
ae8d8a14 3048static int serial8250_remove(struct platform_device *dev)
1da177e4
LT		 3049{
3050 int i;
3051
a61c2d78 3052 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 3053 struct uart_8250_port *up = &serial8250_ports[i];
3054
3ae5eaec 3055 if (up->port.dev == &dev->dev)
1da177e4
LT		 3056 serial8250_unregister_port(i);
3057 }
3058 return 0;
3059}
3060
3ae5eaec 3061static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 3062{
3063 int i;
3064
1da177e4
LT		 3065 for (i = 0; i < UART_NR; i++) {
3066 struct uart_8250_port *up = &serial8250_ports[i];
3067
3ae5eaec 3068 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 3069 uart_suspend_port(&serial8250_reg, &up->port);
3070 }
3071
3072 return 0;
3073}
3074
3ae5eaec 3075static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 3076{
3077 int i;
3078
1da177e4
LT		 3079 for (i = 0; i < UART_NR; i++) {
3080 struct uart_8250_port *up = &serial8250_ports[i];
3081
3ae5eaec 3082 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 3083 serial8250_resume_port(i);
1da177e4
LT		 3084 }
3085
3086 return 0;
3087}
3088
3ae5eaec 3089static struct platform_driver serial8250_isa_driver = {
1da177e4 3090 .probe = serial8250_probe,
2d47b716 3091 .remove = serial8250_remove,
1da177e4
LT		 3092 .suspend = serial8250_suspend,
3093 .resume = serial8250_resume,
3ae5eaec
RK		 3094 .driver = {
3095 .name = "serial8250",
7493a314 3096 .owner = THIS_MODULE,
3ae5eaec 3097 },
1da177e4
LT		 3098};
3099
3100/*
3101 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3102 * in the table in include/asm/serial.h
3103 */
3104static struct platform_device *serial8250_isa_devs;
3105
3106/*
2655a2c7 3107 * serial8250_register_8250_port and serial8250_unregister_port allows for
1da177e4
LT		 3108 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3109 * modems and PCI multiport cards.
3110 */
f392ecfa 3111static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3112
3113static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3114{
3115 int i;
3116
3117 /*
3118 * First, find a port entry which matches.
3119 */
a61c2d78 3120 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3121 if (uart_match_port(&serial8250_ports[i].port, port))
3122 return &serial8250_ports[i];
3123
3124 /*
3125 * We didn't find a matching entry, so look for the first
3126 * free entry. We look for one which hasn't been previously
3127 * used (indicated by zero iobase).
3128 */
a61c2d78 3129 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3130 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3131 serial8250_ports[i].port.iobase == 0)
3132 return &serial8250_ports[i];
3133
3134 /*
3135 * That also failed. Last resort is to find any entry which
3136 * doesn't have a real port associated with it.
3137 */
a61c2d78 3138 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3139 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3140 return &serial8250_ports[i];
3141
3142 return NULL;
3143}
3144
3145/**
f73fa05b 3146 * serial8250_register_8250_port - register a serial port
58bcd332 3147 * @up: serial port template
1da177e4
LT		 3148 *
3149 * Configure the serial port specified by the request. If the
3150 * port exists and is in use, it is hung up and unregistered
3151 * first.
3152 *
3153 * The port is then probed and if necessary the IRQ is autodetected
3154 * If this fails an error is returned.
3155 *
3156 * On success the port is ready to use and the line number is returned.
3157 */
f73fa05b 3158int serial8250_register_8250_port(struct uart_8250_port *up)
1da177e4
LT		 3159{
3160 struct uart_8250_port *uart;
3161 int ret = -ENOSPC;
3162
f73fa05b 3163 if (up->port.uartclk == 0)
1da177e4
LT		 3164 return -EINVAL;
3165
f392ecfa 3166 mutex_lock(&serial_mutex);
1da177e4 3167
f73fa05b 3168 uart = serial8250_find_match_or_unused(&up->port);
65ecc9c0 3169 if (uart && uart->port.type != PORT_8250_CIR) {
835d844d
SY		 3170 if (uart->port.dev)
3171 uart_remove_one_port(&serial8250_reg, &uart->port);
1da177e4 3172
f73fa05b
MD		 3173 uart->port.iobase = up->port.iobase;
3174 uart->port.membase = up->port.membase;
3175 uart->port.irq = up->port.irq;
3176 uart->port.irqflags = up->port.irqflags;
3177 uart->port.uartclk = up->port.uartclk;
3178 uart->port.fifosize = up->port.fifosize;
3179 uart->port.regshift = up->port.regshift;
3180 uart->port.iotype = up->port.iotype;
3181 uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF;
a2d33d87 3182 uart->bugs = up->bugs;
f73fa05b
MD		 3183 uart->port.mapbase = up->port.mapbase;
3184 uart->port.private_data = up->port.private_data;
3185 if (up->port.dev)
3186 uart->port.dev = up->port.dev;
3187
3188 if (up->port.flags & UPF_FIXED_TYPE)
3189 serial8250_init_fixed_type_port(uart, up->port.type);
8e23fcc8 3190
7d6a07d1
DD		 3191 set_io_from_upio(&uart->port);
3192 /* Possibly override default I/O functions. */
f73fa05b
MD		 3193 if (up->port.serial_in)
3194 uart->port.serial_in = up->port.serial_in;
3195 if (up->port.serial_out)
3196 uart->port.serial_out = up->port.serial_out;
3197 if (up->port.handle_irq)
3198 uart->port.handle_irq = up->port.handle_irq;
235dae5d 3199 /* Possibly override set_termios call */
f73fa05b
MD		 3200 if (up->port.set_termios)
3201 uart->port.set_termios = up->port.set_termios;
3202 if (up->port.pm)
3203 uart->port.pm = up->port.pm;
3204 if (up->port.handle_break)
3205 uart->port.handle_break = up->port.handle_break;
3206 if (up->dl_read)
3207 uart->dl_read = up->dl_read;
3208 if (up->dl_write)
3209 uart->dl_write = up->dl_write;
1da177e4 3210
af7f3743
AC		 3211 if (serial8250_isa_config != NULL)
3212 serial8250_isa_config(0, &uart->port,
3213 &uart->capabilities);
3214
1da177e4
LT		 3215 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3216 if (ret == 0)
3217 ret = uart->port.line;
3218 }
f392ecfa 3219 mutex_unlock(&serial_mutex);
1da177e4
LT		 3220
3221 return ret;
3222}
f73fa05b
MD		 3223EXPORT_SYMBOL(serial8250_register_8250_port);
3224
1da177e4
LT		 3225/**
3226 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3227 * @line: serial line number
3228 *
3229 * Remove one serial port. This may not be called from interrupt
3230 * context. We hand the port back to the our control.
3231 */
3232void serial8250_unregister_port(int line)
3233{
3234 struct uart_8250_port *uart = &serial8250_ports[line];
3235
f392ecfa 3236 mutex_lock(&serial_mutex);
1da177e4
LT		 3237 uart_remove_one_port(&serial8250_reg, &uart->port);
3238 if (serial8250_isa_devs) {
3239 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3240 uart->port.type = PORT_UNKNOWN;
3241 uart->port.dev = &serial8250_isa_devs->dev;
cb01ece3 3242 uart->capabilities = uart_config[uart->port.type].flags;
1da177e4
LT		 3243 uart_add_one_port(&serial8250_reg, &uart->port);
3244 } else {
3245 uart->port.dev = NULL;
3246 }
f392ecfa 3247 mutex_unlock(&serial_mutex);
1da177e4
LT		 3248}
3249EXPORT_SYMBOL(serial8250_unregister_port);
3250
3251static int __init serial8250_init(void)
3252{
25db8ad5 3253 int ret;
1da177e4 3254
835d844d 3255 serial8250_isa_init_ports();
a61c2d78 3256
f1fb9bb8 3257 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3258 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3259 share_irqs ? "en" : "dis");
3260
b70ac771
DM		 3261#ifdef CONFIG_SPARC
3262 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3263#else
3264 serial8250_reg.nr = UART_NR;
1da177e4 3265 ret = uart_register_driver(&serial8250_reg);
b70ac771 3266#endif
1da177e4
LT		 3267 if (ret)
3268 goto out;
3269
835d844d
SY		 3270 ret = serial8250_pnp_init();
3271 if (ret)
3272 goto unreg_uart_drv;
3273
7493a314
DT		 3274 serial8250_isa_devs = platform_device_alloc("serial8250",
3275 PLAT8250_DEV_LEGACY);
3276 if (!serial8250_isa_devs) {
3277 ret = -ENOMEM;
835d844d 3278 goto unreg_pnp;
1da177e4
LT		 3279 }
3280
7493a314
DT		 3281 ret = platform_device_add(serial8250_isa_devs);
3282 if (ret)
3283 goto put_dev;
3284
1da177e4
LT		 3285 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3286
bc965a7f
RK		 3287 ret = platform_driver_register(&serial8250_isa_driver);
3288 if (ret == 0)
3289 goto out;
1da177e4 3290
bc965a7f 3291 platform_device_del(serial8250_isa_devs);
25db8ad5 3292put_dev:
7493a314 3293 platform_device_put(serial8250_isa_devs);
835d844d
SY		 3294unreg_pnp:
3295 serial8250_pnp_exit();
25db8ad5 3296unreg_uart_drv:
b70ac771
DM		 3297#ifdef CONFIG_SPARC
3298 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3299#else
1da177e4 3300 uart_unregister_driver(&serial8250_reg);
b70ac771 3301#endif
25db8ad5 3302out:
1da177e4
LT		 3303 return ret;
3304}
3305
3306static void __exit serial8250_exit(void)
3307{
3308 struct platform_device *isa_dev = serial8250_isa_devs;
3309
3310 /*
3311 * This tells serial8250_unregister_port() not to re-register
3312 * the ports (thereby making serial8250_isa_driver permanently
3313 * in use.)
3314 */
3315 serial8250_isa_devs = NULL;
3316
3ae5eaec 3317 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3318 platform_device_unregister(isa_dev);
3319
835d844d
SY		 3320 serial8250_pnp_exit();
3321
b70ac771
DM		 3322#ifdef CONFIG_SPARC
3323 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3324#else
1da177e4 3325 uart_unregister_driver(&serial8250_reg);
b70ac771 3326#endif
1da177e4
LT		 3327}
3328
3329module_init(serial8250_init);
3330module_exit(serial8250_exit);
3331
3332EXPORT_SYMBOL(serial8250_suspend_port);
3333EXPORT_SYMBOL(serial8250_resume_port);
3334
3335MODULE_LICENSE("GPL");
d87a6d95 3336MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3337
3338module_param(share_irqs, uint, 0644);
3339MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3340 " (unsafe)");
3341
a61c2d78
DJ		 3342module_param(nr_uarts, uint, 0644);
3343MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3344
d41a4b51
CE		 3345module_param(skip_txen_test, uint, 0644);
3346MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3347
1da177e4
LT		 3348#ifdef CONFIG_SERIAL_8250_RSA
3349module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3350MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3351#endif
3352MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Linux kernel - Deliverables
This page took 0.9095 seconds and 5 git commands to generate.