Commit | Line | Data |
---|---|---|
194de561 | 1 | /* |
1ba7a3ee | 2 | * Blackfin On-Chip Serial Driver |
194de561 | 3 | * |
b06d2f20 | 4 | * Copyright 2006-2011 Analog Devices Inc. |
194de561 | 5 | * |
1ba7a3ee | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
194de561 | 7 | * |
1ba7a3ee | 8 | * Licensed under the GPL-2 or later. |
194de561 BW |
9 | */ |
10 | ||
11 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
12 | #define SUPPORT_SYSRQ | |
13 | #endif | |
14 | ||
57afb399 SZ |
15 | #define DRIVER_NAME "bfin-uart" |
16 | #define pr_fmt(fmt) DRIVER_NAME ": " fmt | |
17 | ||
194de561 BW |
18 | #include <linux/module.h> |
19 | #include <linux/ioport.h> | |
5a0e3ad6 | 20 | #include <linux/gfp.h> |
599b714c | 21 | #include <linux/io.h> |
194de561 BW |
22 | #include <linux/init.h> |
23 | #include <linux/console.h> | |
24 | #include <linux/sysrq.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/tty.h> | |
27 | #include <linux/tty_flip.h> | |
28 | #include <linux/serial_core.h> | |
57afb399 SZ |
29 | #include <linux/gpio.h> |
30 | #include <linux/irq.h> | |
474f1a66 | 31 | #include <linux/kgdb.h> |
57afb399 SZ |
32 | #include <linux/slab.h> |
33 | #include <linux/dma-mapping.h> | |
194de561 | 34 | |
57afb399 | 35 | #include <asm/portmux.h> |
194de561 | 36 | #include <asm/cacheflush.h> |
57afb399 | 37 | #include <asm/dma.h> |
57afb399 | 38 | #include <asm/bfin_serial.h> |
194de561 | 39 | |
607c268e MF |
40 | #ifdef CONFIG_SERIAL_BFIN_MODULE |
41 | # undef CONFIG_EARLY_PRINTK | |
42 | #endif | |
43 | ||
0271edd4 MF |
44 | #ifdef CONFIG_SERIAL_BFIN_MODULE |
45 | # undef CONFIG_EARLY_PRINTK | |
46 | #endif | |
47 | ||
194de561 | 48 | /* UART name and device definitions */ |
57afb399 | 49 | #define BFIN_SERIAL_DEV_NAME "ttyBF" |
194de561 BW |
50 | #define BFIN_SERIAL_MAJOR 204 |
51 | #define BFIN_SERIAL_MINOR 64 | |
52 | ||
57afb399 | 53 | static struct bfin_serial_port *bfin_serial_ports[BFIN_UART_NR_PORTS]; |
c9607ecc | 54 | |
52e15f0e SZ |
55 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
56 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
57 | ||
58 | # ifndef CONFIG_SERIAL_BFIN_PIO | |
59 | # error KGDB only support UART in PIO mode. | |
60 | # endif | |
61 | ||
62 | static int kgdboc_port_line; | |
63 | static int kgdboc_break_enabled; | |
64 | #endif | |
194de561 BW |
65 | /* |
66 | * Setup for console. Argument comes from the menuconfig | |
67 | */ | |
68 | #define DMA_RX_XCOUNT 512 | |
69 | #define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT) | |
70 | ||
0aef4564 | 71 | #define DMA_RX_FLUSH_JIFFIES (HZ / 50) |
194de561 BW |
72 | |
73 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
74 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart); | |
75 | #else | |
194de561 | 76 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart); |
194de561 BW |
77 | #endif |
78 | ||
80d5c474 GY |
79 | static void bfin_serial_reset_irda(struct uart_port *port); |
80 | ||
d307d36a SZ |
81 | #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \ |
82 | defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS) | |
83 | static unsigned int bfin_serial_get_mctrl(struct uart_port *port) | |
84 | { | |
85 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
86 | if (uart->cts_pin < 0) | |
87 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
88 | ||
89 | /* CTS PIN is negative assertive. */ | |
90 | if (UART_GET_CTS(uart)) | |
91 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
92 | else | |
93 | return TIOCM_DSR | TIOCM_CAR; | |
94 | } | |
95 | ||
96 | static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
97 | { | |
98 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
99 | if (uart->rts_pin < 0) | |
100 | return; | |
101 | ||
102 | /* RTS PIN is negative assertive. */ | |
103 | if (mctrl & TIOCM_RTS) | |
104 | UART_ENABLE_RTS(uart); | |
105 | else | |
106 | UART_DISABLE_RTS(uart); | |
107 | } | |
108 | ||
109 | /* | |
110 | * Handle any change of modem status signal. | |
111 | */ | |
112 | static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id) | |
113 | { | |
114 | struct bfin_serial_port *uart = dev_id; | |
64851636 | 115 | unsigned int status = bfin_serial_get_mctrl(&uart->port); |
d307d36a | 116 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS |
64851636 SZ |
117 | struct tty_struct *tty = uart->port.state->port.tty; |
118 | ||
d307d36a | 119 | UART_CLEAR_SCTS(uart); |
64851636 SZ |
120 | if (tty->hw_stopped) { |
121 | if (status) { | |
122 | tty->hw_stopped = 0; | |
123 | uart_write_wakeup(&uart->port); | |
124 | } | |
125 | } else { | |
126 | if (!status) | |
127 | tty->hw_stopped = 1; | |
128 | } | |
d307d36a | 129 | #endif |
f5b6940c | 130 | uart_handle_cts_change(&uart->port, status & TIOCM_CTS); |
d307d36a SZ |
131 | |
132 | return IRQ_HANDLED; | |
133 | } | |
134 | #else | |
135 | static unsigned int bfin_serial_get_mctrl(struct uart_port *port) | |
136 | { | |
137 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
138 | } | |
139 | ||
140 | static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
141 | { | |
142 | } | |
143 | #endif | |
144 | ||
194de561 BW |
145 | /* |
146 | * interrupts are disabled on entry | |
147 | */ | |
148 | static void bfin_serial_stop_tx(struct uart_port *port) | |
149 | { | |
150 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
68a784cb | 151 | #ifdef CONFIG_SERIAL_BFIN_DMA |
ebd2c8f6 | 152 | struct circ_buf *xmit = &uart->port.state->xmit; |
68a784cb | 153 | #endif |
194de561 | 154 | |
f4d640c9 | 155 | while (!(UART_GET_LSR(uart) & TEMT)) |
0711d857 | 156 | cpu_relax(); |
f4d640c9 | 157 | |
194de561 BW |
158 | #ifdef CONFIG_SERIAL_BFIN_DMA |
159 | disable_dma(uart->tx_dma_channel); | |
0711d857 SZ |
160 | xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1); |
161 | uart->port.icount.tx += uart->tx_count; | |
162 | uart->tx_count = 0; | |
163 | uart->tx_done = 1; | |
f4d640c9 | 164 | #else |
b06d2f20 | 165 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF60x) |
f4d640c9 RH |
166 | /* Clear TFI bit */ |
167 | UART_PUT_LSR(uart, TFI); | |
194de561 | 168 | #endif |
89bf6dc5 | 169 | UART_CLEAR_IER(uart, ETBEI); |
f4d640c9 | 170 | #endif |
194de561 BW |
171 | } |
172 | ||
173 | /* | |
174 | * port is locked and interrupts are disabled | |
175 | */ | |
176 | static void bfin_serial_start_tx(struct uart_port *port) | |
177 | { | |
178 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
ebd2c8f6 | 179 | struct tty_struct *tty = uart->port.state->port.tty; |
80d5c474 GY |
180 | |
181 | /* | |
182 | * To avoid losting RX interrupt, we reset IR function | |
183 | * before sending data. | |
184 | */ | |
adc8d746 | 185 | if (tty->termios.c_line == N_IRDA) |
80d5c474 | 186 | bfin_serial_reset_irda(port); |
194de561 BW |
187 | |
188 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
0711d857 SZ |
189 | if (uart->tx_done) |
190 | bfin_serial_dma_tx_chars(uart); | |
f4d640c9 | 191 | #else |
f4d640c9 | 192 | UART_SET_IER(uart, ETBEI); |
a359cca7 | 193 | bfin_serial_tx_chars(uart); |
f4d640c9 | 194 | #endif |
194de561 BW |
195 | } |
196 | ||
197 | /* | |
198 | * Interrupts are enabled | |
199 | */ | |
200 | static void bfin_serial_stop_rx(struct uart_port *port) | |
201 | { | |
202 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
52e15f0e | 203 | |
f4d640c9 | 204 | UART_CLEAR_IER(uart, ERBFI); |
194de561 BW |
205 | } |
206 | ||
207 | /* | |
208 | * Set the modem control timer to fire immediately. | |
209 | */ | |
210 | static void bfin_serial_enable_ms(struct uart_port *port) | |
211 | { | |
212 | } | |
213 | ||
474f1a66 | 214 | |
50e2e15a | 215 | #if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO) |
8851c71e MF |
216 | # define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold) |
217 | # define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v)) | |
218 | #else | |
219 | # define UART_GET_ANOMALY_THRESHOLD(uart) 0 | |
220 | # define UART_SET_ANOMALY_THRESHOLD(uart, v) | |
221 | #endif | |
222 | ||
194de561 | 223 | #ifdef CONFIG_SERIAL_BFIN_PIO |
194de561 BW |
224 | static void bfin_serial_rx_chars(struct bfin_serial_port *uart) |
225 | { | |
194de561 | 226 | unsigned int status, ch, flg; |
8851c71e | 227 | static struct timeval anomaly_start = { .tv_sec = 0 }; |
194de561 | 228 | |
759eb040 | 229 | status = UART_GET_LSR(uart); |
0bcfd70e MF |
230 | UART_CLEAR_LSR(uart); |
231 | ||
bb7e58f8 SZ |
232 | ch = UART_GET_CHAR(uart); |
233 | uart->port.icount.rx++; | |
194de561 | 234 | |
52e15f0e SZ |
235 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
236 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
cdc592d5 SZ |
237 | if (kgdb_connected && kgdboc_port_line == uart->port.line |
238 | && kgdboc_break_enabled) | |
52e15f0e SZ |
239 | if (ch == 0x3) {/* Ctrl + C */ |
240 | kgdb_breakpoint(); | |
474f1a66 | 241 | return; |
474f1a66 | 242 | } |
52e15f0e | 243 | |
2e124b4a | 244 | if (!uart->port.state) |
52e15f0e | 245 | return; |
474f1a66 | 246 | #endif |
50e2e15a | 247 | if (ANOMALY_05000363) { |
8851c71e MF |
248 | /* The BF533 (and BF561) family of processors have a nice anomaly |
249 | * where they continuously generate characters for a "single" break. | |
bbf275f0 | 250 | * We have to basically ignore this flood until the "next" valid |
8851c71e MF |
251 | * character comes across. Due to the nature of the flood, it is |
252 | * not possible to reliably catch bytes that are sent too quickly | |
253 | * after this break. So application code talking to the Blackfin | |
254 | * which sends a break signal must allow at least 1.5 character | |
255 | * times after the end of the break for things to stabilize. This | |
256 | * timeout was picked as it must absolutely be larger than 1 | |
257 | * character time +/- some percent. So 1.5 sounds good. All other | |
258 | * Blackfin families operate properly. Woo. | |
bbf275f0 | 259 | */ |
8851c71e MF |
260 | if (anomaly_start.tv_sec) { |
261 | struct timeval curr; | |
262 | suseconds_t usecs; | |
263 | ||
264 | if ((~ch & (~ch + 1)) & 0xff) | |
265 | goto known_good_char; | |
266 | ||
267 | do_gettimeofday(&curr); | |
268 | if (curr.tv_sec - anomaly_start.tv_sec > 1) | |
269 | goto known_good_char; | |
270 | ||
271 | usecs = 0; | |
272 | if (curr.tv_sec != anomaly_start.tv_sec) | |
273 | usecs += USEC_PER_SEC; | |
274 | usecs += curr.tv_usec - anomaly_start.tv_usec; | |
275 | ||
276 | if (usecs > UART_GET_ANOMALY_THRESHOLD(uart)) | |
277 | goto known_good_char; | |
278 | ||
279 | if (ch) | |
280 | anomaly_start.tv_sec = 0; | |
281 | else | |
282 | anomaly_start = curr; | |
283 | ||
284 | return; | |
285 | ||
286 | known_good_char: | |
e482a237 | 287 | status &= ~BI; |
8851c71e | 288 | anomaly_start.tv_sec = 0; |
bbf275f0 | 289 | } |
194de561 | 290 | } |
194de561 BW |
291 | |
292 | if (status & BI) { | |
50e2e15a | 293 | if (ANOMALY_05000363) |
8851c71e MF |
294 | if (bfin_revid() < 5) |
295 | do_gettimeofday(&anomaly_start); | |
194de561 BW |
296 | uart->port.icount.brk++; |
297 | if (uart_handle_break(&uart->port)) | |
298 | goto ignore_char; | |
9808901b | 299 | status &= ~(PE | FE); |
2ac5ee47 MF |
300 | } |
301 | if (status & PE) | |
194de561 | 302 | uart->port.icount.parity++; |
2ac5ee47 | 303 | if (status & OE) |
194de561 | 304 | uart->port.icount.overrun++; |
2ac5ee47 | 305 | if (status & FE) |
194de561 | 306 | uart->port.icount.frame++; |
2ac5ee47 MF |
307 | |
308 | status &= uart->port.read_status_mask; | |
309 | ||
310 | if (status & BI) | |
311 | flg = TTY_BREAK; | |
312 | else if (status & PE) | |
313 | flg = TTY_PARITY; | |
314 | else if (status & FE) | |
315 | flg = TTY_FRAME; | |
316 | else | |
194de561 BW |
317 | flg = TTY_NORMAL; |
318 | ||
319 | if (uart_handle_sysrq_char(&uart->port, ch)) | |
320 | goto ignore_char; | |
194de561 | 321 | |
2ac5ee47 MF |
322 | uart_insert_char(&uart->port, status, OE, ch, flg); |
323 | ||
324 | ignore_char: | |
2e124b4a | 325 | tty_flip_buffer_push(&uart->port.state->port); |
194de561 BW |
326 | } |
327 | ||
328 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart) | |
329 | { | |
ebd2c8f6 | 330 | struct circ_buf *xmit = &uart->port.state->xmit; |
194de561 | 331 | |
194de561 | 332 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { |
b06d2f20 | 333 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF60x) |
5ffdeea2 SZ |
334 | /* Clear TFI bit */ |
335 | UART_PUT_LSR(uart, TFI); | |
336 | #endif | |
0efa4f2c SZ |
337 | /* Anomaly notes: |
338 | * 05000215 - we always clear ETBEI within last UART TX | |
339 | * interrupt to end a string. It is always set | |
340 | * when start a new tx. | |
341 | */ | |
5ffdeea2 | 342 | UART_CLEAR_IER(uart, ETBEI); |
194de561 BW |
343 | return; |
344 | } | |
345 | ||
f30ac0ce SZ |
346 | if (uart->port.x_char) { |
347 | UART_PUT_CHAR(uart, uart->port.x_char); | |
348 | uart->port.icount.tx++; | |
349 | uart->port.x_char = 0; | |
350 | } | |
351 | ||
759eb040 SZ |
352 | while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) { |
353 | UART_PUT_CHAR(uart, xmit->buf[xmit->tail]); | |
354 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
355 | uart->port.icount.tx++; | |
759eb040 | 356 | } |
194de561 BW |
357 | |
358 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
359 | uart_write_wakeup(&uart->port); | |
194de561 BW |
360 | } |
361 | ||
5c4e472b AL |
362 | static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id) |
363 | { | |
364 | struct bfin_serial_port *uart = dev_id; | |
365 | ||
0bcfd70e | 366 | while (UART_GET_LSR(uart) & DR) |
f4d640c9 | 367 | bfin_serial_rx_chars(uart); |
759eb040 | 368 | |
5c4e472b AL |
369 | return IRQ_HANDLED; |
370 | } | |
371 | ||
372 | static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id) | |
194de561 BW |
373 | { |
374 | struct bfin_serial_port *uart = dev_id; | |
194de561 | 375 | |
f4d640c9 | 376 | spin_lock(&uart->port.lock); |
0bcfd70e | 377 | if (UART_GET_LSR(uart) & THRE) |
f4d640c9 | 378 | bfin_serial_tx_chars(uart); |
f4d640c9 | 379 | spin_unlock(&uart->port.lock); |
759eb040 | 380 | |
194de561 BW |
381 | return IRQ_HANDLED; |
382 | } | |
4cb4f22b | 383 | #endif |
194de561 | 384 | |
194de561 BW |
385 | #ifdef CONFIG_SERIAL_BFIN_DMA |
386 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart) | |
387 | { | |
ebd2c8f6 | 388 | struct circ_buf *xmit = &uart->port.state->xmit; |
194de561 | 389 | |
194de561 BW |
390 | uart->tx_done = 0; |
391 | ||
1b73351c | 392 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { |
0711d857 | 393 | uart->tx_count = 0; |
1b73351c SZ |
394 | uart->tx_done = 1; |
395 | return; | |
396 | } | |
397 | ||
194de561 BW |
398 | if (uart->port.x_char) { |
399 | UART_PUT_CHAR(uart, uart->port.x_char); | |
400 | uart->port.icount.tx++; | |
401 | uart->port.x_char = 0; | |
194de561 | 402 | } |
1b73351c | 403 | |
194de561 BW |
404 | uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE); |
405 | if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail)) | |
406 | uart->tx_count = UART_XMIT_SIZE - xmit->tail; | |
407 | blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail), | |
408 | (unsigned long)(xmit->buf+xmit->tail+uart->tx_count)); | |
409 | set_dma_config(uart->tx_dma_channel, | |
410 | set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP, | |
411 | INTR_ON_BUF, | |
412 | DIMENSION_LINEAR, | |
2047e40d MH |
413 | DATA_SIZE_8, |
414 | DMA_SYNC_RESTART)); | |
194de561 BW |
415 | set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail)); |
416 | set_dma_x_count(uart->tx_dma_channel, uart->tx_count); | |
417 | set_dma_x_modify(uart->tx_dma_channel, 1); | |
f9d36da9 | 418 | SSYNC(); |
194de561 | 419 | enable_dma(uart->tx_dma_channel); |
99ee7b5f | 420 | |
f4d640c9 | 421 | UART_SET_IER(uart, ETBEI); |
194de561 BW |
422 | } |
423 | ||
2ac5ee47 | 424 | static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart) |
194de561 | 425 | { |
194de561 BW |
426 | int i, flg, status; |
427 | ||
428 | status = UART_GET_LSR(uart); | |
0bcfd70e MF |
429 | UART_CLEAR_LSR(uart); |
430 | ||
56f5de8f SZ |
431 | uart->port.icount.rx += |
432 | CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail, | |
433 | UART_XMIT_SIZE); | |
194de561 BW |
434 | |
435 | if (status & BI) { | |
436 | uart->port.icount.brk++; | |
437 | if (uart_handle_break(&uart->port)) | |
438 | goto dma_ignore_char; | |
9808901b | 439 | status &= ~(PE | FE); |
2ac5ee47 MF |
440 | } |
441 | if (status & PE) | |
194de561 | 442 | uart->port.icount.parity++; |
2ac5ee47 | 443 | if (status & OE) |
194de561 | 444 | uart->port.icount.overrun++; |
2ac5ee47 | 445 | if (status & FE) |
194de561 | 446 | uart->port.icount.frame++; |
2ac5ee47 MF |
447 | |
448 | status &= uart->port.read_status_mask; | |
449 | ||
450 | if (status & BI) | |
451 | flg = TTY_BREAK; | |
452 | else if (status & PE) | |
453 | flg = TTY_PARITY; | |
454 | else if (status & FE) | |
455 | flg = TTY_FRAME; | |
456 | else | |
194de561 BW |
457 | flg = TTY_NORMAL; |
458 | ||
8c4210e3 | 459 | for (i = uart->rx_dma_buf.tail; ; i++) { |
56f5de8f SZ |
460 | if (i >= UART_XMIT_SIZE) |
461 | i = 0; | |
8c4210e3 SZ |
462 | if (i == uart->rx_dma_buf.head) |
463 | break; | |
56f5de8f SZ |
464 | if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i])) |
465 | uart_insert_char(&uart->port, status, OE, | |
466 | uart->rx_dma_buf.buf[i], flg); | |
194de561 | 467 | } |
2ac5ee47 MF |
468 | |
469 | dma_ignore_char: | |
2e124b4a | 470 | tty_flip_buffer_push(&uart->port.state->port); |
194de561 BW |
471 | } |
472 | ||
473 | void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart) | |
474 | { | |
59e4e3e6 | 475 | int x_pos, pos; |
9642dbe7 | 476 | unsigned long flags; |
68a784cb | 477 | |
9642dbe7 | 478 | spin_lock_irqsave(&uart->rx_lock, flags); |
194de561 | 479 | |
8516c568 SZ |
480 | /* 2D DMA RX buffer ring is used. Because curr_y_count and |
481 | * curr_x_count can't be read as an atomic operation, | |
482 | * curr_y_count should be read before curr_x_count. When | |
483 | * curr_x_count is read, curr_y_count may already indicate | |
484 | * next buffer line. But, the position calculated here is | |
485 | * still indicate the old line. The wrong position data may | |
486 | * be smaller than current buffer tail, which cause garbages | |
487 | * are received if it is not prohibit. | |
488 | */ | |
56f5de8f SZ |
489 | uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel); |
490 | x_pos = get_dma_curr_xcount(uart->rx_dma_channel); | |
491 | uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows; | |
35ff6935 | 492 | if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0) |
56f5de8f SZ |
493 | uart->rx_dma_nrows = 0; |
494 | x_pos = DMA_RX_XCOUNT - x_pos; | |
194de561 BW |
495 | if (x_pos == DMA_RX_XCOUNT) |
496 | x_pos = 0; | |
497 | ||
498 | pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos; | |
8516c568 SZ |
499 | /* Ignore receiving data if new position is in the same line of |
500 | * current buffer tail and small. | |
501 | */ | |
502 | if (pos > uart->rx_dma_buf.tail || | |
503 | uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) { | |
56f5de8f | 504 | uart->rx_dma_buf.head = pos; |
194de561 | 505 | bfin_serial_dma_rx_chars(uart); |
56f5de8f | 506 | uart->rx_dma_buf.tail = uart->rx_dma_buf.head; |
194de561 | 507 | } |
0aef4564 | 508 | |
9642dbe7 | 509 | spin_unlock_irqrestore(&uart->rx_lock, flags); |
68a784cb | 510 | |
0a278423 | 511 | mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES); |
194de561 BW |
512 | } |
513 | ||
514 | static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id) | |
515 | { | |
516 | struct bfin_serial_port *uart = dev_id; | |
ebd2c8f6 | 517 | struct circ_buf *xmit = &uart->port.state->xmit; |
194de561 BW |
518 | |
519 | spin_lock(&uart->port.lock); | |
520 | if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) { | |
194de561 | 521 | disable_dma(uart->tx_dma_channel); |
0711d857 | 522 | clear_dma_irqstat(uart->tx_dma_channel); |
0efa4f2c SZ |
523 | /* Anomaly notes: |
524 | * 05000215 - we always clear ETBEI within last UART TX | |
525 | * interrupt to end a string. It is always set | |
526 | * when start a new tx. | |
527 | */ | |
f4d640c9 | 528 | UART_CLEAR_IER(uart, ETBEI); |
0711d857 | 529 | uart->port.icount.tx += uart->tx_count; |
239c25b1 | 530 | if (!(xmit->tail == 0 && xmit->head == 0)) { |
60f4b002 | 531 | xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1); |
1b73351c | 532 | |
60f4b002 SZ |
533 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
534 | uart_write_wakeup(&uart->port); | |
535 | } | |
56f5de8f | 536 | |
1b73351c | 537 | bfin_serial_dma_tx_chars(uart); |
194de561 BW |
538 | } |
539 | ||
540 | spin_unlock(&uart->port.lock); | |
541 | return IRQ_HANDLED; | |
542 | } | |
543 | ||
544 | static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id) | |
545 | { | |
546 | struct bfin_serial_port *uart = dev_id; | |
3c2d0ed2 | 547 | unsigned int irqstat; |
35ff6935 | 548 | int x_pos, pos; |
0711d857 | 549 | |
0f66e50a | 550 | spin_lock(&uart->rx_lock); |
194de561 BW |
551 | irqstat = get_dma_curr_irqstat(uart->rx_dma_channel); |
552 | clear_dma_irqstat(uart->rx_dma_channel); | |
8516c568 SZ |
553 | |
554 | uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel); | |
35ff6935 | 555 | x_pos = get_dma_curr_xcount(uart->rx_dma_channel); |
8516c568 | 556 | uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows; |
35ff6935 | 557 | if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0) |
8516c568 SZ |
558 | uart->rx_dma_nrows = 0; |
559 | ||
560 | pos = uart->rx_dma_nrows * DMA_RX_XCOUNT; | |
561 | if (pos > uart->rx_dma_buf.tail || | |
562 | uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) { | |
563 | uart->rx_dma_buf.head = pos; | |
564 | bfin_serial_dma_rx_chars(uart); | |
565 | uart->rx_dma_buf.tail = uart->rx_dma_buf.head; | |
566 | } | |
567 | ||
0f66e50a | 568 | spin_unlock(&uart->rx_lock); |
0aef4564 | 569 | |
194de561 BW |
570 | return IRQ_HANDLED; |
571 | } | |
572 | #endif | |
573 | ||
574 | /* | |
575 | * Return TIOCSER_TEMT when transmitter is not busy. | |
576 | */ | |
577 | static unsigned int bfin_serial_tx_empty(struct uart_port *port) | |
578 | { | |
579 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
3c2d0ed2 | 580 | unsigned int lsr; |
194de561 BW |
581 | |
582 | lsr = UART_GET_LSR(uart); | |
583 | if (lsr & TEMT) | |
584 | return TIOCSER_TEMT; | |
585 | else | |
586 | return 0; | |
587 | } | |
588 | ||
194de561 BW |
589 | static void bfin_serial_break_ctl(struct uart_port *port, int break_state) |
590 | { | |
cf686762 | 591 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; |
59bd234b | 592 | u32 lcr = UART_GET_LCR(uart); |
cf686762 MF |
593 | if (break_state) |
594 | lcr |= SB; | |
595 | else | |
596 | lcr &= ~SB; | |
597 | UART_PUT_LCR(uart, lcr); | |
598 | SSYNC(); | |
194de561 BW |
599 | } |
600 | ||
601 | static int bfin_serial_startup(struct uart_port *port) | |
602 | { | |
603 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
604 | ||
605 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
606 | dma_addr_t dma_handle; | |
607 | ||
608 | if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) { | |
609 | printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n"); | |
610 | return -EBUSY; | |
611 | } | |
612 | ||
613 | if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) { | |
614 | printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n"); | |
615 | free_dma(uart->rx_dma_channel); | |
616 | return -EBUSY; | |
617 | } | |
618 | ||
619 | set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart); | |
620 | set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart); | |
621 | ||
622 | uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA); | |
623 | uart->rx_dma_buf.head = 0; | |
624 | uart->rx_dma_buf.tail = 0; | |
625 | uart->rx_dma_nrows = 0; | |
626 | ||
627 | set_dma_config(uart->rx_dma_channel, | |
628 | set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO, | |
629 | INTR_ON_ROW, DIMENSION_2D, | |
2047e40d MH |
630 | DATA_SIZE_8, |
631 | DMA_SYNC_RESTART)); | |
194de561 BW |
632 | set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT); |
633 | set_dma_x_modify(uart->rx_dma_channel, 1); | |
634 | set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT); | |
635 | set_dma_y_modify(uart->rx_dma_channel, 1); | |
636 | set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf); | |
637 | enable_dma(uart->rx_dma_channel); | |
638 | ||
639 | uart->rx_dma_timer.data = (unsigned long)(uart); | |
640 | uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout; | |
641 | uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES; | |
642 | add_timer(&(uart->rx_dma_timer)); | |
643 | #else | |
6f95570e | 644 | # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
52e15f0e SZ |
645 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) |
646 | if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled) | |
647 | kgdboc_break_enabled = 0; | |
648 | else { | |
649 | # endif | |
9cfb5c05 | 650 | if (request_irq(uart->rx_irq, bfin_serial_rx_int, 0, |
a359cca7 | 651 | "BFIN_UART_RX", uart)) { |
194de561 BW |
652 | printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n"); |
653 | return -EBUSY; | |
654 | } | |
655 | ||
656 | if (request_irq | |
9cfb5c05 | 657 | (uart->tx_irq, bfin_serial_tx_int, 0, |
194de561 BW |
658 | "BFIN_UART_TX", uart)) { |
659 | printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n"); | |
47918f05 | 660 | free_irq(uart->rx_irq, uart); |
194de561 BW |
661 | return -EBUSY; |
662 | } | |
ab2375f2 SZ |
663 | |
664 | # ifdef CONFIG_BF54x | |
665 | { | |
b6100992 SZ |
666 | /* |
667 | * UART2 and UART3 on BF548 share interrupt PINs and DMA | |
668 | * controllers with SPORT2 and SPORT3. UART rx and tx | |
669 | * interrupts are generated in PIO mode only when configure | |
670 | * their peripheral mapping registers properly, which means | |
671 | * request corresponding DMA channels in PIO mode as well. | |
672 | */ | |
ab2375f2 SZ |
673 | unsigned uart_dma_ch_rx, uart_dma_ch_tx; |
674 | ||
47918f05 | 675 | switch (uart->rx_irq) { |
ab2375f2 SZ |
676 | case IRQ_UART3_RX: |
677 | uart_dma_ch_rx = CH_UART3_RX; | |
678 | uart_dma_ch_tx = CH_UART3_TX; | |
679 | break; | |
680 | case IRQ_UART2_RX: | |
681 | uart_dma_ch_rx = CH_UART2_RX; | |
682 | uart_dma_ch_tx = CH_UART2_TX; | |
683 | break; | |
684 | default: | |
685 | uart_dma_ch_rx = uart_dma_ch_tx = 0; | |
686 | break; | |
687 | }; | |
688 | ||
689 | if (uart_dma_ch_rx && | |
690 | request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) { | |
691 | printk(KERN_NOTICE"Fail to attach UART interrupt\n"); | |
47918f05 SZ |
692 | free_irq(uart->rx_irq, uart); |
693 | free_irq(uart->tx_irq, uart); | |
ab2375f2 SZ |
694 | return -EBUSY; |
695 | } | |
696 | if (uart_dma_ch_tx && | |
697 | request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) { | |
698 | printk(KERN_NOTICE "Fail to attach UART interrupt\n"); | |
699 | free_dma(uart_dma_ch_rx); | |
47918f05 SZ |
700 | free_irq(uart->rx_irq, uart); |
701 | free_irq(uart->tx_irq, uart); | |
ab2375f2 SZ |
702 | return -EBUSY; |
703 | } | |
704 | } | |
705 | # endif | |
6f95570e | 706 | # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
52e15f0e SZ |
707 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) |
708 | } | |
709 | # endif | |
6f95570e SZ |
710 | #endif |
711 | ||
712 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
713 | if (uart->cts_pin >= 0) { | |
714 | if (request_irq(gpio_to_irq(uart->cts_pin), | |
715 | bfin_serial_mctrl_cts_int, | |
716 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | | |
9cfb5c05 | 717 | 0, "BFIN_UART_CTS", uart)) { |
6f95570e | 718 | uart->cts_pin = -1; |
a89f2466 | 719 | pr_info("Unable to attach BlackFin UART CTS interrupt. So, disable it.\n"); |
6f95570e SZ |
720 | } |
721 | } | |
32b44568 SZ |
722 | if (uart->rts_pin >= 0) { |
723 | if (gpio_request(uart->rts_pin, DRIVER_NAME)) { | |
724 | pr_info("fail to request RTS PIN at GPIO_%d\n", uart->rts_pin); | |
725 | uart->rts_pin = -1; | |
726 | } else | |
727 | gpio_direction_output(uart->rts_pin, 0); | |
728 | } | |
194de561 | 729 | #endif |
d307d36a | 730 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS |
b48dc711 SZ |
731 | if (uart->cts_pin >= 0) { |
732 | if (request_irq(uart->status_irq, bfin_serial_mctrl_cts_int, | |
733 | IRQF_DISABLED, "BFIN_UART_MODEM_STATUS", uart)) { | |
734 | uart->cts_pin = -1; | |
735 | dev_info(port->dev, "Unable to attach BlackFin UART Modem Status interrupt.\n"); | |
736 | } | |
d307d36a | 737 | |
b48dc711 | 738 | /* CTS RTS PINs are negative assertive. */ |
3c2d0ed2 | 739 | UART_PUT_MCR(uart, UART_GET_MCR(uart) | ACTS); |
b48dc711 SZ |
740 | UART_SET_IER(uart, EDSSI); |
741 | } | |
d307d36a SZ |
742 | #endif |
743 | ||
f4d640c9 | 744 | UART_SET_IER(uart, ERBFI); |
194de561 BW |
745 | return 0; |
746 | } | |
747 | ||
748 | static void bfin_serial_shutdown(struct uart_port *port) | |
749 | { | |
750 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
751 | ||
752 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
753 | disable_dma(uart->tx_dma_channel); | |
754 | free_dma(uart->tx_dma_channel); | |
755 | disable_dma(uart->rx_dma_channel); | |
756 | free_dma(uart->rx_dma_channel); | |
757 | del_timer(&(uart->rx_dma_timer)); | |
75b780bd | 758 | dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0); |
194de561 | 759 | #else |
ab2375f2 SZ |
760 | #ifdef CONFIG_BF54x |
761 | switch (uart->port.irq) { | |
762 | case IRQ_UART3_RX: | |
763 | free_dma(CH_UART3_RX); | |
764 | free_dma(CH_UART3_TX); | |
765 | break; | |
766 | case IRQ_UART2_RX: | |
767 | free_dma(CH_UART2_RX); | |
768 | free_dma(CH_UART2_TX); | |
769 | break; | |
770 | default: | |
771 | break; | |
772 | }; | |
474f1a66 | 773 | #endif |
47918f05 SZ |
774 | free_irq(uart->rx_irq, uart); |
775 | free_irq(uart->tx_irq, uart); | |
194de561 | 776 | #endif |
6f95570e | 777 | |
d307d36a | 778 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
6f95570e SZ |
779 | if (uart->cts_pin >= 0) |
780 | free_irq(gpio_to_irq(uart->cts_pin), uart); | |
32b44568 SZ |
781 | if (uart->rts_pin >= 0) |
782 | gpio_free(uart->rts_pin); | |
d307d36a SZ |
783 | #endif |
784 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS | |
57afb399 | 785 | if (uart->cts_pin >= 0) |
d307d36a SZ |
786 | free_irq(uart->status_irq, uart); |
787 | #endif | |
194de561 BW |
788 | } |
789 | ||
790 | static void | |
791 | bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios, | |
792 | struct ktermios *old) | |
793 | { | |
794 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
795 | unsigned long flags; | |
796 | unsigned int baud, quot; | |
3c2d0ed2 | 797 | unsigned int ier, lcr = 0; |
1cd3f2d2 | 798 | unsigned long timeout; |
194de561 BW |
799 | |
800 | switch (termios->c_cflag & CSIZE) { | |
801 | case CS8: | |
802 | lcr = WLS(8); | |
803 | break; | |
804 | case CS7: | |
805 | lcr = WLS(7); | |
806 | break; | |
807 | case CS6: | |
808 | lcr = WLS(6); | |
809 | break; | |
810 | case CS5: | |
811 | lcr = WLS(5); | |
812 | break; | |
813 | default: | |
46e99c4a | 814 | printk(KERN_ERR "%s: word length not supported\n", |
71cc2c21 | 815 | __func__); |
194de561 BW |
816 | } |
817 | ||
84507794 SZ |
818 | /* Anomaly notes: |
819 | * 05000231 - STOP bit is always set to 1 whatever the user is set. | |
820 | */ | |
821 | if (termios->c_cflag & CSTOPB) { | |
822 | if (ANOMALY_05000231) | |
823 | printk(KERN_WARNING "STOP bits other than 1 is not " | |
824 | "supported in case of anomaly 05000231.\n"); | |
825 | else | |
826 | lcr |= STB; | |
827 | } | |
19aa6382 | 828 | if (termios->c_cflag & PARENB) |
194de561 | 829 | lcr |= PEN; |
19aa6382 MF |
830 | if (!(termios->c_cflag & PARODD)) |
831 | lcr |= EPS; | |
832 | if (termios->c_cflag & CMSPAR) | |
833 | lcr |= STP; | |
194de561 | 834 | |
5bb06b62 SZ |
835 | spin_lock_irqsave(&uart->port.lock, flags); |
836 | ||
2ac5ee47 MF |
837 | port->read_status_mask = OE; |
838 | if (termios->c_iflag & INPCK) | |
839 | port->read_status_mask |= (FE | PE); | |
840 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
841 | port->read_status_mask |= BI; | |
194de561 | 842 | |
2ac5ee47 MF |
843 | /* |
844 | * Characters to ignore | |
845 | */ | |
846 | port->ignore_status_mask = 0; | |
847 | if (termios->c_iflag & IGNPAR) | |
848 | port->ignore_status_mask |= FE | PE; | |
849 | if (termios->c_iflag & IGNBRK) { | |
850 | port->ignore_status_mask |= BI; | |
851 | /* | |
852 | * If we're ignoring parity and break indicators, | |
853 | * ignore overruns too (for real raw support). | |
854 | */ | |
855 | if (termios->c_iflag & IGNPAR) | |
856 | port->ignore_status_mask |= OE; | |
857 | } | |
194de561 BW |
858 | |
859 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
ca3e442e GY |
860 | quot = uart_get_divisor(port, baud); |
861 | ||
862 | /* If discipline is not IRDA, apply ANOMALY_05000230 */ | |
863 | if (termios->c_line != N_IRDA) | |
864 | quot -= ANOMALY_05000230; | |
865 | ||
8851c71e MF |
866 | UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15); |
867 | ||
1cd3f2d2 SZ |
868 | /* Wait till the transfer buffer is empty */ |
869 | timeout = jiffies + msecs_to_jiffies(10); | |
870 | while (UART_GET_GCTL(uart) & UCEN && !(UART_GET_LSR(uart) & TEMT)) | |
871 | if (time_after(jiffies, timeout)) { | |
872 | dev_warn(port->dev, "timeout waiting for TX buffer empty\n"); | |
873 | break; | |
874 | } | |
875 | ||
194de561 BW |
876 | /* Disable UART */ |
877 | ier = UART_GET_IER(uart); | |
3c2d0ed2 | 878 | UART_PUT_GCTL(uart, UART_GET_GCTL(uart) & ~UCEN); |
1feaa51d | 879 | UART_DISABLE_INTS(uart); |
194de561 | 880 | |
b06d2f20 | 881 | /* Set DLAB in LCR to Access CLK */ |
45828b81 | 882 | UART_SET_DLAB(uart); |
194de561 | 883 | |
b06d2f20 | 884 | UART_PUT_CLK(uart, quot); |
194de561 BW |
885 | SSYNC(); |
886 | ||
887 | /* Clear DLAB in LCR to Access THR RBR IER */ | |
45828b81 | 888 | UART_CLEAR_DLAB(uart); |
194de561 | 889 | |
3c2d0ed2 | 890 | UART_PUT_LCR(uart, (UART_GET_LCR(uart) & ~LCR_MASK) | lcr); |
194de561 BW |
891 | |
892 | /* Enable UART */ | |
1feaa51d | 893 | UART_ENABLE_INTS(uart, ier); |
3c2d0ed2 | 894 | UART_PUT_GCTL(uart, UART_GET_GCTL(uart) | UCEN); |
194de561 | 895 | |
b3ef5aba GY |
896 | /* Port speed changed, update the per-port timeout. */ |
897 | uart_update_timeout(port, termios->c_cflag, baud); | |
898 | ||
194de561 BW |
899 | spin_unlock_irqrestore(&uart->port.lock, flags); |
900 | } | |
901 | ||
902 | static const char *bfin_serial_type(struct uart_port *port) | |
903 | { | |
904 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
905 | ||
906 | return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL; | |
907 | } | |
908 | ||
909 | /* | |
910 | * Release the memory region(s) being used by 'port'. | |
911 | */ | |
912 | static void bfin_serial_release_port(struct uart_port *port) | |
913 | { | |
914 | } | |
915 | ||
916 | /* | |
917 | * Request the memory region(s) being used by 'port'. | |
918 | */ | |
919 | static int bfin_serial_request_port(struct uart_port *port) | |
920 | { | |
921 | return 0; | |
922 | } | |
923 | ||
924 | /* | |
925 | * Configure/autoconfigure the port. | |
926 | */ | |
927 | static void bfin_serial_config_port(struct uart_port *port, int flags) | |
928 | { | |
929 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
930 | ||
931 | if (flags & UART_CONFIG_TYPE && | |
932 | bfin_serial_request_port(&uart->port) == 0) | |
933 | uart->port.type = PORT_BFIN; | |
934 | } | |
935 | ||
936 | /* | |
937 | * Verify the new serial_struct (for TIOCSSERIAL). | |
938 | * The only change we allow are to the flags and type, and | |
939 | * even then only between PORT_BFIN and PORT_UNKNOWN | |
940 | */ | |
941 | static int | |
942 | bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser) | |
943 | { | |
944 | return 0; | |
945 | } | |
946 | ||
7d01b475 GY |
947 | /* |
948 | * Enable the IrDA function if tty->ldisc.num is N_IRDA. | |
949 | * In other cases, disable IrDA function. | |
950 | */ | |
d87d9b7d | 951 | static void bfin_serial_set_ldisc(struct uart_port *port, int ld) |
7d01b475 | 952 | { |
57afb399 | 953 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; |
3c2d0ed2 | 954 | unsigned int val; |
7d01b475 | 955 | |
d87d9b7d | 956 | switch (ld) { |
7d01b475 | 957 | case N_IRDA: |
57afb399 | 958 | val = UART_GET_GCTL(uart); |
b06d2f20 | 959 | val |= (UMOD_IRDA | RPOLC); |
57afb399 | 960 | UART_PUT_GCTL(uart, val); |
7d01b475 GY |
961 | break; |
962 | default: | |
57afb399 | 963 | val = UART_GET_GCTL(uart); |
b06d2f20 | 964 | val &= ~(UMOD_MASK | RPOLC); |
57afb399 | 965 | UART_PUT_GCTL(uart, val); |
7d01b475 GY |
966 | } |
967 | } | |
968 | ||
6f95570e SZ |
969 | static void bfin_serial_reset_irda(struct uart_port *port) |
970 | { | |
57afb399 | 971 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; |
3c2d0ed2 | 972 | unsigned int val; |
6f95570e | 973 | |
57afb399 | 974 | val = UART_GET_GCTL(uart); |
b06d2f20 | 975 | val &= ~(UMOD_MASK | RPOLC); |
57afb399 | 976 | UART_PUT_GCTL(uart, val); |
6f95570e | 977 | SSYNC(); |
b06d2f20 | 978 | val |= (UMOD_IRDA | RPOLC); |
57afb399 | 979 | UART_PUT_GCTL(uart, val); |
6f95570e SZ |
980 | SSYNC(); |
981 | } | |
982 | ||
52e15f0e | 983 | #ifdef CONFIG_CONSOLE_POLL |
0efa4f2c SZ |
984 | /* Anomaly notes: |
985 | * 05000099 - Because we only use THRE in poll_put and DR in poll_get, | |
986 | * losing other bits of UART_LSR is not a problem here. | |
987 | */ | |
52e15f0e SZ |
988 | static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr) |
989 | { | |
990 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
991 | ||
992 | while (!(UART_GET_LSR(uart) & THRE)) | |
993 | cpu_relax(); | |
994 | ||
995 | UART_CLEAR_DLAB(uart); | |
996 | UART_PUT_CHAR(uart, (unsigned char)chr); | |
997 | } | |
998 | ||
999 | static int bfin_serial_poll_get_char(struct uart_port *port) | |
1000 | { | |
1001 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1002 | unsigned char chr; | |
1003 | ||
1004 | while (!(UART_GET_LSR(uart) & DR)) | |
1005 | cpu_relax(); | |
1006 | ||
1007 | UART_CLEAR_DLAB(uart); | |
1008 | chr = UART_GET_CHAR(uart); | |
1009 | ||
1010 | return chr; | |
1011 | } | |
1012 | #endif | |
1013 | ||
1014 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ | |
1015 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
1016 | static void bfin_kgdboc_port_shutdown(struct uart_port *port) | |
1017 | { | |
1018 | if (kgdboc_break_enabled) { | |
1019 | kgdboc_break_enabled = 0; | |
1020 | bfin_serial_shutdown(port); | |
1021 | } | |
1022 | } | |
1023 | ||
1024 | static int bfin_kgdboc_port_startup(struct uart_port *port) | |
1025 | { | |
1026 | kgdboc_port_line = port->line; | |
1027 | kgdboc_break_enabled = !bfin_serial_startup(port); | |
1028 | return 0; | |
1029 | } | |
1030 | #endif | |
1031 | ||
194de561 BW |
1032 | static struct uart_ops bfin_serial_pops = { |
1033 | .tx_empty = bfin_serial_tx_empty, | |
1034 | .set_mctrl = bfin_serial_set_mctrl, | |
1035 | .get_mctrl = bfin_serial_get_mctrl, | |
1036 | .stop_tx = bfin_serial_stop_tx, | |
1037 | .start_tx = bfin_serial_start_tx, | |
1038 | .stop_rx = bfin_serial_stop_rx, | |
1039 | .enable_ms = bfin_serial_enable_ms, | |
1040 | .break_ctl = bfin_serial_break_ctl, | |
1041 | .startup = bfin_serial_startup, | |
1042 | .shutdown = bfin_serial_shutdown, | |
1043 | .set_termios = bfin_serial_set_termios, | |
3b8458a9 | 1044 | .set_ldisc = bfin_serial_set_ldisc, |
194de561 BW |
1045 | .type = bfin_serial_type, |
1046 | .release_port = bfin_serial_release_port, | |
1047 | .request_port = bfin_serial_request_port, | |
1048 | .config_port = bfin_serial_config_port, | |
1049 | .verify_port = bfin_serial_verify_port, | |
52e15f0e SZ |
1050 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
1051 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
1052 | .kgdboc_port_startup = bfin_kgdboc_port_startup, | |
1053 | .kgdboc_port_shutdown = bfin_kgdboc_port_shutdown, | |
1054 | #endif | |
1055 | #ifdef CONFIG_CONSOLE_POLL | |
1056 | .poll_put_char = bfin_serial_poll_put_char, | |
1057 | .poll_get_char = bfin_serial_poll_get_char, | |
1058 | #endif | |
194de561 BW |
1059 | }; |
1060 | ||
b6efa1ea | 1061 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) |
194de561 BW |
1062 | /* |
1063 | * If the port was already initialised (eg, by a boot loader), | |
1064 | * try to determine the current setup. | |
1065 | */ | |
1066 | static void __init | |
1067 | bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud, | |
1068 | int *parity, int *bits) | |
1069 | { | |
3c2d0ed2 | 1070 | unsigned int status; |
194de561 BW |
1071 | |
1072 | status = UART_GET_IER(uart) & (ERBFI | ETBEI); | |
1073 | if (status == (ERBFI | ETBEI)) { | |
1074 | /* ok, the port was enabled */ | |
59bd234b | 1075 | u32 lcr, clk; |
194de561 BW |
1076 | |
1077 | lcr = UART_GET_LCR(uart); | |
1078 | ||
1079 | *parity = 'n'; | |
1080 | if (lcr & PEN) { | |
1081 | if (lcr & EPS) | |
1082 | *parity = 'e'; | |
1083 | else | |
1084 | *parity = 'o'; | |
1085 | } | |
59bd234b SZ |
1086 | *bits = ((lcr & WLS_MASK) >> WLS_OFFSET) + 5; |
1087 | ||
b06d2f20 | 1088 | /* Set DLAB in LCR to Access CLK */ |
45828b81 | 1089 | UART_SET_DLAB(uart); |
194de561 | 1090 | |
b06d2f20 | 1091 | clk = UART_GET_CLK(uart); |
194de561 BW |
1092 | |
1093 | /* Clear DLAB in LCR to Access THR RBR IER */ | |
45828b81 | 1094 | UART_CLEAR_DLAB(uart); |
194de561 | 1095 | |
b06d2f20 | 1096 | *baud = get_sclk() / (16*clk); |
194de561 | 1097 | } |
71cc2c21 | 1098 | pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits); |
194de561 | 1099 | } |
0ae53640 | 1100 | |
0ae53640 | 1101 | static struct uart_driver bfin_serial_reg; |
194de561 | 1102 | |
57afb399 SZ |
1103 | static void bfin_serial_console_putchar(struct uart_port *port, int ch) |
1104 | { | |
1105 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1106 | while (!(UART_GET_LSR(uart) & THRE)) | |
1107 | barrier(); | |
1108 | UART_PUT_CHAR(uart, ch); | |
1109 | } | |
1110 | ||
1111 | #endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) || | |
1112 | defined (CONFIG_EARLY_PRINTK) */ | |
1113 | ||
1114 | #ifdef CONFIG_SERIAL_BFIN_CONSOLE | |
1115 | #define CLASS_BFIN_CONSOLE "bfin-console" | |
1116 | /* | |
1117 | * Interrupts are disabled on entering | |
1118 | */ | |
1119 | static void | |
1120 | bfin_serial_console_write(struct console *co, const char *s, unsigned int count) | |
1121 | { | |
1122 | struct bfin_serial_port *uart = bfin_serial_ports[co->index]; | |
1123 | unsigned long flags; | |
1124 | ||
1125 | spin_lock_irqsave(&uart->port.lock, flags); | |
1126 | uart_console_write(&uart->port, s, count, bfin_serial_console_putchar); | |
1127 | spin_unlock_irqrestore(&uart->port.lock, flags); | |
1128 | ||
1129 | } | |
1130 | ||
194de561 BW |
1131 | static int __init |
1132 | bfin_serial_console_setup(struct console *co, char *options) | |
1133 | { | |
1134 | struct bfin_serial_port *uart; | |
1135 | int baud = 57600; | |
1136 | int bits = 8; | |
1137 | int parity = 'n'; | |
d307d36a SZ |
1138 | # if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \ |
1139 | defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS) | |
194de561 | 1140 | int flow = 'r'; |
b6efa1ea | 1141 | # else |
194de561 | 1142 | int flow = 'n'; |
0ae53640 | 1143 | # endif |
194de561 BW |
1144 | |
1145 | /* | |
1146 | * Check whether an invalid uart number has been specified, and | |
1147 | * if so, search for the first available port that does have | |
1148 | * console support. | |
1149 | */ | |
57afb399 SZ |
1150 | if (co->index < 0 || co->index >= BFIN_UART_NR_PORTS) |
1151 | return -ENODEV; | |
1152 | ||
1153 | uart = bfin_serial_ports[co->index]; | |
1154 | if (!uart) | |
1155 | return -ENODEV; | |
194de561 BW |
1156 | |
1157 | if (options) | |
1158 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1159 | else | |
1160 | bfin_serial_console_get_options(uart, &baud, &parity, &bits); | |
1161 | ||
1162 | return uart_set_options(&uart->port, co, baud, parity, bits, flow); | |
0ae53640 | 1163 | } |
194de561 | 1164 | |
194de561 | 1165 | static struct console bfin_serial_console = { |
57afb399 | 1166 | .name = BFIN_SERIAL_DEV_NAME, |
194de561 BW |
1167 | .write = bfin_serial_console_write, |
1168 | .device = uart_console_device, | |
1169 | .setup = bfin_serial_console_setup, | |
1170 | .flags = CON_PRINTBUFFER, | |
1171 | .index = -1, | |
1172 | .data = &bfin_serial_reg, | |
1173 | }; | |
bb7e58f8 | 1174 | #define BFIN_SERIAL_CONSOLE (&bfin_serial_console) |
194de561 BW |
1175 | #else |
1176 | #define BFIN_SERIAL_CONSOLE NULL | |
0ae53640 RG |
1177 | #endif /* CONFIG_SERIAL_BFIN_CONSOLE */ |
1178 | ||
57afb399 SZ |
1179 | #ifdef CONFIG_EARLY_PRINTK |
1180 | static struct bfin_serial_port bfin_earlyprintk_port; | |
1181 | #define CLASS_BFIN_EARLYPRINTK "bfin-earlyprintk" | |
0ae53640 | 1182 | |
57afb399 SZ |
1183 | /* |
1184 | * Interrupts are disabled on entering | |
1185 | */ | |
1186 | static void | |
1187 | bfin_earlyprintk_console_write(struct console *co, const char *s, unsigned int count) | |
0ae53640 | 1188 | { |
57afb399 | 1189 | unsigned long flags; |
0ae53640 | 1190 | |
57afb399 SZ |
1191 | if (bfin_earlyprintk_port.port.line != co->index) |
1192 | return; | |
0ae53640 | 1193 | |
57afb399 SZ |
1194 | spin_lock_irqsave(&bfin_earlyprintk_port.port.lock, flags); |
1195 | uart_console_write(&bfin_earlyprintk_port.port, s, count, | |
1196 | bfin_serial_console_putchar); | |
1197 | spin_unlock_irqrestore(&bfin_earlyprintk_port.port.lock, flags); | |
0ae53640 RG |
1198 | } |
1199 | ||
7de7c55b RG |
1200 | /* |
1201 | * This should have a .setup or .early_setup in it, but then things get called | |
1202 | * without the command line options, and the baud rate gets messed up - so | |
1203 | * don't let the common infrastructure play with things. (see calls to setup | |
1204 | * & earlysetup in ./kernel/printk.c:register_console() | |
1205 | */ | |
c1113400 | 1206 | static struct __initdata console bfin_early_serial_console = { |
0ae53640 | 1207 | .name = "early_BFuart", |
57afb399 | 1208 | .write = bfin_earlyprintk_console_write, |
0ae53640 RG |
1209 | .device = uart_console_device, |
1210 | .flags = CON_PRINTBUFFER, | |
0ae53640 RG |
1211 | .index = -1, |
1212 | .data = &bfin_serial_reg, | |
1213 | }; | |
6d9e4498 SZ |
1214 | #endif |
1215 | ||
194de561 BW |
1216 | static struct uart_driver bfin_serial_reg = { |
1217 | .owner = THIS_MODULE, | |
57afb399 SZ |
1218 | .driver_name = DRIVER_NAME, |
1219 | .dev_name = BFIN_SERIAL_DEV_NAME, | |
194de561 BW |
1220 | .major = BFIN_SERIAL_MAJOR, |
1221 | .minor = BFIN_SERIAL_MINOR, | |
2ade9729 | 1222 | .nr = BFIN_UART_NR_PORTS, |
194de561 BW |
1223 | .cons = BFIN_SERIAL_CONSOLE, |
1224 | }; | |
1225 | ||
57afb399 | 1226 | static int bfin_serial_suspend(struct platform_device *pdev, pm_message_t state) |
194de561 | 1227 | { |
57afb399 | 1228 | struct bfin_serial_port *uart = platform_get_drvdata(pdev); |
194de561 | 1229 | |
57afb399 SZ |
1230 | return uart_suspend_port(&bfin_serial_reg, &uart->port); |
1231 | } | |
194de561 | 1232 | |
57afb399 SZ |
1233 | static int bfin_serial_resume(struct platform_device *pdev) |
1234 | { | |
1235 | struct bfin_serial_port *uart = platform_get_drvdata(pdev); | |
1236 | ||
1237 | return uart_resume_port(&bfin_serial_reg, &uart->port); | |
194de561 BW |
1238 | } |
1239 | ||
57afb399 | 1240 | static int bfin_serial_probe(struct platform_device *pdev) |
194de561 | 1241 | { |
57afb399 SZ |
1242 | struct resource *res; |
1243 | struct bfin_serial_port *uart = NULL; | |
1244 | int ret = 0; | |
194de561 | 1245 | |
57afb399 SZ |
1246 | if (pdev->id < 0 || pdev->id >= BFIN_UART_NR_PORTS) { |
1247 | dev_err(&pdev->dev, "Wrong bfin uart platform device id.\n"); | |
1248 | return -ENOENT; | |
ccfbc3e1 | 1249 | } |
194de561 | 1250 | |
57afb399 | 1251 | if (bfin_serial_ports[pdev->id] == NULL) { |
194de561 | 1252 | |
57afb399 SZ |
1253 | uart = kzalloc(sizeof(*uart), GFP_KERNEL); |
1254 | if (!uart) { | |
1255 | dev_err(&pdev->dev, | |
1256 | "fail to malloc bfin_serial_port\n"); | |
1257 | return -ENOMEM; | |
1258 | } | |
1259 | bfin_serial_ports[pdev->id] = uart; | |
194de561 | 1260 | |
57afb399 SZ |
1261 | #ifdef CONFIG_EARLY_PRINTK |
1262 | if (!(bfin_earlyprintk_port.port.membase | |
1263 | && bfin_earlyprintk_port.port.line == pdev->id)) { | |
1264 | /* | |
1265 | * If the peripheral PINs of current port is allocated | |
1266 | * in earlyprintk probe stage, don't do it again. | |
1267 | */ | |
1268 | #endif | |
1269 | ret = peripheral_request_list( | |
1270 | (unsigned short *)pdev->dev.platform_data, DRIVER_NAME); | |
1271 | if (ret) { | |
1272 | dev_err(&pdev->dev, | |
1273 | "fail to request bfin serial peripherals\n"); | |
1274 | goto out_error_free_mem; | |
1275 | } | |
1276 | #ifdef CONFIG_EARLY_PRINTK | |
1277 | } | |
1278 | #endif | |
1279 | ||
1280 | spin_lock_init(&uart->port.lock); | |
1281 | uart->port.uartclk = get_sclk(); | |
1282 | uart->port.fifosize = BFIN_UART_TX_FIFO_SIZE; | |
1283 | uart->port.ops = &bfin_serial_pops; | |
1284 | uart->port.line = pdev->id; | |
1285 | uart->port.iotype = UPIO_MEM; | |
1286 | uart->port.flags = UPF_BOOT_AUTOCONF; | |
1287 | ||
1288 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1289 | if (res == NULL) { | |
1290 | dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n"); | |
1291 | ret = -ENOENT; | |
1292 | goto out_error_free_peripherals; | |
1293 | } | |
1294 | ||
28f65c11 | 1295 | uart->port.membase = ioremap(res->start, resource_size(res)); |
57afb399 SZ |
1296 | if (!uart->port.membase) { |
1297 | dev_err(&pdev->dev, "Cannot map uart IO\n"); | |
1298 | ret = -ENXIO; | |
1299 | goto out_error_free_peripherals; | |
1300 | } | |
1301 | uart->port.mapbase = res->start; | |
194de561 | 1302 | |
47918f05 SZ |
1303 | uart->tx_irq = platform_get_irq(pdev, 0); |
1304 | if (uart->tx_irq < 0) { | |
1305 | dev_err(&pdev->dev, "No uart TX IRQ specified\n"); | |
57afb399 SZ |
1306 | ret = -ENOENT; |
1307 | goto out_error_unmap; | |
194de561 | 1308 | } |
57afb399 | 1309 | |
47918f05 SZ |
1310 | uart->rx_irq = platform_get_irq(pdev, 1); |
1311 | if (uart->rx_irq < 0) { | |
1312 | dev_err(&pdev->dev, "No uart RX IRQ specified\n"); | |
1313 | ret = -ENOENT; | |
1314 | goto out_error_unmap; | |
1315 | } | |
1316 | uart->port.irq = uart->rx_irq; | |
1317 | ||
1318 | uart->status_irq = platform_get_irq(pdev, 2); | |
57afb399 SZ |
1319 | if (uart->status_irq < 0) { |
1320 | dev_err(&pdev->dev, "No uart status IRQ specified\n"); | |
1321 | ret = -ENOENT; | |
1322 | goto out_error_unmap; | |
1323 | } | |
1324 | ||
1325 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
0f66e50a | 1326 | spin_lock_init(&uart->rx_lock); |
57afb399 SZ |
1327 | uart->tx_done = 1; |
1328 | uart->tx_count = 0; | |
1329 | ||
1330 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
1331 | if (res == NULL) { | |
1332 | dev_err(&pdev->dev, "No uart TX DMA channel specified\n"); | |
1333 | ret = -ENOENT; | |
1334 | goto out_error_unmap; | |
1335 | } | |
1336 | uart->tx_dma_channel = res->start; | |
1337 | ||
1338 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
1339 | if (res == NULL) { | |
1340 | dev_err(&pdev->dev, "No uart RX DMA channel specified\n"); | |
1341 | ret = -ENOENT; | |
1342 | goto out_error_unmap; | |
1343 | } | |
1344 | uart->rx_dma_channel = res->start; | |
1345 | ||
1346 | init_timer(&(uart->rx_dma_timer)); | |
1347 | #endif | |
1348 | ||
1349 | #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \ | |
1350 | defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS) | |
1351 | res = platform_get_resource(pdev, IORESOURCE_IO, 0); | |
1352 | if (res == NULL) | |
1353 | uart->cts_pin = -1; | |
ee948e37 | 1354 | else { |
57afb399 | 1355 | uart->cts_pin = res->start; |
64851636 | 1356 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
ee948e37 | 1357 | uart->port.flags |= ASYNC_CTS_FLOW; |
64851636 | 1358 | #endif |
ee948e37 | 1359 | } |
57afb399 SZ |
1360 | |
1361 | res = platform_get_resource(pdev, IORESOURCE_IO, 1); | |
1362 | if (res == NULL) | |
1363 | uart->rts_pin = -1; | |
1364 | else | |
1365 | uart->rts_pin = res->start; | |
57afb399 | 1366 | #endif |
194de561 BW |
1367 | } |
1368 | ||
57afb399 SZ |
1369 | #ifdef CONFIG_SERIAL_BFIN_CONSOLE |
1370 | if (!is_early_platform_device(pdev)) { | |
1371 | #endif | |
1372 | uart = bfin_serial_ports[pdev->id]; | |
1373 | uart->port.dev = &pdev->dev; | |
1374 | dev_set_drvdata(&pdev->dev, uart); | |
1375 | ret = uart_add_one_port(&bfin_serial_reg, &uart->port); | |
1376 | #ifdef CONFIG_SERIAL_BFIN_CONSOLE | |
1377 | } | |
1378 | #endif | |
1379 | ||
1380 | if (!ret) | |
1381 | return 0; | |
1382 | ||
1383 | if (uart) { | |
1384 | out_error_unmap: | |
1385 | iounmap(uart->port.membase); | |
1386 | out_error_free_peripherals: | |
1387 | peripheral_free_list( | |
1388 | (unsigned short *)pdev->dev.platform_data); | |
1389 | out_error_free_mem: | |
1390 | kfree(uart); | |
1391 | bfin_serial_ports[pdev->id] = NULL; | |
1392 | } | |
1393 | ||
1394 | return ret; | |
194de561 BW |
1395 | } |
1396 | ||
ae8d8a14 | 1397 | static int bfin_serial_remove(struct platform_device *pdev) |
194de561 | 1398 | { |
57afb399 SZ |
1399 | struct bfin_serial_port *uart = platform_get_drvdata(pdev); |
1400 | ||
1401 | dev_set_drvdata(&pdev->dev, NULL); | |
1402 | ||
1403 | if (uart) { | |
1404 | uart_remove_one_port(&bfin_serial_reg, &uart->port); | |
57afb399 SZ |
1405 | iounmap(uart->port.membase); |
1406 | peripheral_free_list( | |
1407 | (unsigned short *)pdev->dev.platform_data); | |
1408 | kfree(uart); | |
1409 | bfin_serial_ports[pdev->id] = NULL; | |
ccfbc3e1 | 1410 | } |
194de561 BW |
1411 | |
1412 | return 0; | |
1413 | } | |
1414 | ||
1415 | static struct platform_driver bfin_serial_driver = { | |
1416 | .probe = bfin_serial_probe, | |
2d47b716 | 1417 | .remove = bfin_serial_remove, |
194de561 BW |
1418 | .suspend = bfin_serial_suspend, |
1419 | .resume = bfin_serial_resume, | |
1420 | .driver = { | |
57afb399 | 1421 | .name = DRIVER_NAME, |
e169c139 | 1422 | .owner = THIS_MODULE, |
194de561 BW |
1423 | }, |
1424 | }; | |
1425 | ||
57afb399 SZ |
1426 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) |
1427 | static __initdata struct early_platform_driver early_bfin_serial_driver = { | |
1428 | .class_str = CLASS_BFIN_CONSOLE, | |
1429 | .pdrv = &bfin_serial_driver, | |
1430 | .requested_id = EARLY_PLATFORM_ID_UNSET, | |
1431 | }; | |
1432 | ||
1433 | static int __init bfin_serial_rs_console_init(void) | |
1434 | { | |
1435 | early_platform_driver_register(&early_bfin_serial_driver, DRIVER_NAME); | |
1436 | ||
1437 | early_platform_driver_probe(CLASS_BFIN_CONSOLE, BFIN_UART_NR_PORTS, 0); | |
1438 | ||
1439 | register_console(&bfin_serial_console); | |
1440 | ||
1441 | return 0; | |
1442 | } | |
1443 | console_initcall(bfin_serial_rs_console_init); | |
1444 | #endif | |
1445 | ||
1446 | #ifdef CONFIG_EARLY_PRINTK | |
1447 | /* | |
1448 | * Memory can't be allocated dynamically during earlyprink init stage. | |
1449 | * So, do individual probe for earlyprink with a static uart port variable. | |
1450 | */ | |
1451 | static int bfin_earlyprintk_probe(struct platform_device *pdev) | |
194de561 | 1452 | { |
57afb399 | 1453 | struct resource *res; |
194de561 BW |
1454 | int ret; |
1455 | ||
57afb399 SZ |
1456 | if (pdev->id < 0 || pdev->id >= BFIN_UART_NR_PORTS) { |
1457 | dev_err(&pdev->dev, "Wrong earlyprintk platform device id.\n"); | |
1458 | return -ENOENT; | |
1459 | } | |
1460 | ||
1461 | ret = peripheral_request_list( | |
1462 | (unsigned short *)pdev->dev.platform_data, DRIVER_NAME); | |
1463 | if (ret) { | |
1464 | dev_err(&pdev->dev, | |
1465 | "fail to request bfin serial peripherals\n"); | |
1466 | return ret; | |
1467 | } | |
1468 | ||
1469 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1470 | if (res == NULL) { | |
1471 | dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n"); | |
1472 | ret = -ENOENT; | |
1473 | goto out_error_free_peripherals; | |
1474 | } | |
1475 | ||
1476 | bfin_earlyprintk_port.port.membase = ioremap(res->start, | |
28f65c11 | 1477 | resource_size(res)); |
57afb399 SZ |
1478 | if (!bfin_earlyprintk_port.port.membase) { |
1479 | dev_err(&pdev->dev, "Cannot map uart IO\n"); | |
1480 | ret = -ENXIO; | |
1481 | goto out_error_free_peripherals; | |
1482 | } | |
1483 | bfin_earlyprintk_port.port.mapbase = res->start; | |
1484 | bfin_earlyprintk_port.port.line = pdev->id; | |
1485 | bfin_earlyprintk_port.port.uartclk = get_sclk(); | |
1486 | bfin_earlyprintk_port.port.fifosize = BFIN_UART_TX_FIFO_SIZE; | |
1487 | spin_lock_init(&bfin_earlyprintk_port.port.lock); | |
1488 | ||
1489 | return 0; | |
1490 | ||
1491 | out_error_free_peripherals: | |
1492 | peripheral_free_list( | |
1493 | (unsigned short *)pdev->dev.platform_data); | |
1494 | ||
1495 | return ret; | |
1496 | } | |
1497 | ||
1498 | static struct platform_driver bfin_earlyprintk_driver = { | |
1499 | .probe = bfin_earlyprintk_probe, | |
1500 | .driver = { | |
1501 | .name = DRIVER_NAME, | |
1502 | .owner = THIS_MODULE, | |
1503 | }, | |
1504 | }; | |
1505 | ||
1506 | static __initdata struct early_platform_driver early_bfin_earlyprintk_driver = { | |
1507 | .class_str = CLASS_BFIN_EARLYPRINTK, | |
1508 | .pdrv = &bfin_earlyprintk_driver, | |
1509 | .requested_id = EARLY_PLATFORM_ID_UNSET, | |
1510 | }; | |
1511 | ||
1512 | struct console __init *bfin_earlyserial_init(unsigned int port, | |
1513 | unsigned int cflag) | |
1514 | { | |
1515 | struct ktermios t; | |
1516 | char port_name[20]; | |
194de561 | 1517 | |
57afb399 SZ |
1518 | if (port < 0 || port >= BFIN_UART_NR_PORTS) |
1519 | return NULL; | |
1520 | ||
1521 | /* | |
1522 | * Only probe resource of the given port in earlyprintk boot arg. | |
1523 | * The expected port id should be indicated in port name string. | |
1524 | */ | |
1525 | snprintf(port_name, 20, DRIVER_NAME ".%d", port); | |
1526 | early_platform_driver_register(&early_bfin_earlyprintk_driver, | |
1527 | port_name); | |
1528 | early_platform_driver_probe(CLASS_BFIN_EARLYPRINTK, 1, 0); | |
1529 | ||
1530 | if (!bfin_earlyprintk_port.port.membase) | |
1531 | return NULL; | |
1532 | ||
1533 | #ifdef CONFIG_SERIAL_BFIN_CONSOLE | |
1534 | /* | |
1535 | * If we are using early serial, don't let the normal console rewind | |
1536 | * log buffer, since that causes things to be printed multiple times | |
1537 | */ | |
1538 | bfin_serial_console.flags &= ~CON_PRINTBUFFER; | |
1539 | #endif | |
1540 | ||
1541 | bfin_early_serial_console.index = port; | |
1542 | t.c_cflag = cflag; | |
1543 | t.c_iflag = 0; | |
1544 | t.c_oflag = 0; | |
1545 | t.c_lflag = ICANON; | |
1546 | t.c_line = port; | |
1547 | bfin_serial_set_termios(&bfin_earlyprintk_port.port, &t, &t); | |
1548 | ||
1549 | return &bfin_early_serial_console; | |
1550 | } | |
1551 | #endif /* CONFIG_EARLY_PRINTK */ | |
1552 | ||
1553 | static int __init bfin_serial_init(void) | |
1554 | { | |
1555 | int ret; | |
1556 | ||
1557 | pr_info("Blackfin serial driver\n"); | |
194de561 BW |
1558 | |
1559 | ret = uart_register_driver(&bfin_serial_reg); | |
57afb399 SZ |
1560 | if (ret) { |
1561 | pr_err("failed to register %s:%d\n", | |
1562 | bfin_serial_reg.driver_name, ret); | |
1563 | } | |
1564 | ||
1565 | ret = platform_driver_register(&bfin_serial_driver); | |
1566 | if (ret) { | |
1567 | pr_err("fail to register bfin uart\n"); | |
1568 | uart_unregister_driver(&bfin_serial_reg); | |
194de561 | 1569 | } |
57afb399 | 1570 | |
194de561 BW |
1571 | return ret; |
1572 | } | |
1573 | ||
1574 | static void __exit bfin_serial_exit(void) | |
1575 | { | |
1576 | platform_driver_unregister(&bfin_serial_driver); | |
1577 | uart_unregister_driver(&bfin_serial_reg); | |
1578 | } | |
1579 | ||
52e15f0e | 1580 | |
194de561 BW |
1581 | module_init(bfin_serial_init); |
1582 | module_exit(bfin_serial_exit); | |
1583 | ||
57afb399 | 1584 | MODULE_AUTHOR("Sonic Zhang, Aubrey Li"); |
194de561 BW |
1585 | MODULE_DESCRIPTION("Blackfin generic serial port driver"); |
1586 | MODULE_LICENSE("GPL"); | |
1587 | MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR); | |
e169c139 | 1588 | MODULE_ALIAS("platform:bfin-uart"); |