[deliverable/linux.git] / drivers / tty / serial / sh-sci.h

#include <linux/serial_core.h>
#include <linux/io.h>
#include <linux/gpio.h>

#define SCI_MAJOR		204
#define SCI_MINOR_START		8


/*
 * SCI register subset common for all port types.
 * Not all registers will exist on all parts.
 */
enum {
	SCSMR,				/* Serial Mode Register */
	SCBRR,				/* Bit Rate Register */
	SCSCR,				/* Serial Control Register */
	SCxSR,				/* Serial Status Register */
	SCFCR,				/* FIFO Control Register */
	SCFDR,				/* FIFO Data Count Register */
	SCxTDR,				/* Transmit (FIFO) Data Register */
	SCxRDR,				/* Receive (FIFO) Data Register */
	SCLSR,				/* Line Status Register */
	SCTFDR,				/* Transmit FIFO Data Count Register */
	SCRFDR,				/* Receive FIFO Data Count Register */
	SCSPTR,				/* Serial Port Register */
	HSSRR,				/* Sampling Rate Register */
	SCPCR,				/* Serial Port Control Register */
	SCPDR,				/* Serial Port Data Register */

	SCIx_NR_REGS,
};


/* SCSMR (Serial Mode Register) */
#define SCSMR_CHR	(1 << 6)	/* 7-bit Character Length */
#define SCSMR_PE	(1 << 5)	/* Parity Enable */
#define SCSMR_ODD	(1 << 4)	/* Odd Parity */
#define SCSMR_STOP	(1 << 3)	/* Stop Bit Length */
#define SCSMR_CKS	0x0003		/* Clock Select */

/* Serial Control Register, SCIFA/SCIFB only bits */
#define SCSCR_TDRQE	(1 << 15)	/* Tx Data Transfer Request Enable */
#define SCSCR_RDRQE	(1 << 14)	/* Rx Data Transfer Request Enable */

/* SCxSR (Serial Status Register) on SCI */
#define SCI_TDRE  0x80			/* Transmit Data Register Empty */
#define SCI_RDRF  0x40			/* Receive Data Register Full */
#define SCI_ORER  0x20			/* Overrun Error */
#define SCI_FER   0x10			/* Framing Error */
#define SCI_PER   0x08			/* Parity Error */
#define SCI_TEND  0x04			/* Transmit End */

#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)

/* SCxSR (Serial Status Register) on SCIF, HSCIF */
#define SCIF_ER    0x0080		/* Receive Error */
#define SCIF_TEND  0x0040		/* Transmission End */
#define SCIF_TDFE  0x0020		/* Transmit FIFO Data Empty */
#define SCIF_BRK   0x0010		/* Break Detect */
#define SCIF_FER   0x0008		/* Framing Error */
#define SCIF_PER   0x0004		/* Parity Error */
#define SCIF_RDF   0x0002		/* Receive FIFO Data Full */
#define SCIF_DR    0x0001		/* Receive Data Ready */

#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)

/* SCFCR (FIFO Control Register) */
#define SCFCR_MCE	0x0008		/* Modem Control Enable */
#define SCFCR_TFRST	0x0004		/* Transmit FIFO Data Register Reset */
#define SCFCR_RFRST	0x0002		/* Receive FIFO Data Register Reset */
#define SCFCR_LOOP	(1 << 0)	/* Loopback Test */

/* SCSPTR (Serial Port Register), optional */
#define SCSPTR_RTSIO	(1 << 7)	/* Serial Port RTS Pin Input/Output */
#define SCSPTR_RTSDT	(1 << 6)	/* Serial Port RTS Pin Data */
#define SCSPTR_CTSIO	(1 << 5)	/* Serial Port CTS Pin Input/Output */
#define SCSPTR_CTSDT	(1 << 4)	/* Serial Port CTS Pin Data */
#define SCSPTR_SPB2IO	(1 << 1)	/* Serial Port Break Input/Output */
#define SCSPTR_SPB2DT	(1 << 0)	/* Serial Port Break Data */

/* HSSRR HSCIF */
#define HSCIF_SRE	0x8000		/* Sampling Rate Register Enable */

/* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */
#define SCPCR_RTSC	(1 << 4)	/* Serial Port RTS Pin / Output Pin */
#define SCPCR_CTSC	(1 << 3)	/* Serial Port CTS Pin / Input Pin */

/* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */
#define SCPDR_RTSD	(1 << 4)	/* Serial Port RTS Output Pin Data */
#define SCPDR_CTSD	(1 << 3)	/* Serial Port CTS Input Pin Data */


#define SCxSR_TEND(port)	(((port)->type == PORT_SCI) ? SCI_TEND   : SCIF_TEND)
#define SCxSR_RDxF(port)	(((port)->type == PORT_SCI) ? SCI_RDRF   : SCIF_RDF)
#define SCxSR_TDxE(port)	(((port)->type == PORT_SCI) ? SCI_TDRE   : SCIF_TDFE)
#define SCxSR_FER(port)		(((port)->type == PORT_SCI) ? SCI_FER    : SCIF_FER)
#define SCxSR_PER(port)		(((port)->type == PORT_SCI) ? SCI_PER    : SCIF_PER)
#define SCxSR_BRK(port)		(((port)->type == PORT_SCI) ? 0x00       : SCIF_BRK)

#define SCxSR_ERRORS(port)	(to_sci_port(port)->error_mask)

#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
    defined(CONFIG_CPU_SUBTYPE_SH7720) || \
    defined(CONFIG_CPU_SUBTYPE_SH7721) || \
    defined(CONFIG_ARCH_SH73A0) || \
    defined(CONFIG_ARCH_R8A7740)

# define SCxSR_RDxF_CLEAR(port)	 (serial_port_in(port, SCxSR) & 0xfffc)
# define SCxSR_ERROR_CLEAR(port) (serial_port_in(port, SCxSR) & 0xfd73)
# define SCxSR_TDxE_CLEAR(port)	 (serial_port_in(port, SCxSR) & 0xffdf)
# define SCxSR_BREAK_CLEAR(port) (serial_port_in(port, SCxSR) & 0xffe3)
#else
# define SCxSR_RDxF_CLEAR(port)	 (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
# define SCxSR_TDxE_CLEAR(port)  (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
#endif
Commit	Line	Data
1da177e4	1	#include <linux/serial_core.h>
edad1f20	2	#include <linux/io.h>
69edbba0	3	#include <linux/gpio.h>
3ea6bc3d	4
c27ffc10 GU	5	#define SCI_MAJOR 204
	6	#define SCI_MINOR_START 8
	7
	8
	9	/*
	10	* SCI register subset common for all port types.
	11	* Not all registers will exist on all parts.
	12	*/
	13	enum {
	14	SCSMR, /* Serial Mode Register */
	15	SCBRR, /* Bit Rate Register */
	16	SCSCR, /* Serial Control Register */
	17	SCxSR, /* Serial Status Register */
	18	SCFCR, /* FIFO Control Register */
	19	SCFDR, /* FIFO Data Count Register */
	20	SCxTDR, /* Transmit (FIFO) Data Register */
	21	SCxRDR, /* Receive (FIFO) Data Register */
	22	SCLSR, /* Line Status Register */
	23	SCTFDR, /* Transmit FIFO Data Count Register */
	24	SCRFDR, /* Receive FIFO Data Count Register */
	25	SCSPTR, /* Serial Port Register */
	26	HSSRR, /* Sampling Rate Register */
c097abc3 GU	27	SCPCR, /* Serial Port Control Register */
c097abc3 GU	28	SCPDR, /* Serial Port Data Register */
c27ffc10 GU	29
	30	SCIx_NR_REGS,
	31	};
	32
	33
	34	/* SCSMR (Serial Mode Register) */
	35	#define SCSMR_CHR (1 << 6) /* 7-bit Character Length */
	36	#define SCSMR_PE (1 << 5) /* Parity Enable */
	37	#define SCSMR_ODD (1 << 4) /* Odd Parity */
	38	#define SCSMR_STOP (1 << 3) /* Stop Bit Length */
	39	#define SCSMR_CKS 0x0003 /* Clock Select */
	40
	41	/* Serial Control Register, SCIFA/SCIFB only bits */
	42	#define SCSCR_TDRQE (1 << 15) /* Tx Data Transfer Request Enable */
	43	#define SCSCR_RDRQE (1 << 14) /* Rx Data Transfer Request Enable */
	44
	45	/* SCxSR (Serial Status Register) on SCI */
	46	#define SCI_TDRE 0x80 /* Transmit Data Register Empty */
	47	#define SCI_RDRF 0x40 /* Receive Data Register Full */
	48	#define SCI_ORER 0x20 /* Overrun Error */
	49	#define SCI_FER 0x10 /* Framing Error */
	50	#define SCI_PER 0x08 /* Parity Error */
	51	#define SCI_TEND 0x04 /* Transmit End */
	52
	53	#define SCI_DEFAULT_ERROR_MASK (SCI_PER \| SCI_FER)
	54
	55	/* SCxSR (Serial Status Register) on SCIF, HSCIF */
	56	#define SCIF_ER 0x0080 /* Receive Error */
	57	#define SCIF_TEND 0x0040 /* Transmission End */
	58	#define SCIF_TDFE 0x0020 /* Transmit FIFO Data Empty */
	59	#define SCIF_BRK 0x0010 /* Break Detect */
	60	#define SCIF_FER 0x0008 /* Framing Error */
	61	#define SCIF_PER 0x0004 /* Parity Error */
	62	#define SCIF_RDF 0x0002 /* Receive FIFO Data Full */
	63	#define SCIF_DR 0x0001 /* Receive Data Ready */
	64
	65	#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER \| SCIF_FER \| SCIF_ER \| SCIF_BRK)
	66
	67	/* SCFCR (FIFO Control Register) */
31f90796 GU	68	#define SCFCR_MCE 0x0008 /* Modem Control Enable */
	69	#define SCFCR_TFRST 0x0004 /* Transmit FIFO Data Register Reset */
	70	#define SCFCR_RFRST 0x0002 /* Receive FIFO Data Register Reset */
c27ffc10 GU	71	#define SCFCR_LOOP (1 << 0) /* Loopback Test */
	72
	73	/* SCSPTR (Serial Port Register), optional */
	74	#define SCSPTR_RTSIO (1 << 7) /* Serial Port RTS Pin Input/Output */
76735e9d	75	#define SCSPTR_RTSDT (1 << 6) /* Serial Port RTS Pin Data */
c27ffc10	76	#define SCSPTR_CTSIO (1 << 5) /* Serial Port CTS Pin Input/Output */
76735e9d	77	#define SCSPTR_CTSDT (1 << 4) /* Serial Port CTS Pin Data */
c27ffc10 GU	78	#define SCSPTR_SPB2IO (1 << 1) /* Serial Port Break Input/Output */
	79	#define SCSPTR_SPB2DT (1 << 0) /* Serial Port Break Data */
	80
	81	/* HSSRR HSCIF */
	82	#define HSCIF_SRE 0x8000 /* Sampling Rate Register Enable */
	83
c097abc3 GU	84	/* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */
	85	#define SCPCR_RTSC (1 << 4) /* Serial Port RTS Pin / Output Pin */
	86	#define SCPCR_CTSC (1 << 3) /* Serial Port CTS Pin / Input Pin */
	87
	88	/* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */
	89	#define SCPDR_RTSD (1 << 4) /* Serial Port RTS Output Pin Data */
	90	#define SCPDR_CTSD (1 << 3) /* Serial Port CTS Input Pin Data */
	91
c27ffc10	92
15c73aaa	93	#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
15c73aaa PM	94	#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
	95	#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
	96	#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
	97	#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
	98	#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
debf9507	99
3ae988d9	100	#define SCxSR_ERRORS(port) (to_sci_port(port)->error_mask)
15c73aaa	101
3ea6bc3d	102	#if defined(CONFIG_CPU_SUBTYPE_SH7705) \|\| \
31a49c4b	103	defined(CONFIG_CPU_SUBTYPE_SH7720) \|\| \
8a77b8d0	104	defined(CONFIG_CPU_SUBTYPE_SH7721) \|\| \
6d9598e2	105	defined(CONFIG_ARCH_SH73A0) \|\| \
6c01ba44 KM	106	defined(CONFIG_ARCH_R8A7740)
6c01ba44 KM	107
b12bb29f PM	108	# define SCxSR_RDxF_CLEAR(port) (serial_port_in(port, SCxSR) & 0xfffc)
	109	# define SCxSR_ERROR_CLEAR(port) (serial_port_in(port, SCxSR) & 0xfd73)
	110	# define SCxSR_TDxE_CLEAR(port) (serial_port_in(port, SCxSR) & 0xffdf)
	111	# define SCxSR_BREAK_CLEAR(port) (serial_port_in(port, SCxSR) & 0xffe3)
1da177e4	112	#else
1da177e4 LT	113	# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
	114	# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
	115	# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
	116	# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
	117	#endif
	118