projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 | 1 | #include <linux/serial_core.h> |
| edad1f20 | 2 | #include <linux/io.h> |
| 69edbba0 | 3 | #include <linux/gpio.h> |
| 3ea6bc3d | 4 | |
| c27ffc10 GU |
5 | #define SCI_MAJOR 204 |
| 6 | #define SCI_MINOR_START 8 | |
| 7 | ||
| 8 | ||
| 9 | /* | |
| 10 | * SCI register subset common for all port types. | |
| 11 | * Not all registers will exist on all parts. | |
| 12 | */ | |
| 13 | enum { | |
| 14 | SCSMR, /* Serial Mode Register */ | |
| 15 | SCBRR, /* Bit Rate Register */ | |
| 16 | SCSCR, /* Serial Control Register */ | |
| 17 | SCxSR, /* Serial Status Register */ | |
| 18 | SCFCR, /* FIFO Control Register */ | |
| 19 | SCFDR, /* FIFO Data Count Register */ | |
| 20 | SCxTDR, /* Transmit (FIFO) Data Register */ | |
| 21 | SCxRDR, /* Receive (FIFO) Data Register */ | |
| 22 | SCLSR, /* Line Status Register */ | |
| 23 | SCTFDR, /* Transmit FIFO Data Count Register */ | |
| 24 | SCRFDR, /* Receive FIFO Data Count Register */ | |
| 25 | SCSPTR, /* Serial Port Register */ | |
| 26 | HSSRR, /* Sampling Rate Register */ | |
| 27 | ||
| 28 | SCIx_NR_REGS, | |
| 29 | }; | |
| 30 | ||
| 31 | ||
| 32 | /* SCSMR (Serial Mode Register) */ | |
| 33 | #define SCSMR_CHR (1 << 6) /* 7-bit Character Length */ | |
| 34 | #define SCSMR_PE (1 << 5) /* Parity Enable */ | |
| 35 | #define SCSMR_ODD (1 << 4) /* Odd Parity */ | |
| 36 | #define SCSMR_STOP (1 << 3) /* Stop Bit Length */ | |
| 37 | #define SCSMR_CKS 0x0003 /* Clock Select */ | |
| 38 | ||
| 39 | /* Serial Control Register, SCIFA/SCIFB only bits */ | |
| 40 | #define SCSCR_TDRQE (1 << 15) /* Tx Data Transfer Request Enable */ | |
| 41 | #define SCSCR_RDRQE (1 << 14) /* Rx Data Transfer Request Enable */ | |
| 42 | ||
| 43 | /* SCxSR (Serial Status Register) on SCI */ | |
| 44 | #define SCI_TDRE 0x80 /* Transmit Data Register Empty */ | |
| 45 | #define SCI_RDRF 0x40 /* Receive Data Register Full */ | |
| 46 | #define SCI_ORER 0x20 /* Overrun Error */ | |
| 47 | #define SCI_FER 0x10 /* Framing Error */ | |
| 48 | #define SCI_PER 0x08 /* Parity Error */ | |
| 49 | #define SCI_TEND 0x04 /* Transmit End */ | |
| 50 | ||
| 51 | #define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER) | |
| 52 | ||
| 53 | /* SCxSR (Serial Status Register) on SCIF, HSCIF */ | |
| 54 | #define SCIF_ER 0x0080 /* Receive Error */ | |
| 55 | #define SCIF_TEND 0x0040 /* Transmission End */ | |
| 56 | #define SCIF_TDFE 0x0020 /* Transmit FIFO Data Empty */ | |
| 57 | #define SCIF_BRK 0x0010 /* Break Detect */ | |
| 58 | #define SCIF_FER 0x0008 /* Framing Error */ | |
| 59 | #define SCIF_PER 0x0004 /* Parity Error */ | |
| 60 | #define SCIF_RDF 0x0002 /* Receive FIFO Data Full */ | |
| 61 | #define SCIF_DR 0x0001 /* Receive Data Ready */ | |
| 62 | ||
| 63 | #define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) | |
| 64 | ||
| 65 | /* SCFCR (FIFO Control Register) */ | |
| 66 | #define SCFCR_MCE 0x0008 | |
| 67 | #define SCFCR_TFRST 0x0004 | |
| 68 | #define SCFCR_RFRST 0x0002 | |
| 69 | #define SCFCR_LOOP (1 << 0) /* Loopback Test */ | |
| 70 | ||
| 71 | /* SCSPTR (Serial Port Register), optional */ | |
| 72 | #define SCSPTR_RTSIO (1 << 7) /* Serial Port RTS Pin Input/Output */ | |
| 76735e9d | 73 | #define SCSPTR_RTSDT (1 << 6) /* Serial Port RTS Pin Data */ |
| c27ffc10 | 74 | #define SCSPTR_CTSIO (1 << 5) /* Serial Port CTS Pin Input/Output */ |
| 76735e9d | 75 | #define SCSPTR_CTSDT (1 << 4) /* Serial Port CTS Pin Data */ |
| c27ffc10 GU |
76 | #define SCSPTR_SPB2IO (1 << 1) /* Serial Port Break Input/Output */ |
| 77 | #define SCSPTR_SPB2DT (1 << 0) /* Serial Port Break Data */ | |
| 78 | ||
| 79 | /* HSSRR HSCIF */ | |
| 80 | #define HSCIF_SRE 0x8000 /* Sampling Rate Register Enable */ | |
| 81 | ||
| 82 | ||
| 15c73aaa | 83 | #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) |
| 15c73aaa PM |
84 | #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) |
| 85 | #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) | |
| 86 | #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) | |
| 87 | #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) | |
| 88 | #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) | |
| debf9507 | 89 | |
| 3ae988d9 | 90 | #define SCxSR_ERRORS(port) (to_sci_port(port)->error_mask) |
| 15c73aaa | 91 | |
| 3ea6bc3d | 92 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
| 31a49c4b | 93 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 8a77b8d0 | 94 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ |
| 6d9598e2 | 95 | defined(CONFIG_ARCH_SH73A0) || \ |
| 6c01ba44 KM |
96 | defined(CONFIG_ARCH_R8A7740) |
| 97 | ||
| b12bb29f PM |
98 | # define SCxSR_RDxF_CLEAR(port) (serial_port_in(port, SCxSR) & 0xfffc) |
| 99 | # define SCxSR_ERROR_CLEAR(port) (serial_port_in(port, SCxSR) & 0xfd73) | |
| 100 | # define SCxSR_TDxE_CLEAR(port) (serial_port_in(port, SCxSR) & 0xffdf) | |
| 101 | # define SCxSR_BREAK_CLEAR(port) (serial_port_in(port, SCxSR) & 0xffe3) | |
| 1da177e4 | 102 | #else |
| 1da177e4 LT |
103 | # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) |
| 104 | # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) | |
| 105 | # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) | |
| 106 | # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) | |
| 107 | #endif | |
| 108 |