Commit | Line | Data |
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9ecb8875 AKG |
1 | /* |
2 | * Texas Instruments DSPS platforms "glue layer" | |
3 | * | |
4 | * Copyright (C) 2012, by Texas Instruments | |
5 | * | |
6 | * Based on the am35x "glue layer" code. | |
7 | * | |
8 | * This file is part of the Inventra Controller Driver for Linux. | |
9 | * | |
10 | * The Inventra Controller Driver for Linux is free software; you | |
11 | * can redistribute it and/or modify it under the terms of the GNU | |
12 | * General Public License version 2 as published by the Free Software | |
13 | * Foundation. | |
14 | * | |
15 | * The Inventra Controller Driver for Linux is distributed in | |
16 | * the hope that it will be useful, but WITHOUT ANY WARRANTY; | |
17 | * without even the implied warranty of MERCHANTABILITY or | |
18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
19 | * License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with The Inventra Controller Driver for Linux ; if not, | |
23 | * write to the Free Software Foundation, Inc., 59 Temple Place, | |
24 | * Suite 330, Boston, MA 02111-1307 USA | |
25 | * | |
26 | * musb_dsps.c will be a common file for all the TI DSPS platforms | |
27 | * such as dm64x, dm36x, dm35x, da8x, am35x and ti81x. | |
28 | * For now only ti81x is using this and in future davinci.c, am35x.c | |
29 | * da8xx.c would be merged to this file after testing. | |
30 | */ | |
31 | ||
9ecb8875 | 32 | #include <linux/io.h> |
ded017ee | 33 | #include <linux/err.h> |
9ecb8875 AKG |
34 | #include <linux/platform_device.h> |
35 | #include <linux/dma-mapping.h> | |
36 | #include <linux/pm_runtime.h> | |
37 | #include <linux/module.h> | |
d7078df6 | 38 | #include <linux/usb/usb_phy_generic.h> |
e8c4a7ac | 39 | #include <linux/platform_data/usb-omap.h> |
0f53e481 | 40 | #include <linux/sizes.h> |
9ecb8875 AKG |
41 | |
42 | #include <linux/of.h> | |
43 | #include <linux/of_device.h> | |
44 | #include <linux/of_address.h> | |
97238b35 | 45 | #include <linux/of_irq.h> |
c031a7d4 | 46 | #include <linux/usb/of.h> |
9ecb8875 | 47 | |
40f099e3 MP |
48 | #include <linux/debugfs.h> |
49 | ||
9ecb8875 AKG |
50 | #include "musb_core.h" |
51 | ||
65145677 | 52 | static const struct of_device_id musb_dsps_of_match[]; |
65145677 | 53 | |
9ecb8875 AKG |
54 | /** |
55 | * avoid using musb_readx()/musb_writex() as glue layer should not be | |
56 | * dependent on musb core layer symbols. | |
57 | */ | |
58 | static inline u8 dsps_readb(const void __iomem *addr, unsigned offset) | |
fc7af215 LW |
59 | { |
60 | return __raw_readb(addr + offset); | |
61 | } | |
9ecb8875 AKG |
62 | |
63 | static inline u32 dsps_readl(const void __iomem *addr, unsigned offset) | |
fc7af215 LW |
64 | { |
65 | return __raw_readl(addr + offset); | |
66 | } | |
9ecb8875 AKG |
67 | |
68 | static inline void dsps_writeb(void __iomem *addr, unsigned offset, u8 data) | |
fc7af215 LW |
69 | { |
70 | __raw_writeb(data, addr + offset); | |
71 | } | |
9ecb8875 AKG |
72 | |
73 | static inline void dsps_writel(void __iomem *addr, unsigned offset, u32 data) | |
fc7af215 LW |
74 | { |
75 | __raw_writel(data, addr + offset); | |
76 | } | |
9ecb8875 AKG |
77 | |
78 | /** | |
79 | * DSPS musb wrapper register offset. | |
80 | * FIXME: This should be expanded to have all the wrapper registers from TI DSPS | |
81 | * musb ips. | |
82 | */ | |
83 | struct dsps_musb_wrapper { | |
84 | u16 revision; | |
85 | u16 control; | |
86 | u16 status; | |
9ecb8875 AKG |
87 | u16 epintr_set; |
88 | u16 epintr_clear; | |
89 | u16 epintr_status; | |
90 | u16 coreintr_set; | |
91 | u16 coreintr_clear; | |
92 | u16 coreintr_status; | |
93 | u16 phy_utmi; | |
94 | u16 mode; | |
b991f9b7 DM |
95 | u16 tx_mode; |
96 | u16 rx_mode; | |
9ecb8875 AKG |
97 | |
98 | /* bit positions for control */ | |
99 | unsigned reset:5; | |
100 | ||
101 | /* bit positions for interrupt */ | |
102 | unsigned usb_shift:5; | |
103 | u32 usb_mask; | |
104 | u32 usb_bitmap; | |
105 | unsigned drvvbus:5; | |
106 | ||
107 | unsigned txep_shift:5; | |
108 | u32 txep_mask; | |
109 | u32 txep_bitmap; | |
110 | ||
111 | unsigned rxep_shift:5; | |
112 | u32 rxep_mask; | |
113 | u32 rxep_bitmap; | |
114 | ||
115 | /* bit positions for phy_utmi */ | |
116 | unsigned otg_disable:5; | |
117 | ||
118 | /* bit positions for mode */ | |
119 | unsigned iddig:5; | |
943c1397 | 120 | unsigned iddig_mux:5; |
9ecb8875 | 121 | /* miscellaneous stuff */ |
9ecb8875 AKG |
122 | u8 poll_seconds; |
123 | }; | |
124 | ||
869c5978 DM |
125 | /* |
126 | * register shadow for suspend | |
127 | */ | |
128 | struct dsps_context { | |
129 | u32 control; | |
130 | u32 epintr; | |
131 | u32 coreintr; | |
132 | u32 phy_utmi; | |
133 | u32 mode; | |
134 | u32 tx_mode; | |
135 | u32 rx_mode; | |
136 | }; | |
137 | ||
9ecb8875 AKG |
138 | /** |
139 | * DSPS glue structure. | |
140 | */ | |
141 | struct dsps_glue { | |
142 | struct device *dev; | |
97238b35 | 143 | struct platform_device *musb; /* child musb pdev */ |
9ecb8875 | 144 | const struct dsps_musb_wrapper *wrp; /* wrapper register offsets */ |
97238b35 SAS |
145 | struct timer_list timer; /* otg_workaround timer */ |
146 | unsigned long last_timer; /* last timer data for each instance */ | |
371254ce | 147 | bool sw_babble_enabled; |
869c5978 DM |
148 | |
149 | struct dsps_context context; | |
40f099e3 MP |
150 | struct debugfs_regset32 regset; |
151 | struct dentry *dbgfs_root; | |
152 | }; | |
153 | ||
154 | static const struct debugfs_reg32 dsps_musb_regs[] = { | |
155 | { "revision", 0x00 }, | |
156 | { "control", 0x14 }, | |
157 | { "status", 0x18 }, | |
158 | { "eoi", 0x24 }, | |
159 | { "intr0_stat", 0x30 }, | |
160 | { "intr1_stat", 0x34 }, | |
161 | { "intr0_set", 0x38 }, | |
162 | { "intr1_set", 0x3c }, | |
163 | { "txmode", 0x70 }, | |
164 | { "rxmode", 0x74 }, | |
165 | { "autoreq", 0xd0 }, | |
166 | { "srpfixtime", 0xd4 }, | |
167 | { "tdown", 0xd8 }, | |
168 | { "phy_utmi", 0xe0 }, | |
169 | { "mode", 0xe8 }, | |
9ecb8875 AKG |
170 | }; |
171 | ||
807d0d2b SAS |
172 | static void dsps_musb_try_idle(struct musb *musb, unsigned long timeout) |
173 | { | |
174 | struct device *dev = musb->controller; | |
175 | struct dsps_glue *glue = dev_get_drvdata(dev->parent); | |
176 | ||
177 | if (timeout == 0) | |
178 | timeout = jiffies + msecs_to_jiffies(3); | |
179 | ||
180 | /* Never idle if active, or when VBUS timeout is not set as host */ | |
181 | if (musb->is_active || (musb->a_wait_bcon == 0 && | |
e47d9254 | 182 | musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) { |
807d0d2b | 183 | dev_dbg(musb->controller, "%s active, deleting timer\n", |
e47d9254 | 184 | usb_otg_state_string(musb->xceiv->otg->state)); |
807d0d2b SAS |
185 | del_timer(&glue->timer); |
186 | glue->last_timer = jiffies; | |
187 | return; | |
188 | } | |
24616eb6 | 189 | if (musb->port_mode != MUSB_PORT_MODE_DUAL_ROLE) |
807d0d2b SAS |
190 | return; |
191 | ||
192 | if (!musb->g.dev.driver) | |
193 | return; | |
194 | ||
195 | if (time_after(glue->last_timer, timeout) && | |
196 | timer_pending(&glue->timer)) { | |
197 | dev_dbg(musb->controller, | |
198 | "Longer idle timer already pending, ignoring...\n"); | |
199 | return; | |
200 | } | |
201 | glue->last_timer = timeout; | |
202 | ||
203 | dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n", | |
e47d9254 | 204 | usb_otg_state_string(musb->xceiv->otg->state), |
807d0d2b SAS |
205 | jiffies_to_msecs(timeout - jiffies)); |
206 | mod_timer(&glue->timer, timeout); | |
207 | } | |
208 | ||
9ecb8875 AKG |
209 | /** |
210 | * dsps_musb_enable - enable interrupts | |
211 | */ | |
212 | static void dsps_musb_enable(struct musb *musb) | |
213 | { | |
214 | struct device *dev = musb->controller; | |
215 | struct platform_device *pdev = to_platform_device(dev->parent); | |
216 | struct dsps_glue *glue = platform_get_drvdata(pdev); | |
217 | const struct dsps_musb_wrapper *wrp = glue->wrp; | |
218 | void __iomem *reg_base = musb->ctrl_base; | |
219 | u32 epmask, coremask; | |
220 | ||
221 | /* Workaround: setup IRQs through both register sets. */ | |
222 | epmask = ((musb->epmask & wrp->txep_mask) << wrp->txep_shift) | | |
223 | ((musb->epmask & wrp->rxep_mask) << wrp->rxep_shift); | |
224 | coremask = (wrp->usb_bitmap & ~MUSB_INTR_SOF); | |
225 | ||
226 | dsps_writel(reg_base, wrp->epintr_set, epmask); | |
227 | dsps_writel(reg_base, wrp->coreintr_set, coremask); | |
228 | /* Force the DRVVBUS IRQ so we can start polling for ID change. */ | |
032ec49f FB |
229 | dsps_writel(reg_base, wrp->coreintr_set, |
230 | (1 << wrp->drvvbus) << wrp->usb_shift); | |
8b9fcce2 | 231 | dsps_musb_try_idle(musb, 0); |
9ecb8875 AKG |
232 | } |
233 | ||
234 | /** | |
235 | * dsps_musb_disable - disable HDRC and flush interrupts | |
236 | */ | |
237 | static void dsps_musb_disable(struct musb *musb) | |
238 | { | |
239 | struct device *dev = musb->controller; | |
240 | struct platform_device *pdev = to_platform_device(dev->parent); | |
241 | struct dsps_glue *glue = platform_get_drvdata(pdev); | |
242 | const struct dsps_musb_wrapper *wrp = glue->wrp; | |
243 | void __iomem *reg_base = musb->ctrl_base; | |
244 | ||
245 | dsps_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap); | |
246 | dsps_writel(reg_base, wrp->epintr_clear, | |
247 | wrp->txep_bitmap | wrp->rxep_bitmap); | |
248 | dsps_writeb(musb->mregs, MUSB_DEVCTL, 0); | |
9ecb8875 AKG |
249 | } |
250 | ||
251 | static void otg_timer(unsigned long _musb) | |
252 | { | |
253 | struct musb *musb = (void *)_musb; | |
254 | void __iomem *mregs = musb->mregs; | |
255 | struct device *dev = musb->controller; | |
db4a9320 | 256 | struct dsps_glue *glue = dev_get_drvdata(dev->parent); |
9ecb8875 AKG |
257 | const struct dsps_musb_wrapper *wrp = glue->wrp; |
258 | u8 devctl; | |
259 | unsigned long flags; | |
0f901c98 | 260 | int skip_session = 0; |
9ecb8875 AKG |
261 | |
262 | /* | |
263 | * We poll because DSPS IP's won't expose several OTG-critical | |
264 | * status change events (from the transceiver) otherwise. | |
265 | */ | |
266 | devctl = dsps_readb(mregs, MUSB_DEVCTL); | |
267 | dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl, | |
e47d9254 | 268 | usb_otg_state_string(musb->xceiv->otg->state)); |
9ecb8875 AKG |
269 | |
270 | spin_lock_irqsave(&musb->lock, flags); | |
e47d9254 | 271 | switch (musb->xceiv->otg->state) { |
9ecb8875 | 272 | case OTG_STATE_A_WAIT_BCON: |
0f901c98 SAS |
273 | dsps_writeb(musb->mregs, MUSB_DEVCTL, 0); |
274 | skip_session = 1; | |
275 | /* fall */ | |
9ecb8875 | 276 | |
0f901c98 SAS |
277 | case OTG_STATE_A_IDLE: |
278 | case OTG_STATE_B_IDLE: | |
9ecb8875 | 279 | if (devctl & MUSB_DEVCTL_BDEVICE) { |
e47d9254 | 280 | musb->xceiv->otg->state = OTG_STATE_B_IDLE; |
9ecb8875 AKG |
281 | MUSB_DEV_MODE(musb); |
282 | } else { | |
e47d9254 | 283 | musb->xceiv->otg->state = OTG_STATE_A_IDLE; |
9ecb8875 AKG |
284 | MUSB_HST_MODE(musb); |
285 | } | |
0f901c98 SAS |
286 | if (!(devctl & MUSB_DEVCTL_SESSION) && !skip_session) |
287 | dsps_writeb(mregs, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); | |
288 | mod_timer(&glue->timer, jiffies + wrp->poll_seconds * HZ); | |
9ecb8875 AKG |
289 | break; |
290 | case OTG_STATE_A_WAIT_VFALL: | |
e47d9254 | 291 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; |
9ecb8875 AKG |
292 | dsps_writel(musb->ctrl_base, wrp->coreintr_set, |
293 | MUSB_INTR_VBUSERROR << wrp->usb_shift); | |
294 | break; | |
9ecb8875 AKG |
295 | default: |
296 | break; | |
297 | } | |
298 | spin_unlock_irqrestore(&musb->lock, flags); | |
299 | } | |
300 | ||
9ecb8875 AKG |
301 | static irqreturn_t dsps_interrupt(int irq, void *hci) |
302 | { | |
303 | struct musb *musb = hci; | |
304 | void __iomem *reg_base = musb->ctrl_base; | |
305 | struct device *dev = musb->controller; | |
db4a9320 | 306 | struct dsps_glue *glue = dev_get_drvdata(dev->parent); |
9ecb8875 AKG |
307 | const struct dsps_musb_wrapper *wrp = glue->wrp; |
308 | unsigned long flags; | |
309 | irqreturn_t ret = IRQ_NONE; | |
310 | u32 epintr, usbintr; | |
311 | ||
312 | spin_lock_irqsave(&musb->lock, flags); | |
313 | ||
314 | /* Get endpoint interrupts */ | |
315 | epintr = dsps_readl(reg_base, wrp->epintr_status); | |
316 | musb->int_rx = (epintr & wrp->rxep_bitmap) >> wrp->rxep_shift; | |
317 | musb->int_tx = (epintr & wrp->txep_bitmap) >> wrp->txep_shift; | |
318 | ||
319 | if (epintr) | |
320 | dsps_writel(reg_base, wrp->epintr_status, epintr); | |
321 | ||
322 | /* Get usb core interrupts */ | |
323 | usbintr = dsps_readl(reg_base, wrp->coreintr_status); | |
324 | if (!usbintr && !epintr) | |
9be73bae | 325 | goto out; |
9ecb8875 AKG |
326 | |
327 | musb->int_usb = (usbintr & wrp->usb_bitmap) >> wrp->usb_shift; | |
328 | if (usbintr) | |
329 | dsps_writel(reg_base, wrp->coreintr_status, usbintr); | |
330 | ||
331 | dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n", | |
332 | usbintr, epintr); | |
333 | /* | |
334 | * DRVVBUS IRQs are the only proxy we have (a very poor one!) for | |
335 | * DSPS IP's missing ID change IRQ. We need an ID change IRQ to | |
336 | * switch appropriately between halves of the OTG state machine. | |
337 | * Managing DEVCTL.SESSION per Mentor docs requires that we know its | |
338 | * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set. | |
339 | * Also, DRVVBUS pulses for SRP (but not at 5V) ... | |
340 | */ | |
1d57de30 | 341 | if (is_host_active(musb) && usbintr & MUSB_INTR_BABBLE) { |
984e833c | 342 | pr_info("CAUTION: musb: Babble Interrupt Occurred\n"); |
9ecb8875 | 343 | |
1d57de30 DM |
344 | /* |
345 | * When a babble condition occurs, the musb controller removes | |
346 | * the session and is no longer in host mode. Hence, all | |
347 | * devices connected to its root hub get disconnected. | |
348 | * | |
349 | * Hand this error down to the musb core isr, so it can | |
350 | * recover. | |
351 | */ | |
352 | musb->int_usb = MUSB_INTR_BABBLE | MUSB_INTR_DISCONNECT; | |
353 | musb->int_tx = musb->int_rx = 0; | |
354 | } | |
355 | ||
9ecb8875 AKG |
356 | if (usbintr & ((1 << wrp->drvvbus) << wrp->usb_shift)) { |
357 | int drvvbus = dsps_readl(reg_base, wrp->status); | |
358 | void __iomem *mregs = musb->mregs; | |
359 | u8 devctl = dsps_readb(mregs, MUSB_DEVCTL); | |
360 | int err; | |
361 | ||
032ec49f | 362 | err = musb->int_usb & MUSB_INTR_VBUSERROR; |
9ecb8875 AKG |
363 | if (err) { |
364 | /* | |
365 | * The Mentor core doesn't debounce VBUS as needed | |
366 | * to cope with device connect current spikes. This | |
367 | * means it's not uncommon for bus-powered devices | |
368 | * to get VBUS errors during enumeration. | |
369 | * | |
370 | * This is a workaround, but newer RTL from Mentor | |
371 | * seems to allow a better one: "re"-starting sessions | |
372 | * without waiting for VBUS to stop registering in | |
373 | * devctl. | |
374 | */ | |
375 | musb->int_usb &= ~MUSB_INTR_VBUSERROR; | |
e47d9254 | 376 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; |
97238b35 | 377 | mod_timer(&glue->timer, |
9ecb8875 AKG |
378 | jiffies + wrp->poll_seconds * HZ); |
379 | WARNING("VBUS error workaround (delay coming)\n"); | |
032ec49f | 380 | } else if (drvvbus) { |
9ecb8875 AKG |
381 | MUSB_HST_MODE(musb); |
382 | musb->xceiv->otg->default_a = 1; | |
e47d9254 | 383 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; |
97238b35 | 384 | del_timer(&glue->timer); |
9ecb8875 AKG |
385 | } else { |
386 | musb->is_active = 0; | |
387 | MUSB_DEV_MODE(musb); | |
388 | musb->xceiv->otg->default_a = 0; | |
e47d9254 | 389 | musb->xceiv->otg->state = OTG_STATE_B_IDLE; |
9ecb8875 AKG |
390 | } |
391 | ||
392 | /* NOTE: this must complete power-on within 100 ms. */ | |
393 | dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n", | |
394 | drvvbus ? "on" : "off", | |
e47d9254 | 395 | usb_otg_state_string(musb->xceiv->otg->state), |
9ecb8875 AKG |
396 | err ? " ERROR" : "", |
397 | devctl); | |
398 | ret = IRQ_HANDLED; | |
399 | } | |
400 | ||
401 | if (musb->int_tx || musb->int_rx || musb->int_usb) | |
402 | ret |= musb_interrupt(musb); | |
403 | ||
5ace3d00 | 404 | /* Poll for ID change in OTG port mode */ |
e47d9254 | 405 | if (musb->xceiv->otg->state == OTG_STATE_B_IDLE && |
5ace3d00 | 406 | musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE) |
97238b35 | 407 | mod_timer(&glue->timer, jiffies + wrp->poll_seconds * HZ); |
9be73bae | 408 | out: |
9ecb8875 AKG |
409 | spin_unlock_irqrestore(&musb->lock, flags); |
410 | ||
411 | return ret; | |
412 | } | |
413 | ||
40f099e3 MP |
414 | static int dsps_musb_dbg_init(struct musb *musb, struct dsps_glue *glue) |
415 | { | |
416 | struct dentry *root; | |
417 | struct dentry *file; | |
418 | char buf[128]; | |
419 | ||
420 | sprintf(buf, "%s.dsps", dev_name(musb->controller)); | |
421 | root = debugfs_create_dir(buf, NULL); | |
422 | if (!root) | |
423 | return -ENOMEM; | |
424 | glue->dbgfs_root = root; | |
425 | ||
426 | glue->regset.regs = dsps_musb_regs; | |
427 | glue->regset.nregs = ARRAY_SIZE(dsps_musb_regs); | |
428 | glue->regset.base = musb->ctrl_base; | |
429 | ||
430 | file = debugfs_create_regset32("regdump", S_IRUGO, root, &glue->regset); | |
431 | if (!file) { | |
432 | debugfs_remove_recursive(root); | |
433 | return -ENOMEM; | |
434 | } | |
435 | return 0; | |
436 | } | |
437 | ||
9ecb8875 AKG |
438 | static int dsps_musb_init(struct musb *musb) |
439 | { | |
440 | struct device *dev = musb->controller; | |
db4a9320 | 441 | struct dsps_glue *glue = dev_get_drvdata(dev->parent); |
97238b35 | 442 | struct platform_device *parent = to_platform_device(dev->parent); |
9ecb8875 | 443 | const struct dsps_musb_wrapper *wrp = glue->wrp; |
97238b35 SAS |
444 | void __iomem *reg_base; |
445 | struct resource *r; | |
9ecb8875 | 446 | u32 rev, val; |
40f099e3 | 447 | int ret; |
9ecb8875 | 448 | |
97238b35 | 449 | r = platform_get_resource_byname(parent, IORESOURCE_MEM, "control"); |
97238b35 | 450 | reg_base = devm_ioremap_resource(dev, r); |
51ef74f6 JL |
451 | if (IS_ERR(reg_base)) |
452 | return PTR_ERR(reg_base); | |
97238b35 | 453 | musb->ctrl_base = reg_base; |
9ecb8875 | 454 | |
d7554226 | 455 | /* NOP driver needs change if supporting dual instance */ |
97238b35 SAS |
456 | musb->xceiv = devm_usb_get_phy_by_phandle(dev, "phys", 0); |
457 | if (IS_ERR(musb->xceiv)) | |
458 | return PTR_ERR(musb->xceiv); | |
9ecb8875 AKG |
459 | |
460 | /* Returns zero if e.g. not clocked */ | |
461 | rev = dsps_readl(reg_base, wrp->revision); | |
97238b35 SAS |
462 | if (!rev) |
463 | return -ENODEV; | |
9ecb8875 | 464 | |
7557a57f | 465 | usb_phy_init(musb->xceiv); |
97238b35 | 466 | setup_timer(&glue->timer, otg_timer, (unsigned long) musb); |
9ecb8875 AKG |
467 | |
468 | /* Reset the musb */ | |
469 | dsps_writel(reg_base, wrp->control, (1 << wrp->reset)); | |
470 | ||
9ecb8875 AKG |
471 | musb->isr = dsps_interrupt; |
472 | ||
473 | /* reset the otgdisable bit, needed for host mode to work */ | |
474 | val = dsps_readl(reg_base, wrp->phy_utmi); | |
475 | val &= ~(1 << wrp->otg_disable); | |
476 | dsps_writel(musb->ctrl_base, wrp->phy_utmi, val); | |
477 | ||
371254ce GC |
478 | /* |
479 | * Check whether the dsps version has babble control enabled. | |
480 | * In latest silicon revision the babble control logic is enabled. | |
481 | * If MUSB_BABBLE_CTL returns 0x4 then we have the babble control | |
482 | * logic enabled. | |
483 | */ | |
484 | val = dsps_readb(musb->mregs, MUSB_BABBLE_CTL); | |
485 | if (val == MUSB_BABBLE_RCV_DISABLE) { | |
486 | glue->sw_babble_enabled = true; | |
487 | val |= MUSB_BABBLE_SW_SESSION_CTRL; | |
488 | dsps_writeb(musb->mregs, MUSB_BABBLE_CTL, val); | |
489 | } | |
490 | ||
40f099e3 MP |
491 | ret = dsps_musb_dbg_init(musb, glue); |
492 | if (ret) | |
493 | return ret; | |
494 | ||
9ecb8875 | 495 | return 0; |
9ecb8875 AKG |
496 | } |
497 | ||
498 | static int dsps_musb_exit(struct musb *musb) | |
499 | { | |
500 | struct device *dev = musb->controller; | |
db4a9320 | 501 | struct dsps_glue *glue = dev_get_drvdata(dev->parent); |
9ecb8875 | 502 | |
97238b35 | 503 | del_timer_sync(&glue->timer); |
7557a57f | 504 | usb_phy_shutdown(musb->xceiv); |
0fca91b8 DM |
505 | debugfs_remove_recursive(glue->dbgfs_root); |
506 | ||
9ecb8875 AKG |
507 | return 0; |
508 | } | |
509 | ||
943c1397 FB |
510 | static int dsps_musb_set_mode(struct musb *musb, u8 mode) |
511 | { | |
512 | struct device *dev = musb->controller; | |
513 | struct dsps_glue *glue = dev_get_drvdata(dev->parent); | |
514 | const struct dsps_musb_wrapper *wrp = glue->wrp; | |
515 | void __iomem *ctrl_base = musb->ctrl_base; | |
943c1397 FB |
516 | u32 reg; |
517 | ||
80356913 | 518 | reg = dsps_readl(ctrl_base, wrp->mode); |
943c1397 FB |
519 | |
520 | switch (mode) { | |
521 | case MUSB_HOST: | |
522 | reg &= ~(1 << wrp->iddig); | |
523 | ||
524 | /* | |
525 | * if we're setting mode to host-only or device-only, we're | |
526 | * going to ignore whatever the PHY sends us and just force | |
527 | * ID pin status by SW | |
528 | */ | |
529 | reg |= (1 << wrp->iddig_mux); | |
530 | ||
80356913 | 531 | dsps_writel(ctrl_base, wrp->mode, reg); |
943c1397 FB |
532 | dsps_writel(ctrl_base, wrp->phy_utmi, 0x02); |
533 | break; | |
534 | case MUSB_PERIPHERAL: | |
535 | reg |= (1 << wrp->iddig); | |
536 | ||
537 | /* | |
538 | * if we're setting mode to host-only or device-only, we're | |
539 | * going to ignore whatever the PHY sends us and just force | |
540 | * ID pin status by SW | |
541 | */ | |
542 | reg |= (1 << wrp->iddig_mux); | |
543 | ||
80356913 | 544 | dsps_writel(ctrl_base, wrp->mode, reg); |
943c1397 FB |
545 | break; |
546 | case MUSB_OTG: | |
80356913 | 547 | dsps_writel(ctrl_base, wrp->phy_utmi, 0x02); |
943c1397 FB |
548 | break; |
549 | default: | |
550 | dev_err(glue->dev, "unsupported mode %d\n", mode); | |
551 | return -EINVAL; | |
552 | } | |
553 | ||
554 | return 0; | |
555 | } | |
556 | ||
371254ce GC |
557 | static bool sw_babble_control(struct musb *musb) |
558 | { | |
559 | u8 babble_ctl; | |
560 | bool session_restart = false; | |
561 | ||
562 | babble_ctl = dsps_readb(musb->mregs, MUSB_BABBLE_CTL); | |
563 | dev_dbg(musb->controller, "babble: MUSB_BABBLE_CTL value %x\n", | |
564 | babble_ctl); | |
565 | /* | |
566 | * check line monitor flag to check whether babble is | |
567 | * due to noise | |
568 | */ | |
569 | dev_dbg(musb->controller, "STUCK_J is %s\n", | |
570 | babble_ctl & MUSB_BABBLE_STUCK_J ? "set" : "reset"); | |
571 | ||
572 | if (babble_ctl & MUSB_BABBLE_STUCK_J) { | |
573 | int timeout = 10; | |
574 | ||
575 | /* | |
576 | * babble is due to noise, then set transmit idle (d7 bit) | |
577 | * to resume normal operation | |
578 | */ | |
579 | babble_ctl = dsps_readb(musb->mregs, MUSB_BABBLE_CTL); | |
580 | babble_ctl |= MUSB_BABBLE_FORCE_TXIDLE; | |
581 | dsps_writeb(musb->mregs, MUSB_BABBLE_CTL, babble_ctl); | |
582 | ||
583 | /* wait till line monitor flag cleared */ | |
584 | dev_dbg(musb->controller, "Set TXIDLE, wait J to clear\n"); | |
585 | do { | |
586 | babble_ctl = dsps_readb(musb->mregs, MUSB_BABBLE_CTL); | |
587 | udelay(1); | |
588 | } while ((babble_ctl & MUSB_BABBLE_STUCK_J) && timeout--); | |
589 | ||
590 | /* check whether stuck_at_j bit cleared */ | |
591 | if (babble_ctl & MUSB_BABBLE_STUCK_J) { | |
592 | /* | |
593 | * real babble condition has occurred | |
594 | * restart the controller to start the | |
595 | * session again | |
596 | */ | |
597 | dev_dbg(musb->controller, "J not cleared, misc (%x)\n", | |
598 | babble_ctl); | |
599 | session_restart = true; | |
600 | } | |
601 | } else { | |
602 | session_restart = true; | |
603 | } | |
604 | ||
605 | return session_restart; | |
606 | } | |
607 | ||
d871c622 | 608 | static int dsps_musb_reset(struct musb *musb) |
1d57de30 DM |
609 | { |
610 | struct device *dev = musb->controller; | |
611 | struct dsps_glue *glue = dev_get_drvdata(dev->parent); | |
612 | const struct dsps_musb_wrapper *wrp = glue->wrp; | |
371254ce | 613 | int session_restart = 0; |
1d57de30 | 614 | |
371254ce GC |
615 | if (glue->sw_babble_enabled) |
616 | session_restart = sw_babble_control(musb); | |
617 | /* | |
618 | * In case of new silicon version babble condition can be recovered | |
619 | * without resetting the MUSB. But for older silicon versions, MUSB | |
620 | * reset is needed | |
621 | */ | |
622 | if (session_restart || !glue->sw_babble_enabled) { | |
623 | dev_info(musb->controller, "Restarting MUSB to recover from Babble\n"); | |
624 | dsps_writel(musb->ctrl_base, wrp->control, (1 << wrp->reset)); | |
625 | usleep_range(100, 200); | |
626 | usb_phy_shutdown(musb->xceiv); | |
627 | usleep_range(100, 200); | |
628 | usb_phy_init(musb->xceiv); | |
629 | session_restart = 1; | |
630 | } | |
1d57de30 | 631 | |
371254ce | 632 | return !session_restart; |
1d57de30 DM |
633 | } |
634 | ||
9ecb8875 AKG |
635 | static struct musb_platform_ops dsps_ops = { |
636 | .init = dsps_musb_init, | |
637 | .exit = dsps_musb_exit, | |
638 | ||
639 | .enable = dsps_musb_enable, | |
640 | .disable = dsps_musb_disable, | |
641 | ||
642 | .try_idle = dsps_musb_try_idle, | |
943c1397 | 643 | .set_mode = dsps_musb_set_mode, |
1d57de30 | 644 | .reset = dsps_musb_reset, |
9ecb8875 AKG |
645 | }; |
646 | ||
647 | static u64 musb_dmamask = DMA_BIT_MASK(32); | |
648 | ||
97238b35 | 649 | static int get_int_prop(struct device_node *dn, const char *s) |
9ecb8875 | 650 | { |
97238b35 SAS |
651 | int ret; |
652 | u32 val; | |
653 | ||
654 | ret = of_property_read_u32(dn, s, &val); | |
655 | if (ret) | |
656 | return 0; | |
657 | return val; | |
658 | } | |
659 | ||
c031a7d4 SAS |
660 | static int get_musb_port_mode(struct device *dev) |
661 | { | |
662 | enum usb_dr_mode mode; | |
663 | ||
664 | mode = of_usb_get_dr_mode(dev->of_node); | |
665 | switch (mode) { | |
666 | case USB_DR_MODE_HOST: | |
667 | return MUSB_PORT_MODE_HOST; | |
668 | ||
669 | case USB_DR_MODE_PERIPHERAL: | |
670 | return MUSB_PORT_MODE_GADGET; | |
671 | ||
672 | case USB_DR_MODE_UNKNOWN: | |
673 | case USB_DR_MODE_OTG: | |
674 | default: | |
675 | return MUSB_PORT_MODE_DUAL_ROLE; | |
2b84f92b | 676 | } |
c031a7d4 SAS |
677 | } |
678 | ||
97238b35 SAS |
679 | static int dsps_create_musb_pdev(struct dsps_glue *glue, |
680 | struct platform_device *parent) | |
681 | { | |
682 | struct musb_hdrc_platform_data pdata; | |
9ecb8875 | 683 | struct resource resources[2]; |
c031a7d4 | 684 | struct resource *res; |
97238b35 SAS |
685 | struct device *dev = &parent->dev; |
686 | struct musb_hdrc_config *config; | |
687 | struct platform_device *musb; | |
688 | struct device_node *dn = parent->dev.of_node; | |
2f771164 | 689 | int ret; |
9ecb8875 | 690 | |
97238b35 | 691 | memset(resources, 0, sizeof(resources)); |
c031a7d4 SAS |
692 | res = platform_get_resource_byname(parent, IORESOURCE_MEM, "mc"); |
693 | if (!res) { | |
97238b35 | 694 | dev_err(dev, "failed to get memory.\n"); |
c031a7d4 | 695 | return -EINVAL; |
9ecb8875 | 696 | } |
c031a7d4 | 697 | resources[0] = *res; |
97238b35 | 698 | |
c031a7d4 SAS |
699 | res = platform_get_resource_byname(parent, IORESOURCE_IRQ, "mc"); |
700 | if (!res) { | |
97238b35 | 701 | dev_err(dev, "failed to get irq.\n"); |
c031a7d4 | 702 | return -EINVAL; |
9ecb8875 | 703 | } |
c031a7d4 | 704 | resources[1] = *res; |
9ecb8875 AKG |
705 | |
706 | /* allocate the child platform device */ | |
2f771164 | 707 | musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO); |
9ecb8875 AKG |
708 | if (!musb) { |
709 | dev_err(dev, "failed to allocate musb device\n"); | |
97238b35 | 710 | return -ENOMEM; |
9ecb8875 AKG |
711 | } |
712 | ||
713 | musb->dev.parent = dev; | |
714 | musb->dev.dma_mask = &musb_dmamask; | |
715 | musb->dev.coherent_dma_mask = musb_dmamask; | |
c031a7d4 | 716 | musb->dev.of_node = of_node_get(dn); |
9ecb8875 | 717 | |
97238b35 | 718 | glue->musb = musb; |
9ecb8875 | 719 | |
97238b35 SAS |
720 | ret = platform_device_add_resources(musb, resources, |
721 | ARRAY_SIZE(resources)); | |
9ecb8875 AKG |
722 | if (ret) { |
723 | dev_err(dev, "failed to add resources\n"); | |
97238b35 | 724 | goto err; |
9ecb8875 AKG |
725 | } |
726 | ||
97238b35 SAS |
727 | config = devm_kzalloc(&parent->dev, sizeof(*config), GFP_KERNEL); |
728 | if (!config) { | |
97238b35 SAS |
729 | ret = -ENOMEM; |
730 | goto err; | |
65145677 | 731 | } |
97238b35 SAS |
732 | pdata.config = config; |
733 | pdata.platform_ops = &dsps_ops; | |
65145677 | 734 | |
c031a7d4 SAS |
735 | config->num_eps = get_int_prop(dn, "mentor,num-eps"); |
736 | config->ram_bits = get_int_prop(dn, "mentor,ram-bits"); | |
869c5978 | 737 | config->host_port_deassert_reset_at_resume = 1; |
c031a7d4 SAS |
738 | pdata.mode = get_musb_port_mode(dev); |
739 | /* DT keeps this entry in mA, musb expects it as per USB spec */ | |
740 | pdata.power = get_int_prop(dn, "mentor,power") / 2; | |
741 | config->multipoint = of_property_read_bool(dn, "mentor,multipoint"); | |
65145677 | 742 | |
97238b35 | 743 | ret = platform_device_add_data(musb, &pdata, sizeof(pdata)); |
9ecb8875 AKG |
744 | if (ret) { |
745 | dev_err(dev, "failed to add platform_data\n"); | |
97238b35 | 746 | goto err; |
9ecb8875 AKG |
747 | } |
748 | ||
749 | ret = platform_device_add(musb); | |
750 | if (ret) { | |
751 | dev_err(dev, "failed to register musb device\n"); | |
97238b35 | 752 | goto err; |
9ecb8875 | 753 | } |
9ecb8875 AKG |
754 | return 0; |
755 | ||
97238b35 | 756 | err: |
9ecb8875 | 757 | platform_device_put(musb); |
9ecb8875 AKG |
758 | return ret; |
759 | } | |
760 | ||
41ac7b3a | 761 | static int dsps_probe(struct platform_device *pdev) |
9ecb8875 | 762 | { |
65145677 AKG |
763 | const struct of_device_id *match; |
764 | const struct dsps_musb_wrapper *wrp; | |
9ecb8875 | 765 | struct dsps_glue *glue; |
97238b35 | 766 | int ret; |
9ecb8875 | 767 | |
4fc4b274 SAS |
768 | if (!strcmp(pdev->name, "musb-hdrc")) |
769 | return -ENODEV; | |
770 | ||
cc506036 | 771 | match = of_match_node(musb_dsps_of_match, pdev->dev.of_node); |
65145677 AKG |
772 | if (!match) { |
773 | dev_err(&pdev->dev, "fail to get matching of_match struct\n"); | |
97238b35 | 774 | return -EINVAL; |
65145677 AKG |
775 | } |
776 | wrp = match->data; | |
9ecb8875 AKG |
777 | |
778 | /* allocate glue */ | |
de9db572 | 779 | glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL); |
0816ea2f | 780 | if (!glue) |
97238b35 | 781 | return -ENOMEM; |
9ecb8875 AKG |
782 | |
783 | glue->dev = &pdev->dev; | |
97238b35 | 784 | glue->wrp = wrp; |
9ecb8875 | 785 | |
9ecb8875 | 786 | platform_set_drvdata(pdev, glue); |
9ecb8875 AKG |
787 | pm_runtime_enable(&pdev->dev); |
788 | ||
789 | ret = pm_runtime_get_sync(&pdev->dev); | |
790 | if (ret < 0) { | |
791 | dev_err(&pdev->dev, "pm_runtime_get_sync FAILED"); | |
0e38c4ed AKG |
792 | goto err2; |
793 | } | |
794 | ||
97238b35 SAS |
795 | ret = dsps_create_musb_pdev(glue, pdev); |
796 | if (ret) | |
797 | goto err3; | |
9ecb8875 AKG |
798 | |
799 | return 0; | |
800 | ||
801 | err3: | |
0e38c4ed | 802 | pm_runtime_put(&pdev->dev); |
9ecb8875 | 803 | err2: |
0e38c4ed | 804 | pm_runtime_disable(&pdev->dev); |
9ecb8875 AKG |
805 | return ret; |
806 | } | |
97238b35 | 807 | |
fb4e98ab | 808 | static int dsps_remove(struct platform_device *pdev) |
9ecb8875 AKG |
809 | { |
810 | struct dsps_glue *glue = platform_get_drvdata(pdev); | |
811 | ||
97238b35 | 812 | platform_device_unregister(glue->musb); |
9ecb8875 AKG |
813 | |
814 | /* disable usbss clocks */ | |
815 | pm_runtime_put(&pdev->dev); | |
816 | pm_runtime_disable(&pdev->dev); | |
40f099e3 | 817 | |
9ecb8875 AKG |
818 | return 0; |
819 | } | |
820 | ||
fa7b4ca5 | 821 | static const struct dsps_musb_wrapper am33xx_driver_data = { |
9ecb8875 AKG |
822 | .revision = 0x00, |
823 | .control = 0x14, | |
824 | .status = 0x18, | |
9ecb8875 AKG |
825 | .epintr_set = 0x38, |
826 | .epintr_clear = 0x40, | |
827 | .epintr_status = 0x30, | |
828 | .coreintr_set = 0x3c, | |
829 | .coreintr_clear = 0x44, | |
830 | .coreintr_status = 0x34, | |
831 | .phy_utmi = 0xe0, | |
832 | .mode = 0xe8, | |
b991f9b7 DM |
833 | .tx_mode = 0x70, |
834 | .rx_mode = 0x74, | |
9ecb8875 AKG |
835 | .reset = 0, |
836 | .otg_disable = 21, | |
837 | .iddig = 8, | |
943c1397 | 838 | .iddig_mux = 7, |
9ecb8875 AKG |
839 | .usb_shift = 0, |
840 | .usb_mask = 0x1ff, | |
841 | .usb_bitmap = (0x1ff << 0), | |
842 | .drvvbus = 8, | |
843 | .txep_shift = 0, | |
844 | .txep_mask = 0xffff, | |
845 | .txep_bitmap = (0xffff << 0), | |
846 | .rxep_shift = 16, | |
847 | .rxep_mask = 0xfffe, | |
848 | .rxep_bitmap = (0xfffe << 16), | |
9ecb8875 AKG |
849 | .poll_seconds = 2, |
850 | }; | |
851 | ||
2f82686e | 852 | static const struct of_device_id musb_dsps_of_match[] = { |
65145677 | 853 | { .compatible = "ti,musb-am33xx", |
fa7b4ca5 | 854 | .data = (void *) &am33xx_driver_data, }, |
9ecb8875 AKG |
855 | { }, |
856 | }; | |
857 | MODULE_DEVICE_TABLE(of, musb_dsps_of_match); | |
858 | ||
5b783983 | 859 | #ifdef CONFIG_PM_SLEEP |
869c5978 DM |
860 | static int dsps_suspend(struct device *dev) |
861 | { | |
862 | struct dsps_glue *glue = dev_get_drvdata(dev); | |
863 | const struct dsps_musb_wrapper *wrp = glue->wrp; | |
864 | struct musb *musb = platform_get_drvdata(glue->musb); | |
f042e9cb | 865 | void __iomem *mbase; |
869c5978 | 866 | |
468bcc2a | 867 | del_timer_sync(&glue->timer); |
f042e9cb SAS |
868 | |
869 | if (!musb) | |
870 | /* This can happen if the musb device is in -EPROBE_DEFER */ | |
871 | return 0; | |
872 | ||
873 | mbase = musb->ctrl_base; | |
869c5978 DM |
874 | glue->context.control = dsps_readl(mbase, wrp->control); |
875 | glue->context.epintr = dsps_readl(mbase, wrp->epintr_set); | |
876 | glue->context.coreintr = dsps_readl(mbase, wrp->coreintr_set); | |
877 | glue->context.phy_utmi = dsps_readl(mbase, wrp->phy_utmi); | |
878 | glue->context.mode = dsps_readl(mbase, wrp->mode); | |
879 | glue->context.tx_mode = dsps_readl(mbase, wrp->tx_mode); | |
880 | glue->context.rx_mode = dsps_readl(mbase, wrp->rx_mode); | |
881 | ||
882 | return 0; | |
883 | } | |
884 | ||
885 | static int dsps_resume(struct device *dev) | |
886 | { | |
887 | struct dsps_glue *glue = dev_get_drvdata(dev); | |
888 | const struct dsps_musb_wrapper *wrp = glue->wrp; | |
889 | struct musb *musb = platform_get_drvdata(glue->musb); | |
f042e9cb SAS |
890 | void __iomem *mbase; |
891 | ||
892 | if (!musb) | |
893 | return 0; | |
869c5978 | 894 | |
f042e9cb | 895 | mbase = musb->ctrl_base; |
869c5978 DM |
896 | dsps_writel(mbase, wrp->control, glue->context.control); |
897 | dsps_writel(mbase, wrp->epintr_set, glue->context.epintr); | |
898 | dsps_writel(mbase, wrp->coreintr_set, glue->context.coreintr); | |
899 | dsps_writel(mbase, wrp->phy_utmi, glue->context.phy_utmi); | |
900 | dsps_writel(mbase, wrp->mode, glue->context.mode); | |
901 | dsps_writel(mbase, wrp->tx_mode, glue->context.tx_mode); | |
902 | dsps_writel(mbase, wrp->rx_mode, glue->context.rx_mode); | |
e47d9254 | 903 | if (musb->xceiv->otg->state == OTG_STATE_B_IDLE && |
53185b3a SAS |
904 | musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE) |
905 | mod_timer(&glue->timer, jiffies + wrp->poll_seconds * HZ); | |
869c5978 DM |
906 | |
907 | return 0; | |
908 | } | |
909 | #endif | |
910 | ||
911 | static SIMPLE_DEV_PM_OPS(dsps_pm_ops, dsps_suspend, dsps_resume); | |
912 | ||
9ecb8875 AKG |
913 | static struct platform_driver dsps_usbss_driver = { |
914 | .probe = dsps_probe, | |
7690417d | 915 | .remove = dsps_remove, |
9ecb8875 AKG |
916 | .driver = { |
917 | .name = "musb-dsps", | |
869c5978 | 918 | .pm = &dsps_pm_ops, |
b432cb83 | 919 | .of_match_table = musb_dsps_of_match, |
9ecb8875 | 920 | }, |
9ecb8875 AKG |
921 | }; |
922 | ||
923 | MODULE_DESCRIPTION("TI DSPS MUSB Glue Layer"); | |
924 | MODULE_AUTHOR("Ravi B <ravibabu@ti.com>"); | |
925 | MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>"); | |
926 | MODULE_LICENSE("GPL v2"); | |
927 | ||
97238b35 | 928 | module_platform_driver(dsps_usbss_driver); |