Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
6aba47ca DJ |
3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 | |
47a35522 | 5 | Free Software Foundation, Inc. |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 14 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 15 | (at your option) any later version. |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b | 22 | You should have received a copy of the GNU General Public License |
a9762ec7 | 23 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
24 | |
25 | #include "defs.h" | |
26 | #include "gdb_string.h" | |
5e2e9765 | 27 | #include "gdb_assert.h" |
c906108c SS |
28 | #include "frame.h" |
29 | #include "inferior.h" | |
30 | #include "symtab.h" | |
31 | #include "value.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "language.h" | |
34 | #include "gdbcore.h" | |
35 | #include "symfile.h" | |
36 | #include "objfiles.h" | |
37 | #include "gdbtypes.h" | |
38 | #include "target.h" | |
28d069e6 | 39 | #include "arch-utils.h" |
4e052eda | 40 | #include "regcache.h" |
70f80edf | 41 | #include "osabi.h" |
d1973055 | 42 | #include "mips-tdep.h" |
fe898f56 | 43 | #include "block.h" |
a4b8ebc8 | 44 | #include "reggroups.h" |
c906108c | 45 | #include "opcode/mips.h" |
c2d11a7d JM |
46 | #include "elf/mips.h" |
47 | #include "elf-bfd.h" | |
2475bac3 | 48 | #include "symcat.h" |
a4b8ebc8 | 49 | #include "sim-regno.h" |
a89aa300 | 50 | #include "dis-asm.h" |
edfae063 AC |
51 | #include "frame-unwind.h" |
52 | #include "frame-base.h" | |
53 | #include "trad-frame.h" | |
7d9b040b | 54 | #include "infcall.h" |
fed7ba43 | 55 | #include "floatformat.h" |
29709017 DJ |
56 | #include "remote.h" |
57 | #include "target-descriptions.h" | |
2bd0c3d7 | 58 | #include "dwarf2-frame.h" |
f8b73d13 | 59 | #include "user-regs.h" |
c906108c | 60 | |
8d5f9dcb DJ |
61 | static const struct objfile_data *mips_pdr_data; |
62 | ||
5bbcb741 | 63 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 64 | |
24e05951 | 65 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
66 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
67 | #define ST0_FR (1 << 26) | |
68 | ||
b0069a17 AC |
69 | /* The sizes of floating point registers. */ |
70 | ||
71 | enum | |
72 | { | |
73 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
74 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
75 | }; | |
76 | ||
1a69e1e4 DJ |
77 | enum |
78 | { | |
79 | MIPS32_REGSIZE = 4, | |
80 | MIPS64_REGSIZE = 8 | |
81 | }; | |
0dadbba0 | 82 | |
2e4ebe70 DJ |
83 | static const char *mips_abi_string; |
84 | ||
85 | static const char *mips_abi_strings[] = { | |
86 | "auto", | |
87 | "n32", | |
88 | "o32", | |
28d169de | 89 | "n64", |
2e4ebe70 DJ |
90 | "o64", |
91 | "eabi32", | |
92 | "eabi64", | |
93 | NULL | |
94 | }; | |
95 | ||
f8b73d13 DJ |
96 | /* The standard register names, and all the valid aliases for them. */ |
97 | struct register_alias | |
98 | { | |
99 | const char *name; | |
100 | int regnum; | |
101 | }; | |
102 | ||
103 | /* Aliases for o32 and most other ABIs. */ | |
104 | const struct register_alias mips_o32_aliases[] = { | |
105 | { "ta0", 12 }, | |
106 | { "ta1", 13 }, | |
107 | { "ta2", 14 }, | |
108 | { "ta3", 15 } | |
109 | }; | |
110 | ||
111 | /* Aliases for n32 and n64. */ | |
112 | const struct register_alias mips_n32_n64_aliases[] = { | |
113 | { "ta0", 8 }, | |
114 | { "ta1", 9 }, | |
115 | { "ta2", 10 }, | |
116 | { "ta3", 11 } | |
117 | }; | |
118 | ||
119 | /* Aliases for ABI-independent registers. */ | |
120 | const struct register_alias mips_register_aliases[] = { | |
121 | /* The architecture manuals specify these ABI-independent names for | |
122 | the GPRs. */ | |
123 | #define R(n) { "r" #n, n } | |
124 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
125 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
126 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
127 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
128 | #undef R | |
129 | ||
130 | /* k0 and k1 are sometimes called these instead (for "kernel | |
131 | temp"). */ | |
132 | { "kt0", 26 }, | |
133 | { "kt1", 27 }, | |
134 | ||
135 | /* This is the traditional GDB name for the CP0 status register. */ | |
136 | { "sr", MIPS_PS_REGNUM }, | |
137 | ||
138 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
139 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
140 | ||
141 | /* This is the traditional GDB name for the FCSR. */ | |
142 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
143 | }; | |
144 | ||
7a292a7a | 145 | /* Some MIPS boards don't support floating point while others only |
ceae6e75 | 146 | support single-precision floating-point operations. */ |
c906108c SS |
147 | |
148 | enum mips_fpu_type | |
6d82d43b AC |
149 | { |
150 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
151 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
152 | MIPS_FPU_NONE /* No floating point. */ | |
153 | }; | |
c906108c SS |
154 | |
155 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
156 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
157 | #endif | |
158 | static int mips_fpu_type_auto = 1; | |
159 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 160 | |
9ace0497 | 161 | static int mips_debug = 0; |
7a292a7a | 162 | |
29709017 DJ |
163 | /* Properties (for struct target_desc) describing the g/G packet |
164 | layout. */ | |
165 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
166 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
167 | ||
4eb0ad19 DJ |
168 | struct target_desc *mips_tdesc_gp32; |
169 | struct target_desc *mips_tdesc_gp64; | |
170 | ||
c2d11a7d JM |
171 | /* MIPS specific per-architecture information */ |
172 | struct gdbarch_tdep | |
6d82d43b AC |
173 | { |
174 | /* from the elf header */ | |
175 | int elf_flags; | |
176 | ||
177 | /* mips options */ | |
178 | enum mips_abi mips_abi; | |
179 | enum mips_abi found_abi; | |
180 | enum mips_fpu_type mips_fpu_type; | |
181 | int mips_last_arg_regnum; | |
182 | int mips_last_fp_arg_regnum; | |
6d82d43b AC |
183 | int default_mask_address_p; |
184 | /* Is the target using 64-bit raw integer registers but only | |
185 | storing a left-aligned 32-bit value in each? */ | |
186 | int mips64_transfers_32bit_regs_p; | |
187 | /* Indexes for various registers. IRIX and embedded have | |
188 | different values. This contains the "public" fields. Don't | |
189 | add any that do not need to be public. */ | |
190 | const struct mips_regnum *regnum; | |
191 | /* Register names table for the current register set. */ | |
192 | const char **mips_processor_reg_names; | |
29709017 DJ |
193 | |
194 | /* The size of register data available from the target, if known. | |
195 | This doesn't quite obsolete the manual | |
196 | mips64_transfers_32bit_regs_p, since that is documented to force | |
197 | left alignment even for big endian (very strange). */ | |
198 | int register_size_valid_p; | |
199 | int register_size; | |
6d82d43b | 200 | }; |
c2d11a7d | 201 | |
56cea623 AC |
202 | const struct mips_regnum * |
203 | mips_regnum (struct gdbarch *gdbarch) | |
204 | { | |
205 | return gdbarch_tdep (gdbarch)->regnum; | |
206 | } | |
207 | ||
208 | static int | |
209 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
210 | { | |
211 | return mips_regnum (gdbarch)->fp0 + 12; | |
212 | } | |
213 | ||
0dadbba0 | 214 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 215 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 216 | |
c2d11a7d | 217 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 218 | |
c2d11a7d | 219 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 220 | |
c2d11a7d | 221 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 222 | |
95404a3e AC |
223 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
224 | functions to test, set, or clear bit 0 of addresses. */ | |
225 | ||
226 | static CORE_ADDR | |
227 | is_mips16_addr (CORE_ADDR addr) | |
228 | { | |
229 | return ((addr) & 1); | |
230 | } | |
231 | ||
95404a3e AC |
232 | static CORE_ADDR |
233 | unmake_mips16_addr (CORE_ADDR addr) | |
234 | { | |
5b652102 | 235 | return ((addr) & ~(CORE_ADDR) 1); |
95404a3e AC |
236 | } |
237 | ||
d1973055 KB |
238 | /* Return the MIPS ABI associated with GDBARCH. */ |
239 | enum mips_abi | |
240 | mips_abi (struct gdbarch *gdbarch) | |
241 | { | |
242 | return gdbarch_tdep (gdbarch)->mips_abi; | |
243 | } | |
244 | ||
4246e332 | 245 | int |
1b13c4f6 | 246 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 247 | { |
29709017 DJ |
248 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
249 | ||
250 | /* If we know how big the registers are, use that size. */ | |
251 | if (tdep->register_size_valid_p) | |
252 | return tdep->register_size; | |
253 | ||
254 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
255 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
256 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
257 | } | |
258 | ||
480d3dd2 AC |
259 | /* Return the currently configured (or set) saved register size. */ |
260 | ||
e6bc2e8a | 261 | unsigned int |
13326b4e | 262 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 263 | { |
1a69e1e4 DJ |
264 | switch (mips_abi (gdbarch)) |
265 | { | |
266 | case MIPS_ABI_EABI32: | |
267 | case MIPS_ABI_O32: | |
268 | return 4; | |
269 | case MIPS_ABI_N32: | |
270 | case MIPS_ABI_N64: | |
271 | case MIPS_ABI_O64: | |
272 | case MIPS_ABI_EABI64: | |
273 | return 8; | |
274 | case MIPS_ABI_UNKNOWN: | |
275 | case MIPS_ABI_LAST: | |
276 | default: | |
277 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
278 | } | |
d929b26f AC |
279 | } |
280 | ||
71b8ef93 | 281 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 282 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 283 | "info" field is used for this purpose. |
5a89d8aa | 284 | |
95f1da47 | 285 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
5a89d8aa MS |
286 | i.e. refers to a 16-bit function, and sets a "special" bit in a |
287 | minimal symbol to mark it as a 16-bit function | |
288 | ||
f594e5e9 | 289 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 290 | |
5a89d8aa | 291 | static void |
6d82d43b AC |
292 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
293 | { | |
294 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
295 | { | |
296 | MSYMBOL_INFO (msym) = (char *) | |
297 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
298 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
299 | } | |
5a89d8aa MS |
300 | } |
301 | ||
71b8ef93 MS |
302 | static int |
303 | msymbol_is_special (struct minimal_symbol *msym) | |
304 | { | |
305 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
306 | } | |
307 | ||
88658117 AC |
308 | /* XFER a value from the big/little/left end of the register. |
309 | Depending on the size of the value it might occupy the entire | |
310 | register or just part of it. Make an allowance for this, aligning | |
311 | things accordingly. */ | |
312 | ||
313 | static void | |
ba32f989 DJ |
314 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
315 | int reg_num, int length, | |
870cd05e MK |
316 | enum bfd_endian endian, gdb_byte *in, |
317 | const gdb_byte *out, int buf_offset) | |
88658117 | 318 | { |
88658117 | 319 | int reg_offset = 0; |
72a155b4 UW |
320 | |
321 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
322 | /* Need to transfer the left or right part of the register, based on |
323 | the targets byte order. */ | |
88658117 AC |
324 | switch (endian) |
325 | { | |
326 | case BFD_ENDIAN_BIG: | |
72a155b4 | 327 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
328 | break; |
329 | case BFD_ENDIAN_LITTLE: | |
330 | reg_offset = 0; | |
331 | break; | |
6d82d43b | 332 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
333 | reg_offset = 0; |
334 | break; | |
335 | default: | |
e2e0b3e5 | 336 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
337 | } |
338 | if (mips_debug) | |
cb1d2653 AC |
339 | fprintf_unfiltered (gdb_stderr, |
340 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
341 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
342 | if (mips_debug && out != NULL) |
343 | { | |
344 | int i; | |
cb1d2653 | 345 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 346 | for (i = 0; i < length; i++) |
cb1d2653 | 347 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
348 | } |
349 | if (in != NULL) | |
6d82d43b AC |
350 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
351 | in + buf_offset); | |
88658117 | 352 | if (out != NULL) |
6d82d43b AC |
353 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
354 | out + buf_offset); | |
88658117 AC |
355 | if (mips_debug && in != NULL) |
356 | { | |
357 | int i; | |
cb1d2653 | 358 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 359 | for (i = 0; i < length; i++) |
cb1d2653 | 360 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
361 | } |
362 | if (mips_debug) | |
363 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
364 | } | |
365 | ||
dd824b04 DJ |
366 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
367 | compatiblity mode. A return value of 1 means that we have | |
368 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
369 | ||
370 | static int | |
9c9acae0 | 371 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 372 | { |
72a155b4 | 373 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
374 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
375 | meaningful. */ | |
72a155b4 | 376 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
377 | return 0; |
378 | ||
379 | #if 0 | |
380 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
381 | in all the places we deal with FP registers. PR gdb/413. */ | |
382 | /* Otherwise check the FR bit in the status register - it controls | |
383 | the FP compatiblity mode. If it is clear we are in compatibility | |
384 | mode. */ | |
9c9acae0 | 385 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
386 | return 1; |
387 | #endif | |
361d1df0 | 388 | |
dd824b04 DJ |
389 | return 0; |
390 | } | |
391 | ||
7a292a7a | 392 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 393 | |
a14ed312 | 394 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 395 | |
a14ed312 | 396 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 397 | |
67b2c998 DJ |
398 | static struct type *mips_float_register_type (void); |
399 | static struct type *mips_double_register_type (void); | |
400 | ||
acdb74a0 AC |
401 | /* The list of available "set mips " and "show mips " commands */ |
402 | ||
403 | static struct cmd_list_element *setmipscmdlist = NULL; | |
404 | static struct cmd_list_element *showmipscmdlist = NULL; | |
405 | ||
5e2e9765 KB |
406 | /* Integer registers 0 thru 31 are handled explicitly by |
407 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 408 | are listed in the following tables. */ |
691c0433 | 409 | |
6d82d43b AC |
410 | enum |
411 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
412 | |
413 | /* Generic MIPS. */ | |
414 | ||
415 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
416 | "sr", "lo", "hi", "bad", "cause", "pc", |
417 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
418 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
419 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
420 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
421 | "fsr", "fir", "" /*"fp" */ , "", | |
422 | "", "", "", "", "", "", "", "", | |
423 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
424 | }; |
425 | ||
426 | /* Names of IDT R3041 registers. */ | |
427 | ||
428 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
429 | "sr", "lo", "hi", "bad", "cause", "pc", |
430 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
431 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
432 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
433 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
434 | "fsr", "fir", "", /*"fp" */ "", | |
435 | "", "", "bus", "ccfg", "", "", "", "", | |
436 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
437 | }; |
438 | ||
439 | /* Names of tx39 registers. */ | |
440 | ||
441 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
442 | "sr", "lo", "hi", "bad", "cause", "pc", |
443 | "", "", "", "", "", "", "", "", | |
444 | "", "", "", "", "", "", "", "", | |
445 | "", "", "", "", "", "", "", "", | |
446 | "", "", "", "", "", "", "", "", | |
447 | "", "", "", "", | |
448 | "", "", "", "", "", "", "", "", | |
449 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
450 | }; |
451 | ||
452 | /* Names of IRIX registers. */ | |
453 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
454 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
455 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
456 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
457 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
458 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
459 | }; |
460 | ||
cce74817 | 461 | |
5e2e9765 | 462 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 463 | static const char * |
d93859e2 | 464 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 465 | { |
d93859e2 | 466 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 KB |
467 | /* GPR names for all ABIs other than n32/n64. */ |
468 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
469 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
470 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
471 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
472 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
473 | }; |
474 | ||
475 | /* GPR names for n32 and n64 ABIs. */ | |
476 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
477 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
478 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
479 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
480 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
481 | }; |
482 | ||
d93859e2 | 483 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 484 | |
f57d151a UW |
485 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
486 | but then don't make the raw register names visible. */ | |
d93859e2 UW |
487 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
488 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
489 | return ""; |
490 | ||
5e2e9765 KB |
491 | /* The MIPS integer registers are always mapped from 0 to 31. The |
492 | names of the registers (which reflects the conventions regarding | |
493 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 494 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
495 | { |
496 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 497 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 498 | else |
a4b8ebc8 | 499 | return mips_gpr_names[rawnum]; |
5e2e9765 | 500 | } |
d93859e2 UW |
501 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
502 | return tdesc_register_name (gdbarch, rawnum); | |
503 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
504 | { |
505 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
506 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
507 | } | |
5e2e9765 KB |
508 | else |
509 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 510 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 511 | } |
5e2e9765 | 512 | |
a4b8ebc8 | 513 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 514 | |
a4b8ebc8 AC |
515 | static int |
516 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
517 | struct reggroup *reggroup) | |
518 | { | |
519 | int vector_p; | |
520 | int float_p; | |
521 | int raw_p; | |
72a155b4 UW |
522 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
523 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
524 | if (reggroup == all_reggroup) |
525 | return pseudo; | |
526 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
527 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
528 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
529 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
530 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
531 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
532 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
533 | return 0; |
534 | if (reggroup == float_reggroup) | |
535 | return float_p && pseudo; | |
536 | if (reggroup == vector_reggroup) | |
537 | return vector_p && pseudo; | |
538 | if (reggroup == general_reggroup) | |
539 | return (!vector_p && !float_p) && pseudo; | |
540 | /* Save the pseudo registers. Need to make certain that any code | |
541 | extracting register values from a saved register cache also uses | |
542 | pseudo registers. */ | |
543 | if (reggroup == save_reggroup) | |
544 | return raw_p && pseudo; | |
545 | /* Restore the same pseudo register. */ | |
546 | if (reggroup == restore_reggroup) | |
547 | return raw_p && pseudo; | |
6d82d43b | 548 | return 0; |
a4b8ebc8 AC |
549 | } |
550 | ||
f8b73d13 DJ |
551 | /* Return the groups that a MIPS register can be categorised into. |
552 | This version is only used if we have a target description which | |
553 | describes real registers (and their groups). */ | |
554 | ||
555 | static int | |
556 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
557 | struct reggroup *reggroup) | |
558 | { | |
559 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
560 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
561 | int ret; | |
562 | ||
563 | /* Only save, restore, and display the pseudo registers. Need to | |
564 | make certain that any code extracting register values from a | |
565 | saved register cache also uses pseudo registers. | |
566 | ||
567 | Note: saving and restoring the pseudo registers is slightly | |
568 | strange; if we have 64 bits, we should save and restore all | |
569 | 64 bits. But this is hard and has little benefit. */ | |
570 | if (!pseudo) | |
571 | return 0; | |
572 | ||
573 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
574 | if (ret != -1) | |
575 | return ret; | |
576 | ||
577 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
578 | } | |
579 | ||
a4b8ebc8 | 580 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 581 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 582 | registers. Take care of alignment and size problems. */ |
c5aa993b | 583 | |
a4b8ebc8 AC |
584 | static void |
585 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
47a35522 | 586 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 587 | { |
72a155b4 UW |
588 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
589 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
590 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 591 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 592 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
593 | else if (register_size (gdbarch, rawnum) > |
594 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
595 | { |
596 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
72a155b4 | 597 | || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
598 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
599 | else | |
600 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
601 | } | |
602 | else | |
e2e0b3e5 | 603 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
604 | } |
605 | ||
606 | static void | |
6d82d43b AC |
607 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
608 | struct regcache *regcache, int cookednum, | |
47a35522 | 609 | const gdb_byte *buf) |
a4b8ebc8 | 610 | { |
72a155b4 UW |
611 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
612 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
613 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 614 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 615 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
616 | else if (register_size (gdbarch, rawnum) > |
617 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
618 | { |
619 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
72a155b4 | 620 | || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
621 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
622 | else | |
623 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
624 | } | |
625 | else | |
e2e0b3e5 | 626 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 627 | } |
c5aa993b | 628 | |
c906108c | 629 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 630 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
631 | |
632 | /* Heuristic_proc_start may hunt through the text section for a long | |
633 | time across a 2400 baud serial line. Allows the user to limit this | |
634 | search. */ | |
635 | ||
636 | static unsigned int heuristic_fence_post = 0; | |
637 | ||
46cd78fb | 638 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
639 | register N. NOTE: This defines the pseudo register type so need to |
640 | rebuild the architecture vector. */ | |
43e526b9 JM |
641 | |
642 | static int mips64_transfers_32bit_regs_p = 0; | |
643 | ||
719ec221 AC |
644 | static void |
645 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
646 | struct cmd_list_element *c) | |
43e526b9 | 647 | { |
719ec221 AC |
648 | struct gdbarch_info info; |
649 | gdbarch_info_init (&info); | |
650 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
651 | instead of relying on globals. Doing that would let generic code | |
652 | handle the search for this specific architecture. */ | |
653 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 654 | { |
719ec221 | 655 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 656 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 657 | } |
a4b8ebc8 AC |
658 | } |
659 | ||
47ebcfbe | 660 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 661 | |
ff2e87ac AC |
662 | static int |
663 | mips_convert_register_p (int regnum, struct type *type) | |
664 | { | |
4c6b5505 | 665 | return (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
719ec221 | 666 | && register_size (current_gdbarch, regnum) == 4 |
f57d151a UW |
667 | && (regnum % gdbarch_num_regs (current_gdbarch)) |
668 | >= mips_regnum (current_gdbarch)->fp0 | |
669 | && (regnum % gdbarch_num_regs (current_gdbarch)) | |
670 | < mips_regnum (current_gdbarch)->fp0 + 32 | |
6d82d43b | 671 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
672 | } |
673 | ||
42c466d7 | 674 | static void |
ff2e87ac | 675 | mips_register_to_value (struct frame_info *frame, int regnum, |
47a35522 | 676 | struct type *type, gdb_byte *to) |
102182a9 | 677 | { |
47a35522 MK |
678 | get_frame_register (frame, regnum + 0, to + 4); |
679 | get_frame_register (frame, regnum + 1, to + 0); | |
102182a9 MS |
680 | } |
681 | ||
42c466d7 | 682 | static void |
ff2e87ac | 683 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 684 | struct type *type, const gdb_byte *from) |
102182a9 | 685 | { |
47a35522 MK |
686 | put_frame_register (frame, regnum + 0, from + 4); |
687 | put_frame_register (frame, regnum + 1, from + 0); | |
102182a9 MS |
688 | } |
689 | ||
a4b8ebc8 AC |
690 | /* Return the GDB type object for the "standard" data type of data in |
691 | register REG. */ | |
78fde5f8 KB |
692 | |
693 | static struct type * | |
a4b8ebc8 AC |
694 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
695 | { | |
72a155b4 UW |
696 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
697 | if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0 | |
698 | && (regnum % gdbarch_num_regs (gdbarch)) | |
699 | < mips_regnum (gdbarch)->fp0 + 32) | |
a6425924 | 700 | { |
5ef80fb0 | 701 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 702 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 DJ |
703 | if (mips_isa_regsize (gdbarch) == 4) |
704 | return builtin_type_ieee_single; | |
705 | else | |
706 | return builtin_type_ieee_double; | |
a6425924 | 707 | } |
72a155b4 | 708 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
709 | { |
710 | /* The raw or ISA registers. These are all sized according to | |
711 | the ISA regsize. */ | |
712 | if (mips_isa_regsize (gdbarch) == 4) | |
713 | return builtin_type_int32; | |
714 | else | |
715 | return builtin_type_int64; | |
716 | } | |
78fde5f8 | 717 | else |
d5ac5a39 AC |
718 | { |
719 | /* The cooked or ABI registers. These are sized according to | |
720 | the ABI (with a few complications). */ | |
72a155b4 UW |
721 | if (regnum >= (gdbarch_num_regs (gdbarch) |
722 | + mips_regnum (gdbarch)->fp_control_status) | |
723 | && regnum <= gdbarch_num_regs (gdbarch) + MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
724 | /* The pseudo/cooked view of the embedded registers is always |
725 | 32-bit. The raw view is handled below. */ | |
726 | return builtin_type_int32; | |
727 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
728 | /* The target, while possibly using a 64-bit register buffer, | |
729 | is only transfering 32-bits of each integer register. | |
730 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
731 | return builtin_type_int32; | |
732 | else if (mips_abi_regsize (gdbarch) == 4) | |
733 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
734 | 32- or 64-bit). */ | |
735 | return builtin_type_int32; | |
736 | else | |
737 | /* 64-bit ABI. */ | |
738 | return builtin_type_int64; | |
739 | } | |
78fde5f8 KB |
740 | } |
741 | ||
f8b73d13 DJ |
742 | /* Return the GDB type for the pseudo register REGNUM, which is the |
743 | ABI-level view. This function is only called if there is a target | |
744 | description which includes registers, so we know precisely the | |
745 | types of hardware registers. */ | |
746 | ||
747 | static struct type * | |
748 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
749 | { | |
750 | const int num_regs = gdbarch_num_regs (gdbarch); | |
751 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
752 | int rawnum = regnum % num_regs; | |
753 | struct type *rawtype; | |
754 | ||
755 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
756 | ||
757 | /* Absent registers are still absent. */ | |
758 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
759 | if (TYPE_LENGTH (rawtype) == 0) | |
760 | return rawtype; | |
761 | ||
762 | if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32) | |
763 | /* Present the floating point registers however the hardware did; | |
764 | do not try to convert between FPU layouts. */ | |
765 | return rawtype; | |
766 | ||
767 | if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
768 | { | |
769 | /* The pseudo/cooked view of embedded registers is always | |
770 | 32-bit, even if the target transfers 64-bit values for them. | |
771 | New targets relying on XML descriptions should only transfer | |
772 | the necessary 32 bits, but older versions of GDB expected 64, | |
773 | so allow the target to provide 64 bits without interfering | |
774 | with the displayed type. */ | |
775 | return builtin_type_int32; | |
776 | } | |
777 | ||
778 | /* Use pointer types for registers if we can. For n32 we can not, | |
779 | since we do not have a 64-bit pointer type. */ | |
780 | if (mips_abi_regsize (gdbarch) == TYPE_LENGTH (builtin_type_void_data_ptr)) | |
781 | { | |
782 | if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM) | |
783 | return builtin_type_void_data_ptr; | |
784 | else if (rawnum == MIPS_EMBED_PC_REGNUM) | |
785 | return builtin_type_void_func_ptr; | |
786 | } | |
787 | ||
788 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
789 | && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM) | |
790 | return builtin_type_int32; | |
791 | ||
792 | /* For all other registers, pass through the hardware type. */ | |
793 | return rawtype; | |
794 | } | |
bcb0cc15 | 795 | |
c906108c | 796 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 797 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
798 | |
799 | static int | |
480d3dd2 | 800 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
801 | { |
802 | switch (mask_address_var) | |
803 | { | |
7f19b9a2 | 804 | case AUTO_BOOLEAN_TRUE: |
4014092b | 805 | return 1; |
7f19b9a2 | 806 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
807 | return 0; |
808 | break; | |
7f19b9a2 | 809 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 810 | return tdep->default_mask_address_p; |
4014092b | 811 | default: |
e2e0b3e5 | 812 | internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch")); |
4014092b | 813 | return -1; |
361d1df0 | 814 | } |
4014092b AC |
815 | } |
816 | ||
817 | static void | |
08546159 AC |
818 | show_mask_address (struct ui_file *file, int from_tty, |
819 | struct cmd_list_element *c, const char *value) | |
4014092b | 820 | { |
480d3dd2 | 821 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
08546159 AC |
822 | |
823 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
824 | switch (mask_address_var) |
825 | { | |
7f19b9a2 | 826 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
827 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
828 | break; | |
7f19b9a2 | 829 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
830 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
831 | break; | |
7f19b9a2 | 832 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
833 | printf_filtered |
834 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
835 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
836 | break; |
837 | default: | |
e2e0b3e5 | 838 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 839 | break; |
361d1df0 | 840 | } |
4014092b | 841 | } |
c906108c | 842 | |
c906108c SS |
843 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
844 | ||
0fe7e7c8 AC |
845 | int |
846 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
847 | { |
848 | struct minimal_symbol *sym; | |
849 | ||
850 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 851 | if (is_mips16_addr (memaddr)) |
c906108c SS |
852 | return 1; |
853 | ||
854 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
855 | the high bit of the info field. Use this to decide if the function is | |
856 | MIPS16 or normal MIPS. */ | |
857 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
858 | if (sym) | |
71b8ef93 | 859 | return msymbol_is_special (sym); |
c906108c SS |
860 | else |
861 | return 0; | |
862 | } | |
863 | ||
b2fa5097 | 864 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
865 | all registers should be sign extended for simplicity? */ |
866 | ||
867 | static CORE_ADDR | |
61a1198a | 868 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 869 | { |
61a1198a UW |
870 | ULONGEST pc; |
871 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; | |
872 | regcache_cooked_read_signed (regcache, regnum, &pc); | |
873 | return pc; | |
b6cb9035 AC |
874 | } |
875 | ||
58dfe9ff AC |
876 | static CORE_ADDR |
877 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
878 | { | |
72a155b4 UW |
879 | return frame_unwind_register_signed |
880 | (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc); | |
edfae063 AC |
881 | } |
882 | ||
30244cd8 UW |
883 | static CORE_ADDR |
884 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
885 | { | |
72a155b4 UW |
886 | return frame_unwind_register_signed |
887 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
888 | } |
889 | ||
edfae063 AC |
890 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
891 | dummy frame. The frame ID's base needs to match the TOS value | |
892 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
893 | breakpoint. */ | |
894 | ||
895 | static struct frame_id | |
896 | mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
897 | { | |
f57d151a UW |
898 | return frame_id_build |
899 | (frame_unwind_register_signed (next_frame, | |
72a155b4 | 900 | gdbarch_num_regs (gdbarch) |
f57d151a UW |
901 | + MIPS_SP_REGNUM), |
902 | frame_pc_unwind (next_frame)); | |
58dfe9ff AC |
903 | } |
904 | ||
b6cb9035 | 905 | static void |
61a1198a | 906 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 907 | { |
61a1198a UW |
908 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; |
909 | regcache_cooked_write_unsigned (regcache, regnum, pc); | |
6c997a34 | 910 | } |
c906108c | 911 | |
c906108c SS |
912 | /* Fetch and return instruction from the specified location. If the PC |
913 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
914 | ||
d37cca3d | 915 | static ULONGEST |
acdb74a0 | 916 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c | 917 | { |
47a35522 | 918 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
919 | int instlen; |
920 | int status; | |
921 | ||
0fe7e7c8 | 922 | if (mips_pc_is_mips16 (addr)) |
c906108c | 923 | { |
95ac2dcf | 924 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 925 | addr = unmake_mips16_addr (addr); |
c906108c SS |
926 | } |
927 | else | |
95ac2dcf | 928 | instlen = MIPS_INSN32_SIZE; |
359a9262 | 929 | status = read_memory_nobpt (addr, buf, instlen); |
c906108c SS |
930 | if (status) |
931 | memory_error (status, addr); | |
932 | return extract_unsigned_integer (buf, instlen); | |
933 | } | |
934 | ||
c906108c | 935 | /* These the fields of 32 bit mips instructions */ |
e135b889 DJ |
936 | #define mips32_op(x) (x >> 26) |
937 | #define itype_op(x) (x >> 26) | |
938 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 939 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 940 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 941 | |
e135b889 DJ |
942 | #define jtype_op(x) (x >> 26) |
943 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 944 | |
e135b889 DJ |
945 | #define rtype_op(x) (x >> 26) |
946 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
947 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
948 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
949 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
950 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 951 | |
06987e64 MK |
952 | static LONGEST |
953 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 954 | { |
06987e64 | 955 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
956 | } |
957 | ||
f49e4e6d MS |
958 | /* Determine where to set a single step breakpoint while considering |
959 | branch prediction. */ | |
5a89d8aa | 960 | static CORE_ADDR |
0b1b3e42 | 961 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b JM |
962 | { |
963 | unsigned long inst; | |
964 | int op; | |
965 | inst = mips_fetch_instruction (pc); | |
e135b889 | 966 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 967 | { |
e135b889 | 968 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 969 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 970 | { |
e135b889 | 971 | op = (itype_op (inst) & 0x03); |
c906108c SS |
972 | switch (op) |
973 | { | |
e135b889 DJ |
974 | case 0: /* BEQL */ |
975 | goto equal_branch; | |
976 | case 1: /* BNEL */ | |
977 | goto neq_branch; | |
978 | case 2: /* BLEZL */ | |
979 | goto less_branch; | |
313628cc | 980 | case 3: /* BGTZL */ |
e135b889 | 981 | goto greater_branch; |
c5aa993b JM |
982 | default: |
983 | pc += 4; | |
c906108c SS |
984 | } |
985 | } | |
e135b889 | 986 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 987 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
988 | { |
989 | int tf = itype_rt (inst) & 0x01; | |
990 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b | 991 | int fcrcs = |
72a155b4 UW |
992 | get_frame_register_signed (frame, |
993 | mips_regnum (get_frame_arch (frame))-> | |
0b1b3e42 | 994 | fp_control_status); |
e135b889 DJ |
995 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
996 | ||
997 | if (((cond >> cnum) & 0x01) == tf) | |
998 | pc += mips32_relative_offset (inst) + 4; | |
999 | else | |
1000 | pc += 8; | |
1001 | } | |
c5aa993b JM |
1002 | else |
1003 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1004 | } |
1005 | else | |
c5aa993b JM |
1006 | { /* This gets way messy */ |
1007 | ||
c906108c | 1008 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1009 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1010 | { |
c5aa993b JM |
1011 | case 0: /* SPECIAL */ |
1012 | op = rtype_funct (inst); | |
1013 | switch (op) | |
1014 | { | |
1015 | case 8: /* JR */ | |
1016 | case 9: /* JALR */ | |
6c997a34 | 1017 | /* Set PC to that address */ |
0b1b3e42 | 1018 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b JM |
1019 | break; |
1020 | default: | |
1021 | pc += 4; | |
1022 | } | |
1023 | ||
6d82d43b | 1024 | break; /* end SPECIAL */ |
c5aa993b | 1025 | case 1: /* REGIMM */ |
c906108c | 1026 | { |
e135b889 DJ |
1027 | op = itype_rt (inst); /* branch condition */ |
1028 | switch (op) | |
c906108c | 1029 | { |
c5aa993b | 1030 | case 0: /* BLTZ */ |
e135b889 DJ |
1031 | case 2: /* BLTZL */ |
1032 | case 16: /* BLTZAL */ | |
c5aa993b | 1033 | case 18: /* BLTZALL */ |
c906108c | 1034 | less_branch: |
0b1b3e42 | 1035 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1036 | pc += mips32_relative_offset (inst) + 4; |
1037 | else | |
1038 | pc += 8; /* after the delay slot */ | |
1039 | break; | |
e135b889 | 1040 | case 1: /* BGEZ */ |
c5aa993b JM |
1041 | case 3: /* BGEZL */ |
1042 | case 17: /* BGEZAL */ | |
1043 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1044 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1045 | pc += mips32_relative_offset (inst) + 4; |
1046 | else | |
1047 | pc += 8; /* after the delay slot */ | |
1048 | break; | |
e135b889 | 1049 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1050 | default: |
1051 | pc += 4; | |
c906108c SS |
1052 | } |
1053 | } | |
6d82d43b | 1054 | break; /* end REGIMM */ |
c5aa993b JM |
1055 | case 2: /* J */ |
1056 | case 3: /* JAL */ | |
1057 | { | |
1058 | unsigned long reg; | |
1059 | reg = jtype_target (inst) << 2; | |
e135b889 | 1060 | /* Upper four bits get never changed... */ |
5b652102 | 1061 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1062 | } |
c5aa993b JM |
1063 | break; |
1064 | /* FIXME case JALX : */ | |
1065 | { | |
1066 | unsigned long reg; | |
1067 | reg = jtype_target (inst) << 2; | |
5b652102 | 1068 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ |
c906108c SS |
1069 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1070 | } | |
c5aa993b | 1071 | break; /* The new PC will be alternate mode */ |
e135b889 | 1072 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1073 | equal_branch: |
0b1b3e42 UW |
1074 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1075 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1076 | pc += mips32_relative_offset (inst) + 4; |
1077 | else | |
1078 | pc += 8; | |
1079 | break; | |
e135b889 | 1080 | case 5: /* BNE, BNEL */ |
c5aa993b | 1081 | neq_branch: |
0b1b3e42 UW |
1082 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1083 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1084 | pc += mips32_relative_offset (inst) + 4; |
1085 | else | |
1086 | pc += 8; | |
1087 | break; | |
e135b889 | 1088 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1089 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1090 | pc += mips32_relative_offset (inst) + 4; |
1091 | else | |
1092 | pc += 8; | |
1093 | break; | |
1094 | case 7: | |
e135b889 DJ |
1095 | default: |
1096 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1097 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1098 | pc += mips32_relative_offset (inst) + 4; |
1099 | else | |
1100 | pc += 8; | |
1101 | break; | |
c5aa993b JM |
1102 | } /* switch */ |
1103 | } /* else */ | |
1104 | return pc; | |
1105 | } /* mips32_next_pc */ | |
c906108c SS |
1106 | |
1107 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1108 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1109 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1110 | We dont want to set a single step instruction on the extend instruction | |
1111 | either. | |
c5aa993b | 1112 | */ |
c906108c SS |
1113 | |
1114 | /* Lots of mips16 instruction formats */ | |
1115 | /* Predicting jumps requires itype,ritype,i8type | |
1116 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1117 | */ |
c906108c SS |
1118 | enum mips16_inst_fmts |
1119 | { | |
c5aa993b JM |
1120 | itype, /* 0 immediate 5,10 */ |
1121 | ritype, /* 1 5,3,8 */ | |
1122 | rrtype, /* 2 5,3,3,5 */ | |
1123 | rritype, /* 3 5,3,3,5 */ | |
1124 | rrrtype, /* 4 5,3,3,3,2 */ | |
1125 | rriatype, /* 5 5,3,3,1,4 */ | |
1126 | shifttype, /* 6 5,3,3,3,2 */ | |
1127 | i8type, /* 7 5,3,8 */ | |
1128 | i8movtype, /* 8 5,3,3,5 */ | |
1129 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1130 | i64type, /* 10 5,3,8 */ | |
1131 | ri64type, /* 11 5,3,3,5 */ | |
1132 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1133 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1134 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1135 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1136 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1137 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1138 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1139 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1140 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1141 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1142 | }; | |
12f02c2a AC |
1143 | /* I am heaping all the fields of the formats into one structure and |
1144 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1145 | struct upk_mips16 |
6d82d43b AC |
1146 | { |
1147 | CORE_ADDR offset; | |
1148 | unsigned int regx; /* Function in i8 type */ | |
1149 | unsigned int regy; | |
1150 | }; | |
c906108c SS |
1151 | |
1152 | ||
12f02c2a AC |
1153 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1154 | for the bits which make up the immediatate extension. */ | |
c906108c | 1155 | |
12f02c2a AC |
1156 | static CORE_ADDR |
1157 | extended_offset (unsigned int extension) | |
c906108c | 1158 | { |
12f02c2a | 1159 | CORE_ADDR value; |
c5aa993b JM |
1160 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1161 | value = value << 6; | |
1162 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1163 | value = value << 5; | |
1164 | value |= extension & 0x01f; /* extract 4:0 */ | |
1165 | return value; | |
c906108c SS |
1166 | } |
1167 | ||
1168 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
1169 | instruction. It won't malfunction, but why make excess remote memory |
1170 | references? If the immediate operands get sign extended or something, | |
1171 | do it after the extension is performed. */ | |
c906108c | 1172 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 1173 | when the offset is to be used in relative addressing. */ |
c906108c | 1174 | |
12f02c2a | 1175 | static unsigned int |
c5aa993b | 1176 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1177 | { |
47a35522 | 1178 | gdb_byte buf[8]; |
c5aa993b JM |
1179 | pc &= 0xfffffffe; /* clear the low order bit */ |
1180 | target_read_memory (pc, buf, 2); | |
1181 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1182 | } |
1183 | ||
1184 | static void | |
c5aa993b | 1185 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1186 | unsigned int extension, |
1187 | unsigned int inst, | |
6d82d43b | 1188 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1189 | { |
12f02c2a AC |
1190 | CORE_ADDR offset; |
1191 | int regx; | |
1192 | int regy; | |
1193 | switch (insn_format) | |
c906108c | 1194 | { |
c5aa993b | 1195 | case itype: |
c906108c | 1196 | { |
12f02c2a AC |
1197 | CORE_ADDR value; |
1198 | if (extension) | |
c5aa993b JM |
1199 | { |
1200 | value = extended_offset (extension); | |
1201 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1202 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1203 | } |
1204 | else | |
c5aa993b | 1205 | { |
12f02c2a | 1206 | value = inst & 0x7ff; |
c5aa993b | 1207 | /* FIXME : Consider sign extension */ |
c906108c | 1208 | } |
12f02c2a AC |
1209 | offset = value; |
1210 | regx = -1; | |
1211 | regy = -1; | |
c906108c | 1212 | } |
c5aa993b JM |
1213 | break; |
1214 | case ritype: | |
1215 | case i8type: | |
1216 | { /* A register identifier and an offset */ | |
c906108c SS |
1217 | /* Most of the fields are the same as I type but the |
1218 | immediate value is of a different length */ | |
12f02c2a AC |
1219 | CORE_ADDR value; |
1220 | if (extension) | |
c906108c | 1221 | { |
c5aa993b JM |
1222 | value = extended_offset (extension); |
1223 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1224 | value |= inst & 0xff; /* eleven bits from instruction */ |
1225 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1226 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1227 | { | |
1228 | value &= ~0x3fff; /* remove the sign bit */ | |
1229 | value = -value; | |
c906108c SS |
1230 | } |
1231 | } | |
c5aa993b JM |
1232 | else |
1233 | { | |
12f02c2a AC |
1234 | value = inst & 0xff; /* 8 bits */ |
1235 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1236 | /* FIXME: Do sign extension , this format needs it */ |
1237 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1238 | { | |
1239 | value &= 0xef; /* remove the sign bit */ | |
1240 | value = -value; | |
1241 | } | |
c5aa993b | 1242 | } |
12f02c2a AC |
1243 | offset = value; |
1244 | regy = -1; | |
c5aa993b | 1245 | break; |
c906108c | 1246 | } |
c5aa993b | 1247 | case jalxtype: |
c906108c | 1248 | { |
c5aa993b | 1249 | unsigned long value; |
12f02c2a AC |
1250 | unsigned int nexthalf; |
1251 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1252 | value = value << 16; |
1253 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1254 | value |= nexthalf; | |
12f02c2a AC |
1255 | offset = value; |
1256 | regx = -1; | |
1257 | regy = -1; | |
c5aa993b | 1258 | break; |
c906108c SS |
1259 | } |
1260 | default: | |
e2e0b3e5 | 1261 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1262 | } |
12f02c2a AC |
1263 | upk->offset = offset; |
1264 | upk->regx = regx; | |
1265 | upk->regy = regy; | |
c906108c SS |
1266 | } |
1267 | ||
1268 | ||
c5aa993b JM |
1269 | static CORE_ADDR |
1270 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1271 | { |
5b652102 | 1272 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
1273 | } |
1274 | ||
12f02c2a | 1275 | static CORE_ADDR |
0b1b3e42 | 1276 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 1277 | unsigned int extension, unsigned int insn) |
c906108c | 1278 | { |
12f02c2a AC |
1279 | int op = (insn >> 11); |
1280 | switch (op) | |
c906108c | 1281 | { |
6d82d43b | 1282 | case 2: /* Branch */ |
12f02c2a AC |
1283 | { |
1284 | CORE_ADDR offset; | |
1285 | struct upk_mips16 upk; | |
1286 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1287 | offset = upk.offset; | |
1288 | if (offset & 0x800) | |
1289 | { | |
1290 | offset &= 0xeff; | |
1291 | offset = -offset; | |
1292 | } | |
1293 | pc += (offset << 1) + 2; | |
1294 | break; | |
1295 | } | |
6d82d43b | 1296 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1297 | { |
1298 | struct upk_mips16 upk; | |
1299 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1300 | pc = add_offset_16 (pc, upk.offset); | |
1301 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1302 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1303 | else | |
1304 | pc |= 0x01; | |
1305 | break; | |
1306 | } | |
6d82d43b | 1307 | case 4: /* beqz */ |
12f02c2a AC |
1308 | { |
1309 | struct upk_mips16 upk; | |
1310 | int reg; | |
1311 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
0b1b3e42 | 1312 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1313 | if (reg == 0) |
1314 | pc += (upk.offset << 1) + 2; | |
1315 | else | |
1316 | pc += 2; | |
1317 | break; | |
1318 | } | |
6d82d43b | 1319 | case 5: /* bnez */ |
12f02c2a AC |
1320 | { |
1321 | struct upk_mips16 upk; | |
1322 | int reg; | |
1323 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
0b1b3e42 | 1324 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1325 | if (reg != 0) |
1326 | pc += (upk.offset << 1) + 2; | |
1327 | else | |
1328 | pc += 2; | |
1329 | break; | |
1330 | } | |
6d82d43b | 1331 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1332 | { |
1333 | struct upk_mips16 upk; | |
1334 | int reg; | |
1335 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1336 | /* upk.regx contains the opcode */ | |
0b1b3e42 | 1337 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
1338 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
1339 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1340 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1341 | pc += (upk.offset << 1) + 2; | |
1342 | else | |
1343 | pc += 2; | |
1344 | break; | |
1345 | } | |
6d82d43b | 1346 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1347 | { |
1348 | struct upk_mips16 upk; | |
1349 | /* upk.fmt = rrtype; */ | |
1350 | op = insn & 0x1f; | |
1351 | if (op == 0) | |
c5aa993b | 1352 | { |
12f02c2a AC |
1353 | int reg; |
1354 | upk.regx = (insn >> 8) & 0x07; | |
1355 | upk.regy = (insn >> 5) & 0x07; | |
1356 | switch (upk.regy) | |
c5aa993b | 1357 | { |
12f02c2a AC |
1358 | case 0: |
1359 | reg = upk.regx; | |
1360 | break; | |
1361 | case 1: | |
1362 | reg = 31; | |
6d82d43b | 1363 | break; /* Function return instruction */ |
12f02c2a AC |
1364 | case 2: |
1365 | reg = upk.regx; | |
1366 | break; | |
1367 | default: | |
1368 | reg = 31; | |
6d82d43b | 1369 | break; /* BOGUS Guess */ |
c906108c | 1370 | } |
0b1b3e42 | 1371 | pc = get_frame_register_signed (frame, reg); |
c906108c | 1372 | } |
12f02c2a | 1373 | else |
c5aa993b | 1374 | pc += 2; |
12f02c2a AC |
1375 | break; |
1376 | } | |
1377 | case 30: | |
1378 | /* This is an instruction extension. Fetch the real instruction | |
1379 | (which follows the extension) and decode things based on | |
1380 | that. */ | |
1381 | { | |
1382 | pc += 2; | |
0b1b3e42 | 1383 | pc = extended_mips16_next_pc (frame, pc, insn, fetch_mips_16 (pc)); |
12f02c2a AC |
1384 | break; |
1385 | } | |
1386 | default: | |
1387 | { | |
1388 | pc += 2; | |
1389 | break; | |
1390 | } | |
c906108c | 1391 | } |
c5aa993b | 1392 | return pc; |
12f02c2a | 1393 | } |
c906108c | 1394 | |
5a89d8aa | 1395 | static CORE_ADDR |
0b1b3e42 | 1396 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a AC |
1397 | { |
1398 | unsigned int insn = fetch_mips_16 (pc); | |
0b1b3e42 | 1399 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
1400 | } |
1401 | ||
1402 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1403 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1404 | It works by decoding the current instruction and predicting where a |
1405 | branch will go. This isnt hard because all the data is available. | |
ce1f96de | 1406 | The MIPS32 and MIPS16 variants are quite different. */ |
ad527d2e | 1407 | static CORE_ADDR |
0b1b3e42 | 1408 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1409 | { |
ce1f96de | 1410 | if (is_mips16_addr (pc)) |
0b1b3e42 | 1411 | return mips16_next_pc (frame, pc); |
c5aa993b | 1412 | else |
0b1b3e42 | 1413 | return mips32_next_pc (frame, pc); |
12f02c2a | 1414 | } |
c906108c | 1415 | |
edfae063 AC |
1416 | struct mips_frame_cache |
1417 | { | |
1418 | CORE_ADDR base; | |
1419 | struct trad_frame_saved_reg *saved_regs; | |
1420 | }; | |
1421 | ||
29639122 JB |
1422 | /* Set a register's saved stack address in temp_saved_regs. If an |
1423 | address has already been set for this register, do nothing; this | |
1424 | way we will only recognize the first save of a given register in a | |
1425 | function prologue. | |
eec63939 | 1426 | |
f57d151a UW |
1427 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
1428 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
1429 | Strictly speaking, only the second range is used as it is only second | |
1430 | range (the ABI instead of ISA registers) that comes into play when finding | |
1431 | saved registers in a frame. */ | |
eec63939 AC |
1432 | |
1433 | static void | |
29639122 JB |
1434 | set_reg_offset (struct mips_frame_cache *this_cache, int regnum, |
1435 | CORE_ADDR offset) | |
eec63939 | 1436 | { |
29639122 JB |
1437 | if (this_cache != NULL |
1438 | && this_cache->saved_regs[regnum].addr == -1) | |
1439 | { | |
f57d151a UW |
1440 | this_cache->saved_regs[regnum |
1441 | + 0 * gdbarch_num_regs (current_gdbarch)].addr | |
1442 | = offset; | |
1443 | this_cache->saved_regs[regnum | |
1444 | + 1 * gdbarch_num_regs (current_gdbarch)].addr | |
1445 | = offset; | |
29639122 | 1446 | } |
eec63939 AC |
1447 | } |
1448 | ||
eec63939 | 1449 | |
29639122 JB |
1450 | /* Fetch the immediate value from a MIPS16 instruction. |
1451 | If the previous instruction was an EXTEND, use it to extend | |
1452 | the upper bits of the immediate value. This is a helper function | |
1453 | for mips16_scan_prologue. */ | |
eec63939 | 1454 | |
29639122 JB |
1455 | static int |
1456 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1457 | unsigned short inst, /* current instruction */ | |
1458 | int nbits, /* number of bits in imm field */ | |
1459 | int scale, /* scale factor to be applied to imm */ | |
1460 | int is_signed) /* is the imm field signed? */ | |
eec63939 | 1461 | { |
29639122 | 1462 | int offset; |
eec63939 | 1463 | |
29639122 JB |
1464 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1465 | { | |
1466 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1467 | if (offset & 0x8000) /* check for negative extend */ | |
1468 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1469 | return offset | (inst & 0x1f); | |
1470 | } | |
eec63939 | 1471 | else |
29639122 JB |
1472 | { |
1473 | int max_imm = 1 << nbits; | |
1474 | int mask = max_imm - 1; | |
1475 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1476 | |
29639122 JB |
1477 | offset = inst & mask; |
1478 | if (is_signed && (offset & sign_bit)) | |
1479 | offset = 0 - (max_imm - offset); | |
1480 | return offset * scale; | |
1481 | } | |
1482 | } | |
eec63939 | 1483 | |
65596487 | 1484 | |
29639122 JB |
1485 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1486 | the associated FRAME_CACHE if not null. | |
1487 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1488 | |
29639122 JB |
1489 | static CORE_ADDR |
1490 | mips16_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
1491 | struct frame_info *next_frame, | |
1492 | struct mips_frame_cache *this_cache) | |
1493 | { | |
1494 | CORE_ADDR cur_pc; | |
1495 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1496 | CORE_ADDR sp; | |
1497 | long frame_offset = 0; /* Size of stack frame. */ | |
1498 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1499 | int frame_reg = MIPS_SP_REGNUM; | |
1500 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1501 | unsigned inst = 0; /* current instruction */ | |
1502 | unsigned entry_inst = 0; /* the entry instruction */ | |
1503 | int reg, offset; | |
a343eb3c | 1504 | |
29639122 JB |
1505 | int extend_bytes = 0; |
1506 | int prev_extend_bytes; | |
1507 | CORE_ADDR end_prologue_addr = 0; | |
72a155b4 | 1508 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
a343eb3c | 1509 | |
29639122 JB |
1510 | /* Can be called when there's no process, and hence when there's no |
1511 | NEXT_FRAME. */ | |
1512 | if (next_frame != NULL) | |
d2ca4222 | 1513 | sp = frame_unwind_register_signed (next_frame, |
72a155b4 | 1514 | gdbarch_num_regs (gdbarch) |
d2ca4222 | 1515 | + MIPS_SP_REGNUM); |
29639122 JB |
1516 | else |
1517 | sp = 0; | |
eec63939 | 1518 | |
29639122 JB |
1519 | if (limit_pc > start_pc + 200) |
1520 | limit_pc = start_pc + 200; | |
eec63939 | 1521 | |
95ac2dcf | 1522 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1523 | { |
1524 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1525 | the immediate offset extension from it in mips16_get_imm. */ | |
1526 | prev_inst = inst; | |
eec63939 | 1527 | |
29639122 JB |
1528 | /* Fetch and decode the instruction. */ |
1529 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
eec63939 | 1530 | |
29639122 JB |
1531 | /* Normally we ignore extend instructions. However, if it is |
1532 | not followed by a valid prologue instruction, then this | |
1533 | instruction is not part of the prologue either. We must | |
1534 | remember in this case to adjust the end_prologue_addr back | |
1535 | over the extend. */ | |
1536 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1537 | { | |
95ac2dcf | 1538 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1539 | continue; |
1540 | } | |
eec63939 | 1541 | |
29639122 JB |
1542 | prev_extend_bytes = extend_bytes; |
1543 | extend_bytes = 0; | |
eec63939 | 1544 | |
29639122 JB |
1545 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1546 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1547 | { | |
1548 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
1549 | if (offset < 0) /* negative stack adjustment? */ | |
1550 | frame_offset -= offset; | |
1551 | else | |
1552 | /* Exit loop if a positive stack adjustment is found, which | |
1553 | usually means that the stack cleanup code in the function | |
1554 | epilogue is reached. */ | |
1555 | break; | |
1556 | } | |
1557 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1558 | { | |
1559 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1560 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
1561 | set_reg_offset (this_cache, reg, sp + offset); | |
1562 | } | |
1563 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1564 | { | |
1565 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1566 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1567 | set_reg_offset (this_cache, reg, sp + offset); | |
1568 | } | |
1569 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1570 | { | |
1571 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4c7d22cb | 1572 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1573 | } |
1574 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1575 | { | |
1576 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
4c7d22cb | 1577 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1578 | } |
1579 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1580 | { | |
1581 | frame_addr = sp; | |
1582 | frame_reg = 17; | |
1583 | } | |
1584 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1585 | { | |
1586 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1587 | frame_addr = sp + offset; | |
1588 | frame_reg = 17; | |
1589 | frame_adjust = offset; | |
1590 | } | |
1591 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1592 | { | |
1593 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1594 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1595 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1596 | } | |
1597 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1598 | { | |
1599 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1600 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1601 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1602 | } | |
1603 | else if ((inst & 0xf81f) == 0xe809 | |
1604 | && (inst & 0x700) != 0x700) /* entry */ | |
1605 | entry_inst = inst; /* save for later processing */ | |
1606 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ | |
95ac2dcf | 1607 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1608 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1609 | { | |
1610 | /* This instruction is part of the prologue, but we don't | |
1611 | need to do anything special to handle it. */ | |
1612 | } | |
1613 | else | |
1614 | { | |
1615 | /* This instruction is not an instruction typically found | |
1616 | in a prologue, so we must have reached the end of the | |
1617 | prologue. */ | |
1618 | if (end_prologue_addr == 0) | |
1619 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1620 | } | |
1621 | } | |
eec63939 | 1622 | |
29639122 JB |
1623 | /* The entry instruction is typically the first instruction in a function, |
1624 | and it stores registers at offsets relative to the value of the old SP | |
1625 | (before the prologue). But the value of the sp parameter to this | |
1626 | function is the new SP (after the prologue has been executed). So we | |
1627 | can't calculate those offsets until we've seen the entire prologue, | |
1628 | and can calculate what the old SP must have been. */ | |
1629 | if (entry_inst != 0) | |
1630 | { | |
1631 | int areg_count = (entry_inst >> 8) & 7; | |
1632 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1633 | |
29639122 JB |
1634 | /* The entry instruction always subtracts 32 from the SP. */ |
1635 | frame_offset += 32; | |
1636 | ||
1637 | /* Now we can calculate what the SP must have been at the | |
1638 | start of the function prologue. */ | |
1639 | sp += frame_offset; | |
1640 | ||
1641 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1642 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1643 | { | |
1644 | set_reg_offset (this_cache, reg, sp + offset); | |
72a155b4 | 1645 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
1646 | } |
1647 | ||
1648 | /* Check if the ra register was pushed on the stack. */ | |
1649 | offset = -4; | |
1650 | if (entry_inst & 0x20) | |
1651 | { | |
4c7d22cb | 1652 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 1653 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1654 | } |
1655 | ||
1656 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1657 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1658 | { | |
1659 | set_reg_offset (this_cache, reg, sp + offset); | |
72a155b4 | 1660 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1661 | } |
1662 | } | |
1663 | ||
1664 | if (this_cache != NULL) | |
1665 | { | |
1666 | this_cache->base = | |
f57d151a | 1667 | (frame_unwind_register_signed (next_frame, |
72a155b4 | 1668 | gdbarch_num_regs (gdbarch) + frame_reg) |
29639122 JB |
1669 | + frame_offset - frame_adjust); |
1670 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
1671 | be able to get rid of the assignment below, evetually. But it's | |
1672 | still needed for now. */ | |
72a155b4 UW |
1673 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
1674 | + mips_regnum (gdbarch)->pc] | |
1675 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
29639122 JB |
1676 | } |
1677 | ||
1678 | /* If we didn't reach the end of the prologue when scanning the function | |
1679 | instructions, then set end_prologue_addr to the address of the | |
1680 | instruction immediately after the last one we scanned. */ | |
1681 | if (end_prologue_addr == 0) | |
1682 | end_prologue_addr = cur_pc; | |
1683 | ||
1684 | return end_prologue_addr; | |
eec63939 AC |
1685 | } |
1686 | ||
29639122 JB |
1687 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1688 | Procedures that use the 32-bit instruction set are handled by the | |
1689 | mips_insn32 unwinder. */ | |
1690 | ||
1691 | static struct mips_frame_cache * | |
1692 | mips_insn16_frame_cache (struct frame_info *next_frame, void **this_cache) | |
eec63939 | 1693 | { |
29639122 | 1694 | struct mips_frame_cache *cache; |
eec63939 AC |
1695 | |
1696 | if ((*this_cache) != NULL) | |
1697 | return (*this_cache); | |
29639122 JB |
1698 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1699 | (*this_cache) = cache; | |
1700 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
eec63939 | 1701 | |
29639122 JB |
1702 | /* Analyze the function prologue. */ |
1703 | { | |
6de5b849 JB |
1704 | const CORE_ADDR pc = |
1705 | frame_unwind_address_in_block (next_frame, NORMAL_FRAME); | |
29639122 | 1706 | CORE_ADDR start_addr; |
eec63939 | 1707 | |
29639122 JB |
1708 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1709 | if (start_addr == 0) | |
1710 | start_addr = heuristic_proc_start (pc); | |
1711 | /* We can't analyze the prologue if we couldn't find the begining | |
1712 | of the function. */ | |
1713 | if (start_addr == 0) | |
1714 | return cache; | |
eec63939 | 1715 | |
29639122 JB |
1716 | mips16_scan_prologue (start_addr, pc, next_frame, *this_cache); |
1717 | } | |
1718 | ||
3e8c568d | 1719 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 UW |
1720 | trad_frame_set_value (cache->saved_regs, |
1721 | gdbarch_num_regs (get_frame_arch (next_frame)) | |
1722 | + MIPS_SP_REGNUM, | |
1723 | cache->base); | |
eec63939 | 1724 | |
29639122 | 1725 | return (*this_cache); |
eec63939 AC |
1726 | } |
1727 | ||
1728 | static void | |
29639122 JB |
1729 | mips_insn16_frame_this_id (struct frame_info *next_frame, void **this_cache, |
1730 | struct frame_id *this_id) | |
eec63939 | 1731 | { |
29639122 JB |
1732 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1733 | this_cache); | |
93d42b30 DJ |
1734 | (*this_id) = frame_id_build (info->base, |
1735 | frame_func_unwind (next_frame, NORMAL_FRAME)); | |
eec63939 AC |
1736 | } |
1737 | ||
1738 | static void | |
29639122 | 1739 | mips_insn16_frame_prev_register (struct frame_info *next_frame, |
eec63939 AC |
1740 | void **this_cache, |
1741 | int regnum, int *optimizedp, | |
1742 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 1743 | int *realnump, gdb_byte *valuep) |
eec63939 | 1744 | { |
29639122 JB |
1745 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1746 | this_cache); | |
1747 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
1748 | optimizedp, lvalp, addrp, realnump, valuep); | |
eec63939 AC |
1749 | } |
1750 | ||
29639122 | 1751 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
1752 | { |
1753 | NORMAL_FRAME, | |
29639122 JB |
1754 | mips_insn16_frame_this_id, |
1755 | mips_insn16_frame_prev_register | |
eec63939 AC |
1756 | }; |
1757 | ||
1758 | static const struct frame_unwind * | |
29639122 | 1759 | mips_insn16_frame_sniffer (struct frame_info *next_frame) |
eec63939 | 1760 | { |
6de5b849 | 1761 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
0fe7e7c8 | 1762 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
1763 | return &mips_insn16_frame_unwind; |
1764 | return NULL; | |
eec63939 AC |
1765 | } |
1766 | ||
1767 | static CORE_ADDR | |
29639122 JB |
1768 | mips_insn16_frame_base_address (struct frame_info *next_frame, |
1769 | void **this_cache) | |
eec63939 | 1770 | { |
29639122 JB |
1771 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1772 | this_cache); | |
1773 | return info->base; | |
eec63939 AC |
1774 | } |
1775 | ||
29639122 | 1776 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 1777 | { |
29639122 JB |
1778 | &mips_insn16_frame_unwind, |
1779 | mips_insn16_frame_base_address, | |
1780 | mips_insn16_frame_base_address, | |
1781 | mips_insn16_frame_base_address | |
eec63939 AC |
1782 | }; |
1783 | ||
1784 | static const struct frame_base * | |
29639122 | 1785 | mips_insn16_frame_base_sniffer (struct frame_info *next_frame) |
eec63939 | 1786 | { |
29639122 JB |
1787 | if (mips_insn16_frame_sniffer (next_frame) != NULL) |
1788 | return &mips_insn16_frame_base; | |
eec63939 AC |
1789 | else |
1790 | return NULL; | |
edfae063 AC |
1791 | } |
1792 | ||
29639122 JB |
1793 | /* Mark all the registers as unset in the saved_regs array |
1794 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
1795 | ||
1796 | void | |
1797 | reset_saved_regs (struct mips_frame_cache *this_cache) | |
c906108c | 1798 | { |
29639122 JB |
1799 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
1800 | return; | |
1801 | ||
1802 | { | |
f57d151a | 1803 | const int num_regs = gdbarch_num_regs (current_gdbarch); |
29639122 | 1804 | int i; |
64159455 | 1805 | |
29639122 JB |
1806 | for (i = 0; i < num_regs; i++) |
1807 | { | |
1808 | this_cache->saved_regs[i].addr = -1; | |
1809 | } | |
1810 | } | |
c906108c SS |
1811 | } |
1812 | ||
29639122 JB |
1813 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1814 | the associated FRAME_CACHE if not null. | |
1815 | Return the address of the first instruction past the prologue. */ | |
c906108c | 1816 | |
875e1767 | 1817 | static CORE_ADDR |
29639122 JB |
1818 | mips32_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1819 | struct frame_info *next_frame, | |
1820 | struct mips_frame_cache *this_cache) | |
c906108c | 1821 | { |
29639122 JB |
1822 | CORE_ADDR cur_pc; |
1823 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
1824 | CORE_ADDR sp; | |
1825 | long frame_offset; | |
1826 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 1827 | |
29639122 JB |
1828 | CORE_ADDR end_prologue_addr = 0; |
1829 | int seen_sp_adjust = 0; | |
1830 | int load_immediate_bytes = 0; | |
72a155b4 | 1831 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
8fa9cfa1 | 1832 | |
29639122 JB |
1833 | /* Can be called when there's no process, and hence when there's no |
1834 | NEXT_FRAME. */ | |
1835 | if (next_frame != NULL) | |
d2ca4222 | 1836 | sp = frame_unwind_register_signed (next_frame, |
72a155b4 | 1837 | gdbarch_num_regs (gdbarch) |
d2ca4222 | 1838 | + MIPS_SP_REGNUM); |
8fa9cfa1 | 1839 | else |
29639122 | 1840 | sp = 0; |
9022177c | 1841 | |
29639122 JB |
1842 | if (limit_pc > start_pc + 200) |
1843 | limit_pc = start_pc + 200; | |
9022177c | 1844 | |
29639122 | 1845 | restart: |
9022177c | 1846 | |
29639122 | 1847 | frame_offset = 0; |
95ac2dcf | 1848 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 1849 | { |
29639122 JB |
1850 | unsigned long inst, high_word, low_word; |
1851 | int reg; | |
9022177c | 1852 | |
29639122 JB |
1853 | /* Fetch the instruction. */ |
1854 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
9022177c | 1855 | |
29639122 JB |
1856 | /* Save some code by pre-extracting some useful fields. */ |
1857 | high_word = (inst >> 16) & 0xffff; | |
1858 | low_word = inst & 0xffff; | |
1859 | reg = high_word & 0x1f; | |
fe29b929 | 1860 | |
29639122 JB |
1861 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
1862 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
1863 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1864 | { | |
1865 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
1866 | frame_offset += 0x10000 - low_word; | |
1867 | else | |
1868 | /* Exit loop if a positive stack adjustment is found, which | |
1869 | usually means that the stack cleanup code in the function | |
1870 | epilogue is reached. */ | |
1871 | break; | |
1872 | seen_sp_adjust = 1; | |
1873 | } | |
1874 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
1875 | { | |
1876 | set_reg_offset (this_cache, reg, sp + low_word); | |
1877 | } | |
1878 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
1879 | { | |
1880 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
1881 | set_reg_offset (this_cache, reg, sp + low_word); | |
1882 | } | |
1883 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
1884 | { | |
1885 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
1886 | if ((long) low_word != frame_offset) | |
1887 | frame_addr = sp + low_word; | |
d2ca4222 | 1888 | else if (next_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
1889 | { |
1890 | unsigned alloca_adjust; | |
a4b8ebc8 | 1891 | |
29639122 | 1892 | frame_reg = 30; |
d2ca4222 | 1893 | frame_addr = frame_unwind_register_signed |
72a155b4 | 1894 | (next_frame, gdbarch_num_regs (gdbarch) + 30); |
d2ca4222 | 1895 | |
29639122 JB |
1896 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
1897 | if (alloca_adjust > 0) | |
1898 | { | |
1899 | /* FP > SP + frame_size. This may be because of | |
1900 | an alloca or somethings similar. Fix sp to | |
1901 | "pre-alloca" value, and try again. */ | |
1902 | sp += alloca_adjust; | |
1903 | /* Need to reset the status of all registers. Otherwise, | |
1904 | we will hit a guard that prevents the new address | |
1905 | for each register to be recomputed during the second | |
1906 | pass. */ | |
1907 | reset_saved_regs (this_cache); | |
1908 | goto restart; | |
1909 | } | |
1910 | } | |
1911 | } | |
1912 | /* move $30,$sp. With different versions of gas this will be either | |
1913 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
1914 | Accept any one of these. */ | |
1915 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
1916 | { | |
1917 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
d2ca4222 | 1918 | if (next_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
1919 | { |
1920 | unsigned alloca_adjust; | |
c906108c | 1921 | |
29639122 | 1922 | frame_reg = 30; |
d2ca4222 | 1923 | frame_addr = frame_unwind_register_signed |
72a155b4 | 1924 | (next_frame, gdbarch_num_regs (gdbarch) + 30); |
d2ca4222 | 1925 | |
29639122 JB |
1926 | alloca_adjust = (unsigned) (frame_addr - sp); |
1927 | if (alloca_adjust > 0) | |
1928 | { | |
1929 | /* FP > SP + frame_size. This may be because of | |
1930 | an alloca or somethings similar. Fix sp to | |
1931 | "pre-alloca" value, and try again. */ | |
1932 | sp = frame_addr; | |
1933 | /* Need to reset the status of all registers. Otherwise, | |
1934 | we will hit a guard that prevents the new address | |
1935 | for each register to be recomputed during the second | |
1936 | pass. */ | |
1937 | reset_saved_regs (this_cache); | |
1938 | goto restart; | |
1939 | } | |
1940 | } | |
1941 | } | |
1942 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ | |
1943 | { | |
1944 | set_reg_offset (this_cache, reg, frame_addr + low_word); | |
1945 | } | |
1946 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
1947 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
1948 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
1949 | || high_word == 0x3c1c /* lui $gp,n */ | |
1950 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
1951 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
1952 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
1953 | ) | |
1954 | { | |
1955 | /* These instructions are part of the prologue, but we don't | |
1956 | need to do anything special to handle them. */ | |
1957 | } | |
1958 | /* The instructions below load $at or $t0 with an immediate | |
1959 | value in preparation for a stack adjustment via | |
1960 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
1961 | initialize a local variable, so we accept them only before | |
1962 | a stack adjustment instruction was seen. */ | |
1963 | else if (!seen_sp_adjust | |
1964 | && (high_word == 0x3c01 /* lui $at,n */ | |
1965 | || high_word == 0x3c08 /* lui $t0,n */ | |
1966 | || high_word == 0x3421 /* ori $at,$at,n */ | |
1967 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
1968 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
1969 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
1970 | )) | |
1971 | { | |
95ac2dcf | 1972 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
29639122 JB |
1973 | } |
1974 | else | |
1975 | { | |
1976 | /* This instruction is not an instruction typically found | |
1977 | in a prologue, so we must have reached the end of the | |
1978 | prologue. */ | |
1979 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
1980 | loop now? Why would we need to continue scanning the function | |
1981 | instructions? */ | |
1982 | if (end_prologue_addr == 0) | |
1983 | end_prologue_addr = cur_pc; | |
1984 | } | |
a4b8ebc8 | 1985 | } |
c906108c | 1986 | |
29639122 JB |
1987 | if (this_cache != NULL) |
1988 | { | |
1989 | this_cache->base = | |
f57d151a | 1990 | (frame_unwind_register_signed (next_frame, |
72a155b4 | 1991 | gdbarch_num_regs (gdbarch) + frame_reg) |
29639122 JB |
1992 | + frame_offset); |
1993 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
1994 | this assignment below, eventually. But it's still needed | |
1995 | for now. */ | |
72a155b4 UW |
1996 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
1997 | + mips_regnum (gdbarch)->pc] | |
1998 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 1999 | + MIPS_RA_REGNUM]; |
29639122 | 2000 | } |
c906108c | 2001 | |
29639122 JB |
2002 | /* If we didn't reach the end of the prologue when scanning the function |
2003 | instructions, then set end_prologue_addr to the address of the | |
2004 | instruction immediately after the last one we scanned. */ | |
2005 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2006 | we may as well be careful and do our best if we have a null | |
2007 | end_prologue_addr. */ | |
2008 | if (end_prologue_addr == 0) | |
2009 | end_prologue_addr = cur_pc; | |
2010 | ||
2011 | /* In a frameless function, we might have incorrectly | |
2012 | skipped some load immediate instructions. Undo the skipping | |
2013 | if the load immediate was not followed by a stack adjustment. */ | |
2014 | if (load_immediate_bytes && !seen_sp_adjust) | |
2015 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2016 | |
29639122 | 2017 | return end_prologue_addr; |
c906108c SS |
2018 | } |
2019 | ||
29639122 JB |
2020 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2021 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2022 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2023 | unwinder. */ | |
c906108c | 2024 | |
29639122 JB |
2025 | static struct mips_frame_cache * |
2026 | mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache) | |
c906108c | 2027 | { |
29639122 | 2028 | struct mips_frame_cache *cache; |
c906108c | 2029 | |
29639122 JB |
2030 | if ((*this_cache) != NULL) |
2031 | return (*this_cache); | |
c5aa993b | 2032 | |
29639122 JB |
2033 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2034 | (*this_cache) = cache; | |
2035 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
c5aa993b | 2036 | |
29639122 JB |
2037 | /* Analyze the function prologue. */ |
2038 | { | |
6de5b849 JB |
2039 | const CORE_ADDR pc = |
2040 | frame_unwind_address_in_block (next_frame, NORMAL_FRAME); | |
29639122 | 2041 | CORE_ADDR start_addr; |
c906108c | 2042 | |
29639122 JB |
2043 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2044 | if (start_addr == 0) | |
2045 | start_addr = heuristic_proc_start (pc); | |
2046 | /* We can't analyze the prologue if we couldn't find the begining | |
2047 | of the function. */ | |
2048 | if (start_addr == 0) | |
2049 | return cache; | |
c5aa993b | 2050 | |
29639122 JB |
2051 | mips32_scan_prologue (start_addr, pc, next_frame, *this_cache); |
2052 | } | |
2053 | ||
3e8c568d | 2054 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 2055 | trad_frame_set_value (cache->saved_regs, |
72a155b4 UW |
2056 | gdbarch_num_regs (get_frame_arch (next_frame)) |
2057 | + MIPS_SP_REGNUM, | |
f57d151a | 2058 | cache->base); |
c5aa993b | 2059 | |
29639122 | 2060 | return (*this_cache); |
c906108c SS |
2061 | } |
2062 | ||
29639122 JB |
2063 | static void |
2064 | mips_insn32_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2065 | struct frame_id *this_id) | |
c906108c | 2066 | { |
29639122 JB |
2067 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
2068 | this_cache); | |
93d42b30 DJ |
2069 | (*this_id) = frame_id_build (info->base, |
2070 | frame_func_unwind (next_frame, NORMAL_FRAME)); | |
29639122 | 2071 | } |
c906108c | 2072 | |
29639122 JB |
2073 | static void |
2074 | mips_insn32_frame_prev_register (struct frame_info *next_frame, | |
2075 | void **this_cache, | |
2076 | int regnum, int *optimizedp, | |
2077 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 2078 | int *realnump, gdb_byte *valuep) |
29639122 JB |
2079 | { |
2080 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, | |
2081 | this_cache); | |
2082 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
2083 | optimizedp, lvalp, addrp, realnump, valuep); | |
c906108c SS |
2084 | } |
2085 | ||
29639122 JB |
2086 | static const struct frame_unwind mips_insn32_frame_unwind = |
2087 | { | |
2088 | NORMAL_FRAME, | |
2089 | mips_insn32_frame_this_id, | |
2090 | mips_insn32_frame_prev_register | |
2091 | }; | |
c906108c | 2092 | |
29639122 JB |
2093 | static const struct frame_unwind * |
2094 | mips_insn32_frame_sniffer (struct frame_info *next_frame) | |
2095 | { | |
6de5b849 | 2096 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
0fe7e7c8 | 2097 | if (! mips_pc_is_mips16 (pc)) |
29639122 JB |
2098 | return &mips_insn32_frame_unwind; |
2099 | return NULL; | |
2100 | } | |
c906108c | 2101 | |
1c645fec | 2102 | static CORE_ADDR |
29639122 JB |
2103 | mips_insn32_frame_base_address (struct frame_info *next_frame, |
2104 | void **this_cache) | |
c906108c | 2105 | { |
29639122 JB |
2106 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
2107 | this_cache); | |
2108 | return info->base; | |
2109 | } | |
c906108c | 2110 | |
29639122 JB |
2111 | static const struct frame_base mips_insn32_frame_base = |
2112 | { | |
2113 | &mips_insn32_frame_unwind, | |
2114 | mips_insn32_frame_base_address, | |
2115 | mips_insn32_frame_base_address, | |
2116 | mips_insn32_frame_base_address | |
2117 | }; | |
1c645fec | 2118 | |
29639122 JB |
2119 | static const struct frame_base * |
2120 | mips_insn32_frame_base_sniffer (struct frame_info *next_frame) | |
2121 | { | |
2122 | if (mips_insn32_frame_sniffer (next_frame) != NULL) | |
2123 | return &mips_insn32_frame_base; | |
a65bbe44 | 2124 | else |
29639122 JB |
2125 | return NULL; |
2126 | } | |
a65bbe44 | 2127 | |
29639122 JB |
2128 | static struct trad_frame_cache * |
2129 | mips_stub_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2130 | { | |
2131 | CORE_ADDR pc; | |
2132 | CORE_ADDR start_addr; | |
2133 | CORE_ADDR stack_addr; | |
2134 | struct trad_frame_cache *this_trad_cache; | |
72a155b4 | 2135 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
c906108c | 2136 | |
29639122 JB |
2137 | if ((*this_cache) != NULL) |
2138 | return (*this_cache); | |
2139 | this_trad_cache = trad_frame_cache_zalloc (next_frame); | |
2140 | (*this_cache) = this_trad_cache; | |
1c645fec | 2141 | |
29639122 | 2142 | /* The return address is in the link register. */ |
3e8c568d | 2143 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 UW |
2144 | gdbarch_pc_regnum (gdbarch), |
2145 | (gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM)); | |
1c645fec | 2146 | |
29639122 JB |
2147 | /* Frame ID, since it's a frameless / stackless function, no stack |
2148 | space is allocated and SP on entry is the current SP. */ | |
2149 | pc = frame_pc_unwind (next_frame); | |
2150 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
4c7d22cb | 2151 | stack_addr = frame_unwind_register_signed (next_frame, MIPS_SP_REGNUM); |
aa6c981f | 2152 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 2153 | |
29639122 JB |
2154 | /* Assume that the frame's base is the same as the |
2155 | stack-pointer. */ | |
2156 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2157 | |
29639122 JB |
2158 | return this_trad_cache; |
2159 | } | |
c906108c | 2160 | |
29639122 JB |
2161 | static void |
2162 | mips_stub_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2163 | struct frame_id *this_id) | |
2164 | { | |
2165 | struct trad_frame_cache *this_trad_cache | |
2166 | = mips_stub_frame_cache (next_frame, this_cache); | |
2167 | trad_frame_get_id (this_trad_cache, this_id); | |
2168 | } | |
c906108c | 2169 | |
29639122 JB |
2170 | static void |
2171 | mips_stub_frame_prev_register (struct frame_info *next_frame, | |
2172 | void **this_cache, | |
2173 | int regnum, int *optimizedp, | |
2174 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 2175 | int *realnump, gdb_byte *valuep) |
29639122 JB |
2176 | { |
2177 | struct trad_frame_cache *this_trad_cache | |
2178 | = mips_stub_frame_cache (next_frame, this_cache); | |
2179 | trad_frame_get_register (this_trad_cache, next_frame, regnum, optimizedp, | |
2180 | lvalp, addrp, realnump, valuep); | |
2181 | } | |
c906108c | 2182 | |
29639122 JB |
2183 | static const struct frame_unwind mips_stub_frame_unwind = |
2184 | { | |
2185 | NORMAL_FRAME, | |
2186 | mips_stub_frame_this_id, | |
2187 | mips_stub_frame_prev_register | |
2188 | }; | |
c906108c | 2189 | |
29639122 JB |
2190 | static const struct frame_unwind * |
2191 | mips_stub_frame_sniffer (struct frame_info *next_frame) | |
2192 | { | |
aa6c981f | 2193 | gdb_byte dummy[4]; |
979b38e0 | 2194 | struct obj_section *s; |
93d42b30 | 2195 | CORE_ADDR pc = frame_unwind_address_in_block (next_frame, NORMAL_FRAME); |
979b38e0 | 2196 | |
aa6c981f DJ |
2197 | /* Use the stub unwinder for unreadable code. */ |
2198 | if (target_read_memory (frame_pc_unwind (next_frame), dummy, 4) != 0) | |
2199 | return &mips_stub_frame_unwind; | |
2200 | ||
29639122 JB |
2201 | if (in_plt_section (pc, NULL)) |
2202 | return &mips_stub_frame_unwind; | |
979b38e0 DJ |
2203 | |
2204 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2205 | s = find_pc_section (pc); | |
2206 | ||
2207 | if (s != NULL | |
2208 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2209 | ".MIPS.stubs") == 0) | |
2210 | return &mips_stub_frame_unwind; | |
2211 | ||
2212 | return NULL; | |
29639122 | 2213 | } |
c906108c | 2214 | |
29639122 JB |
2215 | static CORE_ADDR |
2216 | mips_stub_frame_base_address (struct frame_info *next_frame, | |
2217 | void **this_cache) | |
2218 | { | |
2219 | struct trad_frame_cache *this_trad_cache | |
2220 | = mips_stub_frame_cache (next_frame, this_cache); | |
2221 | return trad_frame_get_this_base (this_trad_cache); | |
2222 | } | |
0fce0821 | 2223 | |
29639122 JB |
2224 | static const struct frame_base mips_stub_frame_base = |
2225 | { | |
2226 | &mips_stub_frame_unwind, | |
2227 | mips_stub_frame_base_address, | |
2228 | mips_stub_frame_base_address, | |
2229 | mips_stub_frame_base_address | |
2230 | }; | |
2231 | ||
2232 | static const struct frame_base * | |
2233 | mips_stub_frame_base_sniffer (struct frame_info *next_frame) | |
2234 | { | |
2235 | if (mips_stub_frame_sniffer (next_frame) != NULL) | |
2236 | return &mips_stub_frame_base; | |
2237 | else | |
2238 | return NULL; | |
2239 | } | |
2240 | ||
29639122 | 2241 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2242 | |
29639122 JB |
2243 | static CORE_ADDR |
2244 | mips_addr_bits_remove (CORE_ADDR addr) | |
65596487 | 2245 | { |
29639122 JB |
2246 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2247 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) | |
2248 | /* This hack is a work-around for existing boards using PMON, the | |
2249 | simulator, and any other 64-bit targets that doesn't have true | |
2250 | 64-bit addressing. On these targets, the upper 32 bits of | |
2251 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2252 | likely to have been sign extended to all 1s by instruction | |
2253 | sequences that load 32-bit addresses. For example, a typical | |
2254 | piece of code that loads an address is this: | |
65596487 | 2255 | |
29639122 JB |
2256 | lui $r2, <upper 16 bits> |
2257 | ori $r2, <lower 16 bits> | |
65596487 | 2258 | |
29639122 JB |
2259 | But the lui sign-extends the value such that the upper 32 bits |
2260 | may be all 1s. The workaround is simply to mask off these | |
2261 | bits. In the future, gcc may be changed to support true 64-bit | |
2262 | addressing, and this masking will have to be disabled. */ | |
2263 | return addr &= 0xffffffffUL; | |
2264 | else | |
2265 | return addr; | |
65596487 JB |
2266 | } |
2267 | ||
3d5f6d12 DJ |
2268 | /* Instructions used during single-stepping of atomic sequences. */ |
2269 | #define LL_OPCODE 0x30 | |
2270 | #define LLD_OPCODE 0x34 | |
2271 | #define SC_OPCODE 0x38 | |
2272 | #define SCD_OPCODE 0x3c | |
2273 | ||
2274 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
2275 | instruction and ending with a SC/SCD instruction. If such a sequence | |
2276 | is found, attempt to step through it. A breakpoint is placed at the end of | |
2277 | the sequence. */ | |
2278 | ||
2279 | static int | |
2280 | deal_with_atomic_sequence (CORE_ADDR pc) | |
2281 | { | |
2282 | CORE_ADDR breaks[2] = {-1, -1}; | |
2283 | CORE_ADDR loc = pc; | |
2284 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
2285 | unsigned long insn; | |
2286 | int insn_count; | |
2287 | int index; | |
2288 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
2289 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
2290 | ||
2291 | if (pc & 0x01) | |
2292 | return 0; | |
2293 | ||
2294 | insn = mips_fetch_instruction (loc); | |
2295 | /* Assume all atomic sequences start with a ll/lld instruction. */ | |
2296 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
2297 | return 0; | |
2298 | ||
2299 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
2300 | instructions. */ | |
2301 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
2302 | { | |
2303 | int is_branch = 0; | |
2304 | loc += MIPS_INSN32_SIZE; | |
2305 | insn = mips_fetch_instruction (loc); | |
2306 | ||
2307 | /* Assume that there is at most one branch in the atomic | |
2308 | sequence. If a branch is found, put a breakpoint in its | |
2309 | destination address. */ | |
2310 | switch (itype_op (insn)) | |
2311 | { | |
2312 | case 0: /* SPECIAL */ | |
2313 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
2314 | return 0; /* fallback to the standard single-step code. */ | |
2315 | break; | |
2316 | case 1: /* REGIMM */ | |
2317 | is_branch = ((itype_rt (insn) & 0xc0) == 0); /* B{LT,GE}Z* */ | |
2318 | break; | |
2319 | case 2: /* J */ | |
2320 | case 3: /* JAL */ | |
2321 | return 0; /* fallback to the standard single-step code. */ | |
2322 | case 4: /* BEQ */ | |
2323 | case 5: /* BNE */ | |
2324 | case 6: /* BLEZ */ | |
2325 | case 7: /* BGTZ */ | |
2326 | case 20: /* BEQL */ | |
2327 | case 21: /* BNEL */ | |
2328 | case 22: /* BLEZL */ | |
2329 | case 23: /* BGTTL */ | |
2330 | is_branch = 1; | |
2331 | break; | |
2332 | case 17: /* COP1 */ | |
2333 | case 18: /* COP2 */ | |
2334 | case 19: /* COP3 */ | |
2335 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
2336 | break; | |
2337 | } | |
2338 | if (is_branch) | |
2339 | { | |
2340 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
2341 | if (last_breakpoint >= 1) | |
2342 | return 0; /* More than one branch found, fallback to the | |
2343 | standard single-step code. */ | |
2344 | breaks[1] = branch_bp; | |
2345 | last_breakpoint++; | |
2346 | } | |
2347 | ||
2348 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
2349 | break; | |
2350 | } | |
2351 | ||
2352 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
2353 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
2354 | return 0; | |
2355 | ||
2356 | loc += MIPS_INSN32_SIZE; | |
2357 | ||
2358 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
2359 | breaks[0] = loc; | |
2360 | ||
2361 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
2362 | placed (branch instruction's destination) in the atomic sequence */ | |
2363 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) | |
2364 | last_breakpoint = 0; | |
2365 | ||
2366 | /* Effectively inserts the breakpoints. */ | |
2367 | for (index = 0; index <= last_breakpoint; index++) | |
2368 | insert_single_step_breakpoint (breaks[index]); | |
2369 | ||
2370 | return 1; | |
2371 | } | |
2372 | ||
29639122 JB |
2373 | /* mips_software_single_step() is called just before we want to resume |
2374 | the inferior, if we want to single-step it but there is no hardware | |
2375 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 2376 | the target of the coming instruction and breakpoint it. */ |
29639122 | 2377 | |
e6590a1b | 2378 | int |
0b1b3e42 | 2379 | mips_software_single_step (struct frame_info *frame) |
c906108c | 2380 | { |
8181d85f | 2381 | CORE_ADDR pc, next_pc; |
65596487 | 2382 | |
0b1b3e42 | 2383 | pc = get_frame_pc (frame); |
3d5f6d12 DJ |
2384 | if (deal_with_atomic_sequence (pc)) |
2385 | return 1; | |
2386 | ||
0b1b3e42 | 2387 | next_pc = mips_next_pc (frame, pc); |
e6590a1b | 2388 | |
e0cd558a | 2389 | insert_single_step_breakpoint (next_pc); |
e6590a1b | 2390 | return 1; |
29639122 | 2391 | } |
a65bbe44 | 2392 | |
29639122 JB |
2393 | /* Test whether the PC points to the return instruction at the |
2394 | end of a function. */ | |
65596487 | 2395 | |
29639122 JB |
2396 | static int |
2397 | mips_about_to_return (CORE_ADDR pc) | |
2398 | { | |
0fe7e7c8 | 2399 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2400 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2401 | generates a "jr $ra"; other times it generates code to load | |
2402 | the return address from the stack to an accessible register (such | |
2403 | as $a3), then a "jr" using that register. This second case | |
2404 | is almost impossible to distinguish from an indirect jump | |
2405 | used for switch statements, so we don't even try. */ | |
2406 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
2407 | else | |
2408 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
2409 | } | |
c906108c | 2410 | |
c906108c | 2411 | |
29639122 JB |
2412 | /* This fencepost looks highly suspicious to me. Removing it also |
2413 | seems suspicious as it could affect remote debugging across serial | |
2414 | lines. */ | |
c906108c | 2415 | |
29639122 JB |
2416 | static CORE_ADDR |
2417 | heuristic_proc_start (CORE_ADDR pc) | |
2418 | { | |
2419 | CORE_ADDR start_pc; | |
2420 | CORE_ADDR fence; | |
2421 | int instlen; | |
2422 | int seen_adjsp = 0; | |
65596487 | 2423 | |
bf6ae464 | 2424 | pc = gdbarch_addr_bits_remove (current_gdbarch, pc); |
29639122 JB |
2425 | start_pc = pc; |
2426 | fence = start_pc - heuristic_fence_post; | |
2427 | if (start_pc == 0) | |
2428 | return 0; | |
65596487 | 2429 | |
29639122 JB |
2430 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2431 | fence = VM_MIN_ADDRESS; | |
65596487 | 2432 | |
95ac2dcf | 2433 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2434 | |
29639122 JB |
2435 | /* search back for previous return */ |
2436 | for (start_pc -= instlen;; start_pc -= instlen) | |
2437 | if (start_pc < fence) | |
2438 | { | |
2439 | /* It's not clear to me why we reach this point when | |
2440 | stop_soon, but with this test, at least we | |
2441 | don't print out warnings for every child forked (eg, on | |
2442 | decstation). 22apr93 rich@cygnus.com. */ | |
2443 | if (stop_soon == NO_STOP_QUIETLY) | |
2444 | { | |
2445 | static int blurb_printed = 0; | |
98b4dd94 | 2446 | |
8a3fe4f8 | 2447 | warning (_("GDB can't find the start of the function at 0x%s."), |
29639122 JB |
2448 | paddr_nz (pc)); |
2449 | ||
2450 | if (!blurb_printed) | |
2451 | { | |
2452 | /* This actually happens frequently in embedded | |
2453 | development, when you first connect to a board | |
2454 | and your stack pointer and pc are nowhere in | |
2455 | particular. This message needs to give people | |
2456 | in that situation enough information to | |
2457 | determine that it's no big deal. */ | |
2458 | printf_filtered ("\n\ | |
2459 | GDB is unable to find the start of the function at 0x%s\n\ | |
2460 | and thus can't determine the size of that function's stack frame.\n\ | |
2461 | This means that GDB may be unable to access that stack frame, or\n\ | |
2462 | the frames below it.\n\ | |
2463 | This problem is most likely caused by an invalid program counter or\n\ | |
2464 | stack pointer.\n\ | |
2465 | However, if you think GDB should simply search farther back\n\ | |
2466 | from 0x%s for code which looks like the beginning of a\n\ | |
2467 | function, you can increase the range of the search using the `set\n\ | |
2468 | heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); | |
2469 | blurb_printed = 1; | |
2470 | } | |
2471 | } | |
2472 | ||
2473 | return 0; | |
2474 | } | |
0fe7e7c8 | 2475 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2476 | { |
2477 | unsigned short inst; | |
2478 | ||
2479 | /* On MIPS16, any one of the following is likely to be the | |
2480 | start of a function: | |
193774b3 MR |
2481 | extend save |
2482 | save | |
29639122 JB |
2483 | entry |
2484 | addiu sp,-n | |
2485 | daddiu sp,-n | |
2486 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
2487 | inst = mips_fetch_instruction (start_pc); | |
193774b3 MR |
2488 | if ((inst & 0xff80) == 0x6480) /* save */ |
2489 | { | |
2490 | if (start_pc - instlen >= fence) | |
2491 | { | |
2492 | inst = mips_fetch_instruction (start_pc - instlen); | |
2493 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
2494 | start_pc -= instlen; | |
2495 | } | |
2496 | break; | |
2497 | } | |
2498 | else if (((inst & 0xf81f) == 0xe809 | |
2499 | && (inst & 0x700) != 0x700) /* entry */ | |
2500 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2501 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2502 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
2503 | break; |
2504 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2505 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2506 | seen_adjsp = 1; | |
2507 | else | |
2508 | seen_adjsp = 0; | |
2509 | } | |
2510 | else if (mips_about_to_return (start_pc)) | |
2511 | { | |
4c7d22cb | 2512 | /* Skip return and its delay slot. */ |
95ac2dcf | 2513 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2514 | break; |
2515 | } | |
2516 | ||
2517 | return start_pc; | |
c906108c SS |
2518 | } |
2519 | ||
6c0d6680 DJ |
2520 | struct mips_objfile_private |
2521 | { | |
2522 | bfd_size_type size; | |
2523 | char *contents; | |
2524 | }; | |
2525 | ||
f09ded24 AC |
2526 | /* According to the current ABI, should the type be passed in a |
2527 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 2528 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 AC |
2529 | FP registers and, consequently this returns false - forces FP |
2530 | arguments into integer registers. */ | |
2531 | ||
2532 | static int | |
2533 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2534 | { | |
2535 | return ((typecode == TYPE_CODE_FLT | |
2536 | || (MIPS_EABI | |
6d82d43b AC |
2537 | && (typecode == TYPE_CODE_STRUCT |
2538 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 2539 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
2540 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
2541 | == TYPE_CODE_FLT)) | |
c86b5b38 | 2542 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2543 | } |
2544 | ||
49e790b0 DJ |
2545 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2546 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2547 | ||
2548 | static int | |
2549 | mips_type_needs_double_align (struct type *type) | |
2550 | { | |
2551 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2552 | |
49e790b0 DJ |
2553 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2554 | return 1; | |
2555 | else if (typecode == TYPE_CODE_STRUCT) | |
2556 | { | |
2557 | if (TYPE_NFIELDS (type) < 1) | |
2558 | return 0; | |
2559 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2560 | } | |
2561 | else if (typecode == TYPE_CODE_UNION) | |
2562 | { | |
361d1df0 | 2563 | int i, n; |
49e790b0 DJ |
2564 | |
2565 | n = TYPE_NFIELDS (type); | |
2566 | for (i = 0; i < n; i++) | |
2567 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2568 | return 1; | |
2569 | return 0; | |
2570 | } | |
2571 | return 0; | |
2572 | } | |
2573 | ||
dc604539 AC |
2574 | /* Adjust the address downward (direction of stack growth) so that it |
2575 | is correctly aligned for a new stack frame. */ | |
2576 | static CORE_ADDR | |
2577 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2578 | { | |
5b03f266 | 2579 | return align_down (addr, 16); |
dc604539 AC |
2580 | } |
2581 | ||
f7ab6ec6 | 2582 | static CORE_ADDR |
7d9b040b | 2583 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2584 | struct regcache *regcache, CORE_ADDR bp_addr, |
2585 | int nargs, struct value **args, CORE_ADDR sp, | |
2586 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2587 | { |
2588 | int argreg; | |
2589 | int float_argreg; | |
2590 | int argnum; | |
2591 | int len = 0; | |
2592 | int stack_offset = 0; | |
480d3dd2 | 2593 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2594 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 2595 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 2596 | |
25ab4790 AC |
2597 | /* For shared libraries, "t9" needs to point at the function |
2598 | address. */ | |
4c7d22cb | 2599 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2600 | |
2601 | /* Set the return address register to point to the entry point of | |
2602 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2603 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2604 | |
c906108c | 2605 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2606 | are properly aligned. The stack has to be at least 64-bit |
2607 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2608 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2609 | aligned, so we round to this widest known alignment. */ | |
2610 | ||
5b03f266 AC |
2611 | sp = align_down (sp, 16); |
2612 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2613 | |
46e0f506 | 2614 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2615 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2616 | passed in registers, but that's OK. */ |
c906108c | 2617 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 2618 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 2619 | sp -= align_up (len, 16); |
c906108c | 2620 | |
9ace0497 | 2621 | if (mips_debug) |
6d82d43b | 2622 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2623 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2624 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2625 | |
c906108c | 2626 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2627 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 2628 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 2629 | |
46e0f506 | 2630 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2631 | if (struct_return) |
9ace0497 AC |
2632 | { |
2633 | if (mips_debug) | |
2634 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2635 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2636 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 2637 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 2638 | } |
c906108c SS |
2639 | |
2640 | /* Now load as many as possible of the first arguments into | |
2641 | registers, and push the rest onto the stack. Loop thru args | |
2642 | from first to last. */ | |
2643 | for (argnum = 0; argnum < nargs; argnum++) | |
2644 | { | |
47a35522 MK |
2645 | const gdb_byte *val; |
2646 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 2647 | struct value *arg = args[argnum]; |
4991999e | 2648 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
2649 | int len = TYPE_LENGTH (arg_type); |
2650 | enum type_code typecode = TYPE_CODE (arg_type); | |
2651 | ||
9ace0497 AC |
2652 | if (mips_debug) |
2653 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2654 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2655 | argnum + 1, len, (int) typecode); |
9ace0497 | 2656 | |
c906108c | 2657 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2658 | reference. */ |
1a69e1e4 | 2659 | if (len > regsize |
9ace0497 | 2660 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2661 | { |
1a69e1e4 | 2662 | store_unsigned_integer (valbuf, regsize, VALUE_ADDRESS (arg)); |
c906108c | 2663 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 2664 | len = regsize; |
c906108c | 2665 | val = valbuf; |
9ace0497 AC |
2666 | if (mips_debug) |
2667 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2668 | } |
2669 | else | |
47a35522 | 2670 | val = value_contents (arg); |
c906108c SS |
2671 | |
2672 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2673 | even-numbered floating point register. Round the FP register |
2674 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2675 | left. Non MIPS_EABI targets also pass the FP in the integer |
2676 | registers so also round up normal registers. */ | |
1a69e1e4 | 2677 | if (regsize < 8 && fp_register_arg_p (typecode, arg_type)) |
acdb74a0 AC |
2678 | { |
2679 | if ((float_argreg & 1)) | |
2680 | float_argreg++; | |
2681 | } | |
c906108c SS |
2682 | |
2683 | /* Floating point arguments passed in registers have to be | |
2684 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2685 | are passed in register pairs; the even register gets |
2686 | the low word, and the odd register gets the high word. | |
2687 | On non-EABI processors, the first two floating point arguments are | |
2688 | also copied to general registers, because MIPS16 functions | |
2689 | don't use float registers for arguments. This duplication of | |
2690 | arguments in general registers can't hurt non-MIPS16 functions | |
2691 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2692 | /* MIPS_EABI squeezes a struct that contains a single floating |
2693 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2694 | stack. */ |
f09ded24 AC |
2695 | if (fp_register_arg_p (typecode, arg_type) |
2696 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c | 2697 | { |
6da397e0 KB |
2698 | /* EABI32 will pass doubles in consecutive registers, even on |
2699 | 64-bit cores. At one time, we used to check the size of | |
2700 | `float_argreg' to determine whether or not to pass doubles | |
2701 | in consecutive registers, but this is not sufficient for | |
2702 | making the ABI determination. */ | |
2703 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 2704 | { |
72a155b4 | 2705 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 2706 | == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2707 | unsigned long regval; |
2708 | ||
2709 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2710 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2711 | if (mips_debug) |
acdb74a0 | 2712 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2713 | float_argreg, phex (regval, 4)); |
9c9acae0 | 2714 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2715 | |
2716 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2717 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2718 | if (mips_debug) |
acdb74a0 | 2719 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2720 | float_argreg, phex (regval, 4)); |
9c9acae0 | 2721 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2722 | } |
2723 | else | |
2724 | { | |
2725 | /* This is a floating point value that fits entirely | |
2726 | in a single register. */ | |
53a5351d | 2727 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 2728 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2729 | LONGEST regval = extract_unsigned_integer (val, len); |
2730 | if (mips_debug) | |
acdb74a0 | 2731 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2732 | float_argreg, phex (regval, len)); |
9c9acae0 | 2733 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2734 | } |
2735 | } | |
2736 | else | |
2737 | { | |
2738 | /* Copy the argument to general registers or the stack in | |
2739 | register-sized pieces. Large arguments are split between | |
2740 | registers and stack. */ | |
1a69e1e4 DJ |
2741 | /* Note: structs whose size is not a multiple of regsize |
2742 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
2743 | them in registers where gcc sometimes puts them on the |
2744 | stack. For maximum compatibility, we will put them in | |
2745 | both places. */ | |
1a69e1e4 | 2746 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 2747 | |
f09ded24 | 2748 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2749 | register are only written to memory. */ |
c906108c SS |
2750 | while (len > 0) |
2751 | { | |
ebafbe83 | 2752 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2753 | int stack_used_p = 0; |
1a69e1e4 | 2754 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 2755 | |
acdb74a0 AC |
2756 | if (mips_debug) |
2757 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2758 | partial_len); | |
2759 | ||
566f0f7a | 2760 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2761 | if (argreg > MIPS_LAST_ARG_REGNUM |
2762 | || odd_sized_struct | |
2763 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2764 | { |
c906108c SS |
2765 | /* Should shorter than int integer values be |
2766 | promoted to int before being stored? */ | |
c906108c | 2767 | int longword_offset = 0; |
9ace0497 | 2768 | CORE_ADDR addr; |
566f0f7a | 2769 | stack_used_p = 1; |
72a155b4 | 2770 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 2771 | { |
1a69e1e4 | 2772 | if (regsize == 8 |
480d3dd2 AC |
2773 | && (typecode == TYPE_CODE_INT |
2774 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 2775 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 2776 | longword_offset = regsize - len; |
480d3dd2 AC |
2777 | else if ((typecode == TYPE_CODE_STRUCT |
2778 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
2779 | && TYPE_LENGTH (arg_type) < regsize) |
2780 | longword_offset = regsize - len; | |
7a292a7a | 2781 | } |
c5aa993b | 2782 | |
9ace0497 AC |
2783 | if (mips_debug) |
2784 | { | |
cb3d25d1 MS |
2785 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2786 | paddr_nz (stack_offset)); | |
2787 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2788 | paddr_nz (longword_offset)); | |
9ace0497 | 2789 | } |
361d1df0 | 2790 | |
9ace0497 AC |
2791 | addr = sp + stack_offset + longword_offset; |
2792 | ||
2793 | if (mips_debug) | |
2794 | { | |
2795 | int i; | |
6d82d43b | 2796 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 | 2797 | paddr_nz (addr)); |
9ace0497 AC |
2798 | for (i = 0; i < partial_len; i++) |
2799 | { | |
6d82d43b | 2800 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 2801 | val[i] & 0xff); |
9ace0497 AC |
2802 | } |
2803 | } | |
2804 | write_memory (addr, val, partial_len); | |
c906108c SS |
2805 | } |
2806 | ||
f09ded24 AC |
2807 | /* Note!!! This is NOT an else clause. Odd sized |
2808 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2809 | arguments will not. */ |
566f0f7a | 2810 | /* Write this portion of the argument to a general |
6d82d43b | 2811 | purpose register. */ |
f09ded24 AC |
2812 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2813 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2814 | { |
6d82d43b AC |
2815 | LONGEST regval = |
2816 | extract_unsigned_integer (val, partial_len); | |
c906108c | 2817 | |
9ace0497 | 2818 | if (mips_debug) |
acdb74a0 | 2819 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 2820 | argreg, |
1a69e1e4 | 2821 | phex (regval, regsize)); |
9c9acae0 | 2822 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
c906108c | 2823 | argreg++; |
c906108c | 2824 | } |
c5aa993b | 2825 | |
c906108c SS |
2826 | len -= partial_len; |
2827 | val += partial_len; | |
2828 | ||
566f0f7a | 2829 | /* Compute the the offset into the stack at which we |
6d82d43b | 2830 | will copy the next parameter. |
566f0f7a | 2831 | |
566f0f7a | 2832 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2833 | only needs to be adjusted when it has been used. */ |
c906108c | 2834 | |
46e0f506 | 2835 | if (stack_used_p) |
1a69e1e4 | 2836 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
2837 | } |
2838 | } | |
9ace0497 AC |
2839 | if (mips_debug) |
2840 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2841 | } |
2842 | ||
f10683bb | 2843 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 2844 | |
0f71a2f6 JM |
2845 | /* Return adjusted stack pointer. */ |
2846 | return sp; | |
2847 | } | |
2848 | ||
a1f5b845 | 2849 | /* Determine the return value convention being used. */ |
6d82d43b | 2850 | |
9c8fdbfa AC |
2851 | static enum return_value_convention |
2852 | mips_eabi_return_value (struct gdbarch *gdbarch, | |
2853 | struct type *type, struct regcache *regcache, | |
47a35522 | 2854 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 2855 | { |
9c8fdbfa AC |
2856 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
2857 | return RETURN_VALUE_STRUCT_CONVENTION; | |
2858 | if (readbuf) | |
2859 | memset (readbuf, 0, TYPE_LENGTH (type)); | |
2860 | return RETURN_VALUE_REGISTER_CONVENTION; | |
6d82d43b AC |
2861 | } |
2862 | ||
6d82d43b AC |
2863 | |
2864 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 2865 | |
8d26208a DJ |
2866 | /* Search for a naturally aligned double at OFFSET inside a struct |
2867 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
2868 | registers. */ | |
2869 | ||
2870 | static int | |
2871 | mips_n32n64_fp_arg_chunk_p (struct type *arg_type, int offset) | |
2872 | { | |
2873 | int i; | |
2874 | ||
2875 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
2876 | return 0; | |
2877 | ||
2878 | if (MIPS_FPU_TYPE != MIPS_FPU_DOUBLE) | |
2879 | return 0; | |
2880 | ||
2881 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
2882 | return 0; | |
2883 | ||
2884 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
2885 | { | |
2886 | int pos; | |
2887 | struct type *field_type; | |
2888 | ||
2889 | /* We're only looking at normal fields. */ | |
2890 | if (TYPE_FIELD_STATIC (arg_type, i) | |
2891 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) | |
2892 | continue; | |
2893 | ||
2894 | /* If we have gone past the offset, there is no double to pass. */ | |
2895 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
2896 | if (pos > offset) | |
2897 | return 0; | |
2898 | ||
2899 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
2900 | ||
2901 | /* If this field is entirely before the requested offset, go | |
2902 | on to the next one. */ | |
2903 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
2904 | continue; | |
2905 | ||
2906 | /* If this is our special aligned double, we can stop. */ | |
2907 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
2908 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
2909 | return 1; | |
2910 | ||
2911 | /* This field starts at or before the requested offset, and | |
2912 | overlaps it. If it is a structure, recurse inwards. */ | |
2913 | return mips_n32n64_fp_arg_chunk_p (field_type, offset - pos); | |
2914 | } | |
2915 | ||
2916 | return 0; | |
2917 | } | |
2918 | ||
f7ab6ec6 | 2919 | static CORE_ADDR |
7d9b040b | 2920 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2921 | struct regcache *regcache, CORE_ADDR bp_addr, |
2922 | int nargs, struct value **args, CORE_ADDR sp, | |
2923 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
2924 | { |
2925 | int argreg; | |
2926 | int float_argreg; | |
2927 | int argnum; | |
2928 | int len = 0; | |
2929 | int stack_offset = 0; | |
480d3dd2 | 2930 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2931 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 2932 | |
25ab4790 AC |
2933 | /* For shared libraries, "t9" needs to point at the function |
2934 | address. */ | |
4c7d22cb | 2935 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2936 | |
2937 | /* Set the return address register to point to the entry point of | |
2938 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2939 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2940 | |
cb3d25d1 MS |
2941 | /* First ensure that the stack and structure return address (if any) |
2942 | are properly aligned. The stack has to be at least 64-bit | |
2943 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2944 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2945 | aligned, so we round to this widest known alignment. */ | |
2946 | ||
5b03f266 AC |
2947 | sp = align_down (sp, 16); |
2948 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
2949 | |
2950 | /* Now make space on the stack for the args. */ | |
2951 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 2952 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 2953 | sp -= align_up (len, 16); |
cb3d25d1 MS |
2954 | |
2955 | if (mips_debug) | |
6d82d43b | 2956 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2957 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
2958 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
2959 | |
2960 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 2961 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 2962 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 2963 | |
46e0f506 | 2964 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
2965 | if (struct_return) |
2966 | { | |
2967 | if (mips_debug) | |
2968 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2969 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2970 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 2971 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
2972 | } |
2973 | ||
2974 | /* Now load as many as possible of the first arguments into | |
2975 | registers, and push the rest onto the stack. Loop thru args | |
2976 | from first to last. */ | |
2977 | for (argnum = 0; argnum < nargs; argnum++) | |
2978 | { | |
47a35522 | 2979 | const gdb_byte *val; |
cb3d25d1 | 2980 | struct value *arg = args[argnum]; |
4991999e | 2981 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
2982 | int len = TYPE_LENGTH (arg_type); |
2983 | enum type_code typecode = TYPE_CODE (arg_type); | |
2984 | ||
2985 | if (mips_debug) | |
2986 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2987 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
2988 | argnum + 1, len, (int) typecode); |
2989 | ||
47a35522 | 2990 | val = value_contents (arg); |
cb3d25d1 MS |
2991 | |
2992 | if (fp_register_arg_p (typecode, arg_type) | |
8d26208a | 2993 | && argreg <= MIPS_LAST_ARG_REGNUM) |
cb3d25d1 MS |
2994 | { |
2995 | /* This is a floating point value that fits entirely | |
2996 | in a single register. */ | |
cb3d25d1 MS |
2997 | LONGEST regval = extract_unsigned_integer (val, len); |
2998 | if (mips_debug) | |
2999 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3000 | float_argreg, phex (regval, len)); | |
8d26208a | 3001 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
3002 | |
3003 | if (mips_debug) | |
3004 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3005 | argreg, phex (regval, len)); | |
9c9acae0 | 3006 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
3007 | float_argreg++; |
3008 | argreg++; | |
cb3d25d1 MS |
3009 | } |
3010 | else | |
3011 | { | |
3012 | /* Copy the argument to general registers or the stack in | |
3013 | register-sized pieces. Large arguments are split between | |
3014 | registers and stack. */ | |
ab2e1992 MR |
3015 | /* For N32/N64, structs, unions, or other composite types are |
3016 | treated as a sequence of doublewords, and are passed in integer | |
3017 | or floating point registers as though they were simple scalar | |
3018 | parameters to the extent that they fit, with any excess on the | |
3019 | stack packed according to the normal memory layout of the | |
3020 | object. | |
3021 | The caller does not reserve space for the register arguments; | |
3022 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 3023 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3024 | register are only written to memory. */ |
cb3d25d1 MS |
3025 | while (len > 0) |
3026 | { | |
ad018eee | 3027 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 3028 | int stack_used_p = 0; |
1a69e1e4 | 3029 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
3030 | |
3031 | if (mips_debug) | |
3032 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3033 | partial_len); | |
3034 | ||
8d26208a DJ |
3035 | if (fp_register_arg_p (typecode, arg_type)) |
3036 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM); | |
3037 | ||
cb3d25d1 | 3038 | /* Write this portion of the argument to the stack. */ |
ab2e1992 | 3039 | if (argreg > MIPS_LAST_ARG_REGNUM) |
cb3d25d1 MS |
3040 | { |
3041 | /* Should shorter than int integer values be | |
3042 | promoted to int before being stored? */ | |
3043 | int longword_offset = 0; | |
3044 | CORE_ADDR addr; | |
3045 | stack_used_p = 1; | |
72a155b4 | 3046 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 3047 | { |
1a69e1e4 DJ |
3048 | if ((typecode == TYPE_CODE_INT |
3049 | || typecode == TYPE_CODE_PTR | |
3050 | || typecode == TYPE_CODE_FLT) | |
3051 | && len <= 4) | |
3052 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
3053 | } |
3054 | ||
3055 | if (mips_debug) | |
3056 | { | |
3057 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3058 | paddr_nz (stack_offset)); | |
3059 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3060 | paddr_nz (longword_offset)); | |
3061 | } | |
3062 | ||
3063 | addr = sp + stack_offset + longword_offset; | |
3064 | ||
3065 | if (mips_debug) | |
3066 | { | |
3067 | int i; | |
6d82d43b | 3068 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 MS |
3069 | paddr_nz (addr)); |
3070 | for (i = 0; i < partial_len; i++) | |
3071 | { | |
6d82d43b | 3072 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3073 | val[i] & 0xff); |
3074 | } | |
3075 | } | |
3076 | write_memory (addr, val, partial_len); | |
3077 | } | |
3078 | ||
3079 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 3080 | structs may go thru BOTH paths. */ |
cb3d25d1 | 3081 | /* Write this portion of the argument to a general |
6d82d43b | 3082 | purpose register. */ |
8d26208a | 3083 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
cb3d25d1 | 3084 | { |
6d82d43b AC |
3085 | LONGEST regval = |
3086 | extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
3087 | |
3088 | /* A non-floating-point argument being passed in a | |
3089 | general register. If a struct or union, and if | |
3090 | the remaining length is smaller than the register | |
3091 | size, we have to adjust the register value on | |
3092 | big endian targets. | |
3093 | ||
3094 | It does not seem to be necessary to do the | |
1a69e1e4 | 3095 | same for integral types. */ |
cb3d25d1 | 3096 | |
72a155b4 | 3097 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3098 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3099 | && (typecode == TYPE_CODE_STRUCT |
3100 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3101 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3102 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
3103 | |
3104 | if (mips_debug) | |
3105 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3106 | argreg, | |
1a69e1e4 | 3107 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3108 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
3109 | |
3110 | if (mips_n32n64_fp_arg_chunk_p (arg_type, | |
3111 | TYPE_LENGTH (arg_type) - len)) | |
3112 | { | |
3113 | if (mips_debug) | |
3114 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
3115 | float_argreg, | |
3116 | phex (regval, MIPS64_REGSIZE)); | |
3117 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
3118 | regval); | |
3119 | } | |
3120 | ||
3121 | float_argreg++; | |
cb3d25d1 MS |
3122 | argreg++; |
3123 | } | |
3124 | ||
3125 | len -= partial_len; | |
3126 | val += partial_len; | |
3127 | ||
3128 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3129 | will copy the next parameter. |
cb3d25d1 MS |
3130 | |
3131 | In N32 (N64?), the stack_offset only needs to be | |
3132 | adjusted when it has been used. */ | |
3133 | ||
3134 | if (stack_used_p) | |
1a69e1e4 | 3135 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
3136 | } |
3137 | } | |
3138 | if (mips_debug) | |
3139 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3140 | } | |
3141 | ||
f10683bb | 3142 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3143 | |
cb3d25d1 MS |
3144 | /* Return adjusted stack pointer. */ |
3145 | return sp; | |
3146 | } | |
3147 | ||
6d82d43b AC |
3148 | static enum return_value_convention |
3149 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
3150 | struct type *type, struct regcache *regcache, | |
47a35522 | 3151 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 3152 | { |
72a155b4 | 3153 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
3154 | |
3155 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
3156 | ||
3157 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
3158 | if needed), as appropriate for the type. Composite results (struct, | |
3159 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
3160 | following rules: | |
3161 | ||
3162 | * A struct with only one or two floating point fields is returned in $f0 | |
3163 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
3164 | case. | |
3165 | ||
3166 | * Any other struct or union results of at most 128 bits are returned in | |
3167 | $2 (first 64 bits) and $3 (remainder, if necessary). | |
3168 | ||
3169 | * Larger composite results are handled by converting the function to a | |
3170 | procedure with an implicit first parameter, which is a pointer to an area | |
3171 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
3172 | that all composite results be handled by conversion to implicit first | |
3173 | parameters. The MIPS/SGI Fortran implementation has always made a | |
3174 | specific exception to return COMPLEX results in the floating point | |
3175 | registers.] */ | |
3176 | ||
3177 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY | |
1a69e1e4 | 3178 | || TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 3179 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
3180 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3181 | && TYPE_LENGTH (type) == 16 | |
3182 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3183 | { | |
3184 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
3185 | two registers are used in the same as memory order, so the | |
3186 | eight bytes with the lower memory address are in $f0. */ | |
3187 | if (mips_debug) | |
3188 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 3189 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3190 | gdbarch_num_regs (gdbarch) |
3191 | + mips_regnum (gdbarch)->fp0, | |
3192 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3193 | readbuf, writebuf, 0); |
ba32f989 | 3194 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3195 | gdbarch_num_regs (gdbarch) |
3196 | + mips_regnum (gdbarch)->fp0 + 2, | |
3197 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3198 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
3199 | writebuf ? writebuf + 8 : writebuf, 0); |
3200 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3201 | } | |
6d82d43b AC |
3202 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3203 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3204 | { | |
59aa1faa | 3205 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
3206 | if (mips_debug) |
3207 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3208 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3209 | gdbarch_num_regs (gdbarch) |
3210 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3211 | TYPE_LENGTH (type), |
72a155b4 | 3212 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3213 | readbuf, writebuf, 0); |
6d82d43b AC |
3214 | return RETURN_VALUE_REGISTER_CONVENTION; |
3215 | } | |
3216 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3217 | && TYPE_NFIELDS (type) <= 2 | |
3218 | && TYPE_NFIELDS (type) >= 1 | |
3219 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 3220 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
3221 | == TYPE_CODE_FLT)) |
3222 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 3223 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 3224 | == TYPE_CODE_FLT) |
b18bb924 | 3225 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
6d82d43b AC |
3226 | == TYPE_CODE_FLT))) |
3227 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3228 | { | |
3229 | /* A struct that contains one or two floats. Each value is part | |
3230 | in the least significant part of their floating point | |
3231 | register.. */ | |
6d82d43b AC |
3232 | int regnum; |
3233 | int field; | |
72a155b4 | 3234 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
3235 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3236 | { | |
3237 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3238 | / TARGET_CHAR_BIT); | |
3239 | if (mips_debug) | |
3240 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3241 | offset); | |
ba32f989 DJ |
3242 | mips_xfer_register (gdbarch, regcache, |
3243 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 3244 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 3245 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3246 | readbuf, writebuf, offset); |
6d82d43b AC |
3247 | } |
3248 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3249 | } | |
3250 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3251 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3252 | { | |
3253 | /* A structure or union. Extract the left justified value, | |
3254 | regardless of the byte order. I.e. DO NOT USE | |
3255 | mips_xfer_lower. */ | |
3256 | int offset; | |
3257 | int regnum; | |
4c7d22cb | 3258 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3259 | offset < TYPE_LENGTH (type); |
72a155b4 | 3260 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3261 | { |
72a155b4 | 3262 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3263 | if (offset + xfer > TYPE_LENGTH (type)) |
3264 | xfer = TYPE_LENGTH (type) - offset; | |
3265 | if (mips_debug) | |
3266 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3267 | offset, xfer, regnum); | |
ba32f989 DJ |
3268 | mips_xfer_register (gdbarch, regcache, |
3269 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
3270 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
3271 | offset); | |
6d82d43b AC |
3272 | } |
3273 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3274 | } | |
3275 | else | |
3276 | { | |
3277 | /* A scalar extract each part but least-significant-byte | |
3278 | justified. */ | |
3279 | int offset; | |
3280 | int regnum; | |
4c7d22cb | 3281 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3282 | offset < TYPE_LENGTH (type); |
72a155b4 | 3283 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3284 | { |
72a155b4 | 3285 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3286 | if (offset + xfer > TYPE_LENGTH (type)) |
3287 | xfer = TYPE_LENGTH (type) - offset; | |
3288 | if (mips_debug) | |
3289 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3290 | offset, xfer, regnum); | |
ba32f989 DJ |
3291 | mips_xfer_register (gdbarch, regcache, |
3292 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 3293 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 3294 | readbuf, writebuf, offset); |
6d82d43b AC |
3295 | } |
3296 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3297 | } | |
3298 | } | |
3299 | ||
3300 | /* O32 ABI stuff. */ | |
3301 | ||
3302 | static CORE_ADDR | |
7d9b040b | 3303 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3304 | struct regcache *regcache, CORE_ADDR bp_addr, |
3305 | int nargs, struct value **args, CORE_ADDR sp, | |
3306 | int struct_return, CORE_ADDR struct_addr) | |
3307 | { | |
3308 | int argreg; | |
3309 | int float_argreg; | |
3310 | int argnum; | |
3311 | int len = 0; | |
3312 | int stack_offset = 0; | |
3313 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7d9b040b | 3314 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3315 | |
3316 | /* For shared libraries, "t9" needs to point at the function | |
3317 | address. */ | |
4c7d22cb | 3318 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3319 | |
3320 | /* Set the return address register to point to the entry point of | |
3321 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3322 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3323 | |
3324 | /* First ensure that the stack and structure return address (if any) | |
3325 | are properly aligned. The stack has to be at least 64-bit | |
3326 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3327 | aligned. For n32 and n64, stack frames need to be 128-bit |
3328 | aligned, so we round to this widest known alignment. */ | |
3329 | ||
5b03f266 AC |
3330 | sp = align_down (sp, 16); |
3331 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3332 | |
3333 | /* Now make space on the stack for the args. */ | |
3334 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3335 | { |
3336 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3337 | int arglen = TYPE_LENGTH (arg_type); | |
3338 | ||
3339 | /* Align to double-word if necessary. */ | |
2afd3f0a | 3340 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 3341 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 3342 | /* Allocate space on the stack. */ |
1a69e1e4 | 3343 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 3344 | } |
5b03f266 | 3345 | sp -= align_up (len, 16); |
ebafbe83 MS |
3346 | |
3347 | if (mips_debug) | |
6d82d43b | 3348 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3349 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3350 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3351 | |
3352 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3353 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3354 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 3355 | |
bcb0cc15 | 3356 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3357 | if (struct_return) |
3358 | { | |
3359 | if (mips_debug) | |
3360 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3361 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 | 3362 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 3363 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3364 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
3365 | } |
3366 | ||
3367 | /* Now load as many as possible of the first arguments into | |
3368 | registers, and push the rest onto the stack. Loop thru args | |
3369 | from first to last. */ | |
3370 | for (argnum = 0; argnum < nargs; argnum++) | |
3371 | { | |
47a35522 | 3372 | const gdb_byte *val; |
ebafbe83 | 3373 | struct value *arg = args[argnum]; |
4991999e | 3374 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3375 | int len = TYPE_LENGTH (arg_type); |
3376 | enum type_code typecode = TYPE_CODE (arg_type); | |
3377 | ||
3378 | if (mips_debug) | |
3379 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3380 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3381 | argnum + 1, len, (int) typecode); |
3382 | ||
47a35522 | 3383 | val = value_contents (arg); |
46cac009 AC |
3384 | |
3385 | /* 32-bit ABIs always start floating point arguments in an | |
3386 | even-numbered floating point register. Round the FP register | |
3387 | up before the check to see if there are any FP registers | |
3388 | left. O32/O64 targets also pass the FP in the integer | |
3389 | registers so also round up normal registers. */ | |
2afd3f0a | 3390 | if (fp_register_arg_p (typecode, arg_type)) |
46cac009 AC |
3391 | { |
3392 | if ((float_argreg & 1)) | |
3393 | float_argreg++; | |
3394 | } | |
3395 | ||
3396 | /* Floating point arguments passed in registers have to be | |
3397 | treated specially. On 32-bit architectures, doubles | |
3398 | are passed in register pairs; the even register gets | |
3399 | the low word, and the odd register gets the high word. | |
3400 | On O32/O64, the first two floating point arguments are | |
3401 | also copied to general registers, because MIPS16 functions | |
3402 | don't use float registers for arguments. This duplication of | |
3403 | arguments in general registers can't hurt non-MIPS16 functions | |
3404 | because those registers are normally skipped. */ | |
3405 | ||
3406 | if (fp_register_arg_p (typecode, arg_type) | |
3407 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3408 | { | |
8b07f6d8 | 3409 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 3410 | { |
72a155b4 | 3411 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 3412 | == BFD_ENDIAN_BIG ? 4 : 0; |
46cac009 AC |
3413 | unsigned long regval; |
3414 | ||
3415 | /* Write the low word of the double to the even register(s). */ | |
3416 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3417 | if (mips_debug) | |
3418 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3419 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3420 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3421 | if (mips_debug) |
3422 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3423 | argreg, phex (regval, 4)); | |
9c9acae0 | 3424 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3425 | |
3426 | /* Write the high word of the double to the odd register(s). */ | |
3427 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3428 | if (mips_debug) | |
3429 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3430 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3431 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3432 | |
3433 | if (mips_debug) | |
3434 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3435 | argreg, phex (regval, 4)); | |
9c9acae0 | 3436 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3437 | } |
3438 | else | |
3439 | { | |
3440 | /* This is a floating point value that fits entirely | |
3441 | in a single register. */ | |
3442 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3443 | above to ensure that it is even register aligned. */ |
46cac009 AC |
3444 | LONGEST regval = extract_unsigned_integer (val, len); |
3445 | if (mips_debug) | |
3446 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3447 | float_argreg, phex (regval, len)); | |
9c9acae0 | 3448 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 | 3449 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP |
6d82d43b AC |
3450 | registers for each argument. The below is (my |
3451 | guess) to ensure that the corresponding integer | |
3452 | register has reserved the same space. */ | |
46cac009 AC |
3453 | if (mips_debug) |
3454 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3455 | argreg, phex (regval, len)); | |
9c9acae0 | 3456 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 3457 | argreg += 2; |
46cac009 AC |
3458 | } |
3459 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 3460 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
3461 | } |
3462 | else | |
3463 | { | |
3464 | /* Copy the argument to general registers or the stack in | |
3465 | register-sized pieces. Large arguments are split between | |
3466 | registers and stack. */ | |
1a69e1e4 DJ |
3467 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
3468 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3469 | them in registers where gcc sometimes puts them on the |
3470 | stack. For maximum compatibility, we will put them in | |
3471 | both places. */ | |
1a69e1e4 DJ |
3472 | int odd_sized_struct = (len > MIPS32_REGSIZE |
3473 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
3474 | /* Structures should be aligned to eight bytes (even arg registers) |
3475 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 3476 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
3477 | { |
3478 | if ((argreg & 1)) | |
968b5391 MR |
3479 | { |
3480 | argreg++; | |
1a69e1e4 | 3481 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 3482 | } |
46cac009 | 3483 | } |
46cac009 AC |
3484 | while (len > 0) |
3485 | { | |
3486 | /* Remember if the argument was written to the stack. */ | |
3487 | int stack_used_p = 0; | |
1a69e1e4 | 3488 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
3489 | |
3490 | if (mips_debug) | |
3491 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3492 | partial_len); | |
3493 | ||
3494 | /* Write this portion of the argument to the stack. */ | |
3495 | if (argreg > MIPS_LAST_ARG_REGNUM | |
968b5391 | 3496 | || odd_sized_struct) |
46cac009 AC |
3497 | { |
3498 | /* Should shorter than int integer values be | |
3499 | promoted to int before being stored? */ | |
3500 | int longword_offset = 0; | |
3501 | CORE_ADDR addr; | |
3502 | stack_used_p = 1; | |
46cac009 AC |
3503 | |
3504 | if (mips_debug) | |
3505 | { | |
3506 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3507 | paddr_nz (stack_offset)); | |
3508 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3509 | paddr_nz (longword_offset)); | |
3510 | } | |
3511 | ||
3512 | addr = sp + stack_offset + longword_offset; | |
3513 | ||
3514 | if (mips_debug) | |
3515 | { | |
3516 | int i; | |
6d82d43b | 3517 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
46cac009 AC |
3518 | paddr_nz (addr)); |
3519 | for (i = 0; i < partial_len; i++) | |
3520 | { | |
6d82d43b | 3521 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3522 | val[i] & 0xff); |
3523 | } | |
3524 | } | |
3525 | write_memory (addr, val, partial_len); | |
3526 | } | |
3527 | ||
3528 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3529 | structs may go thru BOTH paths. */ |
46cac009 | 3530 | /* Write this portion of the argument to a general |
6d82d43b | 3531 | purpose register. */ |
968b5391 | 3532 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
46cac009 AC |
3533 | { |
3534 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3535 | /* Value may need to be sign extended, because |
1b13c4f6 | 3536 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3537 | |
3538 | /* A non-floating-point argument being passed in a | |
3539 | general register. If a struct or union, and if | |
3540 | the remaining length is smaller than the register | |
3541 | size, we have to adjust the register value on | |
3542 | big endian targets. | |
3543 | ||
3544 | It does not seem to be necessary to do the | |
3545 | same for integral types. | |
3546 | ||
3547 | Also don't do this adjustment on O64 binaries. | |
3548 | ||
3549 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3550 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
3551 | mips_abi_regsize(), generates a left shift |
3552 | as part of storing the argument in a register | |
3553 | (the left shift isn't generated when | |
1b13c4f6 | 3554 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3555 | it is quite possible that this is GCC |
3556 | contradicting the LE/O32 ABI, GDB has not been | |
3557 | adjusted to accommodate this. Either someone | |
3558 | needs to demonstrate that the LE/O32 ABI | |
3559 | specifies such a left shift OR this new ABI gets | |
3560 | identified as such and GDB gets tweaked | |
3561 | accordingly. */ | |
3562 | ||
72a155b4 | 3563 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3564 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
3565 | && (typecode == TYPE_CODE_STRUCT |
3566 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3567 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 3568 | * TARGET_CHAR_BIT); |
46cac009 AC |
3569 | |
3570 | if (mips_debug) | |
3571 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3572 | argreg, | |
1a69e1e4 | 3573 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 3574 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
3575 | argreg++; |
3576 | ||
3577 | /* Prevent subsequent floating point arguments from | |
3578 | being passed in floating point registers. */ | |
3579 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3580 | } | |
3581 | ||
3582 | len -= partial_len; | |
3583 | val += partial_len; | |
3584 | ||
3585 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3586 | will copy the next parameter. |
46cac009 | 3587 | |
6d82d43b AC |
3588 | In older ABIs, the caller reserved space for |
3589 | registers that contained arguments. This was loosely | |
3590 | refered to as their "home". Consequently, space is | |
3591 | always allocated. */ | |
46cac009 | 3592 | |
1a69e1e4 | 3593 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
3594 | } |
3595 | } | |
3596 | if (mips_debug) | |
3597 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3598 | } | |
3599 | ||
f10683bb | 3600 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3601 | |
46cac009 AC |
3602 | /* Return adjusted stack pointer. */ |
3603 | return sp; | |
3604 | } | |
3605 | ||
6d82d43b AC |
3606 | static enum return_value_convention |
3607 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
3608 | struct regcache *regcache, | |
47a35522 | 3609 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3610 | { |
72a155b4 | 3611 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6d82d43b AC |
3612 | |
3613 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3614 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3615 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3616 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3617 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3618 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3619 | { | |
3620 | /* A single-precision floating-point value. It fits in the | |
3621 | least significant part of FP0. */ | |
3622 | if (mips_debug) | |
3623 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3624 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3625 | gdbarch_num_regs (gdbarch) |
3626 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3627 | TYPE_LENGTH (type), |
72a155b4 | 3628 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3629 | readbuf, writebuf, 0); |
6d82d43b AC |
3630 | return RETURN_VALUE_REGISTER_CONVENTION; |
3631 | } | |
3632 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3633 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3634 | { | |
3635 | /* A double-precision floating-point value. The most | |
3636 | significant part goes in FP1, and the least significant in | |
3637 | FP0. */ | |
3638 | if (mips_debug) | |
3639 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
72a155b4 | 3640 | switch (gdbarch_byte_order (gdbarch)) |
6d82d43b AC |
3641 | { |
3642 | case BFD_ENDIAN_LITTLE: | |
ba32f989 | 3643 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3644 | gdbarch_num_regs (gdbarch) |
3645 | + mips_regnum (gdbarch)->fp0 + | |
3646 | 0, 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3647 | readbuf, writebuf, 0); |
ba32f989 | 3648 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3649 | gdbarch_num_regs (gdbarch) |
3650 | + mips_regnum (gdbarch)->fp0 + 1, | |
3651 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3652 | readbuf, writebuf, 4); |
6d82d43b AC |
3653 | break; |
3654 | case BFD_ENDIAN_BIG: | |
ba32f989 | 3655 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3656 | gdbarch_num_regs (gdbarch) |
3657 | + mips_regnum (gdbarch)->fp0 + 1, | |
3658 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3659 | readbuf, writebuf, 0); |
ba32f989 | 3660 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3661 | gdbarch_num_regs (gdbarch) |
3662 | + mips_regnum (gdbarch)->fp0 + 0, | |
3663 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3664 | readbuf, writebuf, 4); |
6d82d43b AC |
3665 | break; |
3666 | default: | |
e2e0b3e5 | 3667 | internal_error (__FILE__, __LINE__, _("bad switch")); |
6d82d43b AC |
3668 | } |
3669 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3670 | } | |
3671 | #if 0 | |
3672 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3673 | && TYPE_NFIELDS (type) <= 2 | |
3674 | && TYPE_NFIELDS (type) >= 1 | |
3675 | && ((TYPE_NFIELDS (type) == 1 | |
3676 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3677 | == TYPE_CODE_FLT)) | |
3678 | || (TYPE_NFIELDS (type) == 2 | |
3679 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3680 | == TYPE_CODE_FLT) | |
3681 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3682 | == TYPE_CODE_FLT))) | |
3683 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3684 | { | |
3685 | /* A struct that contains one or two floats. Each value is part | |
3686 | in the least significant part of their floating point | |
3687 | register.. */ | |
870cd05e | 3688 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
3689 | int regnum; |
3690 | int field; | |
72a155b4 | 3691 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
3692 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3693 | { | |
3694 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3695 | / TARGET_CHAR_BIT); | |
3696 | if (mips_debug) | |
3697 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3698 | offset); | |
ba32f989 DJ |
3699 | mips_xfer_register (gdbarch, regcache, |
3700 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 3701 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 3702 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3703 | readbuf, writebuf, offset); |
6d82d43b AC |
3704 | } |
3705 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3706 | } | |
3707 | #endif | |
3708 | #if 0 | |
3709 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3710 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3711 | { | |
3712 | /* A structure or union. Extract the left justified value, | |
3713 | regardless of the byte order. I.e. DO NOT USE | |
3714 | mips_xfer_lower. */ | |
3715 | int offset; | |
3716 | int regnum; | |
4c7d22cb | 3717 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3718 | offset < TYPE_LENGTH (type); |
72a155b4 | 3719 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3720 | { |
72a155b4 | 3721 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3722 | if (offset + xfer > TYPE_LENGTH (type)) |
3723 | xfer = TYPE_LENGTH (type) - offset; | |
3724 | if (mips_debug) | |
3725 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3726 | offset, xfer, regnum); | |
ba32f989 DJ |
3727 | mips_xfer_register (gdbarch, regcache, |
3728 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
3729 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
3730 | } | |
3731 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3732 | } | |
3733 | #endif | |
3734 | else | |
3735 | { | |
3736 | /* A scalar extract each part but least-significant-byte | |
3737 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 3738 | the ISA. */ |
6d82d43b AC |
3739 | int offset; |
3740 | int regnum; | |
4c7d22cb | 3741 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3742 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 3743 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 3744 | { |
1a69e1e4 | 3745 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
3746 | if (offset + xfer > TYPE_LENGTH (type)) |
3747 | xfer = TYPE_LENGTH (type) - offset; | |
3748 | if (mips_debug) | |
3749 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3750 | offset, xfer, regnum); | |
ba32f989 DJ |
3751 | mips_xfer_register (gdbarch, regcache, |
3752 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 3753 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3754 | readbuf, writebuf, offset); |
6d82d43b AC |
3755 | } |
3756 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3757 | } | |
3758 | } | |
3759 | ||
3760 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
3761 | ABI. */ | |
46cac009 AC |
3762 | |
3763 | static CORE_ADDR | |
7d9b040b | 3764 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3765 | struct regcache *regcache, CORE_ADDR bp_addr, |
3766 | int nargs, | |
3767 | struct value **args, CORE_ADDR sp, | |
3768 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
3769 | { |
3770 | int argreg; | |
3771 | int float_argreg; | |
3772 | int argnum; | |
3773 | int len = 0; | |
3774 | int stack_offset = 0; | |
480d3dd2 | 3775 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3776 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 3777 | |
25ab4790 AC |
3778 | /* For shared libraries, "t9" needs to point at the function |
3779 | address. */ | |
4c7d22cb | 3780 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3781 | |
3782 | /* Set the return address register to point to the entry point of | |
3783 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3784 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3785 | |
46cac009 AC |
3786 | /* First ensure that the stack and structure return address (if any) |
3787 | are properly aligned. The stack has to be at least 64-bit | |
3788 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3789 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3790 | aligned, so we round to this widest known alignment. */ | |
3791 | ||
5b03f266 AC |
3792 | sp = align_down (sp, 16); |
3793 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3794 | |
3795 | /* Now make space on the stack for the args. */ | |
3796 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3797 | { |
3798 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3799 | int arglen = TYPE_LENGTH (arg_type); | |
3800 | ||
968b5391 | 3801 | /* Allocate space on the stack. */ |
1a69e1e4 | 3802 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 3803 | } |
5b03f266 | 3804 | sp -= align_up (len, 16); |
46cac009 AC |
3805 | |
3806 | if (mips_debug) | |
6d82d43b | 3807 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3808 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
3809 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
3810 | |
3811 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3812 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3813 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
3814 | |
3815 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3816 | if (struct_return) | |
3817 | { | |
3818 | if (mips_debug) | |
3819 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3820 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 | 3821 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 3822 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3823 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
3824 | } |
3825 | ||
3826 | /* Now load as many as possible of the first arguments into | |
3827 | registers, and push the rest onto the stack. Loop thru args | |
3828 | from first to last. */ | |
3829 | for (argnum = 0; argnum < nargs; argnum++) | |
3830 | { | |
47a35522 | 3831 | const gdb_byte *val; |
46cac009 | 3832 | struct value *arg = args[argnum]; |
4991999e | 3833 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
3834 | int len = TYPE_LENGTH (arg_type); |
3835 | enum type_code typecode = TYPE_CODE (arg_type); | |
3836 | ||
3837 | if (mips_debug) | |
3838 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3839 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
3840 | argnum + 1, len, (int) typecode); |
3841 | ||
47a35522 | 3842 | val = value_contents (arg); |
ebafbe83 | 3843 | |
ebafbe83 MS |
3844 | /* Floating point arguments passed in registers have to be |
3845 | treated specially. On 32-bit architectures, doubles | |
3846 | are passed in register pairs; the even register gets | |
3847 | the low word, and the odd register gets the high word. | |
3848 | On O32/O64, the first two floating point arguments are | |
3849 | also copied to general registers, because MIPS16 functions | |
3850 | don't use float registers for arguments. This duplication of | |
3851 | arguments in general registers can't hurt non-MIPS16 functions | |
3852 | because those registers are normally skipped. */ | |
3853 | ||
3854 | if (fp_register_arg_p (typecode, arg_type) | |
3855 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3856 | { | |
2afd3f0a MR |
3857 | LONGEST regval = extract_unsigned_integer (val, len); |
3858 | if (mips_debug) | |
3859 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3860 | float_argreg, phex (regval, len)); | |
9c9acae0 | 3861 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
3862 | if (mips_debug) |
3863 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3864 | argreg, phex (regval, len)); | |
9c9acae0 | 3865 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 3866 | argreg++; |
ebafbe83 | 3867 | /* Reserve space for the FP register. */ |
1a69e1e4 | 3868 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
3869 | } |
3870 | else | |
3871 | { | |
3872 | /* Copy the argument to general registers or the stack in | |
3873 | register-sized pieces. Large arguments are split between | |
3874 | registers and stack. */ | |
1a69e1e4 | 3875 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
3876 | are treated specially: Irix cc passes them in registers |
3877 | where gcc sometimes puts them on the stack. For maximum | |
3878 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
3879 | int odd_sized_struct = (len > MIPS64_REGSIZE |
3880 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
3881 | while (len > 0) |
3882 | { | |
3883 | /* Remember if the argument was written to the stack. */ | |
3884 | int stack_used_p = 0; | |
1a69e1e4 | 3885 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
3886 | |
3887 | if (mips_debug) | |
3888 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3889 | partial_len); | |
3890 | ||
3891 | /* Write this portion of the argument to the stack. */ | |
3892 | if (argreg > MIPS_LAST_ARG_REGNUM | |
968b5391 | 3893 | || odd_sized_struct) |
ebafbe83 MS |
3894 | { |
3895 | /* Should shorter than int integer values be | |
3896 | promoted to int before being stored? */ | |
3897 | int longword_offset = 0; | |
3898 | CORE_ADDR addr; | |
3899 | stack_used_p = 1; | |
72a155b4 | 3900 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 3901 | { |
1a69e1e4 DJ |
3902 | if ((typecode == TYPE_CODE_INT |
3903 | || typecode == TYPE_CODE_PTR | |
3904 | || typecode == TYPE_CODE_FLT) | |
3905 | && len <= 4) | |
3906 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
3907 | } |
3908 | ||
3909 | if (mips_debug) | |
3910 | { | |
3911 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3912 | paddr_nz (stack_offset)); | |
3913 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3914 | paddr_nz (longword_offset)); | |
3915 | } | |
3916 | ||
3917 | addr = sp + stack_offset + longword_offset; | |
3918 | ||
3919 | if (mips_debug) | |
3920 | { | |
3921 | int i; | |
6d82d43b | 3922 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
ebafbe83 MS |
3923 | paddr_nz (addr)); |
3924 | for (i = 0; i < partial_len; i++) | |
3925 | { | |
6d82d43b | 3926 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
3927 | val[i] & 0xff); |
3928 | } | |
3929 | } | |
3930 | write_memory (addr, val, partial_len); | |
3931 | } | |
3932 | ||
3933 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3934 | structs may go thru BOTH paths. */ |
ebafbe83 | 3935 | /* Write this portion of the argument to a general |
6d82d43b | 3936 | purpose register. */ |
968b5391 | 3937 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
ebafbe83 MS |
3938 | { |
3939 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3940 | /* Value may need to be sign extended, because |
1b13c4f6 | 3941 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
3942 | |
3943 | /* A non-floating-point argument being passed in a | |
3944 | general register. If a struct or union, and if | |
3945 | the remaining length is smaller than the register | |
3946 | size, we have to adjust the register value on | |
3947 | big endian targets. | |
3948 | ||
3949 | It does not seem to be necessary to do the | |
401835eb | 3950 | same for integral types. */ |
480d3dd2 | 3951 | |
72a155b4 | 3952 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3953 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3954 | && (typecode == TYPE_CODE_STRUCT |
3955 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3956 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3957 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
3958 | |
3959 | if (mips_debug) | |
3960 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3961 | argreg, | |
1a69e1e4 | 3962 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3963 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
3964 | argreg++; |
3965 | ||
3966 | /* Prevent subsequent floating point arguments from | |
3967 | being passed in floating point registers. */ | |
3968 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3969 | } | |
3970 | ||
3971 | len -= partial_len; | |
3972 | val += partial_len; | |
3973 | ||
3974 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3975 | will copy the next parameter. |
ebafbe83 | 3976 | |
6d82d43b AC |
3977 | In older ABIs, the caller reserved space for |
3978 | registers that contained arguments. This was loosely | |
3979 | refered to as their "home". Consequently, space is | |
3980 | always allocated. */ | |
ebafbe83 | 3981 | |
1a69e1e4 | 3982 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
3983 | } |
3984 | } | |
3985 | if (mips_debug) | |
3986 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3987 | } | |
3988 | ||
f10683bb | 3989 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3990 | |
ebafbe83 MS |
3991 | /* Return adjusted stack pointer. */ |
3992 | return sp; | |
3993 | } | |
3994 | ||
9c8fdbfa AC |
3995 | static enum return_value_convention |
3996 | mips_o64_return_value (struct gdbarch *gdbarch, | |
3997 | struct type *type, struct regcache *regcache, | |
47a35522 | 3998 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3999 | { |
72a155b4 | 4000 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a076fd2 FF |
4001 | |
4002 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4003 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4004 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4005 | return RETURN_VALUE_STRUCT_CONVENTION; | |
4006 | else if (fp_register_arg_p (TYPE_CODE (type), type)) | |
4007 | { | |
4008 | /* A floating-point value. It fits in the least significant | |
4009 | part of FP0. */ | |
4010 | if (mips_debug) | |
4011 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 4012 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4013 | gdbarch_num_regs (gdbarch) |
4014 | + mips_regnum (gdbarch)->fp0, | |
7a076fd2 | 4015 | TYPE_LENGTH (type), |
72a155b4 | 4016 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4017 | readbuf, writebuf, 0); |
7a076fd2 FF |
4018 | return RETURN_VALUE_REGISTER_CONVENTION; |
4019 | } | |
4020 | else | |
4021 | { | |
4022 | /* A scalar extract each part but least-significant-byte | |
4023 | justified. */ | |
4024 | int offset; | |
4025 | int regnum; | |
4026 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
4027 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 4028 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 4029 | { |
1a69e1e4 | 4030 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
4031 | if (offset + xfer > TYPE_LENGTH (type)) |
4032 | xfer = TYPE_LENGTH (type) - offset; | |
4033 | if (mips_debug) | |
4034 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4035 | offset, xfer, regnum); | |
ba32f989 DJ |
4036 | mips_xfer_register (gdbarch, regcache, |
4037 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 4038 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4039 | readbuf, writebuf, offset); |
7a076fd2 FF |
4040 | } |
4041 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4042 | } | |
6d82d43b AC |
4043 | } |
4044 | ||
dd824b04 DJ |
4045 | /* Floating point register management. |
4046 | ||
4047 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4048 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4049 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4050 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4051 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4052 | double precision floats into two 32-bit chunks and store them in | |
4053 | consecutive fp regs. To display 64-bit floats stored in this | |
4054 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4055 | Throw in user-configurable endianness and you have a real mess. | |
4056 | ||
4057 | The way this works is: | |
4058 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4059 | double-precision value will be split across two logical registers. | |
4060 | The lower-numbered logical register will hold the low-order bits, | |
4061 | regardless of the processor's endianness. | |
4062 | - If we are on a 64-bit processor, and we are looking for a | |
4063 | single-precision value, it will be in the low ordered bits | |
4064 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4065 | save slot in memory. | |
4066 | - If we are in 64-bit mode, everything is straightforward. | |
4067 | ||
4068 | Note that this code only deals with "live" registers at the top of the | |
4069 | stack. We will attempt to deal with saved registers later, when | |
4070 | the raw/cooked register interface is in place. (We need a general | |
4071 | interface that can deal with dynamic saved register sizes -- fp | |
4072 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4073 | and below). */ | |
4074 | ||
67b2c998 DJ |
4075 | static struct type * |
4076 | mips_float_register_type (void) | |
4077 | { | |
8da61cc4 | 4078 | return builtin_type_ieee_single; |
67b2c998 DJ |
4079 | } |
4080 | ||
4081 | static struct type * | |
4082 | mips_double_register_type (void) | |
4083 | { | |
8da61cc4 | 4084 | return builtin_type_ieee_double; |
67b2c998 DJ |
4085 | } |
4086 | ||
dd824b04 DJ |
4087 | /* Copy a 32-bit single-precision value from the current frame |
4088 | into rare_buffer. */ | |
4089 | ||
4090 | static void | |
e11c53d2 | 4091 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 4092 | gdb_byte *rare_buffer) |
dd824b04 | 4093 | { |
72a155b4 UW |
4094 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4095 | int raw_size = register_size (gdbarch, regno); | |
47a35522 | 4096 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 4097 | |
e11c53d2 | 4098 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 4099 | error (_("can't read register %d (%s)"), |
72a155b4 | 4100 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4101 | if (raw_size == 8) |
4102 | { | |
4103 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4104 | 32 bits. */ |
dd824b04 DJ |
4105 | int offset; |
4106 | ||
72a155b4 | 4107 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
4108 | offset = 4; |
4109 | else | |
4110 | offset = 0; | |
4111 | ||
4112 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4113 | } | |
4114 | else | |
4115 | { | |
4116 | memcpy (rare_buffer, raw_buffer, 4); | |
4117 | } | |
4118 | } | |
4119 | ||
4120 | /* Copy a 64-bit double-precision value from the current frame into | |
4121 | rare_buffer. This may include getting half of it from the next | |
4122 | register. */ | |
4123 | ||
4124 | static void | |
e11c53d2 | 4125 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 4126 | gdb_byte *rare_buffer) |
dd824b04 | 4127 | { |
72a155b4 UW |
4128 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4129 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 4130 | |
9c9acae0 | 4131 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
4132 | { |
4133 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4134 | all 64 bits. */ |
e11c53d2 | 4135 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 4136 | error (_("can't read register %d (%s)"), |
72a155b4 | 4137 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4138 | } |
4139 | else | |
4140 | { | |
72a155b4 | 4141 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 4142 | |
72a155b4 | 4143 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 4144 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
4145 | _("mips_read_fp_register_double: bad access to " |
4146 | "odd-numbered FP register")); | |
dd824b04 DJ |
4147 | |
4148 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4149 | each register. */ |
72a155b4 | 4150 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 4151 | { |
e11c53d2 AC |
4152 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4153 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4154 | } |
361d1df0 | 4155 | else |
dd824b04 | 4156 | { |
e11c53d2 AC |
4157 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4158 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4159 | } |
4160 | } | |
4161 | } | |
4162 | ||
c906108c | 4163 | static void |
e11c53d2 AC |
4164 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4165 | int regnum) | |
c5aa993b | 4166 | { /* do values for FP (float) regs */ |
72a155b4 | 4167 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4168 | gdb_byte *raw_buffer; |
3903d437 AC |
4169 | double doub, flt1; /* doubles extracted from raw hex data */ |
4170 | int inv1, inv2; | |
c5aa993b | 4171 | |
72a155b4 | 4172 | raw_buffer = alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0)); |
c906108c | 4173 | |
72a155b4 | 4174 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 4175 | fprintf_filtered (file, "%*s", |
72a155b4 | 4176 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 4177 | ""); |
f0ef6b29 | 4178 | |
72a155b4 | 4179 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 4180 | { |
f0ef6b29 KB |
4181 | /* 4-byte registers: Print hex and floating. Also print even |
4182 | numbered registers as doubles. */ | |
e11c53d2 | 4183 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4184 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4185 | |
6d82d43b AC |
4186 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', |
4187 | file); | |
dd824b04 | 4188 | |
e11c53d2 | 4189 | fprintf_filtered (file, " flt: "); |
1adad886 | 4190 | if (inv1) |
e11c53d2 | 4191 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4192 | else |
e11c53d2 | 4193 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4194 | |
72a155b4 | 4195 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 4196 | { |
e11c53d2 | 4197 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 | 4198 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
6d82d43b | 4199 | &inv2); |
1adad886 | 4200 | |
e11c53d2 | 4201 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4202 | if (inv2) |
e11c53d2 | 4203 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4204 | else |
e11c53d2 | 4205 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4206 | } |
c906108c SS |
4207 | } |
4208 | else | |
dd824b04 | 4209 | { |
f0ef6b29 | 4210 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4211 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4212 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4213 | |
e11c53d2 | 4214 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4215 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4216 | ||
361d1df0 | 4217 | |
6d82d43b AC |
4218 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', |
4219 | file); | |
f0ef6b29 | 4220 | |
e11c53d2 | 4221 | fprintf_filtered (file, " flt: "); |
1adad886 | 4222 | if (inv1) |
e11c53d2 | 4223 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4224 | else |
e11c53d2 | 4225 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4226 | |
e11c53d2 | 4227 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4228 | if (inv2) |
e11c53d2 | 4229 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4230 | else |
e11c53d2 | 4231 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4232 | } |
4233 | } | |
4234 | ||
4235 | static void | |
e11c53d2 | 4236 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 4237 | int regnum) |
f0ef6b29 | 4238 | { |
a4b8ebc8 | 4239 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4240 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4241 | int offset; |
1adad886 | 4242 | |
7b9ee6a8 | 4243 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4244 | { |
e11c53d2 | 4245 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4246 | return; |
4247 | } | |
4248 | ||
4249 | /* Get the data in raw format. */ | |
e11c53d2 | 4250 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4251 | { |
c9f4d572 | 4252 | fprintf_filtered (file, "%s: [Invalid]", |
72a155b4 | 4253 | gdbarch_register_name (gdbarch, regnum)); |
f0ef6b29 | 4254 | return; |
c906108c | 4255 | } |
f0ef6b29 | 4256 | |
72a155b4 | 4257 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
4258 | |
4259 | /* The problem with printing numeric register names (r26, etc.) is that | |
4260 | the user can't use them on input. Probably the best solution is to | |
4261 | fix it so that either the numeric or the funky (a2, etc.) names | |
4262 | are accepted on input. */ | |
4263 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4264 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4265 | else |
e11c53d2 | 4266 | fprintf_filtered (file, ": "); |
f0ef6b29 | 4267 | |
72a155b4 | 4268 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4269 | offset = |
72a155b4 | 4270 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
f0ef6b29 KB |
4271 | else |
4272 | offset = 0; | |
4273 | ||
6d82d43b | 4274 | print_scalar_formatted (raw_buffer + offset, |
7b9ee6a8 | 4275 | register_type (gdbarch, regnum), 'x', 0, |
6d82d43b | 4276 | file); |
c906108c SS |
4277 | } |
4278 | ||
f0ef6b29 KB |
4279 | /* Replacement for generic do_registers_info. |
4280 | Print regs in pretty columns. */ | |
4281 | ||
4282 | static int | |
e11c53d2 AC |
4283 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4284 | int regnum) | |
f0ef6b29 | 4285 | { |
e11c53d2 AC |
4286 | fprintf_filtered (file, " "); |
4287 | mips_print_fp_register (file, frame, regnum); | |
4288 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4289 | return regnum + 1; |
4290 | } | |
4291 | ||
4292 | ||
c906108c SS |
4293 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4294 | ||
4295 | static int | |
e11c53d2 | 4296 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4297 | int start_regnum) |
c906108c | 4298 | { |
a4b8ebc8 | 4299 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4300 | /* do values for GP (int) regs */ |
47a35522 | 4301 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 4302 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4303 | int col, byte; |
a4b8ebc8 | 4304 | int regnum; |
c906108c SS |
4305 | |
4306 | /* For GP registers, we print a separate row of names above the vals */ | |
a4b8ebc8 | 4307 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4308 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4309 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4310 | regnum++) |
c906108c | 4311 | { |
72a155b4 | 4312 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4313 | continue; /* unused register */ |
7b9ee6a8 | 4314 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4315 | TYPE_CODE_FLT) |
c5aa993b | 4316 | break; /* end the row: reached FP register */ |
0cc93a06 | 4317 | /* Large registers are handled separately. */ |
72a155b4 | 4318 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4319 | { |
4320 | if (col > 0) | |
4321 | break; /* End the row before this register. */ | |
4322 | ||
4323 | /* Print this register on a row by itself. */ | |
4324 | mips_print_register (file, frame, regnum); | |
4325 | fprintf_filtered (file, "\n"); | |
4326 | return regnum + 1; | |
4327 | } | |
d05f6826 DJ |
4328 | if (col == 0) |
4329 | fprintf_filtered (file, " "); | |
6d82d43b | 4330 | fprintf_filtered (file, |
72a155b4 UW |
4331 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
4332 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
4333 | col++; |
4334 | } | |
d05f6826 DJ |
4335 | |
4336 | if (col == 0) | |
4337 | return regnum; | |
4338 | ||
a4b8ebc8 | 4339 | /* print the R0 to R31 names */ |
72a155b4 | 4340 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 4341 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 4342 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
4343 | else |
4344 | fprintf_filtered (file, "\n "); | |
c906108c | 4345 | |
c906108c | 4346 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4347 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4348 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4349 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4350 | regnum++) |
c906108c | 4351 | { |
72a155b4 | 4352 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4353 | continue; /* unused register */ |
7b9ee6a8 | 4354 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4355 | TYPE_CODE_FLT) |
c5aa993b | 4356 | break; /* end row: reached FP register */ |
72a155b4 | 4357 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4358 | break; /* End row: large register. */ |
4359 | ||
c906108c | 4360 | /* OK: get the data in raw format. */ |
e11c53d2 | 4361 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 | 4362 | error (_("can't read register %d (%s)"), |
72a155b4 | 4363 | regnum, gdbarch_register_name (gdbarch, regnum)); |
c906108c | 4364 | /* pad small registers */ |
4246e332 | 4365 | for (byte = 0; |
72a155b4 UW |
4366 | byte < (mips_abi_regsize (gdbarch) |
4367 | - register_size (gdbarch, regnum)); byte++) | |
c906108c SS |
4368 | printf_filtered (" "); |
4369 | /* Now print the register value in hex, endian order. */ | |
72a155b4 | 4370 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4371 | for (byte = |
72a155b4 UW |
4372 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
4373 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 4374 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 4375 | else |
72a155b4 | 4376 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 4377 | byte >= 0; byte--) |
47a35522 | 4378 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 4379 | fprintf_filtered (file, " "); |
c906108c SS |
4380 | col++; |
4381 | } | |
c5aa993b | 4382 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4383 | fprintf_filtered (file, "\n"); |
c906108c SS |
4384 | |
4385 | return regnum; | |
4386 | } | |
4387 | ||
4388 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4389 | ||
bf1f5b4c | 4390 | static void |
e11c53d2 AC |
4391 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4392 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4393 | { |
c5aa993b | 4394 | if (regnum != -1) /* do one specified register */ |
c906108c | 4395 | { |
72a155b4 UW |
4396 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
4397 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 4398 | error (_("Not a valid register for the current processor type")); |
c906108c | 4399 | |
0cc93a06 | 4400 | mips_print_register (file, frame, regnum); |
e11c53d2 | 4401 | fprintf_filtered (file, "\n"); |
c906108c | 4402 | } |
c5aa993b JM |
4403 | else |
4404 | /* do all (or most) registers */ | |
c906108c | 4405 | { |
72a155b4 UW |
4406 | regnum = gdbarch_num_regs (gdbarch); |
4407 | while (regnum < gdbarch_num_regs (gdbarch) | |
4408 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 4409 | { |
7b9ee6a8 | 4410 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4411 | TYPE_CODE_FLT) |
e11c53d2 AC |
4412 | { |
4413 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4414 | regnum = print_fp_register_row (file, frame, regnum); | |
4415 | else | |
4416 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4417 | } | |
c906108c | 4418 | else |
e11c53d2 | 4419 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4420 | } |
4421 | } | |
4422 | } | |
4423 | ||
c906108c SS |
4424 | /* Is this a branch with a delay slot? */ |
4425 | ||
c906108c | 4426 | static int |
acdb74a0 | 4427 | is_delayed (unsigned long insn) |
c906108c SS |
4428 | { |
4429 | int i; | |
4430 | for (i = 0; i < NUMOPCODES; ++i) | |
4431 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4432 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4433 | break; | |
4434 | return (i < NUMOPCODES | |
4435 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4436 | | INSN_COND_BRANCH_DELAY | |
4437 | | INSN_COND_BRANCH_LIKELY))); | |
4438 | } | |
4439 | ||
4440 | int | |
3352ef37 AC |
4441 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
4442 | struct frame_info *frame) | |
c906108c | 4443 | { |
3352ef37 | 4444 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 4445 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
4446 | |
4447 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4448 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4449 | return 0; |
4450 | ||
06648491 MK |
4451 | if (!breakpoint_here_p (pc + 4)) |
4452 | return 0; | |
4453 | ||
3352ef37 AC |
4454 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
4455 | /* If error reading memory, guess that it is not a delayed | |
4456 | branch. */ | |
c906108c | 4457 | return 0; |
4c7d22cb | 4458 | return is_delayed (extract_unsigned_integer (buf, sizeof buf)); |
c906108c SS |
4459 | } |
4460 | ||
6d82d43b AC |
4461 | /* To skip prologues, I use this predicate. Returns either PC itself |
4462 | if the code at PC does not look like a function prologue; otherwise | |
4463 | returns an address that (if we're lucky) follows the prologue. If | |
4464 | LENIENT, then we must skip everything which is involved in setting | |
4465 | up the frame (it's OK to skip more, just so long as we don't skip | |
4466 | anything which might clobber the registers which are being saved. | |
4467 | We must skip more in the case where part of the prologue is in the | |
4468 | delay slot of a non-prologue instruction). */ | |
4469 | ||
4470 | static CORE_ADDR | |
4471 | mips_skip_prologue (CORE_ADDR pc) | |
4472 | { | |
8b622e6a AC |
4473 | CORE_ADDR limit_pc; |
4474 | CORE_ADDR func_addr; | |
4475 | ||
6d82d43b AC |
4476 | /* See if we can determine the end of the prologue via the symbol table. |
4477 | If so, then return either PC, or the PC after the prologue, whichever | |
4478 | is greater. */ | |
8b622e6a AC |
4479 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4480 | { | |
4481 | CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr); | |
4482 | if (post_prologue_pc != 0) | |
4483 | return max (pc, post_prologue_pc); | |
4484 | } | |
6d82d43b AC |
4485 | |
4486 | /* Can't determine prologue from the symbol table, need to examine | |
4487 | instructions. */ | |
4488 | ||
98b4dd94 JB |
4489 | /* Find an upper limit on the function prologue using the debug |
4490 | information. If the debug information could not be used to provide | |
4491 | that bound, then use an arbitrary large number as the upper bound. */ | |
4492 | limit_pc = skip_prologue_using_sal (pc); | |
4493 | if (limit_pc == 0) | |
4494 | limit_pc = pc + 100; /* Magic. */ | |
4495 | ||
0fe7e7c8 | 4496 | if (mips_pc_is_mips16 (pc)) |
a65bbe44 | 4497 | return mips16_scan_prologue (pc, limit_pc, NULL, NULL); |
6d82d43b | 4498 | else |
a65bbe44 | 4499 | return mips32_scan_prologue (pc, limit_pc, NULL, NULL); |
88658117 AC |
4500 | } |
4501 | ||
97ab0fdd MR |
4502 | /* Check whether the PC is in a function epilogue (32-bit version). |
4503 | This is a helper function for mips_in_function_epilogue_p. */ | |
4504 | static int | |
4505 | mips32_in_function_epilogue_p (CORE_ADDR pc) | |
4506 | { | |
4507 | CORE_ADDR func_addr = 0, func_end = 0; | |
4508 | ||
4509 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4510 | { | |
4511 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4512 | CORE_ADDR addr = func_end - 12; | |
4513 | ||
4514 | if (addr < func_addr + 4) | |
4515 | addr = func_addr + 4; | |
4516 | if (pc < addr) | |
4517 | return 0; | |
4518 | ||
4519 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
4520 | { | |
4521 | unsigned long high_word; | |
4522 | unsigned long inst; | |
4523 | ||
4524 | inst = mips_fetch_instruction (pc); | |
4525 | high_word = (inst >> 16) & 0xffff; | |
4526 | ||
4527 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
4528 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
4529 | && inst != 0x03e00008 /* jr $ra */ | |
4530 | && inst != 0x00000000) /* nop */ | |
4531 | return 0; | |
4532 | } | |
4533 | ||
4534 | return 1; | |
4535 | } | |
4536 | ||
4537 | return 0; | |
4538 | } | |
4539 | ||
4540 | /* Check whether the PC is in a function epilogue (16-bit version). | |
4541 | This is a helper function for mips_in_function_epilogue_p. */ | |
4542 | static int | |
4543 | mips16_in_function_epilogue_p (CORE_ADDR pc) | |
4544 | { | |
4545 | CORE_ADDR func_addr = 0, func_end = 0; | |
4546 | ||
4547 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4548 | { | |
4549 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4550 | CORE_ADDR addr = func_end - 12; | |
4551 | ||
4552 | if (addr < func_addr + 4) | |
4553 | addr = func_addr + 4; | |
4554 | if (pc < addr) | |
4555 | return 0; | |
4556 | ||
4557 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
4558 | { | |
4559 | unsigned short inst; | |
4560 | ||
4561 | inst = mips_fetch_instruction (pc); | |
4562 | ||
4563 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
4564 | continue; | |
4565 | ||
4566 | if (inst != 0x6300 /* addiu $sp,offset */ | |
4567 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
4568 | && inst != 0xe820 /* jr $ra */ | |
4569 | && inst != 0xe8a0 /* jrc $ra */ | |
4570 | && inst != 0x6500) /* nop */ | |
4571 | return 0; | |
4572 | } | |
4573 | ||
4574 | return 1; | |
4575 | } | |
4576 | ||
4577 | return 0; | |
4578 | } | |
4579 | ||
4580 | /* The epilogue is defined here as the area at the end of a function, | |
4581 | after an instruction which destroys the function's stack frame. */ | |
4582 | static int | |
4583 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
4584 | { | |
4585 | if (mips_pc_is_mips16 (pc)) | |
4586 | return mips16_in_function_epilogue_p (pc); | |
4587 | else | |
4588 | return mips32_in_function_epilogue_p (pc); | |
4589 | } | |
4590 | ||
a5ea2558 AC |
4591 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4592 | used for all MIPS-specific commands. */ | |
4593 | ||
a5ea2558 | 4594 | static void |
acdb74a0 | 4595 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4596 | { |
4597 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4598 | } | |
4599 | ||
a5ea2558 | 4600 | static void |
acdb74a0 | 4601 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 4602 | { |
6d82d43b AC |
4603 | printf_unfiltered |
4604 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
4605 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
4606 | } | |
4607 | ||
c906108c SS |
4608 | /* Commands to show/set the MIPS FPU type. */ |
4609 | ||
c906108c | 4610 | static void |
acdb74a0 | 4611 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4612 | { |
c906108c SS |
4613 | char *fpu; |
4614 | switch (MIPS_FPU_TYPE) | |
4615 | { | |
4616 | case MIPS_FPU_SINGLE: | |
4617 | fpu = "single-precision"; | |
4618 | break; | |
4619 | case MIPS_FPU_DOUBLE: | |
4620 | fpu = "double-precision"; | |
4621 | break; | |
4622 | case MIPS_FPU_NONE: | |
4623 | fpu = "absent (none)"; | |
4624 | break; | |
93d56215 | 4625 | default: |
e2e0b3e5 | 4626 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
4627 | } |
4628 | if (mips_fpu_type_auto) | |
6d82d43b AC |
4629 | printf_unfiltered |
4630 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4631 | fpu); | |
c906108c | 4632 | else |
6d82d43b AC |
4633 | printf_unfiltered |
4634 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
4635 | } |
4636 | ||
4637 | ||
c906108c | 4638 | static void |
acdb74a0 | 4639 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 4640 | { |
6d82d43b AC |
4641 | printf_unfiltered |
4642 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
4643 | show_mipsfpu_command (args, from_tty); |
4644 | } | |
4645 | ||
c906108c | 4646 | static void |
acdb74a0 | 4647 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 4648 | { |
8d5838b5 AC |
4649 | struct gdbarch_info info; |
4650 | gdbarch_info_init (&info); | |
c906108c SS |
4651 | mips_fpu_type = MIPS_FPU_SINGLE; |
4652 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4653 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4654 | instead of relying on globals. Doing that would let generic code | |
4655 | handle the search for this specific architecture. */ | |
4656 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4657 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4658 | } |
4659 | ||
c906108c | 4660 | static void |
acdb74a0 | 4661 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 4662 | { |
8d5838b5 AC |
4663 | struct gdbarch_info info; |
4664 | gdbarch_info_init (&info); | |
c906108c SS |
4665 | mips_fpu_type = MIPS_FPU_DOUBLE; |
4666 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4667 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4668 | instead of relying on globals. Doing that would let generic code | |
4669 | handle the search for this specific architecture. */ | |
4670 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4671 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4672 | } |
4673 | ||
c906108c | 4674 | static void |
acdb74a0 | 4675 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 4676 | { |
8d5838b5 AC |
4677 | struct gdbarch_info info; |
4678 | gdbarch_info_init (&info); | |
c906108c SS |
4679 | mips_fpu_type = MIPS_FPU_NONE; |
4680 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4681 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4682 | instead of relying on globals. Doing that would let generic code | |
4683 | handle the search for this specific architecture. */ | |
4684 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4685 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4686 | } |
4687 | ||
c906108c | 4688 | static void |
acdb74a0 | 4689 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
4690 | { |
4691 | mips_fpu_type_auto = 1; | |
4692 | } | |
4693 | ||
c906108c | 4694 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
4695 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
4696 | the relevant processor still exists (it dates back to '94) and | |
4697 | secondly this is not the way to do this. The processor type should | |
4698 | be set by forcing an architecture change. */ | |
c906108c | 4699 | |
691c0433 AC |
4700 | void |
4701 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 4702 | { |
691c0433 | 4703 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
a9614958 | 4704 | ULONGEST prid; |
c906108c | 4705 | |
594f7785 | 4706 | regcache_cooked_read_unsigned (get_current_regcache (), |
a9614958 | 4707 | MIPS_PRID_REGNUM, &prid); |
c906108c | 4708 | if ((prid & ~0xf) == 0x700) |
691c0433 | 4709 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
4710 | } |
4711 | ||
4712 | /* Just like reinit_frame_cache, but with the right arguments to be | |
4713 | callable as an sfunc. */ | |
4714 | ||
4715 | static void | |
acdb74a0 AC |
4716 | reinit_frame_cache_sfunc (char *args, int from_tty, |
4717 | struct cmd_list_element *c) | |
c906108c SS |
4718 | { |
4719 | reinit_frame_cache (); | |
4720 | } | |
4721 | ||
a89aa300 AC |
4722 | static int |
4723 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 4724 | { |
e5ab0dce | 4725 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 4726 | |
d31431ed AC |
4727 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
4728 | disassembler needs to be able to locally determine the ISA, and | |
4729 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
4730 | work. */ | |
ec4045ea AC |
4731 | if (mips_pc_is_mips16 (memaddr)) |
4732 | info->mach = bfd_mach_mips16; | |
c906108c SS |
4733 | |
4734 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 4735 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 4736 | |
e5ab0dce | 4737 | /* Set the disassembler options. */ |
6d82d43b | 4738 | if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64) |
e5ab0dce AC |
4739 | { |
4740 | /* Set up the disassembler info, so that we get the right | |
6d82d43b | 4741 | register names from libopcodes. */ |
e5ab0dce AC |
4742 | if (tdep->mips_abi == MIPS_ABI_N32) |
4743 | info->disassembler_options = "gpr-names=n32"; | |
4744 | else | |
4745 | info->disassembler_options = "gpr-names=64"; | |
4746 | info->flavour = bfd_target_elf_flavour; | |
4747 | } | |
4748 | else | |
4749 | /* This string is not recognized explicitly by the disassembler, | |
4750 | but it tells the disassembler to not try to guess the ABI from | |
4751 | the bfd elf headers, such that, if the user overrides the ABI | |
4752 | of a program linked as NewABI, the disassembly will follow the | |
4753 | register naming conventions specified by the user. */ | |
4754 | info->disassembler_options = "gpr-names=32"; | |
4755 | ||
c906108c | 4756 | /* Call the appropriate disassembler based on the target endian-ness. */ |
4c6b5505 | 4757 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
c906108c SS |
4758 | return print_insn_big_mips (memaddr, info); |
4759 | else | |
4760 | return print_insn_little_mips (memaddr, info); | |
4761 | } | |
4762 | ||
3b3b875c UW |
4763 | /* This function implements gdbarch_breakpoint_from_pc. It uses the program |
4764 | counter value to determine whether a 16- or 32-bit breakpoint should be used. | |
4765 | It returns a pointer to a string of bytes that encode a breakpoint | |
4766 | instruction, stores the length of the string to *lenptr, and adjusts pc (if | |
4767 | necessary) to point to the actual memory location where the breakpoint | |
4768 | should be inserted. */ | |
c906108c | 4769 | |
47a35522 | 4770 | static const gdb_byte * |
67d57894 | 4771 | mips_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) |
c906108c | 4772 | { |
67d57894 | 4773 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 4774 | { |
0fe7e7c8 | 4775 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4776 | { |
47a35522 | 4777 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 4778 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4779 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
4780 | return mips16_big_breakpoint; |
4781 | } | |
4782 | else | |
4783 | { | |
aaab4dba AC |
4784 | /* The IDT board uses an unusual breakpoint value, and |
4785 | sometimes gets confused when it sees the usual MIPS | |
4786 | breakpoint instruction. */ | |
47a35522 MK |
4787 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
4788 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
4789 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 4790 | |
c5aa993b | 4791 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
4792 | |
4793 | if (strcmp (target_shortname, "mips") == 0) | |
4794 | return idt_big_breakpoint; | |
4795 | else if (strcmp (target_shortname, "ddb") == 0 | |
4796 | || strcmp (target_shortname, "pmon") == 0 | |
4797 | || strcmp (target_shortname, "lsi") == 0) | |
4798 | return pmon_big_breakpoint; | |
4799 | else | |
4800 | return big_breakpoint; | |
4801 | } | |
4802 | } | |
4803 | else | |
4804 | { | |
0fe7e7c8 | 4805 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4806 | { |
47a35522 | 4807 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 4808 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4809 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
4810 | return mips16_little_breakpoint; |
4811 | } | |
4812 | else | |
4813 | { | |
47a35522 MK |
4814 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
4815 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
4816 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 4817 | |
c5aa993b | 4818 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
4819 | |
4820 | if (strcmp (target_shortname, "mips") == 0) | |
4821 | return idt_little_breakpoint; | |
4822 | else if (strcmp (target_shortname, "ddb") == 0 | |
4823 | || strcmp (target_shortname, "pmon") == 0 | |
4824 | || strcmp (target_shortname, "lsi") == 0) | |
4825 | return pmon_little_breakpoint; | |
4826 | else | |
4827 | return little_breakpoint; | |
4828 | } | |
4829 | } | |
4830 | } | |
4831 | ||
4832 | /* If PC is in a mips16 call or return stub, return the address of the target | |
4833 | PC, which is either the callee or the caller. There are several | |
4834 | cases which must be handled: | |
4835 | ||
4836 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 4837 | target PC is in $31 ($ra). |
c906108c | 4838 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 4839 | and the target PC is in $2. |
c906108c | 4840 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
4841 | before the jal instruction, this is effectively a call stub |
4842 | and the the target PC is in $2. Otherwise this is effectively | |
4843 | a return stub and the target PC is in $18. | |
c906108c SS |
4844 | |
4845 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 4846 | gory details. */ |
c906108c | 4847 | |
757a7cc6 | 4848 | static CORE_ADDR |
52f729a7 | 4849 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c SS |
4850 | { |
4851 | char *name; | |
4852 | CORE_ADDR start_addr; | |
4853 | ||
4854 | /* Find the starting address and name of the function containing the PC. */ | |
4855 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
4856 | return 0; | |
4857 | ||
4858 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
4859 | target PC is in $31 ($ra). */ | |
4860 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
4861 | || strcmp (name, "__mips16_ret_df") == 0) | |
52f729a7 | 4862 | return get_frame_register_signed (frame, MIPS_RA_REGNUM); |
c906108c SS |
4863 | |
4864 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
4865 | { | |
4866 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
4867 | and the target PC is in $2. */ | |
4868 | if (name[19] >= '0' && name[19] <= '9') | |
52f729a7 | 4869 | return get_frame_register_signed (frame, 2); |
c906108c SS |
4870 | |
4871 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
4872 | before the jal instruction, this is effectively a call stub |
4873 | and the the target PC is in $2. Otherwise this is effectively | |
4874 | a return stub and the target PC is in $18. */ | |
c906108c SS |
4875 | else if (name[19] == 's' || name[19] == 'd') |
4876 | { | |
4877 | if (pc == start_addr) | |
4878 | { | |
4879 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
4880 | stub. Such a stub for a function bar might have a name |
4881 | like __fn_stub_bar, and might look like this: | |
4882 | mfc1 $4,$f13 | |
4883 | mfc1 $5,$f12 | |
4884 | mfc1 $6,$f15 | |
4885 | mfc1 $7,$f14 | |
4886 | la $1,bar (becomes a lui/addiu pair) | |
4887 | jr $1 | |
4888 | So scan down to the lui/addi and extract the target | |
4889 | address from those two instructions. */ | |
c906108c | 4890 | |
52f729a7 | 4891 | CORE_ADDR target_pc = get_frame_register_signed (frame, 2); |
d37cca3d | 4892 | ULONGEST inst; |
c906108c SS |
4893 | int i; |
4894 | ||
4895 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
4896 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
4897 | 0) | |
c906108c SS |
4898 | return target_pc; |
4899 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
4900 | && strcmp (name, "etext") != 0 | |
4901 | && strcmp (name, "_etext") != 0) | |
4902 | return target_pc; | |
4903 | ||
4904 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
4905 | The limit on the search is arbitrarily set to 20 |
4906 | instructions. FIXME. */ | |
95ac2dcf | 4907 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
c906108c | 4908 | { |
c5aa993b JM |
4909 | inst = mips_fetch_instruction (target_pc); |
4910 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
4911 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
4912 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
4913 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
4914 | } |
4915 | ||
4916 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
4917 | return target_pc; | |
4918 | } | |
4919 | else | |
4920 | /* This is the 'return' part of a call stub. The return | |
4921 | address is in $r18. */ | |
52f729a7 | 4922 | return get_frame_register_signed (frame, 18); |
c906108c SS |
4923 | } |
4924 | } | |
c5aa993b | 4925 | return 0; /* not a stub */ |
c906108c SS |
4926 | } |
4927 | ||
a4b8ebc8 | 4928 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 4929 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
4930 | |
4931 | static int | |
4932 | mips_stab_reg_to_regnum (int num) | |
4933 | { | |
a4b8ebc8 | 4934 | int regnum; |
2f38ef89 | 4935 | if (num >= 0 && num < 32) |
a4b8ebc8 | 4936 | regnum = num; |
2f38ef89 | 4937 | else if (num >= 38 && num < 70) |
56cea623 | 4938 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 4939 | else if (num == 70) |
56cea623 | 4940 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 4941 | else if (num == 71) |
56cea623 | 4942 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 4943 | else |
a4b8ebc8 AC |
4944 | /* This will hopefully (eventually) provoke a warning. Should |
4945 | we be calling complaint() here? */ | |
f57d151a UW |
4946 | return gdbarch_num_regs (current_gdbarch) |
4947 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4948 | return gdbarch_num_regs (current_gdbarch) + regnum; | |
88c72b7d AC |
4949 | } |
4950 | ||
2f38ef89 | 4951 | |
a4b8ebc8 | 4952 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 4953 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
4954 | |
4955 | static int | |
2f38ef89 | 4956 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 4957 | { |
a4b8ebc8 | 4958 | int regnum; |
2f38ef89 | 4959 | if (num >= 0 && num < 32) |
a4b8ebc8 | 4960 | regnum = num; |
2f38ef89 | 4961 | else if (num >= 32 && num < 64) |
56cea623 | 4962 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 4963 | else if (num == 64) |
56cea623 | 4964 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 4965 | else if (num == 65) |
56cea623 | 4966 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 4967 | else |
a4b8ebc8 AC |
4968 | /* This will hopefully (eventually) provoke a warning. Should we |
4969 | be calling complaint() here? */ | |
f57d151a UW |
4970 | return gdbarch_num_regs (current_gdbarch) |
4971 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4972 | return gdbarch_num_regs (current_gdbarch) + regnum; | |
a4b8ebc8 AC |
4973 | } |
4974 | ||
4975 | static int | |
4976 | mips_register_sim_regno (int regnum) | |
4977 | { | |
4978 | /* Only makes sense to supply raw registers. */ | |
f57d151a | 4979 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch)); |
a4b8ebc8 AC |
4980 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
4981 | decide if it is valid. Should instead define a standard sim/gdb | |
4982 | register numbering scheme. */ | |
c9f4d572 UW |
4983 | if (gdbarch_register_name (current_gdbarch, |
4984 | gdbarch_num_regs | |
4985 | (current_gdbarch) + regnum) != NULL | |
4986 | && gdbarch_register_name (current_gdbarch, | |
4987 | gdbarch_num_regs | |
4988 | (current_gdbarch) + regnum)[0] != '\0') | |
a4b8ebc8 AC |
4989 | return regnum; |
4990 | else | |
6d82d43b | 4991 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
4992 | } |
4993 | ||
2f38ef89 | 4994 | |
4844f454 CV |
4995 | /* Convert an integer into an address. Extracting the value signed |
4996 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
4997 | |
4998 | static CORE_ADDR | |
79dd2d24 | 4999 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 5000 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 5001 | { |
4844f454 | 5002 | return (CORE_ADDR) extract_signed_integer (buf, TYPE_LENGTH (type)); |
fc0c74b1 AC |
5003 | } |
5004 | ||
82e91389 DJ |
5005 | /* Dummy virtual frame pointer method. This is no more or less accurate |
5006 | than most other architectures; we just need to be explicit about it, | |
5007 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
5008 | an assertion failure. */ | |
5009 | ||
5010 | static void | |
a54fba4c MD |
5011 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
5012 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
5013 | { |
5014 | *reg = MIPS_SP_REGNUM; | |
5015 | *offset = 0; | |
5016 | } | |
5017 | ||
caaa3122 DJ |
5018 | static void |
5019 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5020 | { | |
5021 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5022 | const char *name = bfd_get_section_name (abfd, sect); | |
5023 | ||
5024 | if (*abip != MIPS_ABI_UNKNOWN) | |
5025 | return; | |
5026 | ||
5027 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5028 | return; | |
5029 | ||
5030 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5031 | *abip = MIPS_ABI_O32; | |
5032 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5033 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5034 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5035 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5036 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5037 | *abip = MIPS_ABI_O64; | |
5038 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5039 | *abip = MIPS_ABI_EABI32; | |
5040 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5041 | *abip = MIPS_ABI_EABI64; | |
5042 | else | |
8a3fe4f8 | 5043 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
5044 | } |
5045 | ||
22e47e37 FF |
5046 | static void |
5047 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
5048 | { | |
5049 | int *lbp = (int *) obj; | |
5050 | const char *name = bfd_get_section_name (abfd, sect); | |
5051 | ||
5052 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
5053 | *lbp = 32; | |
5054 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
5055 | *lbp = 64; | |
5056 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
5057 | warning (_("unrecognized .gcc_compiled_longXX")); | |
5058 | } | |
5059 | ||
2e4ebe70 DJ |
5060 | static enum mips_abi |
5061 | global_mips_abi (void) | |
5062 | { | |
5063 | int i; | |
5064 | ||
5065 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5066 | if (mips_abi_strings[i] == mips_abi_string) | |
5067 | return (enum mips_abi) i; | |
5068 | ||
e2e0b3e5 | 5069 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
5070 | } |
5071 | ||
29709017 DJ |
5072 | static void |
5073 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
5074 | { | |
29709017 DJ |
5075 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
5076 | assume that's what we've got. */ | |
4eb0ad19 DJ |
5077 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
5078 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5079 | |
5080 | /* If the size matches the full set of registers GDB traditionally | |
5081 | knows about, including floating point, for either 32-bit or | |
5082 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
5083 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
5084 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5085 | |
5086 | /* Otherwise we don't have a useful guess. */ | |
5087 | } | |
5088 | ||
f8b73d13 DJ |
5089 | static struct value * |
5090 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
5091 | { | |
5092 | const int *reg_p = baton; | |
5093 | return value_of_register (*reg_p, frame); | |
5094 | } | |
5095 | ||
c2d11a7d | 5096 | static struct gdbarch * |
6d82d43b | 5097 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5098 | { |
c2d11a7d JM |
5099 | struct gdbarch *gdbarch; |
5100 | struct gdbarch_tdep *tdep; | |
5101 | int elf_flags; | |
2e4ebe70 | 5102 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 5103 | int i, num_regs; |
8d5838b5 | 5104 | enum mips_fpu_type fpu_type; |
f8b73d13 | 5105 | struct tdesc_arch_data *tdesc_data = NULL; |
609ca2b9 | 5106 | int elf_fpu_type = 0; |
f8b73d13 DJ |
5107 | |
5108 | /* Check any target description for validity. */ | |
5109 | if (tdesc_has_registers (info.target_desc)) | |
5110 | { | |
5111 | static const char *const mips_gprs[] = { | |
5112 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
5113 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
5114 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
5115 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
5116 | }; | |
5117 | static const char *const mips_fprs[] = { | |
5118 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
5119 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
5120 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
5121 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
5122 | }; | |
5123 | ||
5124 | const struct tdesc_feature *feature; | |
5125 | int valid_p; | |
5126 | ||
5127 | feature = tdesc_find_feature (info.target_desc, | |
5128 | "org.gnu.gdb.mips.cpu"); | |
5129 | if (feature == NULL) | |
5130 | return NULL; | |
5131 | ||
5132 | tdesc_data = tdesc_data_alloc (); | |
5133 | ||
5134 | valid_p = 1; | |
5135 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
5136 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
5137 | mips_gprs[i]); | |
5138 | ||
5139 | ||
5140 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5141 | MIPS_EMBED_LO_REGNUM, "lo"); | |
5142 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5143 | MIPS_EMBED_HI_REGNUM, "hi"); | |
5144 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5145 | MIPS_EMBED_PC_REGNUM, "pc"); | |
5146 | ||
5147 | if (!valid_p) | |
5148 | { | |
5149 | tdesc_data_cleanup (tdesc_data); | |
5150 | return NULL; | |
5151 | } | |
5152 | ||
5153 | feature = tdesc_find_feature (info.target_desc, | |
5154 | "org.gnu.gdb.mips.cp0"); | |
5155 | if (feature == NULL) | |
5156 | { | |
5157 | tdesc_data_cleanup (tdesc_data); | |
5158 | return NULL; | |
5159 | } | |
5160 | ||
5161 | valid_p = 1; | |
5162 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5163 | MIPS_EMBED_BADVADDR_REGNUM, | |
5164 | "badvaddr"); | |
5165 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5166 | MIPS_PS_REGNUM, "status"); | |
5167 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5168 | MIPS_EMBED_CAUSE_REGNUM, "cause"); | |
5169 | ||
5170 | if (!valid_p) | |
5171 | { | |
5172 | tdesc_data_cleanup (tdesc_data); | |
5173 | return NULL; | |
5174 | } | |
5175 | ||
5176 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
5177 | backend is not prepared for that, though. */ | |
5178 | feature = tdesc_find_feature (info.target_desc, | |
5179 | "org.gnu.gdb.mips.fpu"); | |
5180 | if (feature == NULL) | |
5181 | { | |
5182 | tdesc_data_cleanup (tdesc_data); | |
5183 | return NULL; | |
5184 | } | |
5185 | ||
5186 | valid_p = 1; | |
5187 | for (i = 0; i < 32; i++) | |
5188 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5189 | i + MIPS_EMBED_FP0_REGNUM, | |
5190 | mips_fprs[i]); | |
5191 | ||
5192 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5193 | MIPS_EMBED_FP0_REGNUM + 32, "fcsr"); | |
5194 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5195 | MIPS_EMBED_FP0_REGNUM + 33, "fir"); | |
5196 | ||
5197 | if (!valid_p) | |
5198 | { | |
5199 | tdesc_data_cleanup (tdesc_data); | |
5200 | return NULL; | |
5201 | } | |
5202 | ||
5203 | /* It would be nice to detect an attempt to use a 64-bit ABI | |
5204 | when only 32-bit registers are provided. */ | |
5205 | } | |
c2d11a7d | 5206 | |
ec03c1ac AC |
5207 | /* First of all, extract the elf_flags, if available. */ |
5208 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5209 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5210 | else if (arches != NULL) |
5211 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5212 | else |
5213 | elf_flags = 0; | |
5214 | if (gdbarch_debug) | |
5215 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5216 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5217 | |
102182a9 | 5218 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5219 | switch ((elf_flags & EF_MIPS_ABI)) |
5220 | { | |
5221 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5222 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5223 | break; |
5224 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5225 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5226 | break; |
5227 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5228 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5229 | break; |
5230 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5231 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5232 | break; |
5233 | default: | |
acdb74a0 | 5234 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5235 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5236 | else |
ec03c1ac | 5237 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5238 | break; |
5239 | } | |
acdb74a0 | 5240 | |
caaa3122 | 5241 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5242 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5243 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5244 | |
dc305454 | 5245 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
5246 | MIPS architecture (if there is one). */ |
5247 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5248 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5249 | |
32a6503c | 5250 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5251 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5252 | && info.bfd_arch_info != NULL |
5253 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5254 | { | |
5255 | switch (info.bfd_arch_info->mach) | |
5256 | { | |
5257 | case bfd_mach_mips3900: | |
ec03c1ac | 5258 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5259 | break; |
5260 | case bfd_mach_mips4100: | |
5261 | case bfd_mach_mips5000: | |
ec03c1ac | 5262 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5263 | break; |
1d06468c EZ |
5264 | case bfd_mach_mips8000: |
5265 | case bfd_mach_mips10000: | |
32a6503c KB |
5266 | /* On Irix, ELF64 executables use the N64 ABI. The |
5267 | pseudo-sections which describe the ABI aren't present | |
5268 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5269 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5270 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5271 | found_abi = MIPS_ABI_N64; |
28d169de | 5272 | else |
ec03c1ac | 5273 | found_abi = MIPS_ABI_N32; |
1d06468c | 5274 | break; |
bf64bfd6 AC |
5275 | } |
5276 | } | |
2e4ebe70 | 5277 | |
26c53e50 DJ |
5278 | /* Default 64-bit objects to N64 instead of O32. */ |
5279 | if (found_abi == MIPS_ABI_UNKNOWN | |
5280 | && info.abfd != NULL | |
5281 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
5282 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5283 | found_abi = MIPS_ABI_N64; | |
5284 | ||
ec03c1ac AC |
5285 | if (gdbarch_debug) |
5286 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5287 | found_abi); | |
5288 | ||
5289 | /* What has the user specified from the command line? */ | |
5290 | wanted_abi = global_mips_abi (); | |
5291 | if (gdbarch_debug) | |
5292 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5293 | wanted_abi); | |
2e4ebe70 DJ |
5294 | |
5295 | /* Now that we have found what the ABI for this binary would be, | |
5296 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5297 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5298 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5299 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5300 | mips_abi = found_abi; | |
5301 | else | |
5302 | mips_abi = MIPS_ABI_O32; | |
5303 | if (gdbarch_debug) | |
5304 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5305 | mips_abi); | |
2e4ebe70 | 5306 | |
ec03c1ac | 5307 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5308 | if (gdbarch_debug) |
ec03c1ac AC |
5309 | fprintf_unfiltered (gdb_stdlog, |
5310 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
5311 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 5312 | |
8d5838b5 | 5313 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
5314 | #ifdef HAVE_ELF |
5315 | if (info.abfd | |
5316 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5317 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
5318 | Tag_GNU_MIPS_ABI_FP); | |
5319 | #endif /* HAVE_ELF */ | |
5320 | ||
8d5838b5 AC |
5321 | if (!mips_fpu_type_auto) |
5322 | fpu_type = mips_fpu_type; | |
609ca2b9 DJ |
5323 | else if (elf_fpu_type != 0) |
5324 | { | |
5325 | switch (elf_fpu_type) | |
5326 | { | |
5327 | case 1: | |
5328 | fpu_type = MIPS_FPU_DOUBLE; | |
5329 | break; | |
5330 | case 2: | |
5331 | fpu_type = MIPS_FPU_SINGLE; | |
5332 | break; | |
5333 | case 3: | |
5334 | default: | |
5335 | /* Soft float or unknown. */ | |
5336 | fpu_type = MIPS_FPU_NONE; | |
5337 | break; | |
5338 | } | |
5339 | } | |
8d5838b5 AC |
5340 | else if (info.bfd_arch_info != NULL |
5341 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5342 | switch (info.bfd_arch_info->mach) | |
5343 | { | |
5344 | case bfd_mach_mips3900: | |
5345 | case bfd_mach_mips4100: | |
5346 | case bfd_mach_mips4111: | |
a9d61c86 | 5347 | case bfd_mach_mips4120: |
8d5838b5 AC |
5348 | fpu_type = MIPS_FPU_NONE; |
5349 | break; | |
5350 | case bfd_mach_mips4650: | |
5351 | fpu_type = MIPS_FPU_SINGLE; | |
5352 | break; | |
5353 | default: | |
5354 | fpu_type = MIPS_FPU_DOUBLE; | |
5355 | break; | |
5356 | } | |
5357 | else if (arches != NULL) | |
5358 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5359 | else | |
5360 | fpu_type = MIPS_FPU_DOUBLE; | |
5361 | if (gdbarch_debug) | |
5362 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5363 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5364 | |
29709017 DJ |
5365 | /* Check for blatant incompatibilities. */ |
5366 | ||
5367 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
5368 | ABI. */ | |
5369 | if (info.target_desc | |
5370 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
5371 | && mips_abi != MIPS_ABI_EABI32 | |
5372 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
5373 | { |
5374 | if (tdesc_data != NULL) | |
5375 | tdesc_data_cleanup (tdesc_data); | |
5376 | return NULL; | |
5377 | } | |
29709017 | 5378 | |
c2d11a7d JM |
5379 | /* try to find a pre-existing architecture */ |
5380 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5381 | arches != NULL; | |
5382 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5383 | { | |
5384 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5385 | using. */ |
9103eae0 | 5386 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5387 | continue; |
9103eae0 | 5388 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5389 | continue; |
719ec221 AC |
5390 | /* Need to be pedantic about which register virtual size is |
5391 | used. */ | |
5392 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5393 | != mips64_transfers_32bit_regs_p) | |
5394 | continue; | |
8d5838b5 AC |
5395 | /* Be pedantic about which FPU is selected. */ |
5396 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5397 | continue; | |
f8b73d13 DJ |
5398 | |
5399 | if (tdesc_data != NULL) | |
5400 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 5401 | return arches->gdbarch; |
c2d11a7d JM |
5402 | } |
5403 | ||
102182a9 | 5404 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5405 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5406 | gdbarch = gdbarch_alloc (&info, tdep); | |
5407 | tdep->elf_flags = elf_flags; | |
719ec221 | 5408 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5409 | tdep->found_abi = found_abi; |
5410 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5411 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
5412 | tdep->register_size_valid_p = 0; |
5413 | tdep->register_size = 0; | |
5414 | ||
5415 | if (info.target_desc) | |
5416 | { | |
5417 | /* Some useful properties can be inferred from the target. */ | |
5418 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
5419 | { | |
5420 | tdep->register_size_valid_p = 1; | |
5421 | tdep->register_size = 4; | |
5422 | } | |
5423 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
5424 | { | |
5425 | tdep->register_size_valid_p = 1; | |
5426 | tdep->register_size = 8; | |
5427 | } | |
5428 | } | |
c2d11a7d | 5429 | |
102182a9 | 5430 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5431 | set_gdbarch_short_bit (gdbarch, 16); |
5432 | set_gdbarch_int_bit (gdbarch, 32); | |
5433 | set_gdbarch_float_bit (gdbarch, 32); | |
5434 | set_gdbarch_double_bit (gdbarch, 64); | |
5435 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5436 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5437 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5438 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5439 | |
6d82d43b | 5440 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
5441 | mips_elf_make_msymbol_special); |
5442 | ||
16e109ca | 5443 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5444 | { |
16e109ca | 5445 | const char **reg_names; |
56cea623 AC |
5446 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5447 | struct mips_regnum); | |
f8b73d13 DJ |
5448 | if (tdesc_has_registers (info.target_desc)) |
5449 | { | |
5450 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5451 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5452 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5453 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5454 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5455 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5456 | regnum->fp_control_status = 70; | |
5457 | regnum->fp_implementation_revision = 71; | |
5458 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
5459 | reg_names = NULL; | |
5460 | } | |
5461 | else if (info.osabi == GDB_OSABI_IRIX) | |
56cea623 AC |
5462 | { |
5463 | regnum->fp0 = 32; | |
5464 | regnum->pc = 64; | |
5465 | regnum->cause = 65; | |
5466 | regnum->badvaddr = 66; | |
5467 | regnum->hi = 67; | |
5468 | regnum->lo = 68; | |
5469 | regnum->fp_control_status = 69; | |
5470 | regnum->fp_implementation_revision = 70; | |
5471 | num_regs = 71; | |
16e109ca | 5472 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5473 | } |
5474 | else | |
5475 | { | |
5476 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5477 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5478 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5479 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5480 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5481 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5482 | regnum->fp_control_status = 70; | |
5483 | regnum->fp_implementation_revision = 71; | |
5484 | num_regs = 90; | |
16e109ca AC |
5485 | if (info.bfd_arch_info != NULL |
5486 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5487 | reg_names = mips_tx39_reg_names; | |
5488 | else | |
5489 | reg_names = mips_generic_reg_names; | |
56cea623 | 5490 | } |
3e8c568d | 5491 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been |
56cea623 | 5492 | replaced by read_pc? */ |
f10683bb MH |
5493 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
5494 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
5495 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
5496 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5497 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca | 5498 | set_gdbarch_register_name (gdbarch, mips_register_name); |
82e91389 | 5499 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); |
16e109ca AC |
5500 | tdep->mips_processor_reg_names = reg_names; |
5501 | tdep->regnum = regnum; | |
56cea623 | 5502 | } |
fe29b929 | 5503 | |
0dadbba0 | 5504 | switch (mips_abi) |
c2d11a7d | 5505 | { |
0dadbba0 | 5506 | case MIPS_ABI_O32: |
25ab4790 | 5507 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5508 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 5509 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5510 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5511 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5512 | set_gdbarch_long_bit (gdbarch, 32); |
5513 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5514 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5515 | break; | |
0dadbba0 | 5516 | case MIPS_ABI_O64: |
25ab4790 | 5517 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 5518 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 5519 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5520 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5521 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5522 | set_gdbarch_long_bit (gdbarch, 32); |
5523 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5524 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5525 | break; | |
0dadbba0 | 5526 | case MIPS_ABI_EABI32: |
25ab4790 | 5527 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5528 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5529 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5530 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5531 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5532 | set_gdbarch_long_bit (gdbarch, 32); |
5533 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5534 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5535 | break; | |
0dadbba0 | 5536 | case MIPS_ABI_EABI64: |
25ab4790 | 5537 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5538 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5539 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5540 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5541 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5542 | set_gdbarch_long_bit (gdbarch, 64); |
5543 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5544 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5545 | break; | |
0dadbba0 | 5546 | case MIPS_ABI_N32: |
25ab4790 | 5547 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5548 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5549 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5550 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5551 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5552 | set_gdbarch_long_bit (gdbarch, 32); |
5553 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5554 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5555 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 5556 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
5557 | break; |
5558 | case MIPS_ABI_N64: | |
25ab4790 | 5559 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5560 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5561 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5562 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5563 | tdep->default_mask_address_p = 0; |
5564 | set_gdbarch_long_bit (gdbarch, 64); | |
5565 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5566 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5567 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 5568 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 5569 | break; |
c2d11a7d | 5570 | default: |
e2e0b3e5 | 5571 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
5572 | } |
5573 | ||
22e47e37 FF |
5574 | /* GCC creates a pseudo-section whose name specifies the size of |
5575 | longs, since -mlong32 or -mlong64 may be used independent of | |
5576 | other options. How those options affect pointer sizes is ABI and | |
5577 | architecture dependent, so use them to override the default sizes | |
5578 | set by the ABI. This table shows the relationship between ABI, | |
5579 | -mlongXX, and size of pointers: | |
5580 | ||
5581 | ABI -mlongXX ptr bits | |
5582 | --- -------- -------- | |
5583 | o32 32 32 | |
5584 | o32 64 32 | |
5585 | n32 32 32 | |
5586 | n32 64 64 | |
5587 | o64 32 32 | |
5588 | o64 64 64 | |
5589 | n64 32 32 | |
5590 | n64 64 64 | |
5591 | eabi32 32 32 | |
5592 | eabi32 64 32 | |
5593 | eabi64 32 32 | |
5594 | eabi64 64 64 | |
5595 | ||
5596 | Note that for o32 and eabi32, pointers are always 32 bits | |
5597 | regardless of any -mlongXX option. For all others, pointers and | |
5598 | longs are the same, as set by -mlongXX or set by defaults. | |
5599 | */ | |
5600 | ||
5601 | if (info.abfd != NULL) | |
5602 | { | |
5603 | int long_bit = 0; | |
5604 | ||
5605 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
5606 | if (long_bit) | |
5607 | { | |
5608 | set_gdbarch_long_bit (gdbarch, long_bit); | |
5609 | switch (mips_abi) | |
5610 | { | |
5611 | case MIPS_ABI_O32: | |
5612 | case MIPS_ABI_EABI32: | |
5613 | break; | |
5614 | case MIPS_ABI_N32: | |
5615 | case MIPS_ABI_O64: | |
5616 | case MIPS_ABI_N64: | |
5617 | case MIPS_ABI_EABI64: | |
5618 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
5619 | break; | |
5620 | default: | |
5621 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
5622 | } | |
5623 | } | |
5624 | } | |
5625 | ||
a5ea2558 AC |
5626 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5627 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5628 | comment: | |
5629 | ||
5630 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5631 | flag in object files because to do so would make it impossible to | |
102182a9 | 5632 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5633 | unnecessarily restrictive. |
361d1df0 | 5634 | |
a5ea2558 AC |
5635 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5636 | but to set this flag before gcc is built with such multilibs will | |
5637 | break too many systems.'' | |
5638 | ||
5639 | But even more unhelpfully, the default linker output target for | |
5640 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5641 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5642 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5643 | this flag to detect 32-bit mode would do the wrong thing given |
5644 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5645 | as 32-bit programs by default. */ |
a5ea2558 | 5646 | |
6c997a34 | 5647 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 5648 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 5649 | |
102182a9 MS |
5650 | /* Add/remove bits from an address. The MIPS needs be careful to |
5651 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5652 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5653 | ||
58dfe9ff AC |
5654 | /* Unwind the frame. */ |
5655 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 5656 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
edfae063 | 5657 | set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id); |
10312cc4 | 5658 | |
102182a9 | 5659 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5660 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
5661 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
5662 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5663 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, | |
5664 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5665 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, | |
5666 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5667 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5668 | |
c2d11a7d JM |
5669 | /* MIPS version of CALL_DUMMY */ |
5670 | ||
9710e734 AC |
5671 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
5672 | replaced by a command, and all targets will default to on stack | |
5673 | (regardless of the stack's execute status). */ | |
5674 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 5675 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 5676 | |
87783b8b AC |
5677 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
5678 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
5679 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
5680 | ||
f7b9e9fc AC |
5681 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5682 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
5683 | |
5684 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 5685 | |
97ab0fdd MR |
5686 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
5687 | ||
fc0c74b1 AC |
5688 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5689 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5690 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5691 | |
a4b8ebc8 | 5692 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 5693 | |
e11c53d2 | 5694 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 5695 | |
e5ab0dce AC |
5696 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
5697 | ||
3a3bc038 AC |
5698 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
5699 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
5700 | need to all be folded into the target vector. Since they are | |
5701 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
5702 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
5703 | is sitting on? */ | |
5704 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
5705 | ||
e7d6a6d2 | 5706 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 5707 | |
3352ef37 AC |
5708 | set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay); |
5709 | ||
0d5de010 DJ |
5710 | /* Virtual tables. */ |
5711 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
5712 | ||
29709017 DJ |
5713 | mips_register_g_packet_guesses (gdbarch); |
5714 | ||
6de918a6 | 5715 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 5716 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 5717 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 5718 | |
5792a79b | 5719 | /* Unwind the frame. */ |
2bd0c3d7 | 5720 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
eec63939 | 5721 | frame_unwind_append_sniffer (gdbarch, mips_stub_frame_sniffer); |
45c9dd44 AC |
5722 | frame_unwind_append_sniffer (gdbarch, mips_insn16_frame_sniffer); |
5723 | frame_unwind_append_sniffer (gdbarch, mips_insn32_frame_sniffer); | |
2bd0c3d7 | 5724 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 5725 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
5726 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
5727 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 5728 | |
f8b73d13 DJ |
5729 | if (tdesc_data) |
5730 | { | |
5731 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 5732 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
5733 | |
5734 | /* Override the normal target description methods to handle our | |
5735 | dual real and pseudo registers. */ | |
5736 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
5737 | set_gdbarch_register_reggroup_p (gdbarch, mips_tdesc_register_reggroup_p); | |
5738 | ||
5739 | num_regs = gdbarch_num_regs (gdbarch); | |
5740 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
5741 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
5742 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
5743 | } | |
5744 | ||
5745 | /* Add ABI-specific aliases for the registers. */ | |
5746 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
5747 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
5748 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
5749 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
5750 | else | |
5751 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
5752 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
5753 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
5754 | ||
5755 | /* Add some other standard aliases. */ | |
5756 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
5757 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
5758 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
5759 | ||
4b9b3959 AC |
5760 | return gdbarch; |
5761 | } | |
5762 | ||
2e4ebe70 | 5763 | static void |
6d82d43b | 5764 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
5765 | { |
5766 | struct gdbarch_info info; | |
5767 | ||
5768 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
5769 | mips_gdbarch_init will take care of the rest. */ | |
5770 | gdbarch_info_init (&info); | |
5771 | gdbarch_update_p (info); | |
5772 | } | |
5773 | ||
ad188201 KB |
5774 | /* Print out which MIPS ABI is in use. */ |
5775 | ||
5776 | static void | |
1f8ca57c JB |
5777 | show_mips_abi (struct ui_file *file, |
5778 | int from_tty, | |
5779 | struct cmd_list_element *ignored_cmd, | |
5780 | const char *ignored_value) | |
ad188201 KB |
5781 | { |
5782 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
1f8ca57c JB |
5783 | fprintf_filtered |
5784 | (file, | |
5785 | "The MIPS ABI is unknown because the current architecture " | |
5786 | "is not MIPS.\n"); | |
ad188201 KB |
5787 | else |
5788 | { | |
5789 | enum mips_abi global_abi = global_mips_abi (); | |
5790 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
5791 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
5792 | ||
5793 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
5794 | fprintf_filtered |
5795 | (file, | |
5796 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 5797 | actual_abi_str); |
ad188201 | 5798 | else if (global_abi == actual_abi) |
1f8ca57c JB |
5799 | fprintf_filtered |
5800 | (file, | |
5801 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 5802 | actual_abi_str); |
ad188201 KB |
5803 | else |
5804 | { | |
5805 | /* Probably shouldn't happen... */ | |
1f8ca57c JB |
5806 | fprintf_filtered |
5807 | (file, | |
5808 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6d82d43b | 5809 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
5810 | } |
5811 | } | |
5812 | } | |
5813 | ||
4b9b3959 | 5814 | static void |
72a155b4 | 5815 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 5816 | { |
72a155b4 | 5817 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 5818 | if (tdep != NULL) |
c2d11a7d | 5819 | { |
acdb74a0 AC |
5820 | int ef_mips_arch; |
5821 | int ef_mips_32bitmode; | |
f49e4e6d | 5822 | /* Determine the ISA. */ |
acdb74a0 AC |
5823 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
5824 | { | |
5825 | case E_MIPS_ARCH_1: | |
5826 | ef_mips_arch = 1; | |
5827 | break; | |
5828 | case E_MIPS_ARCH_2: | |
5829 | ef_mips_arch = 2; | |
5830 | break; | |
5831 | case E_MIPS_ARCH_3: | |
5832 | ef_mips_arch = 3; | |
5833 | break; | |
5834 | case E_MIPS_ARCH_4: | |
93d56215 | 5835 | ef_mips_arch = 4; |
acdb74a0 AC |
5836 | break; |
5837 | default: | |
93d56215 | 5838 | ef_mips_arch = 0; |
acdb74a0 AC |
5839 | break; |
5840 | } | |
f49e4e6d | 5841 | /* Determine the size of a pointer. */ |
acdb74a0 | 5842 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
5843 | fprintf_unfiltered (file, |
5844 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 5845 | tdep->elf_flags); |
4b9b3959 | 5846 | fprintf_unfiltered (file, |
acdb74a0 AC |
5847 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
5848 | ef_mips_32bitmode); | |
5849 | fprintf_unfiltered (file, | |
5850 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
5851 | ef_mips_arch); | |
5852 | fprintf_unfiltered (file, | |
5853 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 5854 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
5855 | fprintf_unfiltered (file, |
5856 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 5857 | mips_mask_address_p (tdep), |
4014092b | 5858 | tdep->default_mask_address_p); |
c2d11a7d | 5859 | } |
4b9b3959 AC |
5860 | fprintf_unfiltered (file, |
5861 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
5862 | MIPS_DEFAULT_FPU_TYPE, | |
5863 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5864 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5865 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5866 | : "???")); | |
6d82d43b | 5867 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI); |
4b9b3959 AC |
5868 | fprintf_unfiltered (file, |
5869 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
5870 | MIPS_FPU_TYPE, | |
5871 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5872 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5873 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5874 | : "???")); | |
c2d11a7d JM |
5875 | } |
5876 | ||
6d82d43b | 5877 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 5878 | |
c906108c | 5879 | void |
acdb74a0 | 5880 | _initialize_mips_tdep (void) |
c906108c SS |
5881 | { |
5882 | static struct cmd_list_element *mipsfpulist = NULL; | |
5883 | struct cmd_list_element *c; | |
5884 | ||
6d82d43b | 5885 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
5886 | if (MIPS_ABI_LAST + 1 |
5887 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 5888 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 5889 | |
4b9b3959 | 5890 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 5891 | |
8d5f9dcb DJ |
5892 | mips_pdr_data = register_objfile_data (); |
5893 | ||
4eb0ad19 DJ |
5894 | /* Create feature sets with the appropriate properties. The values |
5895 | are not important. */ | |
5896 | mips_tdesc_gp32 = allocate_target_description (); | |
5897 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
5898 | ||
5899 | mips_tdesc_gp64 = allocate_target_description (); | |
5900 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
5901 | ||
a5ea2558 AC |
5902 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
5903 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
1bedd215 | 5904 | _("Various MIPS specific commands."), |
a5ea2558 AC |
5905 | &setmipscmdlist, "set mips ", 0, &setlist); |
5906 | ||
5907 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 5908 | _("Various MIPS specific commands."), |
a5ea2558 AC |
5909 | &showmipscmdlist, "show mips ", 0, &showlist); |
5910 | ||
2e4ebe70 | 5911 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
5912 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
5913 | &mips_abi_string, _("\ | |
5914 | Set the MIPS ABI used by this program."), _("\ | |
5915 | Show the MIPS ABI used by this program."), _("\ | |
5916 | This option can be set to one of:\n\ | |
5917 | auto - the default ABI associated with the current binary\n\ | |
5918 | o32\n\ | |
5919 | o64\n\ | |
5920 | n32\n\ | |
5921 | n64\n\ | |
5922 | eabi32\n\ | |
5923 | eabi64"), | |
5924 | mips_abi_update, | |
5925 | show_mips_abi, | |
5926 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 5927 | |
c906108c SS |
5928 | /* Let the user turn off floating point and set the fence post for |
5929 | heuristic_proc_start. */ | |
5930 | ||
5931 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 5932 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
5933 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
5934 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 5935 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
5936 | &mipsfpulist); |
5937 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 5938 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
5939 | &mipsfpulist); |
5940 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
5941 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
5942 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
5943 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 5944 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
5945 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
5946 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
5947 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
5948 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 5949 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
5950 | &mipsfpulist); |
5951 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 5952 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
5953 | &showlist); |
5954 | ||
c906108c SS |
5955 | /* We really would like to have both "0" and "unlimited" work, but |
5956 | command.c doesn't deal with that. So make it a var_zinteger | |
5957 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 5958 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
5959 | &heuristic_fence_post, _("\ |
5960 | Set the distance searched for the start of a function."), _("\ | |
5961 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
5962 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
5963 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 5964 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 5965 | reinit_frame_cache_sfunc, |
7915a72c | 5966 | NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */ |
6bcadd06 | 5967 | &setlist, &showlist); |
c906108c SS |
5968 | |
5969 | /* Allow the user to control whether the upper bits of 64-bit | |
5970 | addresses should be zeroed. */ | |
7915a72c AC |
5971 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
5972 | &mask_address_var, _("\ | |
5973 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
5974 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
e9e68a56 | 5975 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ |
7915a72c | 5976 | allow GDB to determine the correct value."), |
08546159 AC |
5977 | NULL, show_mask_address, |
5978 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
5979 | |
5980 | /* Allow the user to control the size of 32 bit registers within the | |
5981 | raw remote packet. */ | |
b3f42336 | 5982 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
5983 | &mips64_transfers_32bit_regs_p, _("\ |
5984 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
5985 | _("\ | |
5986 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
5987 | _("\ | |
719ec221 AC |
5988 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
5989 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 5990 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 5991 | set_mips64_transfers_32bit_regs, |
7915a72c | 5992 | NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */ |
7915a72c | 5993 | &setlist, &showlist); |
9ace0497 AC |
5994 | |
5995 | /* Debug this files internals. */ | |
6bcadd06 | 5996 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
5997 | &mips_debug, _("\ |
5998 | Set mips debugging."), _("\ | |
5999 | Show mips debugging."), _("\ | |
6000 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 6001 | NULL, |
7915a72c | 6002 | NULL, /* FIXME: i18n: Mips debugging is currently %s. */ |
6bcadd06 | 6003 | &setdebuglist, &showdebuglist); |
c906108c | 6004 | } |