Commit | Line | Data |
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ca3bf3bd DJ |
1 | /* Target-dependent code for the Xtensa port of GDB, the GNU debugger. |
2 | ||
3666a048 | 3 | Copyright (C) 2003-2021 Free Software Foundation, Inc. |
ca3bf3bd DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
ca3bf3bd DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ca3bf3bd DJ |
19 | |
20 | #include "defs.h" | |
21 | #include "frame.h" | |
ee967b5f | 22 | #include "solib-svr4.h" |
ca3bf3bd | 23 | #include "symtab.h" |
ca3bf3bd DJ |
24 | #include "gdbtypes.h" |
25 | #include "gdbcore.h" | |
26 | #include "value.h" | |
40045d91 | 27 | #include "osabi.h" |
ca3bf3bd DJ |
28 | #include "regcache.h" |
29 | #include "reggroups.h" | |
30 | #include "regset.h" | |
31 | ||
82ca8957 | 32 | #include "dwarf2/frame.h" |
ca3bf3bd DJ |
33 | #include "frame-base.h" |
34 | #include "frame-unwind.h" | |
35 | ||
36 | #include "arch-utils.h" | |
37 | #include "gdbarch.h" | |
ca3bf3bd DJ |
38 | |
39 | #include "command.h" | |
40 | #include "gdbcmd.h" | |
ca3bf3bd | 41 | |
bdb4c075 | 42 | #include "xtensa-isa.h" |
ca3bf3bd | 43 | #include "xtensa-tdep.h" |
94a0e877 | 44 | #include "xtensa-config.h" |
325fac50 | 45 | #include <algorithm> |
ca3bf3bd DJ |
46 | |
47 | ||
ccce17b0 | 48 | static unsigned int xtensa_debug_level = 0; |
ca3bf3bd DJ |
49 | |
50 | #define DEBUGWARN(args...) \ | |
51 | if (xtensa_debug_level > 0) \ | |
52 | fprintf_unfiltered (gdb_stdlog, "(warn ) " args) | |
53 | ||
54 | #define DEBUGINFO(args...) \ | |
55 | if (xtensa_debug_level > 1) \ | |
56 | fprintf_unfiltered (gdb_stdlog, "(info ) " args) | |
57 | ||
58 | #define DEBUGTRACE(args...) \ | |
59 | if (xtensa_debug_level > 2) \ | |
60 | fprintf_unfiltered (gdb_stdlog, "(trace) " args) | |
61 | ||
62 | #define DEBUGVERB(args...) \ | |
63 | if (xtensa_debug_level > 3) \ | |
64 | fprintf_unfiltered (gdb_stdlog, "(verb ) " args) | |
65 | ||
66 | ||
67 | /* According to the ABI, the SP must be aligned to 16-byte boundaries. */ | |
ca3bf3bd DJ |
68 | #define SP_ALIGNMENT 16 |
69 | ||
70 | ||
bdb4c075 MG |
71 | /* On Windowed ABI, we use a6 through a11 for passing arguments |
72 | to a function called by GDB because CALL4 is used. */ | |
bdb4c075 MG |
73 | #define ARGS_NUM_REGS 6 |
74 | #define REGISTER_SIZE 4 | |
ca3bf3bd | 75 | |
ca3bf3bd | 76 | |
bdb4c075 MG |
77 | /* Extract the call size from the return address or PS register. */ |
78 | #define PS_CALLINC_SHIFT 16 | |
79 | #define PS_CALLINC_MASK 0x00030000 | |
80 | #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT) | |
81 | #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3)) | |
ca3bf3bd | 82 | |
98689b25 MG |
83 | /* On TX, hardware can be configured without Exception Option. |
84 | There is no PS register in this case. Inside XT-GDB, let us treat | |
85 | it as a virtual read-only register always holding the same value. */ | |
86 | #define TX_PS 0x20 | |
87 | ||
bdb4c075 | 88 | /* ABI-independent macros. */ |
91d8eb23 MD |
89 | #define ARG_NOF(gdbarch) \ |
90 | (gdbarch_tdep (gdbarch)->call_abi \ | |
91 | == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS)) | |
92 | #define ARG_1ST(gdbarch) \ | |
93 | (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \ | |
94a0e877 | 94 | ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \ |
91d8eb23 | 95 | : (gdbarch_tdep (gdbarch)->a0_base + 6)) |
ca3bf3bd | 96 | |
ca3bf3bd DJ |
97 | /* XTENSA_IS_ENTRY tests whether the first byte of an instruction |
98 | indicates that the instruction is an ENTRY instruction. */ | |
99 | ||
91d8eb23 MD |
100 | #define XTENSA_IS_ENTRY(gdbarch, op1) \ |
101 | ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \ | |
4c6b5505 | 102 | ? ((op1) == 0x6c) : ((op1) == 0x36)) |
ca3bf3bd | 103 | |
bdb4c075 | 104 | #define XTENSA_ENTRY_LENGTH 3 |
ca3bf3bd DJ |
105 | |
106 | /* windowing_enabled() returns true, if windowing is enabled. | |
107 | WOE must be set to 1; EXCM to 0. | |
108 | Note: We assume that EXCM is always 0 for XEA1. */ | |
109 | ||
bdb4c075 MG |
110 | #define PS_WOE (1<<18) |
111 | #define PS_EXC (1<<4) | |
112 | ||
0dd5cbc5 AH |
113 | /* Big enough to hold the size of the largest register in bytes. */ |
114 | #define XTENSA_MAX_REGISTER_SIZE 64 | |
115 | ||
b801de47 | 116 | static int |
98689b25 MG |
117 | windowing_enabled (struct gdbarch *gdbarch, unsigned int ps) |
118 | { | |
119 | /* If we know CALL0 ABI is set explicitly, say it is Call0. */ | |
120 | if (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only) | |
121 | return 0; | |
122 | ||
123 | return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0); | |
124 | } | |
125 | ||
581e13c1 MS |
126 | /* Convert a live A-register number to the corresponding AR-register |
127 | number. */ | |
91d8eb23 | 128 | static int |
ee967b5f | 129 | arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb) |
91d8eb23 MD |
130 | { |
131 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
ee967b5f | 132 | int arreg; |
91d8eb23 | 133 | |
ee967b5f MG |
134 | arreg = a_regnum - tdep->a0_base; |
135 | arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT; | |
136 | arreg &= tdep->num_aregs - 1; | |
91d8eb23 | 137 | |
ee967b5f MG |
138 | return arreg + tdep->ar_base; |
139 | } | |
140 | ||
141 | /* Convert a live AR-register number to the corresponding A-register order | |
142 | number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */ | |
143 | static int | |
144 | areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb) | |
145 | { | |
146 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
147 | int areg; | |
148 | ||
149 | areg = ar_regnum - tdep->ar_base; | |
150 | if (areg < 0 || areg >= tdep->num_aregs) | |
151 | return -1; | |
152 | areg = (areg - wb * 4) & (tdep->num_aregs - 1); | |
153 | return (areg > 15) ? -1 : areg; | |
91d8eb23 MD |
154 | } |
155 | ||
68d6df83 | 156 | /* Read Xtensa register directly from the hardware. */ |
b801de47 | 157 | static unsigned long |
08b9c608 MG |
158 | xtensa_read_register (int regnum) |
159 | { | |
160 | ULONGEST value; | |
161 | ||
162 | regcache_raw_read_unsigned (get_current_regcache (), regnum, &value); | |
163 | return (unsigned long) value; | |
164 | } | |
165 | ||
68d6df83 | 166 | /* Write Xtensa register directly to the hardware. */ |
b801de47 | 167 | static void |
08b9c608 MG |
168 | xtensa_write_register (int regnum, ULONGEST value) |
169 | { | |
170 | regcache_raw_write_unsigned (get_current_regcache (), regnum, value); | |
171 | } | |
172 | ||
ca3bf3bd DJ |
173 | /* Return the window size of the previous call to the function from which we |
174 | have just returned. | |
175 | ||
176 | This function is used to extract the return value after a called function | |
bdb4c075 | 177 | has returned to the caller. On Xtensa, the register that holds the return |
ca3bf3bd DJ |
178 | value (from the perspective of the caller) depends on what call |
179 | instruction was used. For now, we are assuming that the call instruction | |
180 | precedes the current address, so we simply analyze the call instruction. | |
181 | If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4' | |
182 | method to call the inferior function. */ | |
183 | ||
184 | static int | |
91d8eb23 | 185 | extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc) |
ca3bf3bd | 186 | { |
e17a4113 | 187 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
bdb4c075 | 188 | int winsize = 4; |
ca3bf3bd | 189 | int insn; |
ff7a4c00 | 190 | gdb_byte buf[4]; |
ca3bf3bd DJ |
191 | |
192 | DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc); | |
193 | ||
194 | /* Read the previous instruction (should be a call[x]{4|8|12}. */ | |
195 | read_memory (pc-3, buf, 3); | |
e17a4113 | 196 | insn = extract_unsigned_integer (buf, 3, byte_order); |
ca3bf3bd DJ |
197 | |
198 | /* Decode call instruction: | |
199 | Little Endian | |
200 | call{0,4,8,12} OFFSET || {00,01,10,11} || 0101 | |
201 | callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000 | |
202 | Big Endian | |
203 | call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET | |
204 | callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */ | |
205 | ||
e17a4113 | 206 | if (byte_order == BFD_ENDIAN_LITTLE) |
ca3bf3bd DJ |
207 | { |
208 | if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0)) | |
bdb4c075 | 209 | winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */ |
ca3bf3bd DJ |
210 | } |
211 | else | |
212 | { | |
213 | if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03)) | |
bdb4c075 | 214 | winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */ |
ca3bf3bd DJ |
215 | } |
216 | return winsize; | |
217 | } | |
218 | ||
219 | ||
220 | /* REGISTER INFORMATION */ | |
221 | ||
08b9c608 MG |
222 | /* Find register by name. */ |
223 | static int | |
a121b7c1 | 224 | xtensa_find_register_by_name (struct gdbarch *gdbarch, const char *name) |
08b9c608 MG |
225 | { |
226 | int i; | |
227 | ||
f6efe3f8 | 228 | for (i = 0; i < gdbarch_num_cooked_regs (gdbarch); i++) |
08b9c608 MG |
229 | |
230 | if (strcasecmp (gdbarch_tdep (gdbarch)->regmap[i].name, name) == 0) | |
231 | return i; | |
232 | ||
233 | return -1; | |
234 | } | |
235 | ||
ca3bf3bd | 236 | /* Returns the name of a register. */ |
ca3bf3bd | 237 | static const char * |
d93859e2 | 238 | xtensa_register_name (struct gdbarch *gdbarch, int regnum) |
ca3bf3bd DJ |
239 | { |
240 | /* Return the name stored in the register map. */ | |
f6efe3f8 | 241 | if (regnum >= 0 && regnum < gdbarch_num_cooked_regs (gdbarch)) |
d93859e2 | 242 | return gdbarch_tdep (gdbarch)->regmap[regnum].name; |
ca3bf3bd | 243 | |
ca3bf3bd DJ |
244 | internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum); |
245 | return 0; | |
246 | } | |
247 | ||
ca3bf3bd DJ |
248 | /* Return the type of a register. Create a new type, if necessary. */ |
249 | ||
ca3bf3bd DJ |
250 | static struct type * |
251 | xtensa_register_type (struct gdbarch *gdbarch, int regnum) | |
252 | { | |
df4df182 UW |
253 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
254 | ||
ca3bf3bd | 255 | /* Return signed integer for ARx and Ax registers. */ |
df4df182 UW |
256 | if ((regnum >= tdep->ar_base |
257 | && regnum < tdep->ar_base + tdep->num_aregs) | |
258 | || (regnum >= tdep->a0_base | |
259 | && regnum < tdep->a0_base + 16)) | |
0dfff4cb | 260 | return builtin_type (gdbarch)->builtin_int; |
ca3bf3bd | 261 | |
6b50c0b0 | 262 | if (regnum == gdbarch_pc_regnum (gdbarch) |
df4df182 | 263 | || regnum == tdep->a0_base + 1) |
fde6c819 | 264 | return builtin_type (gdbarch)->builtin_data_ptr; |
ca3bf3bd DJ |
265 | |
266 | /* Return the stored type for all other registers. */ | |
f6efe3f8 | 267 | else if (regnum >= 0 && regnum < gdbarch_num_cooked_regs (gdbarch)) |
ca3bf3bd | 268 | { |
df4df182 | 269 | xtensa_register_t* reg = &tdep->regmap[regnum]; |
ca3bf3bd | 270 | |
bdb4c075 | 271 | /* Set ctype for this register (only the first time). */ |
ca3bf3bd DJ |
272 | |
273 | if (reg->ctype == 0) | |
274 | { | |
275 | struct ctype_cache *tp; | |
276 | int size = reg->byte_size; | |
277 | ||
bdb4c075 MG |
278 | /* We always use the memory representation, |
279 | even if the register width is smaller. */ | |
ca3bf3bd DJ |
280 | switch (size) |
281 | { | |
282 | case 1: | |
df4df182 | 283 | reg->ctype = builtin_type (gdbarch)->builtin_uint8; |
ca3bf3bd DJ |
284 | break; |
285 | ||
286 | case 2: | |
df4df182 | 287 | reg->ctype = builtin_type (gdbarch)->builtin_uint16; |
ca3bf3bd DJ |
288 | break; |
289 | ||
290 | case 4: | |
df4df182 | 291 | reg->ctype = builtin_type (gdbarch)->builtin_uint32; |
ca3bf3bd DJ |
292 | break; |
293 | ||
294 | case 8: | |
df4df182 | 295 | reg->ctype = builtin_type (gdbarch)->builtin_uint64; |
ca3bf3bd DJ |
296 | break; |
297 | ||
298 | case 16: | |
df4df182 | 299 | reg->ctype = builtin_type (gdbarch)->builtin_uint128; |
ca3bf3bd DJ |
300 | break; |
301 | ||
302 | default: | |
df4df182 | 303 | for (tp = tdep->type_entries; tp != NULL; tp = tp->next) |
ca3bf3bd DJ |
304 | if (tp->size == size) |
305 | break; | |
306 | ||
307 | if (tp == NULL) | |
308 | { | |
528e1572 | 309 | std::string name = string_printf ("int%d", size * 8); |
8d749320 SM |
310 | |
311 | tp = XNEW (struct ctype_cache); | |
df4df182 UW |
312 | tp->next = tdep->type_entries; |
313 | tdep->type_entries = tp; | |
ca3bf3bd | 314 | tp->size = size; |
e9bb382b | 315 | tp->virtual_type |
528e1572 | 316 | = arch_integer_type (gdbarch, size * 8, 1, name.c_str ()); |
ca3bf3bd DJ |
317 | } |
318 | ||
319 | reg->ctype = tp->virtual_type; | |
320 | } | |
321 | } | |
322 | return reg->ctype; | |
323 | } | |
324 | ||
ca3bf3bd DJ |
325 | internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum); |
326 | return 0; | |
327 | } | |
328 | ||
329 | ||
bdb4c075 | 330 | /* Return the 'local' register number for stubs, dwarf2, etc. |
ca3bf3bd DJ |
331 | The debugging information enumerates registers starting from 0 for A0 |
332 | to n for An. So, we only have to add the base number for A0. */ | |
333 | ||
334 | static int | |
d3f73121 | 335 | xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum) |
ca3bf3bd DJ |
336 | { |
337 | int i; | |
338 | ||
339 | if (regnum >= 0 && regnum < 16) | |
d3f73121 | 340 | return gdbarch_tdep (gdbarch)->a0_base + regnum; |
ca3bf3bd | 341 | |
f6efe3f8 | 342 | for (i = 0; i < gdbarch_num_cooked_regs (gdbarch); i++) |
d3f73121 | 343 | if (regnum == gdbarch_tdep (gdbarch)->regmap[i].target_number) |
ca3bf3bd DJ |
344 | return i; |
345 | ||
0fde2c53 | 346 | return -1; |
ca3bf3bd DJ |
347 | } |
348 | ||
349 | ||
bdb4c075 MG |
350 | /* Write the bits of a masked register to the various registers. |
351 | Only the masked areas of these registers are modified; the other | |
352 | fields are untouched. The size of masked registers is always less | |
353 | than or equal to 32 bits. */ | |
ca3bf3bd DJ |
354 | |
355 | static void | |
9c9acae0 UW |
356 | xtensa_register_write_masked (struct regcache *regcache, |
357 | xtensa_register_t *reg, const gdb_byte *buffer) | |
ca3bf3bd | 358 | { |
0dd5cbc5 | 359 | unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4]; |
ca3bf3bd DJ |
360 | const xtensa_mask_t *mask = reg->mask; |
361 | ||
362 | int shift = 0; /* Shift for next mask (mod 32). */ | |
363 | int start, size; /* Start bit and size of current mask. */ | |
364 | ||
365 | unsigned int *ptr = value; | |
366 | unsigned int regval, m, mem = 0; | |
367 | ||
368 | int bytesize = reg->byte_size; | |
369 | int bitsize = bytesize * 8; | |
370 | int i, r; | |
371 | ||
372 | DEBUGTRACE ("xtensa_register_write_masked ()\n"); | |
373 | ||
374 | /* Copy the masked register to host byte-order. */ | |
ac7936df | 375 | if (gdbarch_byte_order (regcache->arch ()) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
376 | for (i = 0; i < bytesize; i++) |
377 | { | |
378 | mem >>= 8; | |
379 | mem |= (buffer[bytesize - i - 1] << 24); | |
380 | if ((i & 3) == 3) | |
381 | *ptr++ = mem; | |
382 | } | |
383 | else | |
384 | for (i = 0; i < bytesize; i++) | |
385 | { | |
386 | mem >>= 8; | |
387 | mem |= (buffer[i] << 24); | |
388 | if ((i & 3) == 3) | |
389 | *ptr++ = mem; | |
390 | } | |
391 | ||
392 | /* We might have to shift the final value: | |
393 | bytesize & 3 == 0 -> nothing to do, we use the full 32 bits, | |
394 | bytesize & 3 == x -> shift (4-x) * 8. */ | |
395 | ||
396 | *ptr = mem >> (((0 - bytesize) & 3) * 8); | |
397 | ptr = value; | |
398 | mem = *ptr; | |
399 | ||
400 | /* Write the bits to the masked areas of the other registers. */ | |
401 | for (i = 0; i < mask->count; i++) | |
402 | { | |
403 | start = mask->mask[i].bit_start; | |
404 | size = mask->mask[i].bit_size; | |
405 | regval = mem >> shift; | |
406 | ||
407 | if ((shift += size) > bitsize) | |
408 | error (_("size of all masks is larger than the register")); | |
409 | ||
410 | if (shift >= 32) | |
411 | { | |
412 | mem = *(++ptr); | |
413 | shift -= 32; | |
414 | bitsize -= 32; | |
415 | ||
416 | if (shift > 0) | |
417 | regval |= mem << (size - shift); | |
418 | } | |
419 | ||
420 | /* Make sure we have a valid register. */ | |
421 | r = mask->mask[i].reg_num; | |
422 | if (r >= 0 && size > 0) | |
423 | { | |
424 | /* Don't overwrite the unmasked areas. */ | |
9c9acae0 UW |
425 | ULONGEST old_val; |
426 | regcache_cooked_read_unsigned (regcache, r, &old_val); | |
ca3bf3bd DJ |
427 | m = 0xffffffff >> (32 - size) << start; |
428 | regval <<= start; | |
9c9acae0 UW |
429 | regval = (regval & m) | (old_val & ~m); |
430 | regcache_cooked_write_unsigned (regcache, r, regval); | |
ca3bf3bd DJ |
431 | } |
432 | } | |
433 | } | |
434 | ||
435 | ||
bdb4c075 MG |
436 | /* Read a tie state or mapped registers. Read the masked areas |
437 | of the registers and assemble them into a single value. */ | |
ca3bf3bd | 438 | |
05d1431c | 439 | static enum register_status |
849d0ba8 | 440 | xtensa_register_read_masked (readable_regcache *regcache, |
9c9acae0 | 441 | xtensa_register_t *reg, gdb_byte *buffer) |
ca3bf3bd | 442 | { |
0dd5cbc5 | 443 | unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4]; |
ca3bf3bd DJ |
444 | const xtensa_mask_t *mask = reg->mask; |
445 | ||
446 | int shift = 0; | |
447 | int start, size; | |
448 | ||
449 | unsigned int *ptr = value; | |
450 | unsigned int regval, mem = 0; | |
451 | ||
452 | int bytesize = reg->byte_size; | |
453 | int bitsize = bytesize * 8; | |
454 | int i; | |
455 | ||
456 | DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n", | |
457 | reg->name == 0 ? "" : reg->name); | |
458 | ||
459 | /* Assemble the register from the masked areas of other registers. */ | |
460 | for (i = 0; i < mask->count; i++) | |
461 | { | |
462 | int r = mask->mask[i].reg_num; | |
9c9acae0 UW |
463 | if (r >= 0) |
464 | { | |
05d1431c | 465 | enum register_status status; |
9c9acae0 | 466 | ULONGEST val; |
05d1431c | 467 | |
11f57cb6 | 468 | status = regcache->cooked_read (r, &val); |
05d1431c PA |
469 | if (status != REG_VALID) |
470 | return status; | |
9c9acae0 UW |
471 | regval = (unsigned int) val; |
472 | } | |
473 | else | |
474 | regval = 0; | |
475 | ||
ca3bf3bd DJ |
476 | start = mask->mask[i].bit_start; |
477 | size = mask->mask[i].bit_size; | |
478 | ||
479 | regval >>= start; | |
480 | ||
481 | if (size < 32) | |
482 | regval &= (0xffffffff >> (32 - size)); | |
483 | ||
484 | mem |= regval << shift; | |
485 | ||
486 | if ((shift += size) > bitsize) | |
487 | error (_("size of all masks is larger than the register")); | |
488 | ||
489 | if (shift >= 32) | |
490 | { | |
491 | *ptr++ = mem; | |
492 | bitsize -= 32; | |
493 | shift -= 32; | |
494 | ||
495 | if (shift == 0) | |
496 | mem = 0; | |
497 | else | |
498 | mem = regval >> (size - shift); | |
499 | } | |
500 | } | |
501 | ||
502 | if (shift > 0) | |
503 | *ptr = mem; | |
504 | ||
505 | /* Copy value to target byte order. */ | |
506 | ptr = value; | |
507 | mem = *ptr; | |
508 | ||
ac7936df | 509 | if (gdbarch_byte_order (regcache->arch ()) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
510 | for (i = 0; i < bytesize; i++) |
511 | { | |
512 | if ((i & 3) == 0) | |
513 | mem = *ptr++; | |
514 | buffer[bytesize - i - 1] = mem & 0xff; | |
515 | mem >>= 8; | |
516 | } | |
517 | else | |
518 | for (i = 0; i < bytesize; i++) | |
519 | { | |
520 | if ((i & 3) == 0) | |
521 | mem = *ptr++; | |
522 | buffer[i] = mem & 0xff; | |
523 | mem >>= 8; | |
524 | } | |
05d1431c PA |
525 | |
526 | return REG_VALID; | |
ca3bf3bd DJ |
527 | } |
528 | ||
529 | ||
530 | /* Read pseudo registers. */ | |
531 | ||
05d1431c | 532 | static enum register_status |
ca3bf3bd | 533 | xtensa_pseudo_register_read (struct gdbarch *gdbarch, |
849d0ba8 | 534 | readable_regcache *regcache, |
ca3bf3bd DJ |
535 | int regnum, |
536 | gdb_byte *buffer) | |
537 | { | |
538 | DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n", | |
d93859e2 | 539 | regnum, xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd | 540 | |
bdb4c075 | 541 | /* Read aliases a0..a15, if this is a Windowed ABI. */ |
6b50c0b0 | 542 | if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers |
94a0e877 | 543 | && (regnum >= gdbarch_tdep (gdbarch)->a0_base) |
6b50c0b0 | 544 | && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) |
ca3bf3bd | 545 | { |
c185f580 | 546 | ULONGEST value; |
05d1431c | 547 | enum register_status status; |
ca3bf3bd | 548 | |
03f50fc8 YQ |
549 | status = regcache->raw_read (gdbarch_tdep (gdbarch)->wb_regnum, |
550 | &value); | |
05d1431c PA |
551 | if (status != REG_VALID) |
552 | return status; | |
c185f580 | 553 | regnum = arreg_number (gdbarch, regnum, value); |
ca3bf3bd DJ |
554 | } |
555 | ||
bdb4c075 | 556 | /* We can always read non-pseudo registers. */ |
6b50c0b0 | 557 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
03f50fc8 | 558 | return regcache->raw_read (regnum, buffer); |
94a0e877 MG |
559 | |
560 | /* We have to find out how to deal with priveleged registers. | |
561 | Let's treat them as pseudo-registers, but we cannot read/write them. */ | |
562 | ||
0d0bf81a MF |
563 | else if (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only |
564 | || regnum < gdbarch_tdep (gdbarch)->a0_base) | |
94a0e877 MG |
565 | { |
566 | buffer[0] = (gdb_byte)0; | |
567 | buffer[1] = (gdb_byte)0; | |
568 | buffer[2] = (gdb_byte)0; | |
569 | buffer[3] = (gdb_byte)0; | |
05d1431c | 570 | return REG_VALID; |
94a0e877 | 571 | } |
ca3bf3bd | 572 | /* Pseudo registers. */ |
f6efe3f8 | 573 | else if (regnum >= 0 && regnum < gdbarch_num_cooked_regs (gdbarch)) |
ca3bf3bd | 574 | { |
6b50c0b0 | 575 | xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd | 576 | xtensa_register_type_t type = reg->type; |
6b50c0b0 | 577 | int flags = gdbarch_tdep (gdbarch)->target_flags; |
ca3bf3bd | 578 | |
bdb4c075 | 579 | /* We cannot read Unknown or Unmapped registers. */ |
ca3bf3bd DJ |
580 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) |
581 | { | |
582 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
583 | { | |
584 | warning (_("cannot read register %s"), | |
d93859e2 | 585 | xtensa_register_name (gdbarch, regnum)); |
05d1431c | 586 | return REG_VALID; |
ca3bf3bd DJ |
587 | } |
588 | } | |
589 | ||
590 | /* Some targets cannot read TIE register files. */ | |
591 | else if (type == xtRegisterTypeTieRegfile) | |
dda83cd7 | 592 | { |
ca3bf3bd DJ |
593 | /* Use 'fetch' to get register? */ |
594 | if (flags & xtTargetFlagsUseFetchStore) | |
595 | { | |
596 | warning (_("cannot read register")); | |
05d1431c | 597 | return REG_VALID; |
ca3bf3bd DJ |
598 | } |
599 | ||
600 | /* On some targets (esp. simulators), we can always read the reg. */ | |
601 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
602 | { | |
603 | warning (_("cannot read register")); | |
05d1431c | 604 | return REG_VALID; |
ca3bf3bd DJ |
605 | } |
606 | } | |
607 | ||
608 | /* We can always read mapped registers. */ | |
609 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) | |
05d1431c | 610 | return xtensa_register_read_masked (regcache, reg, buffer); |
ca3bf3bd DJ |
611 | |
612 | /* Assume that we can read the register. */ | |
03f50fc8 | 613 | return regcache->raw_read (regnum, buffer); |
ca3bf3bd | 614 | } |
ca3bf3bd DJ |
615 | else |
616 | internal_error (__FILE__, __LINE__, | |
617 | _("invalid register number %d"), regnum); | |
618 | } | |
619 | ||
620 | ||
621 | /* Write pseudo registers. */ | |
622 | ||
623 | static void | |
624 | xtensa_pseudo_register_write (struct gdbarch *gdbarch, | |
625 | struct regcache *regcache, | |
626 | int regnum, | |
627 | const gdb_byte *buffer) | |
628 | { | |
629 | DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n", | |
d93859e2 | 630 | regnum, xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd | 631 | |
30baf67b | 632 | /* Renumber register, if aliases a0..a15 on Windowed ABI. */ |
6b50c0b0 | 633 | if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers |
94a0e877 | 634 | && (regnum >= gdbarch_tdep (gdbarch)->a0_base) |
6b50c0b0 | 635 | && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) |
ca3bf3bd | 636 | { |
c185f580 AH |
637 | ULONGEST value; |
638 | regcache_raw_read_unsigned (regcache, | |
639 | gdbarch_tdep (gdbarch)->wb_regnum, &value); | |
640 | regnum = arreg_number (gdbarch, regnum, value); | |
ca3bf3bd DJ |
641 | } |
642 | ||
643 | /* We can always write 'core' registers. | |
644 | Note: We might have converted Ax->ARy. */ | |
6b50c0b0 | 645 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
10eaee5f | 646 | regcache->raw_write (regnum, buffer); |
ca3bf3bd | 647 | |
94a0e877 MG |
648 | /* We have to find out how to deal with priveleged registers. |
649 | Let's treat them as pseudo-registers, but we cannot read/write them. */ | |
650 | ||
651 | else if (regnum < gdbarch_tdep (gdbarch)->a0_base) | |
652 | { | |
653 | return; | |
654 | } | |
ca3bf3bd | 655 | /* Pseudo registers. */ |
f6efe3f8 | 656 | else if (regnum >= 0 && regnum < gdbarch_num_cooked_regs (gdbarch)) |
ca3bf3bd | 657 | { |
6b50c0b0 | 658 | xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd | 659 | xtensa_register_type_t type = reg->type; |
6b50c0b0 | 660 | int flags = gdbarch_tdep (gdbarch)->target_flags; |
ca3bf3bd | 661 | |
bdb4c075 MG |
662 | /* On most targets, we cannot write registers |
663 | of type "Unknown" or "Unmapped". */ | |
ca3bf3bd | 664 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) |
dda83cd7 | 665 | { |
ca3bf3bd DJ |
666 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) |
667 | { | |
668 | warning (_("cannot write register %s"), | |
d93859e2 | 669 | xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd DJ |
670 | return; |
671 | } | |
672 | } | |
673 | ||
674 | /* Some targets cannot read TIE register files. */ | |
675 | else if (type == xtRegisterTypeTieRegfile) | |
dda83cd7 | 676 | { |
ca3bf3bd DJ |
677 | /* Use 'store' to get register? */ |
678 | if (flags & xtTargetFlagsUseFetchStore) | |
679 | { | |
680 | warning (_("cannot write register")); | |
681 | return; | |
682 | } | |
683 | ||
684 | /* On some targets (esp. simulators), we can always write | |
685 | the register. */ | |
ca3bf3bd DJ |
686 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) |
687 | { | |
688 | warning (_("cannot write register")); | |
689 | return; | |
690 | } | |
691 | } | |
692 | ||
693 | /* We can always write mapped registers. */ | |
694 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) | |
dda83cd7 | 695 | { |
9c9acae0 | 696 | xtensa_register_write_masked (regcache, reg, buffer); |
ca3bf3bd DJ |
697 | return; |
698 | } | |
699 | ||
700 | /* Assume that we can write the register. */ | |
10eaee5f | 701 | regcache->raw_write (regnum, buffer); |
ca3bf3bd | 702 | } |
ca3bf3bd DJ |
703 | else |
704 | internal_error (__FILE__, __LINE__, | |
705 | _("invalid register number %d"), regnum); | |
706 | } | |
707 | ||
ca3bf3bd DJ |
708 | static struct reggroup *xtensa_ar_reggroup; |
709 | static struct reggroup *xtensa_user_reggroup; | |
710 | static struct reggroup *xtensa_vectra_reggroup; | |
7b871568 | 711 | static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR]; |
ca3bf3bd DJ |
712 | |
713 | static void | |
714 | xtensa_init_reggroups (void) | |
715 | { | |
98689b25 | 716 | int i; |
98689b25 | 717 | |
ca3bf3bd DJ |
718 | xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP); |
719 | xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP); | |
720 | xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP); | |
ca3bf3bd | 721 | |
98689b25 | 722 | for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) |
9c3cc999 | 723 | xtensa_cp[i] = reggroup_new (xstrprintf ("cp%d", i), USER_REGGROUP); |
7b871568 | 724 | } |
ca3bf3bd DJ |
725 | |
726 | static void | |
727 | xtensa_add_reggroups (struct gdbarch *gdbarch) | |
728 | { | |
7b871568 MG |
729 | int i; |
730 | ||
731 | /* Predefined groups. */ | |
ca3bf3bd DJ |
732 | reggroup_add (gdbarch, all_reggroup); |
733 | reggroup_add (gdbarch, save_reggroup); | |
734 | reggroup_add (gdbarch, restore_reggroup); | |
735 | reggroup_add (gdbarch, system_reggroup); | |
7b871568 MG |
736 | reggroup_add (gdbarch, vector_reggroup); |
737 | reggroup_add (gdbarch, general_reggroup); | |
738 | reggroup_add (gdbarch, float_reggroup); | |
739 | ||
740 | /* Xtensa-specific groups. */ | |
741 | reggroup_add (gdbarch, xtensa_ar_reggroup); | |
742 | reggroup_add (gdbarch, xtensa_user_reggroup); | |
743 | reggroup_add (gdbarch, xtensa_vectra_reggroup); | |
ca3bf3bd | 744 | |
7b871568 MG |
745 | for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) |
746 | reggroup_add (gdbarch, xtensa_cp[i]); | |
ca3bf3bd DJ |
747 | } |
748 | ||
7b871568 MG |
749 | static int |
750 | xtensa_coprocessor_register_group (struct reggroup *group) | |
751 | { | |
752 | int i; | |
753 | ||
754 | for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) | |
755 | if (group == xtensa_cp[i]) | |
756 | return i; | |
757 | ||
758 | return -1; | |
759 | } | |
ca3bf3bd DJ |
760 | |
761 | #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \ | |
762 | | XTENSA_REGISTER_FLAGS_WRITABLE \ | |
763 | | XTENSA_REGISTER_FLAGS_VOLATILE) | |
764 | ||
765 | #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \ | |
766 | | XTENSA_REGISTER_FLAGS_WRITABLE) | |
767 | ||
768 | static int | |
769 | xtensa_register_reggroup_p (struct gdbarch *gdbarch, | |
770 | int regnum, | |
24b21115 | 771 | struct reggroup *group) |
ca3bf3bd | 772 | { |
6b50c0b0 | 773 | xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd DJ |
774 | xtensa_register_type_t type = reg->type; |
775 | xtensa_register_group_t rg = reg->group; | |
7b871568 | 776 | int cp_number; |
ca3bf3bd | 777 | |
57041825 MG |
778 | if (group == save_reggroup) |
779 | /* Every single register should be included into the list of registers | |
780 | to be watched for changes while using -data-list-changed-registers. */ | |
781 | return 1; | |
782 | ||
ca3bf3bd DJ |
783 | /* First, skip registers that are not visible to this target |
784 | (unknown and unmapped registers when not using ISS). */ | |
785 | ||
786 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) | |
787 | return 0; | |
788 | if (group == all_reggroup) | |
789 | return 1; | |
790 | if (group == xtensa_ar_reggroup) | |
791 | return rg & xtRegisterGroupAddrReg; | |
792 | if (group == xtensa_user_reggroup) | |
793 | return rg & xtRegisterGroupUser; | |
794 | if (group == float_reggroup) | |
795 | return rg & xtRegisterGroupFloat; | |
796 | if (group == general_reggroup) | |
797 | return rg & xtRegisterGroupGeneral; | |
ca3bf3bd DJ |
798 | if (group == system_reggroup) |
799 | return rg & xtRegisterGroupState; | |
800 | if (group == vector_reggroup || group == xtensa_vectra_reggroup) | |
801 | return rg & xtRegisterGroupVectra; | |
57041825 | 802 | if (group == restore_reggroup) |
6b50c0b0 | 803 | return (regnum < gdbarch_num_regs (gdbarch) |
ca3bf3bd | 804 | && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID); |
1448a0a2 PM |
805 | cp_number = xtensa_coprocessor_register_group (group); |
806 | if (cp_number >= 0) | |
7b871568 | 807 | return rg & (xtRegisterGroupCP0 << cp_number); |
ca3bf3bd DJ |
808 | else |
809 | return 1; | |
810 | } | |
811 | ||
812 | ||
ca3bf3bd DJ |
813 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
814 | in the general-purpose register set REGSET to register cache | |
bdb4c075 | 815 | REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */ |
ca3bf3bd DJ |
816 | |
817 | static void | |
818 | xtensa_supply_gregset (const struct regset *regset, | |
819 | struct regcache *rc, | |
820 | int regnum, | |
821 | const void *gregs, | |
822 | size_t len) | |
823 | { | |
19ba03f4 | 824 | const xtensa_elf_gregset_t *regs = (const xtensa_elf_gregset_t *) gregs; |
ac7936df | 825 | struct gdbarch *gdbarch = rc->arch (); |
ca3bf3bd DJ |
826 | int i; |
827 | ||
cce7e648 | 828 | DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum); |
ca3bf3bd | 829 | |
6b50c0b0 | 830 | if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1) |
73e1c03f | 831 | rc->raw_supply (gdbarch_pc_regnum (gdbarch), (char *) ®s->pc); |
6b50c0b0 | 832 | if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1) |
73e1c03f | 833 | rc->raw_supply (gdbarch_ps_regnum (gdbarch), (char *) ®s->ps); |
6b50c0b0 | 834 | if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1) |
73e1c03f SM |
835 | rc->raw_supply (gdbarch_tdep (gdbarch)->wb_regnum, |
836 | (char *) ®s->windowbase); | |
6b50c0b0 | 837 | if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1) |
73e1c03f SM |
838 | rc->raw_supply (gdbarch_tdep (gdbarch)->ws_regnum, |
839 | (char *) ®s->windowstart); | |
6b50c0b0 | 840 | if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1) |
73e1c03f SM |
841 | rc->raw_supply (gdbarch_tdep (gdbarch)->lbeg_regnum, |
842 | (char *) ®s->lbeg); | |
6b50c0b0 | 843 | if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1) |
73e1c03f SM |
844 | rc->raw_supply (gdbarch_tdep (gdbarch)->lend_regnum, |
845 | (char *) ®s->lend); | |
6b50c0b0 | 846 | if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1) |
73e1c03f SM |
847 | rc->raw_supply (gdbarch_tdep (gdbarch)->lcount_regnum, |
848 | (char *) ®s->lcount); | |
6b50c0b0 | 849 | if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1) |
73e1c03f SM |
850 | rc->raw_supply (gdbarch_tdep (gdbarch)->sar_regnum, |
851 | (char *) ®s->sar); | |
6b50c0b0 UW |
852 | if (regnum >=gdbarch_tdep (gdbarch)->ar_base |
853 | && regnum < gdbarch_tdep (gdbarch)->ar_base | |
854 | + gdbarch_tdep (gdbarch)->num_aregs) | |
73e1c03f SM |
855 | rc->raw_supply |
856 | (regnum, (char *) ®s->ar[regnum - gdbarch_tdep (gdbarch)->ar_base]); | |
ca3bf3bd DJ |
857 | else if (regnum == -1) |
858 | { | |
6b50c0b0 | 859 | for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i) |
73e1c03f SM |
860 | rc->raw_supply (gdbarch_tdep (gdbarch)->ar_base + i, |
861 | (char *) ®s->ar[i]); | |
ca3bf3bd DJ |
862 | } |
863 | } | |
864 | ||
865 | ||
866 | /* Xtensa register set. */ | |
867 | ||
868 | static struct regset | |
869 | xtensa_gregset = | |
870 | { | |
871 | NULL, | |
872 | xtensa_supply_gregset | |
873 | }; | |
874 | ||
875 | ||
97094034 | 876 | /* Iterate over supported core file register note sections. */ |
ca3bf3bd | 877 | |
97094034 AA |
878 | static void |
879 | xtensa_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
880 | iterate_over_regset_sections_cb *cb, | |
881 | void *cb_data, | |
882 | const struct regcache *regcache) | |
ca3bf3bd | 883 | { |
97094034 | 884 | DEBUGTRACE ("xtensa_iterate_over_regset_sections\n"); |
ca3bf3bd | 885 | |
a616bb94 AH |
886 | cb (".reg", sizeof (xtensa_elf_gregset_t), sizeof (xtensa_elf_gregset_t), |
887 | &xtensa_gregset, NULL, cb_data); | |
ca3bf3bd DJ |
888 | } |
889 | ||
890 | ||
bdb4c075 | 891 | /* Handling frames. */ |
ca3bf3bd | 892 | |
bdb4c075 MG |
893 | /* Number of registers to save in case of Windowed ABI. */ |
894 | #define XTENSA_NUM_SAVED_AREGS 12 | |
ca3bf3bd | 895 | |
bdb4c075 MG |
896 | /* Frame cache part for Windowed ABI. */ |
897 | typedef struct xtensa_windowed_frame_cache | |
ca3bf3bd | 898 | { |
ee967b5f MG |
899 | int wb; /* WINDOWBASE of the previous frame. */ |
900 | int callsize; /* Call size of this frame. */ | |
08b9c608 MG |
901 | int ws; /* WINDOWSTART of the previous frame. It keeps track of |
902 | life windows only. If there is no bit set for the | |
903 | window, that means it had been already spilled | |
904 | because of window overflow. */ | |
905 | ||
906 | /* Addresses of spilled A-registers. | |
907 | AREGS[i] == -1, if corresponding AR is alive. */ | |
ca3bf3bd | 908 | CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS]; |
bdb4c075 MG |
909 | } xtensa_windowed_frame_cache_t; |
910 | ||
911 | /* Call0 ABI Definitions. */ | |
912 | ||
581e13c1 MS |
913 | #define C0_MAXOPDS 3 /* Maximum number of operands for prologue |
914 | analysis. */ | |
bdb4c075 MG |
915 | #define C0_CLESV 12 /* Callee-saved registers are here and up. */ |
916 | #define C0_SP 1 /* Register used as SP. */ | |
917 | #define C0_FP 15 /* Register used as FP. */ | |
918 | #define C0_RA 0 /* Register used as return address. */ | |
919 | #define C0_ARGS 2 /* Register used as first arg/retval. */ | |
920 | #define C0_NARGS 6 /* Number of A-regs for args/retvals. */ | |
921 | ||
922 | /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each | |
923 | A-register where the current content of the reg came from (in terms | |
924 | of an original reg and a constant). Negative values of c0_rt[n].fp_reg | |
85102364 | 925 | mean that the original content of the register was saved to the stack. |
bdb4c075 MG |
926 | c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't |
927 | know where SP will end up until the entire prologue has been analyzed. */ | |
928 | ||
929 | #define C0_CONST -1 /* fr_reg value if register contains a constant. */ | |
930 | #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */ | |
931 | #define C0_NOSTK -1 /* to_stk value if register has not been stored. */ | |
932 | ||
933 | extern xtensa_isa xtensa_default_isa; | |
934 | ||
935 | typedef struct xtensa_c0reg | |
936 | { | |
dbab50de MG |
937 | int fr_reg; /* original register from which register content |
938 | is derived, or C0_CONST, or C0_INEXP. */ | |
939 | int fr_ofs; /* constant offset from reg, or immediate value. */ | |
940 | int to_stk; /* offset from original SP to register (4-byte aligned), | |
941 | or C0_NOSTK if register has not been saved. */ | |
bdb4c075 MG |
942 | } xtensa_c0reg_t; |
943 | ||
bdb4c075 MG |
944 | /* Frame cache part for Call0 ABI. */ |
945 | typedef struct xtensa_call0_frame_cache | |
946 | { | |
dbab50de MG |
947 | int c0_frmsz; /* Stack frame size. */ |
948 | int c0_hasfp; /* Current frame uses frame pointer. */ | |
949 | int fp_regnum; /* A-register used as FP. */ | |
950 | int c0_fp; /* Actual value of frame pointer. */ | |
85102364 | 951 | int c0_fpalign; /* Dynamic adjustment for the stack |
dbab50de MG |
952 | pointer. It's an AND mask. Zero, |
953 | if alignment was not adjusted. */ | |
954 | int c0_old_sp; /* In case of dynamic adjustment, it is | |
955 | a register holding unaligned sp. | |
956 | C0_INEXP, when undefined. */ | |
957 | int c0_sp_ofs; /* If "c0_old_sp" was spilled it's a | |
958 | stack offset. C0_NOSTK otherwise. */ | |
959 | ||
960 | xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */ | |
bdb4c075 MG |
961 | } xtensa_call0_frame_cache_t; |
962 | ||
963 | typedef struct xtensa_frame_cache | |
964 | { | |
ee967b5f | 965 | CORE_ADDR base; /* Stack pointer of this frame. */ |
08b9c608 MG |
966 | CORE_ADDR pc; /* PC of this frame at the function entry point. */ |
967 | CORE_ADDR ra; /* The raw return address of this frame. */ | |
968 | CORE_ADDR ps; /* The PS register of the previous (older) frame. */ | |
969 | CORE_ADDR prev_sp; /* Stack Pointer of the previous (older) frame. */ | |
bdb4c075 MG |
970 | int call0; /* It's a call0 framework (else windowed). */ |
971 | union | |
972 | { | |
973 | xtensa_windowed_frame_cache_t wd; /* call0 == false. */ | |
974 | xtensa_call0_frame_cache_t c0; /* call0 == true. */ | |
975 | }; | |
ca3bf3bd DJ |
976 | } xtensa_frame_cache_t; |
977 | ||
978 | ||
979 | static struct xtensa_frame_cache * | |
bdb4c075 | 980 | xtensa_alloc_frame_cache (int windowed) |
ca3bf3bd DJ |
981 | { |
982 | xtensa_frame_cache_t *cache; | |
983 | int i; | |
984 | ||
985 | DEBUGTRACE ("xtensa_alloc_frame_cache ()\n"); | |
986 | ||
987 | cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t); | |
988 | ||
989 | cache->base = 0; | |
990 | cache->pc = 0; | |
991 | cache->ra = 0; | |
ca3bf3bd | 992 | cache->ps = 0; |
ca3bf3bd | 993 | cache->prev_sp = 0; |
bdb4c075 MG |
994 | cache->call0 = !windowed; |
995 | if (cache->call0) | |
996 | { | |
997 | cache->c0.c0_frmsz = -1; | |
998 | cache->c0.c0_hasfp = 0; | |
999 | cache->c0.fp_regnum = -1; | |
1000 | cache->c0.c0_fp = -1; | |
dbab50de MG |
1001 | cache->c0.c0_fpalign = 0; |
1002 | cache->c0.c0_old_sp = C0_INEXP; | |
1003 | cache->c0.c0_sp_ofs = C0_NOSTK; | |
ca3bf3bd | 1004 | |
bdb4c075 MG |
1005 | for (i = 0; i < C0_NREGS; i++) |
1006 | { | |
1007 | cache->c0.c0_rt[i].fr_reg = i; | |
1008 | cache->c0.c0_rt[i].fr_ofs = 0; | |
1009 | cache->c0.c0_rt[i].to_stk = C0_NOSTK; | |
1010 | } | |
1011 | } | |
1012 | else | |
1013 | { | |
1014 | cache->wd.wb = 0; | |
ee967b5f | 1015 | cache->wd.ws = 0; |
bdb4c075 | 1016 | cache->wd.callsize = -1; |
ca3bf3bd | 1017 | |
bdb4c075 MG |
1018 | for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++) |
1019 | cache->wd.aregs[i] = -1; | |
1020 | } | |
ca3bf3bd DJ |
1021 | return cache; |
1022 | } | |
1023 | ||
1024 | ||
1025 | static CORE_ADDR | |
1026 | xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
1027 | { | |
1028 | return address & ~15; | |
1029 | } | |
1030 | ||
1031 | ||
1032 | static CORE_ADDR | |
1033 | xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1034 | { | |
ff7a4c00 | 1035 | gdb_byte buf[8]; |
0dfff4cb | 1036 | CORE_ADDR pc; |
ca3bf3bd | 1037 | |
a74ce742 PM |
1038 | DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n", |
1039 | host_address_to_string (next_frame)); | |
ca3bf3bd | 1040 | |
6b50c0b0 | 1041 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1042 | pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
ca3bf3bd | 1043 | |
0dfff4cb | 1044 | DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc); |
ca3bf3bd | 1045 | |
0dfff4cb | 1046 | return pc; |
ca3bf3bd DJ |
1047 | } |
1048 | ||
1049 | ||
1050 | static struct frame_id | |
5142f611 | 1051 | xtensa_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
ca3bf3bd DJ |
1052 | { |
1053 | CORE_ADDR pc, fp; | |
ca3bf3bd | 1054 | |
5142f611 | 1055 | /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */ |
ca3bf3bd | 1056 | |
5142f611 MG |
1057 | pc = get_frame_pc (this_frame); |
1058 | fp = get_frame_register_unsigned | |
1059 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); | |
ca3bf3bd DJ |
1060 | |
1061 | /* Make dummy frame ID unique by adding a constant. */ | |
bdb4c075 | 1062 | return frame_id_build (fp + SP_ALIGNMENT, pc); |
ca3bf3bd DJ |
1063 | } |
1064 | ||
08b9c608 MG |
1065 | /* Returns true, if instruction to execute next is unique to Xtensa Window |
1066 | Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */ | |
1067 | ||
1068 | static int | |
1069 | xtensa_window_interrupt_insn (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1070 | { | |
1071 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1072 | unsigned int insn = read_memory_integer (pc, 4, byte_order); | |
1073 | unsigned int code; | |
1074 | ||
1075 | if (byte_order == BFD_ENDIAN_BIG) | |
1076 | { | |
1077 | /* Check, if this is L32E or S32E. */ | |
1078 | code = insn & 0xf000ff00; | |
1079 | if ((code == 0x00009000) || (code == 0x00009400)) | |
1080 | return 1; | |
1081 | /* Check, if this is RFWU or RFWO. */ | |
1082 | code = insn & 0xffffff00; | |
1083 | return ((code == 0x00430000) || (code == 0x00530000)); | |
1084 | } | |
1085 | else | |
1086 | { | |
1087 | /* Check, if this is L32E or S32E. */ | |
1088 | code = insn & 0x00ff000f; | |
1089 | if ((code == 0x090000) || (code == 0x490000)) | |
1090 | return 1; | |
1091 | /* Check, if this is RFWU or RFWO. */ | |
1092 | code = insn & 0x00ffffff; | |
1093 | return ((code == 0x00003400) || (code == 0x00003500)); | |
1094 | } | |
1095 | } | |
1096 | ||
ee967b5f MG |
1097 | /* Returns the best guess about which register is a frame pointer |
1098 | for the function containing CURRENT_PC. */ | |
1099 | ||
d4709618 MG |
1100 | #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */ |
1101 | #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */ | |
ee967b5f MG |
1102 | |
1103 | static unsigned int | |
1104 | xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc) | |
1105 | { | |
1106 | #define RETURN_FP goto done | |
1107 | ||
1108 | unsigned int fp_regnum = gdbarch_tdep (gdbarch)->a0_base + 1; | |
1109 | CORE_ADDR start_addr; | |
1110 | xtensa_isa isa; | |
1111 | xtensa_insnbuf ins, slot; | |
948f8e3d | 1112 | gdb_byte ibuf[XTENSA_ISA_BSZ]; |
ee967b5f MG |
1113 | CORE_ADDR ia, bt, ba; |
1114 | xtensa_format ifmt; | |
1115 | int ilen, islots, is; | |
1116 | xtensa_opcode opc; | |
1117 | const char *opcname; | |
1118 | ||
1119 | find_pc_partial_function (current_pc, NULL, &start_addr, NULL); | |
1120 | if (start_addr == 0) | |
1121 | return fp_regnum; | |
1122 | ||
ee967b5f MG |
1123 | isa = xtensa_default_isa; |
1124 | gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); | |
1125 | ins = xtensa_insnbuf_alloc (isa); | |
1126 | slot = xtensa_insnbuf_alloc (isa); | |
1127 | ba = 0; | |
1128 | ||
1129 | for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen) | |
1130 | { | |
1131 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
dda83cd7 | 1132 | { |
ee967b5f MG |
1133 | ba = ia; |
1134 | bt = (ba + XTENSA_ISA_BSZ) < current_pc | |
1135 | ? ba + XTENSA_ISA_BSZ : current_pc; | |
d4709618 MG |
1136 | if (target_read_memory (ba, ibuf, bt - ba) != 0) |
1137 | RETURN_FP; | |
ee967b5f MG |
1138 | } |
1139 | ||
1140 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
1141 | ifmt = xtensa_format_decode (isa, ins); | |
1142 | if (ifmt == XTENSA_UNDEFINED) | |
1143 | RETURN_FP; | |
1144 | ilen = xtensa_format_length (isa, ifmt); | |
1145 | if (ilen == XTENSA_UNDEFINED) | |
1146 | RETURN_FP; | |
1147 | islots = xtensa_format_num_slots (isa, ifmt); | |
1148 | if (islots == XTENSA_UNDEFINED) | |
1149 | RETURN_FP; | |
1150 | ||
1151 | for (is = 0; is < islots; ++is) | |
1152 | { | |
1153 | if (xtensa_format_get_slot (isa, ifmt, is, ins, slot)) | |
1154 | RETURN_FP; | |
1155 | ||
1156 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
1157 | if (opc == XTENSA_UNDEFINED) | |
1158 | RETURN_FP; | |
1159 | ||
1160 | opcname = xtensa_opcode_name (isa, opc); | |
1161 | ||
1162 | if (strcasecmp (opcname, "mov.n") == 0 | |
1163 | || strcasecmp (opcname, "or") == 0) | |
1164 | { | |
1165 | unsigned int register_operand; | |
1166 | ||
1167 | /* Possible candidate for setting frame pointer | |
581e13c1 | 1168 | from A1. This is what we are looking for. */ |
ee967b5f MG |
1169 | |
1170 | if (xtensa_operand_get_field (isa, opc, 1, ifmt, | |
1171 | is, slot, ®ister_operand) != 0) | |
1172 | RETURN_FP; | |
1173 | if (xtensa_operand_decode (isa, opc, 1, ®ister_operand) != 0) | |
1174 | RETURN_FP; | |
1175 | if (register_operand == 1) /* Mov{.n} FP A1. */ | |
1176 | { | |
1177 | if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, | |
1178 | ®ister_operand) != 0) | |
1179 | RETURN_FP; | |
1180 | if (xtensa_operand_decode (isa, opc, 0, | |
1181 | ®ister_operand) != 0) | |
1182 | RETURN_FP; | |
1183 | ||
581e13c1 MS |
1184 | fp_regnum |
1185 | = gdbarch_tdep (gdbarch)->a0_base + register_operand; | |
ee967b5f MG |
1186 | RETURN_FP; |
1187 | } | |
1188 | } | |
1189 | ||
1190 | if ( | |
1191 | /* We have problems decoding the memory. */ | |
1192 | opcname == NULL | |
1193 | || strcasecmp (opcname, "ill") == 0 | |
1194 | || strcasecmp (opcname, "ill.n") == 0 | |
1195 | /* Hit planted breakpoint. */ | |
1196 | || strcasecmp (opcname, "break") == 0 | |
1197 | || strcasecmp (opcname, "break.n") == 0 | |
1198 | /* Flow control instructions finish prologue. */ | |
1199 | || xtensa_opcode_is_branch (isa, opc) > 0 | |
1200 | || xtensa_opcode_is_jump (isa, opc) > 0 | |
1201 | || xtensa_opcode_is_loop (isa, opc) > 0 | |
1202 | || xtensa_opcode_is_call (isa, opc) > 0 | |
1203 | || strcasecmp (opcname, "simcall") == 0 | |
1204 | || strcasecmp (opcname, "syscall") == 0) | |
1205 | /* Can not continue analysis. */ | |
1206 | RETURN_FP; | |
1207 | } | |
1208 | } | |
1209 | done: | |
1210 | xtensa_insnbuf_free(isa, slot); | |
1211 | xtensa_insnbuf_free(isa, ins); | |
1212 | return fp_regnum; | |
1213 | } | |
1214 | ||
bdb4c075 MG |
1215 | /* The key values to identify the frame using "cache" are |
1216 | ||
ee967b5f | 1217 | cache->base = SP (or best guess about FP) of this frame; |
bdb4c075 | 1218 | cache->pc = entry-PC (entry point of the frame function); |
581e13c1 | 1219 | cache->prev_sp = SP of the previous frame. */ |
bdb4c075 MG |
1220 | |
1221 | static void | |
5142f611 | 1222 | call0_frame_cache (struct frame_info *this_frame, |
dbab50de | 1223 | xtensa_frame_cache_t *cache, CORE_ADDR pc); |
ca3bf3bd | 1224 | |
08b9c608 MG |
1225 | static void |
1226 | xtensa_window_interrupt_frame_cache (struct frame_info *this_frame, | |
1227 | xtensa_frame_cache_t *cache, | |
1228 | CORE_ADDR pc); | |
1229 | ||
ca3bf3bd | 1230 | static struct xtensa_frame_cache * |
5142f611 | 1231 | xtensa_frame_cache (struct frame_info *this_frame, void **this_cache) |
ca3bf3bd DJ |
1232 | { |
1233 | xtensa_frame_cache_t *cache; | |
ca3bf3bd | 1234 | CORE_ADDR ra, wb, ws, pc, sp, ps; |
5142f611 | 1235 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e17a4113 | 1236 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
ee967b5f | 1237 | unsigned int fp_regnum; |
98689b25 | 1238 | int windowed, ps_regnum; |
ca3bf3bd | 1239 | |
ca3bf3bd | 1240 | if (*this_cache) |
19ba03f4 | 1241 | return (struct xtensa_frame_cache *) *this_cache; |
ca3bf3bd | 1242 | |
98689b25 MG |
1243 | pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch)); |
1244 | ps_regnum = gdbarch_ps_regnum (gdbarch); | |
68d6df83 MG |
1245 | ps = (ps_regnum >= 0 |
1246 | ? get_frame_register_unsigned (this_frame, ps_regnum) : TX_PS); | |
98689b25 MG |
1247 | |
1248 | windowed = windowing_enabled (gdbarch, ps); | |
bdb4c075 | 1249 | |
ca3bf3bd | 1250 | /* Get pristine xtensa-frame. */ |
bdb4c075 | 1251 | cache = xtensa_alloc_frame_cache (windowed); |
ca3bf3bd DJ |
1252 | *this_cache = cache; |
1253 | ||
bdb4c075 | 1254 | if (windowed) |
ca3bf3bd | 1255 | { |
a08b52b5 | 1256 | LONGEST op1; |
98689b25 | 1257 | |
bdb4c075 | 1258 | /* Get WINDOWBASE, WINDOWSTART, and PS registers. */ |
5142f611 MG |
1259 | wb = get_frame_register_unsigned (this_frame, |
1260 | gdbarch_tdep (gdbarch)->wb_regnum); | |
1261 | ws = get_frame_register_unsigned (this_frame, | |
1262 | gdbarch_tdep (gdbarch)->ws_regnum); | |
ca3bf3bd | 1263 | |
a08b52b5 MF |
1264 | if (safe_read_memory_integer (pc, 1, byte_order, &op1) |
1265 | && XTENSA_IS_ENTRY (gdbarch, op1)) | |
ca3bf3bd | 1266 | { |
bdb4c075 | 1267 | int callinc = CALLINC (ps); |
5142f611 MG |
1268 | ra = get_frame_register_unsigned |
1269 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + callinc * 4); | |
bdb4c075 MG |
1270 | |
1271 | /* ENTRY hasn't been executed yet, therefore callsize is still 0. */ | |
1272 | cache->wd.callsize = 0; | |
1273 | cache->wd.wb = wb; | |
1274 | cache->wd.ws = ws; | |
5142f611 MG |
1275 | cache->prev_sp = get_frame_register_unsigned |
1276 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); | |
ee967b5f MG |
1277 | |
1278 | /* This only can be the outermost frame since we are | |
1279 | just about to execute ENTRY. SP hasn't been set yet. | |
1280 | We can assume any frame size, because it does not | |
1281 | matter, and, let's fake frame base in cache. */ | |
98689b25 | 1282 | cache->base = cache->prev_sp - 16; |
ee967b5f MG |
1283 | |
1284 | cache->pc = pc; | |
1285 | cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff); | |
1286 | cache->ps = (ps & ~PS_CALLINC_MASK) | |
1287 | | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT); | |
1288 | ||
1289 | return cache; | |
bdb4c075 MG |
1290 | } |
1291 | else | |
1292 | { | |
ee967b5f | 1293 | fp_regnum = xtensa_scan_prologue (gdbarch, pc); |
5142f611 MG |
1294 | ra = get_frame_register_unsigned (this_frame, |
1295 | gdbarch_tdep (gdbarch)->a0_base); | |
bdb4c075 | 1296 | cache->wd.callsize = WINSIZE (ra); |
304fe255 | 1297 | cache->wd.wb = (wb - cache->wd.callsize / 4) |
6b50c0b0 | 1298 | & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1); |
bdb4c075 | 1299 | cache->wd.ws = ws & ~(1 << wb); |
ca3bf3bd | 1300 | |
5142f611 | 1301 | cache->pc = get_frame_func (this_frame); |
f6402f18 | 1302 | cache->ra = (pc & 0xc0000000) | (ra & 0x3fffffff); |
ee967b5f MG |
1303 | cache->ps = (ps & ~PS_CALLINC_MASK) |
1304 | | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT); | |
1305 | } | |
bdb4c075 MG |
1306 | |
1307 | if (cache->wd.ws == 0) | |
ca3bf3bd | 1308 | { |
bdb4c075 | 1309 | int i; |
ca3bf3bd | 1310 | |
bdb4c075 | 1311 | /* Set A0...A3. */ |
5142f611 MG |
1312 | sp = get_frame_register_unsigned |
1313 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16; | |
bdb4c075 MG |
1314 | |
1315 | for (i = 0; i < 4; i++, sp += 4) | |
1316 | { | |
1317 | cache->wd.aregs[i] = sp; | |
1318 | } | |
ca3bf3bd | 1319 | |
bdb4c075 | 1320 | if (cache->wd.callsize > 4) |
ca3bf3bd | 1321 | { |
bdb4c075 | 1322 | /* Set A4...A7/A11. */ |
ee967b5f | 1323 | /* Get the SP of the frame previous to the previous one. |
dda83cd7 | 1324 | To achieve this, we have to dereference SP twice. */ |
e17a4113 UW |
1325 | sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order); |
1326 | sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order); | |
bdb4c075 MG |
1327 | sp -= cache->wd.callsize * 4; |
1328 | ||
ee967b5f | 1329 | for ( i = 4; i < cache->wd.callsize; i++, sp += 4) |
bdb4c075 MG |
1330 | { |
1331 | cache->wd.aregs[i] = sp; | |
1332 | } | |
ca3bf3bd DJ |
1333 | } |
1334 | } | |
ca3bf3bd | 1335 | |
bdb4c075 | 1336 | if ((cache->prev_sp == 0) && ( ra != 0 )) |
08b9c608 MG |
1337 | /* If RA is equal to 0 this frame is an outermost frame. Leave |
1338 | cache->prev_sp unchanged marking the boundary of the frame stack. */ | |
ca3bf3bd | 1339 | { |
ee967b5f | 1340 | if ((cache->wd.ws & (1 << cache->wd.wb)) == 0) |
bdb4c075 MG |
1341 | { |
1342 | /* Register window overflow already happened. | |
85102364 | 1343 | We can read caller's SP from the proper spill location. */ |
5142f611 MG |
1344 | sp = get_frame_register_unsigned |
1345 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); | |
e17a4113 | 1346 | cache->prev_sp = read_memory_integer (sp - 12, 4, byte_order); |
bdb4c075 MG |
1347 | } |
1348 | else | |
1349 | { | |
1350 | /* Read caller's frame SP directly from the previous window. */ | |
ee967b5f | 1351 | int regnum = arreg_number |
91d8eb23 | 1352 | (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1, |
304fe255 | 1353 | cache->wd.wb); |
ca3bf3bd | 1354 | |
08b9c608 | 1355 | cache->prev_sp = xtensa_read_register (regnum); |
bdb4c075 | 1356 | } |
ca3bf3bd DJ |
1357 | } |
1358 | } | |
08b9c608 MG |
1359 | else if (xtensa_window_interrupt_insn (gdbarch, pc)) |
1360 | { | |
1361 | /* Execution stopped inside Xtensa Window Interrupt Handler. */ | |
1362 | ||
1363 | xtensa_window_interrupt_frame_cache (this_frame, cache, pc); | |
1364 | /* Everything was set already, including cache->base. */ | |
1365 | return cache; | |
1366 | } | |
bdb4c075 MG |
1367 | else /* Call0 framework. */ |
1368 | { | |
dbab50de | 1369 | call0_frame_cache (this_frame, cache, pc); |
ee967b5f | 1370 | fp_regnum = cache->c0.fp_regnum; |
bdb4c075 | 1371 | } |
ca3bf3bd | 1372 | |
5142f611 | 1373 | cache->base = get_frame_register_unsigned (this_frame, fp_regnum); |
ca3bf3bd | 1374 | |
ca3bf3bd DJ |
1375 | return cache; |
1376 | } | |
1377 | ||
dbab50de MG |
1378 | static int xtensa_session_once_reported = 1; |
1379 | ||
1380 | /* Report a problem with prologue analysis while doing backtracing. | |
85102364 | 1381 | But, do it only once to avoid annoying repeated messages. */ |
dbab50de | 1382 | |
4e6ca6d5 MG |
1383 | static void |
1384 | warning_once (void) | |
dbab50de MG |
1385 | { |
1386 | if (xtensa_session_once_reported == 0) | |
1387 | warning (_("\ | |
1388 | \nUnrecognised function prologue. Stack trace cannot be resolved. \ | |
1389 | This message will not be repeated in this session.\n")); | |
1390 | ||
1391 | xtensa_session_once_reported = 1; | |
1392 | } | |
1393 | ||
1394 | ||
ca3bf3bd | 1395 | static void |
5142f611 | 1396 | xtensa_frame_this_id (struct frame_info *this_frame, |
ca3bf3bd DJ |
1397 | void **this_cache, |
1398 | struct frame_id *this_id) | |
1399 | { | |
1400 | struct xtensa_frame_cache *cache = | |
5142f611 | 1401 | xtensa_frame_cache (this_frame, this_cache); |
ca3bf3bd DJ |
1402 | |
1403 | if (cache->prev_sp == 0) | |
1404 | return; | |
1405 | ||
5142f611 | 1406 | (*this_id) = frame_id_build (cache->prev_sp, cache->pc); |
bdb4c075 | 1407 | } |
ca3bf3bd | 1408 | |
5142f611 MG |
1409 | static struct value * |
1410 | xtensa_frame_prev_register (struct frame_info *this_frame, | |
ca3bf3bd | 1411 | void **this_cache, |
5142f611 | 1412 | int regnum) |
ca3bf3bd | 1413 | { |
5142f611 MG |
1414 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1415 | struct xtensa_frame_cache *cache; | |
1416 | ULONGEST saved_reg = 0; | |
ca3bf3bd DJ |
1417 | int done = 1; |
1418 | ||
5142f611 MG |
1419 | if (*this_cache == NULL) |
1420 | *this_cache = xtensa_frame_cache (this_frame, this_cache); | |
19ba03f4 | 1421 | cache = (struct xtensa_frame_cache *) *this_cache; |
ca3bf3bd | 1422 | |
6b50c0b0 | 1423 | if (regnum ==gdbarch_pc_regnum (gdbarch)) |
bdb4c075 | 1424 | saved_reg = cache->ra; |
6b50c0b0 | 1425 | else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1) |
bdb4c075 MG |
1426 | saved_reg = cache->prev_sp; |
1427 | else if (!cache->call0) | |
ca3bf3bd | 1428 | { |
6b50c0b0 | 1429 | if (regnum == gdbarch_tdep (gdbarch)->ws_regnum) |
ee967b5f | 1430 | saved_reg = cache->wd.ws; |
6b50c0b0 | 1431 | else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum) |
bdb4c075 | 1432 | saved_reg = cache->wd.wb; |
6b50c0b0 | 1433 | else if (regnum == gdbarch_ps_regnum (gdbarch)) |
bdb4c075 | 1434 | saved_reg = cache->ps; |
ca3bf3bd | 1435 | else |
bdb4c075 | 1436 | done = 0; |
ca3bf3bd | 1437 | } |
ca3bf3bd DJ |
1438 | else |
1439 | done = 0; | |
1440 | ||
1441 | if (done) | |
5142f611 | 1442 | return frame_unwind_got_constant (this_frame, regnum, saved_reg); |
ca3bf3bd | 1443 | |
bdb4c075 | 1444 | if (!cache->call0) /* Windowed ABI. */ |
ca3bf3bd | 1445 | { |
ee967b5f MG |
1446 | /* Convert A-register numbers to AR-register numbers, |
1447 | if we deal with A-register. */ | |
94a0e877 | 1448 | if (regnum >= gdbarch_tdep (gdbarch)->a0_base |
dda83cd7 | 1449 | && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15) |
ee967b5f | 1450 | regnum = arreg_number (gdbarch, regnum, cache->wd.wb); |
ca3bf3bd | 1451 | |
ee967b5f | 1452 | /* Check, if we deal with AR-register saved on stack. */ |
6b50c0b0 UW |
1453 | if (regnum >= gdbarch_tdep (gdbarch)->ar_base |
1454 | && regnum <= (gdbarch_tdep (gdbarch)->ar_base | |
1455 | + gdbarch_tdep (gdbarch)->num_aregs)) | |
bdb4c075 | 1456 | { |
ee967b5f | 1457 | int areg = areg_number (gdbarch, regnum, cache->wd.wb); |
ca3bf3bd | 1458 | |
bdb4c075 MG |
1459 | if (areg >= 0 |
1460 | && areg < XTENSA_NUM_SAVED_AREGS | |
1461 | && cache->wd.aregs[areg] != -1) | |
5142f611 MG |
1462 | return frame_unwind_got_memory (this_frame, regnum, |
1463 | cache->wd.aregs[areg]); | |
ca3bf3bd DJ |
1464 | } |
1465 | } | |
bdb4c075 MG |
1466 | else /* Call0 ABI. */ |
1467 | { | |
6b50c0b0 UW |
1468 | int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base |
1469 | && regnum <= (gdbarch_tdep (gdbarch)->ar_base | |
304fe255 | 1470 | + C0_NREGS)) |
6b50c0b0 | 1471 | ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum; |
ca3bf3bd | 1472 | |
bdb4c075 MG |
1473 | if (reg < C0_NREGS) |
1474 | { | |
1475 | CORE_ADDR spe; | |
1476 | int stkofs; | |
1477 | ||
1478 | /* If register was saved in the prologue, retrieve it. */ | |
1479 | stkofs = cache->c0.c0_rt[reg].to_stk; | |
1480 | if (stkofs != C0_NOSTK) | |
1481 | { | |
1482 | /* Determine SP on entry based on FP. */ | |
1483 | spe = cache->c0.c0_fp | |
1484 | - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs; | |
5142f611 | 1485 | |
581e13c1 MS |
1486 | return frame_unwind_got_memory (this_frame, regnum, |
1487 | spe + stkofs); | |
bdb4c075 MG |
1488 | } |
1489 | } | |
1490 | } | |
1491 | ||
1492 | /* All other registers have been either saved to | |
1493 | the stack or are still alive in the processor. */ | |
ca3bf3bd | 1494 | |
5142f611 | 1495 | return frame_unwind_got_register (this_frame, regnum, regnum); |
ca3bf3bd DJ |
1496 | } |
1497 | ||
1498 | ||
1499 | static const struct frame_unwind | |
5142f611 | 1500 | xtensa_unwind = |
ca3bf3bd | 1501 | { |
a154d838 | 1502 | "xtensa prologue", |
ca3bf3bd | 1503 | NORMAL_FRAME, |
8fbca658 | 1504 | default_frame_unwind_stop_reason, |
ca3bf3bd | 1505 | xtensa_frame_this_id, |
5142f611 MG |
1506 | xtensa_frame_prev_register, |
1507 | NULL, | |
1508 | default_frame_sniffer | |
ca3bf3bd DJ |
1509 | }; |
1510 | ||
ca3bf3bd | 1511 | static CORE_ADDR |
5142f611 | 1512 | xtensa_frame_base_address (struct frame_info *this_frame, void **this_cache) |
ca3bf3bd DJ |
1513 | { |
1514 | struct xtensa_frame_cache *cache = | |
5142f611 | 1515 | xtensa_frame_cache (this_frame, this_cache); |
ca3bf3bd DJ |
1516 | |
1517 | return cache->base; | |
1518 | } | |
1519 | ||
1520 | static const struct frame_base | |
1521 | xtensa_frame_base = | |
1522 | { | |
5142f611 | 1523 | &xtensa_unwind, |
ca3bf3bd DJ |
1524 | xtensa_frame_base_address, |
1525 | xtensa_frame_base_address, | |
1526 | xtensa_frame_base_address | |
1527 | }; | |
1528 | ||
1529 | ||
1530 | static void | |
1531 | xtensa_extract_return_value (struct type *type, | |
1532 | struct regcache *regcache, | |
1533 | void *dst) | |
1534 | { | |
ac7936df | 1535 | struct gdbarch *gdbarch = regcache->arch (); |
19ba03f4 | 1536 | bfd_byte *valbuf = (bfd_byte *) dst; |
ca3bf3bd DJ |
1537 | int len = TYPE_LENGTH (type); |
1538 | ULONGEST pc, wb; | |
1539 | int callsize, areg; | |
1540 | int offset = 0; | |
1541 | ||
1542 | DEBUGTRACE ("xtensa_extract_return_value (...)\n"); | |
1543 | ||
1544 | gdb_assert(len > 0); | |
1545 | ||
6b50c0b0 | 1546 | if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
bdb4c075 MG |
1547 | { |
1548 | /* First, we have to find the caller window in the register file. */ | |
6b50c0b0 | 1549 | regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc); |
91d8eb23 | 1550 | callsize = extract_call_winsize (gdbarch, pc); |
ca3bf3bd | 1551 | |
bdb4c075 MG |
1552 | /* On Xtensa, we can return up to 4 words (or 2 for call12). */ |
1553 | if (len > (callsize > 8 ? 8 : 16)) | |
1554 | internal_error (__FILE__, __LINE__, | |
581e13c1 MS |
1555 | _("cannot extract return value of %d bytes long"), |
1556 | len); | |
ca3bf3bd | 1557 | |
bdb4c075 MG |
1558 | /* Get the register offset of the return |
1559 | register (A2) in the caller window. */ | |
304fe255 | 1560 | regcache_raw_read_unsigned |
6b50c0b0 | 1561 | (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb); |
ee967b5f | 1562 | areg = arreg_number (gdbarch, |
91d8eb23 | 1563 | gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb); |
bdb4c075 MG |
1564 | } |
1565 | else | |
1566 | { | |
1567 | /* No windowing hardware - Call0 ABI. */ | |
94a0e877 | 1568 | areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS; |
bdb4c075 | 1569 | } |
ca3bf3bd DJ |
1570 | |
1571 | DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len); | |
1572 | ||
6b50c0b0 | 1573 | if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1574 | offset = 4 - len; |
1575 | ||
1576 | for (; len > 0; len -= 4, areg++, valbuf += 4) | |
1577 | { | |
1578 | if (len < 4) | |
502fe83e | 1579 | regcache->raw_read_part (areg, offset, len, valbuf); |
ca3bf3bd | 1580 | else |
0b883586 | 1581 | regcache->raw_read (areg, valbuf); |
ca3bf3bd DJ |
1582 | } |
1583 | } | |
1584 | ||
1585 | ||
1586 | static void | |
1587 | xtensa_store_return_value (struct type *type, | |
1588 | struct regcache *regcache, | |
1589 | const void *dst) | |
1590 | { | |
ac7936df | 1591 | struct gdbarch *gdbarch = regcache->arch (); |
19ba03f4 | 1592 | const bfd_byte *valbuf = (const bfd_byte *) dst; |
ca3bf3bd DJ |
1593 | unsigned int areg; |
1594 | ULONGEST pc, wb; | |
1595 | int callsize; | |
1596 | int len = TYPE_LENGTH (type); | |
1597 | int offset = 0; | |
1598 | ||
1599 | DEBUGTRACE ("xtensa_store_return_value (...)\n"); | |
1600 | ||
6b50c0b0 | 1601 | if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
bdb4c075 | 1602 | { |
6b50c0b0 UW |
1603 | regcache_raw_read_unsigned |
1604 | (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb); | |
1605 | regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc); | |
91d8eb23 | 1606 | callsize = extract_call_winsize (gdbarch, pc); |
ca3bf3bd | 1607 | |
bdb4c075 MG |
1608 | if (len > (callsize > 8 ? 8 : 16)) |
1609 | internal_error (__FILE__, __LINE__, | |
cc1defb1 KS |
1610 | _("unimplemented for this length: %s"), |
1611 | pulongest (TYPE_LENGTH (type))); | |
ee967b5f MG |
1612 | areg = arreg_number (gdbarch, |
1613 | gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb); | |
ca3bf3bd | 1614 | |
bdb4c075 | 1615 | DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n", |
dda83cd7 | 1616 | callsize, (int) wb); |
bdb4c075 MG |
1617 | } |
1618 | else | |
1619 | { | |
94a0e877 | 1620 | areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS; |
bdb4c075 | 1621 | } |
ca3bf3bd | 1622 | |
6b50c0b0 | 1623 | if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1624 | offset = 4 - len; |
1625 | ||
ca3bf3bd DJ |
1626 | for (; len > 0; len -= 4, areg++, valbuf += 4) |
1627 | { | |
1628 | if (len < 4) | |
4f0420fd | 1629 | regcache->raw_write_part (areg, offset, len, valbuf); |
ca3bf3bd | 1630 | else |
10eaee5f | 1631 | regcache->raw_write (areg, valbuf); |
ca3bf3bd DJ |
1632 | } |
1633 | } | |
1634 | ||
1635 | ||
bdb4c075 | 1636 | static enum return_value_convention |
ca3bf3bd | 1637 | xtensa_return_value (struct gdbarch *gdbarch, |
6a3a010b | 1638 | struct value *function, |
ca3bf3bd DJ |
1639 | struct type *valtype, |
1640 | struct regcache *regcache, | |
1641 | gdb_byte *readbuf, | |
1642 | const gdb_byte *writebuf) | |
1643 | { | |
bdb4c075 | 1644 | /* Structures up to 16 bytes are returned in registers. */ |
ca3bf3bd | 1645 | |
78134374 SM |
1646 | int struct_return = ((valtype->code () == TYPE_CODE_STRUCT |
1647 | || valtype->code () == TYPE_CODE_UNION | |
1648 | || valtype->code () == TYPE_CODE_ARRAY) | |
ca3bf3bd DJ |
1649 | && TYPE_LENGTH (valtype) > 16); |
1650 | ||
1651 | if (struct_return) | |
1652 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1653 | ||
1654 | DEBUGTRACE ("xtensa_return_value(...)\n"); | |
1655 | ||
1656 | if (writebuf != NULL) | |
1657 | { | |
1658 | xtensa_store_return_value (valtype, regcache, writebuf); | |
1659 | } | |
1660 | ||
1661 | if (readbuf != NULL) | |
1662 | { | |
1663 | gdb_assert (!struct_return); | |
1664 | xtensa_extract_return_value (valtype, regcache, readbuf); | |
1665 | } | |
1666 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1667 | } | |
1668 | ||
1669 | ||
1670 | /* DUMMY FRAME */ | |
1671 | ||
1672 | static CORE_ADDR | |
1673 | xtensa_push_dummy_call (struct gdbarch *gdbarch, | |
1674 | struct value *function, | |
1675 | struct regcache *regcache, | |
1676 | CORE_ADDR bp_addr, | |
1677 | int nargs, | |
1678 | struct value **args, | |
1679 | CORE_ADDR sp, | |
cf84fa6b | 1680 | function_call_return_method return_method, |
ca3bf3bd DJ |
1681 | CORE_ADDR struct_addr) |
1682 | { | |
e17a4113 | 1683 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
ca3bf3bd | 1684 | int size, onstack_size; |
ff7a4c00 | 1685 | gdb_byte *buf = (gdb_byte *) alloca (16); |
ca3bf3bd DJ |
1686 | CORE_ADDR ra, ps; |
1687 | struct argument_info | |
1688 | { | |
1689 | const bfd_byte *contents; | |
1690 | int length; | |
1691 | int onstack; /* onstack == 0 => in reg */ | |
1692 | int align; /* alignment */ | |
1693 | union | |
1694 | { | |
581e13c1 MS |
1695 | int offset; /* stack offset if on stack. */ |
1696 | int regno; /* regno if in register. */ | |
ca3bf3bd DJ |
1697 | } u; |
1698 | }; | |
1699 | ||
1700 | struct argument_info *arg_info = | |
1701 | (struct argument_info *) alloca (nargs * sizeof (struct argument_info)); | |
1702 | ||
1703 | CORE_ADDR osp = sp; | |
1704 | ||
1705 | DEBUGTRACE ("xtensa_push_dummy_call (...)\n"); | |
1706 | ||
1707 | if (xtensa_debug_level > 3) | |
1708 | { | |
ca3bf3bd | 1709 | DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs); |
cf84fa6b | 1710 | DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, return_method=%d, " |
ca3bf3bd | 1711 | "struct_addr=0x%x\n", |
cf84fa6b | 1712 | (int) sp, (int) return_method, (int) struct_addr); |
ca3bf3bd | 1713 | |
b926417a | 1714 | for (int i = 0; i < nargs; i++) |
dda83cd7 | 1715 | { |
ca3bf3bd DJ |
1716 | struct value *arg = args[i]; |
1717 | struct type *arg_type = check_typedef (value_type (arg)); | |
cc1defb1 | 1718 | fprintf_unfiltered (gdb_stdlog, "%2d: %s %3s ", i, |
3329c4b5 | 1719 | host_address_to_string (arg), |
cc1defb1 | 1720 | pulongest (TYPE_LENGTH (arg_type))); |
78134374 | 1721 | switch (arg_type->code ()) |
ca3bf3bd DJ |
1722 | { |
1723 | case TYPE_CODE_INT: | |
1724 | fprintf_unfiltered (gdb_stdlog, "int"); | |
1725 | break; | |
1726 | case TYPE_CODE_STRUCT: | |
1727 | fprintf_unfiltered (gdb_stdlog, "struct"); | |
1728 | break; | |
1729 | default: | |
78134374 | 1730 | fprintf_unfiltered (gdb_stdlog, "%3d", arg_type->code ()); |
ca3bf3bd DJ |
1731 | break; |
1732 | } | |
3329c4b5 PM |
1733 | fprintf_unfiltered (gdb_stdlog, " %s\n", |
1734 | host_address_to_string (value_contents (arg))); | |
ca3bf3bd DJ |
1735 | } |
1736 | } | |
1737 | ||
1738 | /* First loop: collect information. | |
1739 | Cast into type_long. (This shouldn't happen often for C because | |
1740 | GDB already does this earlier.) It's possible that GDB could | |
1741 | do it all the time but it's harmless to leave this code here. */ | |
1742 | ||
1743 | size = 0; | |
1744 | onstack_size = 0; | |
ca3bf3bd | 1745 | |
cf84fa6b | 1746 | if (return_method == return_method_struct) |
ca3bf3bd DJ |
1747 | size = REGISTER_SIZE; |
1748 | ||
b926417a | 1749 | for (int i = 0; i < nargs; i++) |
ca3bf3bd DJ |
1750 | { |
1751 | struct argument_info *info = &arg_info[i]; | |
1752 | struct value *arg = args[i]; | |
1753 | struct type *arg_type = check_typedef (value_type (arg)); | |
1754 | ||
78134374 | 1755 | switch (arg_type->code ()) |
ca3bf3bd DJ |
1756 | { |
1757 | case TYPE_CODE_INT: | |
1758 | case TYPE_CODE_BOOL: | |
1759 | case TYPE_CODE_CHAR: | |
1760 | case TYPE_CODE_RANGE: | |
1761 | case TYPE_CODE_ENUM: | |
1762 | ||
1763 | /* Cast argument to long if necessary as the mask does it too. */ | |
0dfff4cb UW |
1764 | if (TYPE_LENGTH (arg_type) |
1765 | < TYPE_LENGTH (builtin_type (gdbarch)->builtin_long)) | |
ca3bf3bd | 1766 | { |
0dfff4cb | 1767 | arg_type = builtin_type (gdbarch)->builtin_long; |
ca3bf3bd DJ |
1768 | arg = value_cast (arg_type, arg); |
1769 | } | |
bdb4c075 MG |
1770 | /* Aligment is equal to the type length for the basic types. */ |
1771 | info->align = TYPE_LENGTH (arg_type); | |
ca3bf3bd DJ |
1772 | break; |
1773 | ||
1774 | case TYPE_CODE_FLT: | |
1775 | ||
1776 | /* Align doubles correctly. */ | |
0dfff4cb UW |
1777 | if (TYPE_LENGTH (arg_type) |
1778 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_double)) | |
1779 | info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_double); | |
ca3bf3bd | 1780 | else |
0dfff4cb | 1781 | info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long); |
ca3bf3bd DJ |
1782 | break; |
1783 | ||
1784 | case TYPE_CODE_STRUCT: | |
1785 | default: | |
0dfff4cb | 1786 | info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long); |
ca3bf3bd DJ |
1787 | break; |
1788 | } | |
1789 | info->length = TYPE_LENGTH (arg_type); | |
1790 | info->contents = value_contents (arg); | |
1791 | ||
1792 | /* Align size and onstack_size. */ | |
1793 | size = (size + info->align - 1) & ~(info->align - 1); | |
1794 | onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1); | |
1795 | ||
91d8eb23 | 1796 | if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch)) |
ca3bf3bd DJ |
1797 | { |
1798 | info->onstack = 1; | |
1799 | info->u.offset = onstack_size; | |
1800 | onstack_size += info->length; | |
1801 | } | |
1802 | else | |
1803 | { | |
1804 | info->onstack = 0; | |
91d8eb23 | 1805 | info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE; |
ca3bf3bd DJ |
1806 | } |
1807 | size += info->length; | |
1808 | } | |
1809 | ||
1810 | /* Adjust the stack pointer and align it. */ | |
1811 | sp = align_down (sp - onstack_size, SP_ALIGNMENT); | |
1812 | ||
bdb4c075 | 1813 | /* Simulate MOVSP, if Windowed ABI. */ |
6b50c0b0 | 1814 | if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
304fe255 | 1815 | && (sp != osp)) |
ca3bf3bd DJ |
1816 | { |
1817 | read_memory (osp - 16, buf, 16); | |
1818 | write_memory (sp - 16, buf, 16); | |
1819 | } | |
1820 | ||
1821 | /* Second Loop: Load arguments. */ | |
1822 | ||
cf84fa6b | 1823 | if (return_method == return_method_struct) |
ca3bf3bd | 1824 | { |
e17a4113 | 1825 | store_unsigned_integer (buf, REGISTER_SIZE, byte_order, struct_addr); |
b66f5587 | 1826 | regcache->cooked_write (ARG_1ST (gdbarch), buf); |
ca3bf3bd DJ |
1827 | } |
1828 | ||
b926417a | 1829 | for (int i = 0; i < nargs; i++) |
ca3bf3bd DJ |
1830 | { |
1831 | struct argument_info *info = &arg_info[i]; | |
1832 | ||
1833 | if (info->onstack) | |
1834 | { | |
1835 | int n = info->length; | |
1836 | CORE_ADDR offset = sp + info->u.offset; | |
1837 | ||
1838 | /* Odd-sized structs are aligned to the lower side of a memory | |
1839 | word in big-endian mode and require a shift. This only | |
1840 | applies for structures smaller than one word. */ | |
1841 | ||
4c6b5505 | 1842 | if (n < REGISTER_SIZE |
6b50c0b0 | 1843 | && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1844 | offset += (REGISTER_SIZE - n); |
1845 | ||
1846 | write_memory (offset, info->contents, info->length); | |
1847 | ||
1848 | } | |
1849 | else | |
1850 | { | |
1851 | int n = info->length; | |
1852 | const bfd_byte *cp = info->contents; | |
1853 | int r = info->u.regno; | |
1854 | ||
1855 | /* Odd-sized structs are aligned to the lower side of registers in | |
1856 | big-endian mode and require a shift. The odd-sized leftover will | |
1857 | be at the end. Note that this is only true for structures smaller | |
1858 | than REGISTER_SIZE; for larger odd-sized structures the excess | |
1859 | will be left-aligned in the register on both endiannesses. */ | |
1860 | ||
e17a4113 | 1861 | if (n < REGISTER_SIZE && byte_order == BFD_ENDIAN_BIG) |
ca3bf3bd | 1862 | { |
e17a4113 UW |
1863 | ULONGEST v; |
1864 | v = extract_unsigned_integer (cp, REGISTER_SIZE, byte_order); | |
ca3bf3bd DJ |
1865 | v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT); |
1866 | ||
e17a4113 | 1867 | store_unsigned_integer (buf, REGISTER_SIZE, byte_order, v); |
b66f5587 | 1868 | regcache->cooked_write (r, buf); |
ca3bf3bd DJ |
1869 | |
1870 | cp += REGISTER_SIZE; | |
1871 | n -= REGISTER_SIZE; | |
1872 | r++; | |
1873 | } | |
1874 | else | |
1875 | while (n > 0) | |
1876 | { | |
b66f5587 | 1877 | regcache->cooked_write (r, cp); |
ca3bf3bd | 1878 | |
ca3bf3bd DJ |
1879 | cp += REGISTER_SIZE; |
1880 | n -= REGISTER_SIZE; | |
1881 | r++; | |
1882 | } | |
1883 | } | |
1884 | } | |
1885 | ||
ca3bf3bd | 1886 | /* Set the return address of dummy frame to the dummy address. |
bdb4c075 | 1887 | The return address for the current function (in A0) is |
85102364 | 1888 | saved in the dummy frame, so we can safely overwrite A0 here. */ |
ca3bf3bd | 1889 | |
6b50c0b0 | 1890 | if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
bdb4c075 | 1891 | { |
98689b25 | 1892 | ULONGEST val; |
68d6df83 | 1893 | |
bdb4c075 | 1894 | ra = (bp_addr & 0x3fffffff) | 0x40000000; |
98689b25 MG |
1895 | regcache_raw_read_unsigned (regcache, gdbarch_ps_regnum (gdbarch), &val); |
1896 | ps = (unsigned long) val & ~0x00030000; | |
304fe255 | 1897 | regcache_cooked_write_unsigned |
6b50c0b0 | 1898 | (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra); |
bdb4c075 | 1899 | regcache_cooked_write_unsigned (regcache, |
6b50c0b0 | 1900 | gdbarch_ps_regnum (gdbarch), |
bdb4c075 | 1901 | ps | 0x00010000); |
94a0e877 MG |
1902 | |
1903 | /* All the registers have been saved. After executing | |
1904 | dummy call, they all will be restored. So it's safe | |
1905 | to modify WINDOWSTART register to make it look like there | |
1906 | is only one register window corresponding to WINDOWEBASE. */ | |
1907 | ||
0b883586 | 1908 | regcache->raw_read (gdbarch_tdep (gdbarch)->wb_regnum, buf); |
e17a4113 UW |
1909 | regcache_cooked_write_unsigned |
1910 | (regcache, gdbarch_tdep (gdbarch)->ws_regnum, | |
1911 | 1 << extract_unsigned_integer (buf, 4, byte_order)); | |
bdb4c075 MG |
1912 | } |
1913 | else | |
1914 | { | |
1915 | /* Simulate CALL0: write RA into A0 register. */ | |
304fe255 | 1916 | regcache_cooked_write_unsigned |
94a0e877 | 1917 | (regcache, gdbarch_tdep (gdbarch)->a0_base, bp_addr); |
bdb4c075 | 1918 | } |
ca3bf3bd DJ |
1919 | |
1920 | /* Set new stack pointer and return it. */ | |
304fe255 | 1921 | regcache_cooked_write_unsigned (regcache, |
6b50c0b0 | 1922 | gdbarch_tdep (gdbarch)->a0_base + 1, sp); |
ca3bf3bd DJ |
1923 | /* Make dummy frame ID unique by adding a constant. */ |
1924 | return sp + SP_ALIGNMENT; | |
1925 | } | |
1926 | ||
cd6c3b4f YQ |
1927 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
1928 | ||
d19280ad YQ |
1929 | static int |
1930 | xtensa_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
1931 | { | |
1932 | if (gdbarch_tdep (gdbarch)->isa_use_density_instructions) | |
1933 | return 2; | |
1934 | else | |
1935 | return 4; | |
1936 | } | |
ca3bf3bd DJ |
1937 | |
1938 | /* Return a breakpoint for the current location of PC. We always use | |
1939 | the density version if we have density instructions (regardless of the | |
1940 | current instruction at PC), and use regular instructions otherwise. */ | |
1941 | ||
1942 | #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 } | |
1943 | #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 } | |
1944 | #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f } | |
1945 | #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 } | |
1946 | ||
cd6c3b4f YQ |
1947 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
1948 | ||
d19280ad YQ |
1949 | static const gdb_byte * |
1950 | xtensa_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
ca3bf3bd | 1951 | { |
d19280ad | 1952 | *size = kind; |
ca3bf3bd | 1953 | |
d19280ad | 1954 | if (kind == 4) |
ca3bf3bd | 1955 | { |
d19280ad YQ |
1956 | static unsigned char big_breakpoint[] = BIG_BREAKPOINT; |
1957 | static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT; | |
1958 | ||
67d57894 | 1959 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d19280ad | 1960 | return big_breakpoint; |
ca3bf3bd | 1961 | else |
d19280ad | 1962 | return little_breakpoint; |
ca3bf3bd DJ |
1963 | } |
1964 | else | |
1965 | { | |
d19280ad YQ |
1966 | static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT; |
1967 | static unsigned char density_little_breakpoint[] | |
1968 | = DENSITY_LITTLE_BREAKPOINT; | |
1969 | ||
67d57894 | 1970 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d19280ad | 1971 | return density_big_breakpoint; |
ca3bf3bd | 1972 | else |
d19280ad | 1973 | return density_little_breakpoint; |
ca3bf3bd DJ |
1974 | } |
1975 | } | |
1976 | ||
bdb4c075 MG |
1977 | /* Call0 ABI support routines. */ |
1978 | ||
f976a05d MG |
1979 | /* Return true, if PC points to "ret" or "ret.n". */ |
1980 | ||
1981 | static int | |
1982 | call0_ret (CORE_ADDR start_pc, CORE_ADDR finish_pc) | |
1983 | { | |
1984 | #define RETURN_RET goto done | |
1985 | xtensa_isa isa; | |
1986 | xtensa_insnbuf ins, slot; | |
948f8e3d | 1987 | gdb_byte ibuf[XTENSA_ISA_BSZ]; |
f976a05d MG |
1988 | CORE_ADDR ia, bt, ba; |
1989 | xtensa_format ifmt; | |
1990 | int ilen, islots, is; | |
1991 | xtensa_opcode opc; | |
1992 | const char *opcname; | |
1993 | int found_ret = 0; | |
1994 | ||
1995 | isa = xtensa_default_isa; | |
1996 | gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); | |
1997 | ins = xtensa_insnbuf_alloc (isa); | |
1998 | slot = xtensa_insnbuf_alloc (isa); | |
1999 | ba = 0; | |
2000 | ||
2001 | for (ia = start_pc, bt = ia; ia < finish_pc ; ia += ilen) | |
2002 | { | |
2003 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
dda83cd7 | 2004 | { |
f976a05d MG |
2005 | ba = ia; |
2006 | bt = (ba + XTENSA_ISA_BSZ) < finish_pc | |
2007 | ? ba + XTENSA_ISA_BSZ : finish_pc; | |
2008 | if (target_read_memory (ba, ibuf, bt - ba) != 0 ) | |
2009 | RETURN_RET; | |
2010 | } | |
2011 | ||
2012 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
2013 | ifmt = xtensa_format_decode (isa, ins); | |
2014 | if (ifmt == XTENSA_UNDEFINED) | |
2015 | RETURN_RET; | |
2016 | ilen = xtensa_format_length (isa, ifmt); | |
2017 | if (ilen == XTENSA_UNDEFINED) | |
2018 | RETURN_RET; | |
2019 | islots = xtensa_format_num_slots (isa, ifmt); | |
2020 | if (islots == XTENSA_UNDEFINED) | |
2021 | RETURN_RET; | |
2022 | ||
2023 | for (is = 0; is < islots; ++is) | |
2024 | { | |
2025 | if (xtensa_format_get_slot (isa, ifmt, is, ins, slot)) | |
2026 | RETURN_RET; | |
2027 | ||
2028 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
2029 | if (opc == XTENSA_UNDEFINED) | |
2030 | RETURN_RET; | |
2031 | ||
2032 | opcname = xtensa_opcode_name (isa, opc); | |
2033 | ||
2034 | if ((strcasecmp (opcname, "ret.n") == 0) | |
2035 | || (strcasecmp (opcname, "ret") == 0)) | |
2036 | { | |
2037 | found_ret = 1; | |
2038 | RETURN_RET; | |
2039 | } | |
2040 | } | |
2041 | } | |
2042 | done: | |
2043 | xtensa_insnbuf_free(isa, slot); | |
2044 | xtensa_insnbuf_free(isa, ins); | |
2045 | return found_ret; | |
2046 | } | |
2047 | ||
bdb4c075 MG |
2048 | /* Call0 opcode class. Opcodes are preclassified according to what they |
2049 | mean for Call0 prologue analysis, and their number of significant operands. | |
2050 | The purpose of this is to simplify prologue analysis by separating | |
2051 | instruction decoding (libisa) from the semantics of prologue analysis. */ | |
2052 | ||
68d6df83 MG |
2053 | typedef enum |
2054 | { | |
bdb4c075 MG |
2055 | c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */ |
2056 | c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */ | |
2057 | c0opc_flow, /* Flow control insn. */ | |
2058 | c0opc_entry, /* ENTRY indicates non-Call0 prologue. */ | |
2059 | c0opc_break, /* Debugger software breakpoints. */ | |
2060 | c0opc_add, /* Adding two registers. */ | |
2061 | c0opc_addi, /* Adding a register and an immediate. */ | |
dbab50de | 2062 | c0opc_and, /* Bitwise "and"-ing two registers. */ |
bdb4c075 MG |
2063 | c0opc_sub, /* Subtracting a register from a register. */ |
2064 | c0opc_mov, /* Moving a register to a register. */ | |
2065 | c0opc_movi, /* Moving an immediate to a register. */ | |
2066 | c0opc_l32r, /* Loading a literal. */ | |
08b9c608 MG |
2067 | c0opc_s32i, /* Storing word at fixed offset from a base register. */ |
2068 | c0opc_rwxsr, /* RSR, WRS, or XSR instructions. */ | |
2069 | c0opc_l32e, /* L32E instruction. */ | |
2070 | c0opc_s32e, /* S32E instruction. */ | |
2071 | c0opc_rfwo, /* RFWO instruction. */ | |
2072 | c0opc_rfwu, /* RFWU instruction. */ | |
bdb4c075 MG |
2073 | c0opc_NrOf /* Number of opcode classifications. */ |
2074 | } xtensa_insn_kind; | |
2075 | ||
08b9c608 MG |
2076 | /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */ |
2077 | ||
2078 | static int | |
2079 | rwx_special_register (const char *opcname) | |
2080 | { | |
2081 | char ch = *opcname++; | |
2082 | ||
2083 | if ((ch != 'r') && (ch != 'w') && (ch != 'x')) | |
2084 | return 0; | |
2085 | if (*opcname++ != 's') | |
2086 | return 0; | |
2087 | if (*opcname++ != 'r') | |
2088 | return 0; | |
2089 | if (*opcname++ != '.') | |
2090 | return 0; | |
2091 | ||
2092 | return 1; | |
2093 | } | |
bdb4c075 MG |
2094 | |
2095 | /* Classify an opcode based on what it means for Call0 prologue analysis. */ | |
2096 | ||
2097 | static xtensa_insn_kind | |
2098 | call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc) | |
2099 | { | |
2100 | const char *opcname; | |
2101 | xtensa_insn_kind opclass = c0opc_uninteresting; | |
2102 | ||
2103 | DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc); | |
2104 | ||
2105 | /* Get opcode name and handle special classifications. */ | |
2106 | ||
2107 | opcname = xtensa_opcode_name (isa, opc); | |
2108 | ||
2109 | if (opcname == NULL | |
2110 | || strcasecmp (opcname, "ill") == 0 | |
2111 | || strcasecmp (opcname, "ill.n") == 0) | |
2112 | opclass = c0opc_illegal; | |
2113 | else if (strcasecmp (opcname, "break") == 0 | |
2114 | || strcasecmp (opcname, "break.n") == 0) | |
2115 | opclass = c0opc_break; | |
2116 | else if (strcasecmp (opcname, "entry") == 0) | |
2117 | opclass = c0opc_entry; | |
08b9c608 MG |
2118 | else if (strcasecmp (opcname, "rfwo") == 0) |
2119 | opclass = c0opc_rfwo; | |
2120 | else if (strcasecmp (opcname, "rfwu") == 0) | |
2121 | opclass = c0opc_rfwu; | |
bdb4c075 MG |
2122 | else if (xtensa_opcode_is_branch (isa, opc) > 0 |
2123 | || xtensa_opcode_is_jump (isa, opc) > 0 | |
2124 | || xtensa_opcode_is_loop (isa, opc) > 0 | |
2125 | || xtensa_opcode_is_call (isa, opc) > 0 | |
2126 | || strcasecmp (opcname, "simcall") == 0 | |
2127 | || strcasecmp (opcname, "syscall") == 0) | |
2128 | opclass = c0opc_flow; | |
2129 | ||
2130 | /* Also, classify specific opcodes that need to be tracked. */ | |
2131 | else if (strcasecmp (opcname, "add") == 0 | |
2132 | || strcasecmp (opcname, "add.n") == 0) | |
2133 | opclass = c0opc_add; | |
dbab50de MG |
2134 | else if (strcasecmp (opcname, "and") == 0) |
2135 | opclass = c0opc_and; | |
bdb4c075 MG |
2136 | else if (strcasecmp (opcname, "addi") == 0 |
2137 | || strcasecmp (opcname, "addi.n") == 0 | |
2138 | || strcasecmp (opcname, "addmi") == 0) | |
2139 | opclass = c0opc_addi; | |
2140 | else if (strcasecmp (opcname, "sub") == 0) | |
2141 | opclass = c0opc_sub; | |
2142 | else if (strcasecmp (opcname, "mov.n") == 0 | |
2143 | || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */ | |
2144 | opclass = c0opc_mov; | |
2145 | else if (strcasecmp (opcname, "movi") == 0 | |
2146 | || strcasecmp (opcname, "movi.n") == 0) | |
2147 | opclass = c0opc_movi; | |
2148 | else if (strcasecmp (opcname, "l32r") == 0) | |
2149 | opclass = c0opc_l32r; | |
2150 | else if (strcasecmp (opcname, "s32i") == 0 | |
2151 | || strcasecmp (opcname, "s32i.n") == 0) | |
2152 | opclass = c0opc_s32i; | |
08b9c608 MG |
2153 | else if (strcasecmp (opcname, "l32e") == 0) |
2154 | opclass = c0opc_l32e; | |
2155 | else if (strcasecmp (opcname, "s32e") == 0) | |
2156 | opclass = c0opc_s32e; | |
2157 | else if (rwx_special_register (opcname)) | |
2158 | opclass = c0opc_rwxsr; | |
bdb4c075 MG |
2159 | |
2160 | return opclass; | |
2161 | } | |
2162 | ||
2163 | /* Tracks register movement/mutation for a given operation, which may | |
2164 | be within a bundle. Updates the destination register tracking info | |
2165 | accordingly. The pc is needed only for pc-relative load instructions | |
2166 | (eg. l32r). The SP register number is needed to identify stores to | |
85102364 | 2167 | the stack frame. Returns 0, if analysis was successful, non-zero |
dbab50de | 2168 | otherwise. */ |
bdb4c075 | 2169 | |
dbab50de MG |
2170 | static int |
2171 | call0_track_op (struct gdbarch *gdbarch, xtensa_c0reg_t dst[], xtensa_c0reg_t src[], | |
bdb4c075 | 2172 | xtensa_insn_kind opclass, int nods, unsigned odv[], |
dbab50de | 2173 | CORE_ADDR pc, int spreg, xtensa_frame_cache_t *cache) |
bdb4c075 | 2174 | { |
e17a4113 | 2175 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
dbab50de | 2176 | unsigned litbase, litaddr, litval; |
bdb4c075 MG |
2177 | |
2178 | switch (opclass) | |
2179 | { | |
2180 | case c0opc_addi: | |
2181 | /* 3 operands: dst, src, imm. */ | |
2182 | gdb_assert (nods == 3); | |
2183 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
2184 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2]; | |
2185 | break; | |
2186 | case c0opc_add: | |
2187 | /* 3 operands: dst, src1, src2. */ | |
08b9c608 | 2188 | gdb_assert (nods == 3); |
bdb4c075 | 2189 | if (src[odv[1]].fr_reg == C0_CONST) |
dda83cd7 | 2190 | { |
bdb4c075 MG |
2191 | dst[odv[0]].fr_reg = src[odv[2]].fr_reg; |
2192 | dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs; | |
2193 | } | |
2194 | else if (src[odv[2]].fr_reg == C0_CONST) | |
dda83cd7 | 2195 | { |
bdb4c075 MG |
2196 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; |
2197 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs; | |
2198 | } | |
2199 | else dst[odv[0]].fr_reg = C0_INEXP; | |
2200 | break; | |
dbab50de MG |
2201 | case c0opc_and: |
2202 | /* 3 operands: dst, src1, src2. */ | |
2203 | gdb_assert (nods == 3); | |
2204 | if (cache->c0.c0_fpalign == 0) | |
2205 | { | |
2206 | /* Handle dynamic stack alignment. */ | |
2207 | if ((src[odv[0]].fr_reg == spreg) && (src[odv[1]].fr_reg == spreg)) | |
2208 | { | |
2209 | if (src[odv[2]].fr_reg == C0_CONST) | |
2210 | cache->c0.c0_fpalign = src[odv[2]].fr_ofs; | |
2211 | break; | |
2212 | } | |
2213 | else if ((src[odv[0]].fr_reg == spreg) | |
2214 | && (src[odv[2]].fr_reg == spreg)) | |
2215 | { | |
2216 | if (src[odv[1]].fr_reg == C0_CONST) | |
2217 | cache->c0.c0_fpalign = src[odv[1]].fr_ofs; | |
2218 | break; | |
2219 | } | |
2220 | /* else fall through. */ | |
2221 | } | |
2222 | if (src[odv[1]].fr_reg == C0_CONST) | |
dda83cd7 | 2223 | { |
dbab50de MG |
2224 | dst[odv[0]].fr_reg = src[odv[2]].fr_reg; |
2225 | dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs & src[odv[1]].fr_ofs; | |
2226 | } | |
2227 | else if (src[odv[2]].fr_reg == C0_CONST) | |
dda83cd7 | 2228 | { |
dbab50de MG |
2229 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; |
2230 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs & src[odv[2]].fr_ofs; | |
2231 | } | |
2232 | else dst[odv[0]].fr_reg = C0_INEXP; | |
2233 | break; | |
bdb4c075 MG |
2234 | case c0opc_sub: |
2235 | /* 3 operands: dst, src1, src2. */ | |
2236 | gdb_assert (nods == 3); | |
2237 | if (src[odv[2]].fr_reg == C0_CONST) | |
dda83cd7 | 2238 | { |
bdb4c075 MG |
2239 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; |
2240 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs; | |
2241 | } | |
2242 | else dst[odv[0]].fr_reg = C0_INEXP; | |
2243 | break; | |
2244 | case c0opc_mov: | |
2245 | /* 2 operands: dst, src [, src]. */ | |
2246 | gdb_assert (nods == 2); | |
dbab50de MG |
2247 | /* First, check if it's a special case of saving unaligned SP |
2248 | to a spare register in case of dynamic stack adjustment. | |
2249 | But, only do it one time. The second time could be initializing | |
2250 | frame pointer. We don't want to overwrite the first one. */ | |
2251 | if ((odv[1] == spreg) && (cache->c0.c0_old_sp == C0_INEXP)) | |
2252 | cache->c0.c0_old_sp = odv[0]; | |
2253 | ||
bdb4c075 MG |
2254 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; |
2255 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs; | |
2256 | break; | |
2257 | case c0opc_movi: | |
2258 | /* 2 operands: dst, imm. */ | |
2259 | gdb_assert (nods == 2); | |
2260 | dst[odv[0]].fr_reg = C0_CONST; | |
2261 | dst[odv[0]].fr_ofs = odv[1]; | |
2262 | break; | |
2263 | case c0opc_l32r: | |
2264 | /* 2 operands: dst, literal offset. */ | |
2265 | gdb_assert (nods == 2); | |
dbab50de MG |
2266 | /* litbase = xtensa_get_litbase (pc); can be also used. */ |
2267 | litbase = (gdbarch_tdep (gdbarch)->litbase_regnum == -1) | |
2268 | ? 0 : xtensa_read_register | |
2269 | (gdbarch_tdep (gdbarch)->litbase_regnum); | |
bdb4c075 MG |
2270 | litaddr = litbase & 1 |
2271 | ? (litbase & ~1) + (signed)odv[1] | |
2272 | : (pc + 3 + (signed)odv[1]) & ~3; | |
e17a4113 | 2273 | litval = read_memory_integer (litaddr, 4, byte_order); |
bdb4c075 MG |
2274 | dst[odv[0]].fr_reg = C0_CONST; |
2275 | dst[odv[0]].fr_ofs = litval; | |
2276 | break; | |
2277 | case c0opc_s32i: | |
2278 | /* 3 operands: value, base, offset. */ | |
2279 | gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS); | |
dbab50de MG |
2280 | /* First, check if it's a spill for saved unaligned SP, |
2281 | when dynamic stack adjustment was applied to this frame. */ | |
2282 | if ((cache->c0.c0_fpalign != 0) /* Dynamic stack adjustment. */ | |
2283 | && (odv[1] == spreg) /* SP usage indicates spill. */ | |
2284 | && (odv[0] == cache->c0.c0_old_sp)) /* Old SP register spilled. */ | |
2285 | cache->c0.c0_sp_ofs = odv[2]; | |
2286 | ||
bdb4c075 MG |
2287 | if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */ |
2288 | && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */ | |
2289 | && src[odv[0]].fr_reg >= 0 /* Value is from a register. */ | |
2290 | && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */ | |
2291 | && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */ | |
dda83cd7 | 2292 | { |
bdb4c075 MG |
2293 | /* ISA encoding guarantees alignment. But, check it anyway. */ |
2294 | gdb_assert ((odv[2] & 3) == 0); | |
2295 | dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2]; | |
2296 | } | |
2297 | break; | |
dbab50de MG |
2298 | /* If we end up inside Window Overflow / Underflow interrupt handler |
2299 | report an error because these handlers should have been handled | |
2300 | already in a different way. */ | |
2301 | case c0opc_l32e: | |
2302 | case c0opc_s32e: | |
2303 | case c0opc_rfwo: | |
2304 | case c0opc_rfwu: | |
2305 | return 1; | |
bdb4c075 | 2306 | default: |
dbab50de | 2307 | return 1; |
bdb4c075 | 2308 | } |
dbab50de | 2309 | return 0; |
bdb4c075 MG |
2310 | } |
2311 | ||
dbab50de | 2312 | /* Analyze prologue of the function at start address to determine if it uses |
bdb4c075 | 2313 | the Call0 ABI, and if so track register moves and linear modifications |
dbab50de MG |
2314 | in the prologue up to the PC or just beyond the prologue, whichever is |
2315 | first. An 'entry' instruction indicates non-Call0 ABI and the end of the | |
2316 | prologue. The prologue may overlap non-prologue instructions but is | |
2317 | guaranteed to end by the first flow-control instruction (jump, branch, | |
2318 | call or return). Since an optimized function may move information around | |
2319 | and change the stack frame arbitrarily during the prologue, the information | |
2320 | is guaranteed valid only at the point in the function indicated by the PC. | |
bdb4c075 MG |
2321 | May be used to skip the prologue or identify the ABI, w/o tracking. |
2322 | ||
2323 | Returns: Address of first instruction after prologue, or PC (whichever | |
2324 | is first), or 0, if decoding failed (in libisa). | |
2325 | Input args: | |
2326 | start Start address of function/prologue. | |
2327 | pc Program counter to stop at. Use 0 to continue to end of prologue. | |
2328 | If 0, avoids infinite run-on in corrupt code memory by bounding | |
2329 | the scan to the end of the function if that can be determined. | |
dbab50de | 2330 | nregs Number of general registers to track. |
bdb4c075 | 2331 | InOut args: |
dbab50de | 2332 | cache Xtensa frame cache. |
bdb4c075 MG |
2333 | |
2334 | Note that these may produce useful results even if decoding fails | |
2335 | because they begin with default assumptions that analysis may change. */ | |
2336 | ||
2337 | static CORE_ADDR | |
e17a4113 | 2338 | call0_analyze_prologue (struct gdbarch *gdbarch, |
dbab50de MG |
2339 | CORE_ADDR start, CORE_ADDR pc, |
2340 | int nregs, xtensa_frame_cache_t *cache) | |
bdb4c075 MG |
2341 | { |
2342 | CORE_ADDR ia; /* Current insn address in prologue. */ | |
2343 | CORE_ADDR ba = 0; /* Current address at base of insn buffer. */ | |
2344 | CORE_ADDR bt; /* Current address at top+1 of insn buffer. */ | |
948f8e3d | 2345 | gdb_byte ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */ |
bdb4c075 MG |
2346 | xtensa_isa isa; /* libisa ISA handle. */ |
2347 | xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */ | |
2348 | xtensa_format ifmt; /* libisa instruction format. */ | |
2349 | int ilen, islots, is; /* Instruction length, nbr slots, current slot. */ | |
2350 | xtensa_opcode opc; /* Opcode in current slot. */ | |
2351 | xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */ | |
2352 | int nods; /* Opcode number of operands. */ | |
2353 | unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */ | |
2354 | xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */ | |
2355 | int j; /* General loop counter. */ | |
2356 | int fail = 0; /* Set non-zero and exit, if decoding fails. */ | |
2357 | CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */ | |
2358 | CORE_ADDR end_pc; /* The PC for the lust function insn. */ | |
2359 | ||
2360 | struct symtab_and_line prologue_sal; | |
2361 | ||
2362 | DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n", | |
2363 | (int)start, (int)pc); | |
2364 | ||
2365 | /* Try to limit the scan to the end of the function if a non-zero pc | |
2366 | arg was not supplied to avoid probing beyond the end of valid memory. | |
2367 | If memory is full of garbage that classifies as c0opc_uninteresting. | |
2368 | If this fails (eg. if no symbols) pc ends up 0 as it was. | |
26c4b26f | 2369 | Initialize the Call0 frame and register tracking info. |
bdb4c075 MG |
2370 | Assume it's Call0 until an 'entry' instruction is encountered. |
2371 | Assume we may be in the prologue until we hit a flow control instr. */ | |
2372 | ||
2373 | rtmp = NULL; | |
8179e739 | 2374 | body_pc = UINT_MAX; |
bdb4c075 MG |
2375 | end_pc = 0; |
2376 | ||
2377 | /* Find out, if we have an information about the prologue from DWARF. */ | |
2378 | prologue_sal = find_pc_line (start, 0); | |
2379 | if (prologue_sal.line != 0) /* Found debug info. */ | |
2380 | body_pc = prologue_sal.end; | |
2381 | ||
2382 | /* If we are going to analyze the prologue in general without knowing about | |
85102364 | 2383 | the current PC, make the best assumption for the end of the prologue. */ |
bdb4c075 MG |
2384 | if (pc == 0) |
2385 | { | |
2386 | find_pc_partial_function (start, 0, NULL, &end_pc); | |
325fac50 | 2387 | body_pc = std::min (end_pc, body_pc); |
bdb4c075 MG |
2388 | } |
2389 | else | |
325fac50 | 2390 | body_pc = std::min (pc, body_pc); |
bdb4c075 | 2391 | |
dbab50de MG |
2392 | cache->call0 = 1; |
2393 | rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t)); | |
bdb4c075 MG |
2394 | |
2395 | isa = xtensa_default_isa; | |
2ff5e605 | 2396 | gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); |
bdb4c075 MG |
2397 | ins = xtensa_insnbuf_alloc (isa); |
2398 | slot = xtensa_insnbuf_alloc (isa); | |
2399 | ||
2400 | for (ia = start, bt = ia; ia < body_pc ; ia += ilen) | |
2401 | { | |
2402 | /* (Re)fill instruction buffer from memory if necessary, but do not | |
dda83cd7 | 2403 | read memory beyond PC to be sure we stay within text section |
bdb4c075 MG |
2404 | (this protection only works if a non-zero pc is supplied). */ |
2405 | ||
2406 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
dda83cd7 | 2407 | { |
bdb4c075 | 2408 | ba = ia; |
2ff5e605 | 2409 | bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc; |
dbab50de MG |
2410 | if (target_read_memory (ba, ibuf, bt - ba) != 0 ) |
2411 | error (_("Unable to read target memory ...")); | |
bdb4c075 MG |
2412 | } |
2413 | ||
2414 | /* Decode format information. */ | |
2415 | ||
2416 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
2417 | ifmt = xtensa_format_decode (isa, ins); | |
2418 | if (ifmt == XTENSA_UNDEFINED) | |
2419 | { | |
2420 | fail = 1; | |
2421 | goto done; | |
2422 | } | |
2423 | ilen = xtensa_format_length (isa, ifmt); | |
2424 | if (ilen == XTENSA_UNDEFINED) | |
2425 | { | |
2426 | fail = 1; | |
2427 | goto done; | |
2428 | } | |
2429 | islots = xtensa_format_num_slots (isa, ifmt); | |
2430 | if (islots == XTENSA_UNDEFINED) | |
2431 | { | |
2432 | fail = 1; | |
2433 | goto done; | |
2434 | } | |
2435 | ||
2436 | /* Analyze a bundle or a single instruction, using a snapshot of | |
dda83cd7 | 2437 | the register tracking info as input for the entire bundle so that |
bdb4c075 | 2438 | register changes do not take effect within this bundle. */ |
ca3bf3bd | 2439 | |
bdb4c075 | 2440 | for (j = 0; j < nregs; ++j) |
dbab50de | 2441 | rtmp[j] = cache->c0.c0_rt[j]; |
bdb4c075 MG |
2442 | |
2443 | for (is = 0; is < islots; ++is) | |
dda83cd7 | 2444 | { |
bdb4c075 MG |
2445 | /* Decode a slot and classify the opcode. */ |
2446 | ||
2447 | fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot); | |
2448 | if (fail) | |
2449 | goto done; | |
2450 | ||
2451 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
dbab50de | 2452 | DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n", |
bdb4c075 MG |
2453 | (unsigned)ia, opc); |
2454 | if (opc == XTENSA_UNDEFINED) | |
2455 | opclass = c0opc_illegal; | |
2456 | else | |
2457 | opclass = call0_classify_opcode (isa, opc); | |
2458 | ||
2459 | /* Decide whether to track this opcode, ignore it, or bail out. */ | |
2460 | ||
2461 | switch (opclass) | |
2462 | { | |
2463 | case c0opc_illegal: | |
2464 | case c0opc_break: | |
2465 | fail = 1; | |
2466 | goto done; | |
2467 | ||
2468 | case c0opc_uninteresting: | |
2469 | continue; | |
2470 | ||
dbab50de MG |
2471 | case c0opc_flow: /* Flow control instructions stop analysis. */ |
2472 | case c0opc_rwxsr: /* RSR, WSR, XSR instructions stop analysis. */ | |
bdb4c075 MG |
2473 | goto done; |
2474 | ||
2475 | case c0opc_entry: | |
dbab50de | 2476 | cache->call0 = 0; |
bdb4c075 MG |
2477 | ia += ilen; /* Skip over 'entry' insn. */ |
2478 | goto done; | |
2479 | ||
2480 | default: | |
dbab50de | 2481 | cache->call0 = 1; |
bdb4c075 MG |
2482 | } |
2483 | ||
2484 | /* Only expected opcodes should get this far. */ | |
bdb4c075 MG |
2485 | |
2486 | /* Extract and decode the operands. */ | |
2487 | nods = xtensa_opcode_num_operands (isa, opc); | |
2488 | if (nods == XTENSA_UNDEFINED) | |
2489 | { | |
2490 | fail = 1; | |
2491 | goto done; | |
2492 | } | |
2493 | ||
2494 | for (j = 0; j < nods && j < C0_MAXOPDS; ++j) | |
2495 | { | |
2496 | fail = xtensa_operand_get_field (isa, opc, j, ifmt, | |
2497 | is, slot, &odv[j]); | |
2498 | if (fail) | |
2499 | goto done; | |
2500 | ||
2501 | fail = xtensa_operand_decode (isa, opc, j, &odv[j]); | |
2502 | if (fail) | |
2503 | goto done; | |
2504 | } | |
2505 | ||
2506 | /* Check operands to verify use of 'mov' assembler macro. */ | |
2507 | if (opclass == c0opc_mov && nods == 3) | |
2508 | { | |
2509 | if (odv[2] == odv[1]) | |
dbab50de MG |
2510 | { |
2511 | nods = 2; | |
2512 | if ((odv[0] == 1) && (odv[1] != 1)) | |
2513 | /* OR A1, An, An , where n != 1. | |
2514 | This means we are inside epilogue already. */ | |
2515 | goto done; | |
2516 | } | |
bdb4c075 MG |
2517 | else |
2518 | { | |
2519 | opclass = c0opc_uninteresting; | |
2520 | continue; | |
2521 | } | |
2522 | } | |
2523 | ||
2524 | /* Track register movement and modification for this operation. */ | |
dbab50de MG |
2525 | fail = call0_track_op (gdbarch, cache->c0.c0_rt, rtmp, |
2526 | opclass, nods, odv, ia, 1, cache); | |
2527 | if (fail) | |
2528 | goto done; | |
bdb4c075 MG |
2529 | } |
2530 | } | |
2531 | done: | |
2532 | DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n", | |
2533 | (unsigned)ia, fail ? "failed" : "succeeded"); | |
2534 | xtensa_insnbuf_free(isa, slot); | |
2535 | xtensa_insnbuf_free(isa, ins); | |
d4709618 | 2536 | return fail ? XTENSA_ISA_BADPC : ia; |
bdb4c075 MG |
2537 | } |
2538 | ||
5142f611 | 2539 | /* Initialize frame cache for the current frame in CALL0 ABI. */ |
bdb4c075 MG |
2540 | |
2541 | static void | |
5142f611 | 2542 | call0_frame_cache (struct frame_info *this_frame, |
dbab50de | 2543 | xtensa_frame_cache_t *cache, CORE_ADDR pc) |
bdb4c075 | 2544 | { |
5142f611 | 2545 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e17a4113 | 2546 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
bdb4c075 MG |
2547 | CORE_ADDR start_pc; /* The beginning of the function. */ |
2548 | CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */ | |
2549 | CORE_ADDR sp, fp, ra; | |
dbab50de | 2550 | int fp_regnum = C0_SP, c0_hasfp = 0, c0_frmsz = 0, prev_sp = 0, to_stk; |
bdb4c075 | 2551 | |
dbab50de MG |
2552 | sp = get_frame_register_unsigned |
2553 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); | |
2554 | fp = sp; /* Assume FP == SP until proven otherwise. */ | |
2555 | ||
bdb4c075 MG |
2556 | /* Find the beginning of the prologue of the function containing the PC |
2557 | and analyze it up to the PC or the end of the prologue. */ | |
2558 | ||
2559 | if (find_pc_partial_function (pc, NULL, &start_pc, NULL)) | |
2560 | { | |
dbab50de | 2561 | body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, C0_NREGS, cache); |
d4709618 MG |
2562 | |
2563 | if (body_pc == XTENSA_ISA_BADPC) | |
dbab50de MG |
2564 | { |
2565 | warning_once (); | |
2566 | ra = 0; | |
2567 | goto finish_frame_analysis; | |
2568 | } | |
bdb4c075 MG |
2569 | } |
2570 | ||
bdb4c075 MG |
2571 | /* Get the frame information and FP (if used) at the current PC. |
2572 | If PC is in the prologue, the prologue analysis is more reliable | |
dbab50de MG |
2573 | than DWARF info. We don't not know for sure, if PC is in the prologue, |
2574 | but we do know no calls have yet taken place, so we can almost | |
bdb4c075 MG |
2575 | certainly rely on the prologue analysis. */ |
2576 | ||
2577 | if (body_pc <= pc) | |
2578 | { | |
2579 | /* Prologue analysis was successful up to the PC. | |
dda83cd7 | 2580 | It includes the cases when PC == START_PC. */ |
bdb4c075 MG |
2581 | c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP; |
2582 | /* c0_hasfp == true means there is a frame pointer because | |
2583 | we analyzed the prologue and found that cache->c0.c0_rt[C0_FP] | |
2584 | was derived from SP. Otherwise, it would be C0_FP. */ | |
2585 | fp_regnum = c0_hasfp ? C0_FP : C0_SP; | |
2586 | c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs; | |
6b50c0b0 | 2587 | fp_regnum += gdbarch_tdep (gdbarch)->a0_base; |
bdb4c075 MG |
2588 | } |
2589 | else /* No data from the prologue analysis. */ | |
2590 | { | |
2591 | c0_hasfp = 0; | |
6b50c0b0 | 2592 | fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP; |
bdb4c075 MG |
2593 | c0_frmsz = 0; |
2594 | start_pc = pc; | |
2595 | } | |
2596 | ||
dbab50de MG |
2597 | if (cache->c0.c0_fpalign) |
2598 | { | |
2599 | /* This frame has a special prologue with a dynamic stack adjustment | |
2600 | to force an alignment, which is bigger than standard 16 bytes. */ | |
2601 | ||
2602 | CORE_ADDR unaligned_sp; | |
2603 | ||
2604 | if (cache->c0.c0_old_sp == C0_INEXP) | |
2605 | /* This can't be. Prologue code should be consistent. | |
2606 | Unaligned stack pointer should be saved in a spare register. */ | |
2607 | { | |
2608 | warning_once (); | |
2609 | ra = 0; | |
2610 | goto finish_frame_analysis; | |
2611 | } | |
2612 | ||
2613 | if (cache->c0.c0_sp_ofs == C0_NOSTK) | |
2614 | /* Saved unaligned value of SP is kept in a register. */ | |
2615 | unaligned_sp = get_frame_register_unsigned | |
2616 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_old_sp); | |
2617 | else | |
2618 | /* Get the value from stack. */ | |
2619 | unaligned_sp = (CORE_ADDR) | |
2620 | read_memory_integer (fp + cache->c0.c0_sp_ofs, 4, byte_order); | |
2621 | ||
2622 | prev_sp = unaligned_sp + c0_frmsz; | |
2623 | } | |
2624 | else | |
2625 | prev_sp = fp + c0_frmsz; | |
bdb4c075 MG |
2626 | |
2627 | /* Frame size from debug info or prologue tracking does not account for | |
2628 | alloca() and other dynamic allocations. Adjust frame size by FP - SP. */ | |
2629 | if (c0_hasfp) | |
2630 | { | |
5142f611 | 2631 | fp = get_frame_register_unsigned (this_frame, fp_regnum); |
bdb4c075 | 2632 | |
bdb4c075 MG |
2633 | /* Update the stack frame size. */ |
2634 | c0_frmsz += fp - sp; | |
2635 | } | |
2636 | ||
2637 | /* Get the return address (RA) from the stack if saved, | |
2638 | or try to get it from a register. */ | |
2639 | ||
2640 | to_stk = cache->c0.c0_rt[C0_RA].to_stk; | |
2641 | if (to_stk != C0_NOSTK) | |
2642 | ra = (CORE_ADDR) | |
e17a4113 UW |
2643 | read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk, |
2644 | 4, byte_order); | |
bdb4c075 MG |
2645 | |
2646 | else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST | |
2647 | && cache->c0.c0_rt[C0_RA].fr_ofs == 0) | |
2648 | { | |
dbab50de MG |
2649 | /* Special case for terminating backtrace at a function that wants to |
2650 | be seen as the outermost one. Such a function will clear it's RA (A0) | |
2651 | register to 0 in the prologue instead of saving its original value. */ | |
bdb4c075 MG |
2652 | ra = 0; |
2653 | } | |
2654 | else | |
2655 | { | |
dbab50de MG |
2656 | /* RA was copied to another register or (before any function call) may |
2657 | still be in the original RA register. This is not always reliable: | |
2658 | even in a leaf function, register tracking stops after prologue, and | |
2659 | even in prologue, non-prologue instructions (not tracked) may overwrite | |
2660 | RA or any register it was copied to. If likely in prologue or before | |
2661 | any call, use retracking info and hope for the best (compiler should | |
2662 | have saved RA in stack if not in a leaf function). If not in prologue, | |
2663 | too bad. */ | |
bdb4c075 MG |
2664 | |
2665 | int i; | |
1448a0a2 PM |
2666 | for (i = 0; |
2667 | (i < C0_NREGS) | |
2668 | && (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA); | |
bdb4c075 MG |
2669 | ++i); |
2670 | if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA) | |
2671 | i = C0_RA; | |
5142f611 | 2672 | if (i < C0_NREGS) |
bdb4c075 | 2673 | { |
5142f611 MG |
2674 | ra = get_frame_register_unsigned |
2675 | (this_frame, | |
2676 | gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_rt[i].fr_reg); | |
bdb4c075 MG |
2677 | } |
2678 | else ra = 0; | |
2679 | } | |
2680 | ||
dbab50de | 2681 | finish_frame_analysis: |
bdb4c075 MG |
2682 | cache->pc = start_pc; |
2683 | cache->ra = ra; | |
2684 | /* RA == 0 marks the outermost frame. Do not go past it. */ | |
2685 | cache->prev_sp = (ra != 0) ? prev_sp : 0; | |
2686 | cache->c0.fp_regnum = fp_regnum; | |
2687 | cache->c0.c0_frmsz = c0_frmsz; | |
2688 | cache->c0.c0_hasfp = c0_hasfp; | |
2689 | cache->c0.c0_fp = fp; | |
2690 | } | |
2691 | ||
08b9c608 MG |
2692 | static CORE_ADDR a0_saved; |
2693 | static CORE_ADDR a7_saved; | |
2694 | static CORE_ADDR a11_saved; | |
2695 | static int a0_was_saved; | |
2696 | static int a7_was_saved; | |
2697 | static int a11_was_saved; | |
2698 | ||
68d6df83 | 2699 | /* Simulate L32E instruction: AT <-- ref (AS + offset). */ |
08b9c608 MG |
2700 | static void |
2701 | execute_l32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb) | |
2702 | { | |
2703 | int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb); | |
2704 | int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb); | |
2705 | CORE_ADDR addr = xtensa_read_register (asreg) + offset; | |
2706 | unsigned int spilled_value | |
2707 | = read_memory_unsigned_integer (addr, 4, gdbarch_byte_order (gdbarch)); | |
2708 | ||
2709 | if ((at == 0) && !a0_was_saved) | |
2710 | { | |
2711 | a0_saved = xtensa_read_register (atreg); | |
2712 | a0_was_saved = 1; | |
2713 | } | |
2714 | else if ((at == 7) && !a7_was_saved) | |
2715 | { | |
2716 | a7_saved = xtensa_read_register (atreg); | |
2717 | a7_was_saved = 1; | |
2718 | } | |
2719 | else if ((at == 11) && !a11_was_saved) | |
2720 | { | |
2721 | a11_saved = xtensa_read_register (atreg); | |
2722 | a11_was_saved = 1; | |
2723 | } | |
2724 | ||
2725 | xtensa_write_register (atreg, spilled_value); | |
2726 | } | |
2727 | ||
68d6df83 | 2728 | /* Simulate S32E instruction: AT --> ref (AS + offset). */ |
08b9c608 MG |
2729 | static void |
2730 | execute_s32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb) | |
2731 | { | |
2732 | int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb); | |
2733 | int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb); | |
2734 | CORE_ADDR addr = xtensa_read_register (asreg) + offset; | |
2735 | ULONGEST spilled_value = xtensa_read_register (atreg); | |
2736 | ||
2737 | write_memory_unsigned_integer (addr, 4, | |
2738 | gdbarch_byte_order (gdbarch), | |
2739 | spilled_value); | |
2740 | } | |
2741 | ||
2742 | #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200 | |
2743 | ||
68d6df83 MG |
2744 | typedef enum |
2745 | { | |
08b9c608 MG |
2746 | xtWindowOverflow, |
2747 | xtWindowUnderflow, | |
2748 | xtNoExceptionHandler | |
2749 | } xtensa_exception_handler_t; | |
2750 | ||
68d6df83 | 2751 | /* Execute instruction stream from current PC until hitting RFWU or RFWO. |
08b9c608 MG |
2752 | Return type of Xtensa Window Interrupt Handler on success. */ |
2753 | static xtensa_exception_handler_t | |
2754 | execute_code (struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb) | |
2755 | { | |
2756 | xtensa_isa isa; | |
2757 | xtensa_insnbuf ins, slot; | |
948f8e3d | 2758 | gdb_byte ibuf[XTENSA_ISA_BSZ]; |
08b9c608 MG |
2759 | CORE_ADDR ia, bt, ba; |
2760 | xtensa_format ifmt; | |
2761 | int ilen, islots, is; | |
2762 | xtensa_opcode opc; | |
2763 | int insn_num = 0; | |
08b9c608 MG |
2764 | void (*func) (struct gdbarch *, int, int, int, CORE_ADDR); |
2765 | ||
19afdd07 | 2766 | uint32_t at, as, offset; |
08b9c608 MG |
2767 | |
2768 | /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */ | |
2769 | int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140; | |
2770 | ||
2771 | isa = xtensa_default_isa; | |
2772 | gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); | |
2773 | ins = xtensa_insnbuf_alloc (isa); | |
2774 | slot = xtensa_insnbuf_alloc (isa); | |
2775 | ba = 0; | |
2776 | ia = current_pc; | |
2777 | bt = ia; | |
2778 | ||
2779 | a0_was_saved = 0; | |
2780 | a7_was_saved = 0; | |
2781 | a11_was_saved = 0; | |
2782 | ||
2783 | while (insn_num++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN) | |
2784 | { | |
2785 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
dda83cd7 | 2786 | { |
08b9c608 MG |
2787 | ba = ia; |
2788 | bt = (ba + XTENSA_ISA_BSZ); | |
2789 | if (target_read_memory (ba, ibuf, bt - ba) != 0) | |
2790 | return xtNoExceptionHandler; | |
2791 | } | |
2792 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
2793 | ifmt = xtensa_format_decode (isa, ins); | |
2794 | if (ifmt == XTENSA_UNDEFINED) | |
2795 | return xtNoExceptionHandler; | |
2796 | ilen = xtensa_format_length (isa, ifmt); | |
2797 | if (ilen == XTENSA_UNDEFINED) | |
2798 | return xtNoExceptionHandler; | |
2799 | islots = xtensa_format_num_slots (isa, ifmt); | |
2800 | if (islots == XTENSA_UNDEFINED) | |
2801 | return xtNoExceptionHandler; | |
2802 | for (is = 0; is < islots; ++is) | |
2803 | { | |
2804 | if (xtensa_format_get_slot (isa, ifmt, is, ins, slot)) | |
2805 | return xtNoExceptionHandler; | |
2806 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
2807 | if (opc == XTENSA_UNDEFINED) | |
2808 | return xtNoExceptionHandler; | |
2809 | switch (call0_classify_opcode (isa, opc)) | |
2810 | { | |
2811 | case c0opc_illegal: | |
2812 | case c0opc_flow: | |
2813 | case c0opc_entry: | |
2814 | case c0opc_break: | |
2815 | /* We expect none of them here. */ | |
2816 | return xtNoExceptionHandler; | |
2817 | case c0opc_l32e: | |
2818 | func = execute_l32e; | |
2819 | break; | |
2820 | case c0opc_s32e: | |
2821 | func = execute_s32e; | |
2822 | break; | |
2823 | case c0opc_rfwo: /* RFWO. */ | |
2824 | /* Here, we return from WindowOverflow handler and, | |
2825 | if we stopped at the very beginning, which means | |
2826 | A0 was saved, we have to restore it now. */ | |
2827 | if (a0_was_saved) | |
2828 | { | |
2829 | int arreg = arreg_number (gdbarch, | |
2830 | gdbarch_tdep (gdbarch)->a0_base, | |
2831 | wb); | |
2832 | xtensa_write_register (arreg, a0_saved); | |
2833 | } | |
2834 | return xtWindowOverflow; | |
2835 | case c0opc_rfwu: /* RFWU. */ | |
2836 | /* Here, we return from WindowUnderflow handler. | |
2837 | Let's see if either A7 or A11 has to be restored. */ | |
2838 | if (WindowUnderflow12) | |
2839 | { | |
2840 | if (a11_was_saved) | |
2841 | { | |
2842 | int arreg = arreg_number (gdbarch, | |
2843 | gdbarch_tdep (gdbarch)->a0_base + 11, | |
2844 | wb); | |
2845 | xtensa_write_register (arreg, a11_saved); | |
2846 | } | |
2847 | } | |
2848 | else if (a7_was_saved) | |
2849 | { | |
2850 | int arreg = arreg_number (gdbarch, | |
2851 | gdbarch_tdep (gdbarch)->a0_base + 7, | |
2852 | wb); | |
2853 | xtensa_write_register (arreg, a7_saved); | |
2854 | } | |
2855 | return xtWindowUnderflow; | |
24b21115 | 2856 | default: /* Simply skip this insns. */ |
08b9c608 MG |
2857 | continue; |
2858 | } | |
2859 | ||
2860 | /* Decode arguments for L32E / S32E and simulate their execution. */ | |
2861 | if ( xtensa_opcode_num_operands (isa, opc) != 3 ) | |
2862 | return xtNoExceptionHandler; | |
2863 | if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, &at)) | |
2864 | return xtNoExceptionHandler; | |
2865 | if (xtensa_operand_decode (isa, opc, 0, &at)) | |
2866 | return xtNoExceptionHandler; | |
2867 | if (xtensa_operand_get_field (isa, opc, 1, ifmt, is, slot, &as)) | |
2868 | return xtNoExceptionHandler; | |
2869 | if (xtensa_operand_decode (isa, opc, 1, &as)) | |
2870 | return xtNoExceptionHandler; | |
2871 | if (xtensa_operand_get_field (isa, opc, 2, ifmt, is, slot, &offset)) | |
2872 | return xtNoExceptionHandler; | |
2873 | if (xtensa_operand_decode (isa, opc, 2, &offset)) | |
2874 | return xtNoExceptionHandler; | |
2875 | ||
2876 | (*func) (gdbarch, at, as, offset, wb); | |
2877 | } | |
2878 | ||
2879 | ia += ilen; | |
2880 | } | |
2881 | return xtNoExceptionHandler; | |
2882 | } | |
2883 | ||
2884 | /* Handle Window Overflow / Underflow exception frames. */ | |
2885 | ||
2886 | static void | |
2887 | xtensa_window_interrupt_frame_cache (struct frame_info *this_frame, | |
2888 | xtensa_frame_cache_t *cache, | |
2889 | CORE_ADDR pc) | |
2890 | { | |
2891 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2892 | CORE_ADDR ps, wb, ws, ra; | |
2893 | int epc1_regnum, i, regnum; | |
2894 | xtensa_exception_handler_t eh_type; | |
2895 | ||
2896 | /* Read PS, WB, and WS from the hardware. Note that PS register | |
2897 | must be present, if Windowed ABI is supported. */ | |
2898 | ps = xtensa_read_register (gdbarch_ps_regnum (gdbarch)); | |
2899 | wb = xtensa_read_register (gdbarch_tdep (gdbarch)->wb_regnum); | |
2900 | ws = xtensa_read_register (gdbarch_tdep (gdbarch)->ws_regnum); | |
2901 | ||
2902 | /* Execute all the remaining instructions from Window Interrupt Handler | |
2903 | by simulating them on the remote protocol level. On return, set the | |
2904 | type of Xtensa Window Interrupt Handler, or report an error. */ | |
2905 | eh_type = execute_code (gdbarch, pc, wb); | |
2906 | if (eh_type == xtNoExceptionHandler) | |
2907 | error (_("\ | |
2908 | Unable to decode Xtensa Window Interrupt Handler's code.")); | |
2909 | ||
2910 | cache->ps = ps ^ PS_EXC; /* Clear the exception bit in PS. */ | |
2911 | cache->call0 = 0; /* It's Windowed ABI. */ | |
2912 | ||
2913 | /* All registers for the cached frame will be alive. */ | |
2914 | for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++) | |
2915 | cache->wd.aregs[i] = -1; | |
2916 | ||
2917 | if (eh_type == xtWindowOverflow) | |
2918 | cache->wd.ws = ws ^ (1 << wb); | |
2919 | else /* eh_type == xtWindowUnderflow. */ | |
2920 | cache->wd.ws = ws | (1 << wb); | |
2921 | ||
2922 | cache->wd.wb = (ps & 0xf00) >> 8; /* Set WB to OWB. */ | |
2923 | regnum = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base, | |
2924 | cache->wd.wb); | |
2925 | ra = xtensa_read_register (regnum); | |
2926 | cache->wd.callsize = WINSIZE (ra); | |
2927 | cache->prev_sp = xtensa_read_register (regnum + 1); | |
2928 | /* Set regnum to a frame pointer of the frame being cached. */ | |
2929 | regnum = xtensa_scan_prologue (gdbarch, pc); | |
2930 | regnum = arreg_number (gdbarch, | |
2931 | gdbarch_tdep (gdbarch)->a0_base + regnum, | |
2932 | cache->wd.wb); | |
2933 | cache->base = get_frame_register_unsigned (this_frame, regnum); | |
2934 | ||
2935 | /* Read PC of interrupted function from EPC1 register. */ | |
2936 | epc1_regnum = xtensa_find_register_by_name (gdbarch,"epc1"); | |
2937 | if (epc1_regnum < 0) | |
2938 | error(_("Unable to read Xtensa register EPC1")); | |
2939 | cache->ra = xtensa_read_register (epc1_regnum); | |
2940 | cache->pc = get_frame_func (this_frame); | |
2941 | } | |
2942 | ||
bdb4c075 MG |
2943 | |
2944 | /* Skip function prologue. | |
2945 | ||
2946 | Return the pc of the first instruction after prologue. GDB calls this to | |
2947 | find the address of the first line of the function or (if there is no line | |
2948 | number information) to skip the prologue for planting breakpoints on | |
2949 | function entries. Use debug info (if present) or prologue analysis to skip | |
2950 | the prologue to achieve reliable debugging behavior. For windowed ABI, | |
2951 | only the 'entry' instruction is skipped. It is not strictly necessary to | |
2952 | skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to | |
2953 | backtrace at any point in the prologue, however certain potential hazards | |
2954 | are avoided and a more "normal" debugging experience is ensured by | |
2955 | skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG). | |
2956 | For example, if we don't skip the prologue: | |
2957 | - Some args may not yet have been saved to the stack where the debug | |
2958 | info expects to find them (true anyway when only 'entry' is skipped); | |
2959 | - Software breakpoints ('break' instrs) may not have been unplanted | |
2960 | when the prologue analysis is done on initializing the frame cache, | |
2961 | and breaks in the prologue will throw off the analysis. | |
ca3bf3bd DJ |
2962 | |
2963 | If we have debug info ( line-number info, in particular ) we simply skip | |
2964 | the code associated with the first function line effectively skipping | |
bdb4c075 | 2965 | the prologue code. It works even in cases like |
ca3bf3bd DJ |
2966 | |
2967 | int main() | |
2968 | { int local_var = 1; | |
24b21115 | 2969 | .... |
ca3bf3bd DJ |
2970 | } |
2971 | ||
2972 | because, for this source code, both Xtensa compilers will generate two | |
2973 | separate entries ( with the same line number ) in dwarf line-number | |
2974 | section to make sure there is a boundary between the prologue code and | |
2975 | the rest of the function. | |
2976 | ||
bdb4c075 MG |
2977 | If there is no debug info, we need to analyze the code. */ |
2978 | ||
2979 | /* #define DONT_SKIP_PROLOGUE */ | |
ca3bf3bd | 2980 | |
63807e1d | 2981 | static CORE_ADDR |
6093d2eb | 2982 | xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
ca3bf3bd | 2983 | { |
bdb4c075 MG |
2984 | struct symtab_and_line prologue_sal; |
2985 | CORE_ADDR body_pc; | |
2986 | ||
ca3bf3bd DJ |
2987 | DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc); |
2988 | ||
bdb4c075 MG |
2989 | #if DONT_SKIP_PROLOGUE |
2990 | return start_pc; | |
2991 | #endif | |
2992 | ||
2993 | /* Try to find first body line from debug info. */ | |
2994 | ||
2995 | prologue_sal = find_pc_line (start_pc, 0); | |
2996 | if (prologue_sal.line != 0) /* Found debug info. */ | |
ca3bf3bd | 2997 | { |
f976a05d MG |
2998 | /* In Call0, it is possible to have a function with only one instruction |
2999 | ('ret') resulting from a one-line optimized function that does nothing. | |
3000 | In that case, prologue_sal.end may actually point to the start of the | |
3001 | next function in the text section, causing a breakpoint to be set at | |
3002 | the wrong place. Check, if the end address is within a different | |
3003 | function, and if so return the start PC. We know we have symbol | |
3004 | information. */ | |
ca3bf3bd | 3005 | |
bdb4c075 MG |
3006 | CORE_ADDR end_func; |
3007 | ||
f976a05d MG |
3008 | if ((gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only) |
3009 | && call0_ret (start_pc, prologue_sal.end)) | |
3010 | return start_pc; | |
3011 | ||
bdb4c075 MG |
3012 | find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL); |
3013 | if (end_func != start_pc) | |
ca3bf3bd DJ |
3014 | return start_pc; |
3015 | ||
bdb4c075 | 3016 | return prologue_sal.end; |
ca3bf3bd | 3017 | } |
ca3bf3bd | 3018 | |
bdb4c075 | 3019 | /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */ |
dbab50de MG |
3020 | body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0, |
3021 | xtensa_alloc_frame_cache (0)); | |
bdb4c075 MG |
3022 | return body_pc != 0 ? body_pc : start_pc; |
3023 | } | |
ca3bf3bd DJ |
3024 | |
3025 | /* Verify the current configuration. */ | |
ca3bf3bd DJ |
3026 | static void |
3027 | xtensa_verify_config (struct gdbarch *gdbarch) | |
3028 | { | |
d7e74731 PA |
3029 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3030 | string_file log; | |
ca3bf3bd DJ |
3031 | |
3032 | /* Verify that we got a reasonable number of AREGS. */ | |
3033 | if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs) | |
d7e74731 | 3034 | log.printf (_("\ |
bdb4c075 | 3035 | \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"), |
d7e74731 | 3036 | tdep->num_aregs); |
ca3bf3bd DJ |
3037 | |
3038 | /* Verify that certain registers exist. */ | |
bdb4c075 | 3039 | |
ca3bf3bd | 3040 | if (tdep->pc_regnum == -1) |
d7e74731 | 3041 | log.printf (_("\n\tpc_regnum: No PC register")); |
bdb4c075 | 3042 | if (tdep->isa_use_exceptions && tdep->ps_regnum == -1) |
d7e74731 | 3043 | log.printf (_("\n\tps_regnum: No PS register")); |
bdb4c075 MG |
3044 | |
3045 | if (tdep->isa_use_windowed_registers) | |
3046 | { | |
3047 | if (tdep->wb_regnum == -1) | |
d7e74731 | 3048 | log.printf (_("\n\twb_regnum: No WB register")); |
bdb4c075 | 3049 | if (tdep->ws_regnum == -1) |
d7e74731 | 3050 | log.printf (_("\n\tws_regnum: No WS register")); |
bdb4c075 | 3051 | if (tdep->ar_base == -1) |
d7e74731 | 3052 | log.printf (_("\n\tar_base: No AR registers")); |
bdb4c075 MG |
3053 | } |
3054 | ||
ca3bf3bd | 3055 | if (tdep->a0_base == -1) |
d7e74731 | 3056 | log.printf (_("\n\ta0_base: No Ax registers")); |
ca3bf3bd | 3057 | |
d7e74731 | 3058 | if (!log.empty ()) |
ca3bf3bd | 3059 | internal_error (__FILE__, __LINE__, |
d7e74731 | 3060 | _("the following are invalid: %s"), log.c_str ()); |
ca3bf3bd DJ |
3061 | } |
3062 | ||
94a0e877 MG |
3063 | |
3064 | /* Derive specific register numbers from the array of registers. */ | |
3065 | ||
63807e1d | 3066 | static void |
94a0e877 MG |
3067 | xtensa_derive_tdep (struct gdbarch_tdep *tdep) |
3068 | { | |
3069 | xtensa_register_t* rmap; | |
3070 | int n, max_size = 4; | |
3071 | ||
3072 | tdep->num_regs = 0; | |
3073 | tdep->num_nopriv_regs = 0; | |
3074 | ||
3075 | /* Special registers 0..255 (core). */ | |
3076 | #define XTENSA_DBREGN_SREG(n) (0x0200+(n)) | |
f74f865e MF |
3077 | /* User registers 0..255. */ |
3078 | #define XTENSA_DBREGN_UREG(n) (0x0300+(n)) | |
94a0e877 MG |
3079 | |
3080 | for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++) | |
3081 | { | |
3082 | if (rmap->target_number == 0x0020) | |
3083 | tdep->pc_regnum = n; | |
3084 | else if (rmap->target_number == 0x0100) | |
3085 | tdep->ar_base = n; | |
3086 | else if (rmap->target_number == 0x0000) | |
3087 | tdep->a0_base = n; | |
3088 | else if (rmap->target_number == XTENSA_DBREGN_SREG(72)) | |
3089 | tdep->wb_regnum = n; | |
3090 | else if (rmap->target_number == XTENSA_DBREGN_SREG(73)) | |
3091 | tdep->ws_regnum = n; | |
3092 | else if (rmap->target_number == XTENSA_DBREGN_SREG(233)) | |
3093 | tdep->debugcause_regnum = n; | |
3094 | else if (rmap->target_number == XTENSA_DBREGN_SREG(232)) | |
3095 | tdep->exccause_regnum = n; | |
3096 | else if (rmap->target_number == XTENSA_DBREGN_SREG(238)) | |
3097 | tdep->excvaddr_regnum = n; | |
3098 | else if (rmap->target_number == XTENSA_DBREGN_SREG(0)) | |
3099 | tdep->lbeg_regnum = n; | |
3100 | else if (rmap->target_number == XTENSA_DBREGN_SREG(1)) | |
3101 | tdep->lend_regnum = n; | |
3102 | else if (rmap->target_number == XTENSA_DBREGN_SREG(2)) | |
3103 | tdep->lcount_regnum = n; | |
3104 | else if (rmap->target_number == XTENSA_DBREGN_SREG(3)) | |
3105 | tdep->sar_regnum = n; | |
3106 | else if (rmap->target_number == XTENSA_DBREGN_SREG(5)) | |
3107 | tdep->litbase_regnum = n; | |
3108 | else if (rmap->target_number == XTENSA_DBREGN_SREG(230)) | |
3109 | tdep->ps_regnum = n; | |
f74f865e MF |
3110 | else if (rmap->target_number == XTENSA_DBREGN_UREG(231)) |
3111 | tdep->threadptr_regnum = n; | |
94a0e877 MG |
3112 | #if 0 |
3113 | else if (rmap->target_number == XTENSA_DBREGN_SREG(226)) | |
3114 | tdep->interrupt_regnum = n; | |
3115 | else if (rmap->target_number == XTENSA_DBREGN_SREG(227)) | |
3116 | tdep->interrupt2_regnum = n; | |
3117 | else if (rmap->target_number == XTENSA_DBREGN_SREG(224)) | |
3118 | tdep->cpenable_regnum = n; | |
3119 | #endif | |
3120 | ||
3121 | if (rmap->byte_size > max_size) | |
3122 | max_size = rmap->byte_size; | |
3123 | if (rmap->mask != 0 && tdep->num_regs == 0) | |
3124 | tdep->num_regs = n; | |
94a0e877 | 3125 | if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0 |
37d9e062 MF |
3126 | && tdep->num_nopriv_regs == 0) |
3127 | tdep->num_nopriv_regs = n; | |
94a0e877 | 3128 | } |
37d9e062 MF |
3129 | if (tdep->num_regs == 0) |
3130 | tdep->num_regs = tdep->num_nopriv_regs; | |
94a0e877 MG |
3131 | |
3132 | /* Number of pseudo registers. */ | |
3133 | tdep->num_pseudo_regs = n - tdep->num_regs; | |
3134 | ||
3135 | /* Empirically determined maximum sizes. */ | |
3136 | tdep->max_register_raw_size = max_size; | |
3137 | tdep->max_register_virtual_size = max_size; | |
3138 | } | |
3139 | ||
ca3bf3bd DJ |
3140 | /* Module "constructor" function. */ |
3141 | ||
94a0e877 MG |
3142 | extern struct gdbarch_tdep xtensa_tdep; |
3143 | ||
ca3bf3bd DJ |
3144 | static struct gdbarch * |
3145 | xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
3146 | { | |
3147 | struct gdbarch_tdep *tdep; | |
3148 | struct gdbarch *gdbarch; | |
ca3bf3bd DJ |
3149 | |
3150 | DEBUGTRACE ("gdbarch_init()\n"); | |
3151 | ||
a4398628 MF |
3152 | if (!xtensa_default_isa) |
3153 | xtensa_default_isa = xtensa_isa_init (0, 0); | |
3154 | ||
ca3bf3bd | 3155 | /* We have to set the byte order before we call gdbarch_alloc. */ |
94a0e877 | 3156 | info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE; |
ca3bf3bd | 3157 | |
94a0e877 | 3158 | tdep = &xtensa_tdep; |
ca3bf3bd | 3159 | gdbarch = gdbarch_alloc (&info, tdep); |
94a0e877 | 3160 | xtensa_derive_tdep (tdep); |
ca3bf3bd DJ |
3161 | |
3162 | /* Verify our configuration. */ | |
3163 | xtensa_verify_config (gdbarch); | |
dbab50de | 3164 | xtensa_session_once_reported = 0; |
ca3bf3bd | 3165 | |
53375380 PA |
3166 | set_gdbarch_wchar_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
3167 | set_gdbarch_wchar_signed (gdbarch, 0); | |
3168 | ||
bdb4c075 | 3169 | /* Pseudo-Register read/write. */ |
ca3bf3bd DJ |
3170 | set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read); |
3171 | set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write); | |
3172 | ||
3173 | /* Set target information. */ | |
3174 | set_gdbarch_num_regs (gdbarch, tdep->num_regs); | |
3175 | set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs); | |
3176 | set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1); | |
3177 | set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum); | |
3178 | set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum); | |
3179 | ||
ba2b1c56 | 3180 | /* Renumber registers for known formats (stabs and dwarf2). */ |
ca3bf3bd | 3181 | set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); |
ca3bf3bd DJ |
3182 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); |
3183 | ||
3184 | /* We provide our own function to get register information. */ | |
3185 | set_gdbarch_register_name (gdbarch, xtensa_register_name); | |
3186 | set_gdbarch_register_type (gdbarch, xtensa_register_type); | |
3187 | ||
581e13c1 | 3188 | /* To call functions from GDB using dummy frame. */ |
ca3bf3bd DJ |
3189 | set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call); |
3190 | ||
3191 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); | |
3192 | ||
3193 | set_gdbarch_return_value (gdbarch, xtensa_return_value); | |
3194 | ||
3195 | /* Advance PC across any prologue instructions to reach "real" code. */ | |
3196 | set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue); | |
3197 | ||
3198 | /* Stack grows downward. */ | |
3199 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
3200 | ||
3201 | /* Set breakpoints. */ | |
04180708 YQ |
3202 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
3203 | xtensa_breakpoint_kind_from_pc); | |
3204 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
3205 | xtensa_sw_breakpoint_from_kind); | |
ca3bf3bd DJ |
3206 | |
3207 | /* After breakpoint instruction or illegal instruction, pc still | |
3208 | points at break instruction, so don't decrement. */ | |
3209 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
3210 | ||
3211 | /* We don't skip args. */ | |
3212 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
3213 | ||
3214 | set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc); | |
3215 | ||
3216 | set_gdbarch_frame_align (gdbarch, xtensa_frame_align); | |
3217 | ||
5142f611 | 3218 | set_gdbarch_dummy_id (gdbarch, xtensa_dummy_id); |
ca3bf3bd DJ |
3219 | |
3220 | /* Frame handling. */ | |
3221 | frame_base_set_default (gdbarch, &xtensa_frame_base); | |
5142f611 MG |
3222 | frame_unwind_append_unwinder (gdbarch, &xtensa_unwind); |
3223 | dwarf2_append_unwinders (gdbarch); | |
ca3bf3bd | 3224 | |
ca3bf3bd DJ |
3225 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
3226 | ||
3227 | xtensa_add_reggroups (gdbarch); | |
3228 | set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p); | |
3229 | ||
97094034 AA |
3230 | set_gdbarch_iterate_over_regset_sections |
3231 | (gdbarch, xtensa_iterate_over_regset_sections); | |
ca3bf3bd | 3232 | |
ee967b5f MG |
3233 | set_solib_svr4_fetch_link_map_offsets |
3234 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); | |
3235 | ||
40045d91 MF |
3236 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
3237 | gdbarch_init_osabi (info, gdbarch); | |
3238 | ||
ca3bf3bd DJ |
3239 | return gdbarch; |
3240 | } | |
3241 | ||
ca3bf3bd | 3242 | static void |
6b50c0b0 | 3243 | xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
ca3bf3bd DJ |
3244 | { |
3245 | error (_("xtensa_dump_tdep(): not implemented")); | |
3246 | } | |
3247 | ||
6c265988 | 3248 | void _initialize_xtensa_tdep (); |
ca3bf3bd | 3249 | void |
6c265988 | 3250 | _initialize_xtensa_tdep () |
ca3bf3bd | 3251 | { |
ca3bf3bd DJ |
3252 | gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep); |
3253 | xtensa_init_reggroups (); | |
3254 | ||
ccce17b0 YQ |
3255 | add_setshow_zuinteger_cmd ("xtensa", |
3256 | class_maintenance, | |
3257 | &xtensa_debug_level, | |
581e13c1 MS |
3258 | _("Set Xtensa debugging."), |
3259 | _("Show Xtensa debugging."), _("\ | |
ca3bf3bd DJ |
3260 | When non-zero, Xtensa-specific debugging is enabled. \ |
3261 | Can be 1, 2, 3, or 4 indicating the level of debugging."), | |
ccce17b0 YQ |
3262 | NULL, |
3263 | NULL, | |
3264 | &setdebuglist, &showdebuglist); | |
ca3bf3bd | 3265 | } |