[deliverable/linux.git] / include / asm-powerpc / pasemi_dma.h

/*
 * Copyright (C) 2006 PA Semi, Inc
 *
 * Hardware register layout and descriptor formats for the on-board
 * DMA engine on PA Semi PWRficient. Used by ethernet, function and security
 * drivers.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#ifndef ASM_PASEMI_DMA_H
#define ASM_PASEMI_DMA_H

/* status register layout in IOB region, at 0xfb800000 */
struct pasdma_status {
	u64 rx_sta[64];		/* RX channel status */
	u64 tx_sta[20];		/* TX channel status */
};


/* All these registers live in the PCI configuration space for the DMA PCI
 * device. Use the normal PCI config access functions for them.
 */
enum {
	PAS_DMA_COM_TXCMD = 0x100,	/* Transmit Command Register  */
	PAS_DMA_COM_TXSTA = 0x104,	/* Transmit Status Register   */
	PAS_DMA_COM_RXCMD = 0x108,	/* Receive Command Register   */
	PAS_DMA_COM_RXSTA = 0x10c,	/* Receive Status Register    */
};
#define PAS_DMA_COM_TXCMD_EN	0x00000001 /* enable */
#define PAS_DMA_COM_TXSTA_ACT	0x00000001 /* active */
#define PAS_DMA_COM_RXCMD_EN	0x00000001 /* enable */
#define PAS_DMA_COM_RXSTA_ACT	0x00000001 /* active */


/* Per-interface and per-channel registers */
#define _PAS_DMA_RXINT_STRIDE		0x20
#define PAS_DMA_RXINT_RCMDSTA(i)	(0x200+(i)*_PAS_DMA_RXINT_STRIDE)
#define    PAS_DMA_RXINT_RCMDSTA_EN	0x00000001
#define    PAS_DMA_RXINT_RCMDSTA_ST	0x00000002
#define    PAS_DMA_RXINT_RCMDSTA_MBT	0x00000008
#define    PAS_DMA_RXINT_RCMDSTA_MDR	0x00000010
#define    PAS_DMA_RXINT_RCMDSTA_MOO	0x00000020
#define    PAS_DMA_RXINT_RCMDSTA_MBP	0x00000040
#define    PAS_DMA_RXINT_RCMDSTA_BT	0x00000800
#define    PAS_DMA_RXINT_RCMDSTA_DR	0x00001000
#define    PAS_DMA_RXINT_RCMDSTA_OO	0x00002000
#define    PAS_DMA_RXINT_RCMDSTA_BP	0x00004000
#define    PAS_DMA_RXINT_RCMDSTA_TB	0x00008000
#define    PAS_DMA_RXINT_RCMDSTA_ACT	0x00010000
#define    PAS_DMA_RXINT_RCMDSTA_DROPS_M	0xfffe0000
#define    PAS_DMA_RXINT_RCMDSTA_DROPS_S	17
#define PAS_DMA_RXINT_CFG(i)		(0x204+(i)*_PAS_DMA_RXINT_STRIDE)
#define    PAS_DMA_RXINT_CFG_RBP	0x80000000
#define    PAS_DMA_RXINT_CFG_ITRR	0x40000000
#define    PAS_DMA_RXINT_CFG_DHL_M	0x07000000
#define    PAS_DMA_RXINT_CFG_DHL_S	24
#define    PAS_DMA_RXINT_CFG_DHL(x)	(((x) << PAS_DMA_RXINT_CFG_DHL_S) & \
					 PAS_DMA_RXINT_CFG_DHL_M)
#define    PAS_DMA_RXINT_CFG_ITR	0x00400000
#define    PAS_DMA_RXINT_CFG_LW		0x00200000
#define    PAS_DMA_RXINT_CFG_L2		0x00100000
#define    PAS_DMA_RXINT_CFG_HEN	0x00080000
#define    PAS_DMA_RXINT_CFG_WIF	0x00000002
#define    PAS_DMA_RXINT_CFG_WIL	0x00000001

#define PAS_DMA_RXINT_INCR(i)		(0x210+(i)*_PAS_DMA_RXINT_STRIDE)
#define    PAS_DMA_RXINT_INCR_INCR_M	0x0000ffff
#define    PAS_DMA_RXINT_INCR_INCR_S	0
#define    PAS_DMA_RXINT_INCR_INCR(x)	((x) & 0x0000ffff)
#define PAS_DMA_RXINT_BASEL(i)		(0x218+(i)*_PAS_DMA_RXINT_STRIDE)
#define    PAS_DMA_RXINT_BASEL_BRBL(x)	((x) & ~0x3f)
#define PAS_DMA_RXINT_BASEU(i)		(0x21c+(i)*_PAS_DMA_RXINT_STRIDE)
#define    PAS_DMA_RXINT_BASEU_BRBH(x)	((x) & 0xfff)
#define    PAS_DMA_RXINT_BASEU_SIZ_M	0x3fff0000	/* # of cache lines worth of buffer ring */
#define    PAS_DMA_RXINT_BASEU_SIZ_S	16		/* 0 = 16K */
#define    PAS_DMA_RXINT_BASEU_SIZ(x)	(((x) << PAS_DMA_RXINT_BASEU_SIZ_S) & \
					 PAS_DMA_RXINT_BASEU_SIZ_M)


#define _PAS_DMA_TXCHAN_STRIDE	0x20    /* Size per channel		*/
#define _PAS_DMA_TXCHAN_TCMDSTA	0x300	/* Command / Status		*/
#define _PAS_DMA_TXCHAN_CFG	0x304	/* Configuration		*/
#define _PAS_DMA_TXCHAN_DSCRBU	0x308	/* Descriptor BU Allocation	*/
#define _PAS_DMA_TXCHAN_INCR	0x310	/* Descriptor increment		*/
#define _PAS_DMA_TXCHAN_CNT	0x314	/* Descriptor count/offset	*/
#define _PAS_DMA_TXCHAN_BASEL	0x318	/* Descriptor ring base (low)	*/
#define _PAS_DMA_TXCHAN_BASEU	0x31c	/*			(high)	*/
#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE)
#define    PAS_DMA_TXCHAN_TCMDSTA_EN	0x00000001	/* Enabled */
#define    PAS_DMA_TXCHAN_TCMDSTA_ST	0x00000002	/* Stop interface */
#define    PAS_DMA_TXCHAN_TCMDSTA_ACT	0x00010000	/* Active */
#define    PAS_DMA_TXCHAN_TCMDSTA_SZ	0x00000800
#define    PAS_DMA_TXCHAN_TCMDSTA_DB	0x00000400
#define    PAS_DMA_TXCHAN_TCMDSTA_DE	0x00000200
#define    PAS_DMA_TXCHAN_TCMDSTA_DA	0x00000100
#define PAS_DMA_TXCHAN_CFG(c)     (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE)
#define    PAS_DMA_TXCHAN_CFG_TY_IFACE	0x00000000	/* Type = interface */
#define    PAS_DMA_TXCHAN_CFG_TATTR_M	0x0000003c
#define    PAS_DMA_TXCHAN_CFG_TATTR_S	2
#define    PAS_DMA_TXCHAN_CFG_TATTR(x)	(((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \
					 PAS_DMA_TXCHAN_CFG_TATTR_M)
#define    PAS_DMA_TXCHAN_CFG_WT_M	0x000001c0
#define    PAS_DMA_TXCHAN_CFG_WT_S	6
#define    PAS_DMA_TXCHAN_CFG_WT(x)	(((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \
					 PAS_DMA_TXCHAN_CFG_WT_M)
#define    PAS_DMA_TXCHAN_CFG_TRD	0x00010000	/* translate data */
#define    PAS_DMA_TXCHAN_CFG_TRR	0x00008000	/* translate rings */
#define    PAS_DMA_TXCHAN_CFG_UP	0x00004000	/* update tx descr when sent */
#define    PAS_DMA_TXCHAN_CFG_CL	0x00002000	/* Clean last line */
#define    PAS_DMA_TXCHAN_CFG_CF	0x00001000	/* Clean first line */
#define PAS_DMA_TXCHAN_INCR(c)    (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE)
#define PAS_DMA_TXCHAN_BASEL(c)   (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE)
#define    PAS_DMA_TXCHAN_BASEL_BRBL_M	0xffffffc0
#define    PAS_DMA_TXCHAN_BASEL_BRBL_S	0
#define    PAS_DMA_TXCHAN_BASEL_BRBL(x)	(((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \
					 PAS_DMA_TXCHAN_BASEL_BRBL_M)
#define PAS_DMA_TXCHAN_BASEU(c)   (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE)
#define    PAS_DMA_TXCHAN_BASEU_BRBH_M	0x00000fff
#define    PAS_DMA_TXCHAN_BASEU_BRBH_S	0
#define    PAS_DMA_TXCHAN_BASEU_BRBH(x)	(((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \
					 PAS_DMA_TXCHAN_BASEU_BRBH_M)
/* # of cache lines worth of buffer ring */
#define    PAS_DMA_TXCHAN_BASEU_SIZ_M	0x3fff0000
#define    PAS_DMA_TXCHAN_BASEU_SIZ_S	16		/* 0 = 16K */
#define    PAS_DMA_TXCHAN_BASEU_SIZ(x)	(((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \
					 PAS_DMA_TXCHAN_BASEU_SIZ_M)

#define _PAS_DMA_RXCHAN_STRIDE	0x20    /* Size per channel		*/
#define _PAS_DMA_RXCHAN_CCMDSTA	0x800	/* Command / Status		*/
#define _PAS_DMA_RXCHAN_CFG	0x804	/* Configuration		*/
#define _PAS_DMA_RXCHAN_INCR	0x810	/* Descriptor increment		*/
#define _PAS_DMA_RXCHAN_CNT	0x814	/* Descriptor count/offset	*/
#define _PAS_DMA_RXCHAN_BASEL	0x818	/* Descriptor ring base (low)	*/
#define _PAS_DMA_RXCHAN_BASEU	0x81c	/*			(high)	*/
#define PAS_DMA_RXCHAN_CCMDSTA(c) (0x800+(c)*_PAS_DMA_RXCHAN_STRIDE)
#define    PAS_DMA_RXCHAN_CCMDSTA_EN	0x00000001	/* Enabled */
#define    PAS_DMA_RXCHAN_CCMDSTA_ST	0x00000002	/* Stop interface */
#define    PAS_DMA_RXCHAN_CCMDSTA_ACT	0x00010000	/* Active */
#define    PAS_DMA_RXCHAN_CCMDSTA_DU	0x00020000
#define    PAS_DMA_RXCHAN_CCMDSTA_OD	0x00002000
#define    PAS_DMA_RXCHAN_CCMDSTA_FD	0x00001000
#define    PAS_DMA_RXCHAN_CCMDSTA_DT	0x00000800
#define PAS_DMA_RXCHAN_CFG(c)     (0x804+(c)*_PAS_DMA_RXCHAN_STRIDE)
#define    PAS_DMA_RXCHAN_CFG_CTR	0x00000400
#define    PAS_DMA_RXCHAN_CFG_HBU_M	0x00000380
#define    PAS_DMA_RXCHAN_CFG_HBU_S	7
#define    PAS_DMA_RXCHAN_CFG_HBU(x)	(((x) << PAS_DMA_RXCHAN_CFG_HBU_S) & \
					 PAS_DMA_RXCHAN_CFG_HBU_M)
#define PAS_DMA_RXCHAN_INCR(c)    (0x810+(c)*_PAS_DMA_RXCHAN_STRIDE)
#define PAS_DMA_RXCHAN_BASEL(c)   (0x818+(c)*_PAS_DMA_RXCHAN_STRIDE)
#define    PAS_DMA_RXCHAN_BASEL_BRBL_M	0xffffffc0
#define    PAS_DMA_RXCHAN_BASEL_BRBL_S	0
#define    PAS_DMA_RXCHAN_BASEL_BRBL(x)	(((x) << PAS_DMA_RXCHAN_BASEL_BRBL_S) & \
					 PAS_DMA_RXCHAN_BASEL_BRBL_M)
#define PAS_DMA_RXCHAN_BASEU(c)   (0x81c+(c)*_PAS_DMA_RXCHAN_STRIDE)
#define    PAS_DMA_RXCHAN_BASEU_BRBH_M	0x00000fff
#define    PAS_DMA_RXCHAN_BASEU_BRBH_S	0
#define    PAS_DMA_RXCHAN_BASEU_BRBH(x)	(((x) << PAS_DMA_RXCHAN_BASEU_BRBH_S) & \
					 PAS_DMA_RXCHAN_BASEU_BRBH_M)
/* # of cache lines worth of buffer ring */
#define    PAS_DMA_RXCHAN_BASEU_SIZ_M	0x3fff0000
#define    PAS_DMA_RXCHAN_BASEU_SIZ_S	16		/* 0 = 16K */
#define    PAS_DMA_RXCHAN_BASEU_SIZ(x)	(((x) << PAS_DMA_RXCHAN_BASEU_SIZ_S) & \
					 PAS_DMA_RXCHAN_BASEU_SIZ_M)

#define    PAS_STATUS_PCNT_M		0x000000000000ffffull
#define    PAS_STATUS_PCNT_S		0
#define    PAS_STATUS_DCNT_M		0x00000000ffff0000ull
#define    PAS_STATUS_DCNT_S		16
#define    PAS_STATUS_BPCNT_M		0x0000ffff00000000ull
#define    PAS_STATUS_BPCNT_S		32
#define    PAS_STATUS_CAUSE_M		0xf000000000000000ull
#define    PAS_STATUS_TIMER		0x1000000000000000ull
#define    PAS_STATUS_ERROR		0x2000000000000000ull
#define    PAS_STATUS_SOFT		0x4000000000000000ull
#define    PAS_STATUS_INT		0x8000000000000000ull

#define PAS_IOB_COM_PKTHDRCNT		0x120
#define    PAS_IOB_COM_PKTHDRCNT_PKTHDR1_M	0x0fff0000
#define    PAS_IOB_COM_PKTHDRCNT_PKTHDR1_S	16
#define    PAS_IOB_COM_PKTHDRCNT_PKTHDR0_M	0x00000fff
#define    PAS_IOB_COM_PKTHDRCNT_PKTHDR0_S	0

#define PAS_IOB_DMA_RXCH_CFG(i)		(0x1100 + (i)*4)
#define    PAS_IOB_DMA_RXCH_CFG_CNTTH_M		0x00000fff
#define    PAS_IOB_DMA_RXCH_CFG_CNTTH_S		0
#define    PAS_IOB_DMA_RXCH_CFG_CNTTH(x)	(((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \
						 PAS_IOB_DMA_RXCH_CFG_CNTTH_M)
#define PAS_IOB_DMA_TXCH_CFG(i)		(0x1200 + (i)*4)
#define    PAS_IOB_DMA_TXCH_CFG_CNTTH_M		0x00000fff
#define    PAS_IOB_DMA_TXCH_CFG_CNTTH_S		0
#define    PAS_IOB_DMA_TXCH_CFG_CNTTH(x)	(((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \
						 PAS_IOB_DMA_TXCH_CFG_CNTTH_M)
#define PAS_IOB_DMA_RXCH_STAT(i)	(0x1300 + (i)*4)
#define    PAS_IOB_DMA_RXCH_STAT_INTGEN	0x00001000
#define    PAS_IOB_DMA_RXCH_STAT_CNTDEL_M	0x00000fff
#define    PAS_IOB_DMA_RXCH_STAT_CNTDEL_S	0
#define    PAS_IOB_DMA_RXCH_STAT_CNTDEL(x)	(((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\
						 PAS_IOB_DMA_RXCH_STAT_CNTDEL_M)
#define PAS_IOB_DMA_TXCH_STAT(i)	(0x1400 + (i)*4)
#define    PAS_IOB_DMA_TXCH_STAT_INTGEN	0x00001000
#define    PAS_IOB_DMA_TXCH_STAT_CNTDEL_M	0x00000fff
#define    PAS_IOB_DMA_TXCH_STAT_CNTDEL_S	0
#define    PAS_IOB_DMA_TXCH_STAT_CNTDEL(x)	(((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\
						 PAS_IOB_DMA_TXCH_STAT_CNTDEL_M)
#define PAS_IOB_DMA_RXCH_RESET(i)	(0x1500 + (i)*4)
#define    PAS_IOB_DMA_RXCH_RESET_PCNT_M	0xffff0000
#define    PAS_IOB_DMA_RXCH_RESET_PCNT_S	16
#define    PAS_IOB_DMA_RXCH_RESET_PCNT(x)	(((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \
						 PAS_IOB_DMA_RXCH_RESET_PCNT_M)
#define    PAS_IOB_DMA_RXCH_RESET_PCNTRST	0x00000020
#define    PAS_IOB_DMA_RXCH_RESET_DCNTRST	0x00000010
#define    PAS_IOB_DMA_RXCH_RESET_TINTC		0x00000008
#define    PAS_IOB_DMA_RXCH_RESET_DINTC		0x00000004
#define    PAS_IOB_DMA_RXCH_RESET_SINTC		0x00000002
#define    PAS_IOB_DMA_RXCH_RESET_PINTC		0x00000001
#define PAS_IOB_DMA_TXCH_RESET(i)	(0x1600 + (i)*4)
#define    PAS_IOB_DMA_TXCH_RESET_PCNT_M	0xffff0000
#define    PAS_IOB_DMA_TXCH_RESET_PCNT_S	16
#define    PAS_IOB_DMA_TXCH_RESET_PCNT(x)	(((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \
						 PAS_IOB_DMA_TXCH_RESET_PCNT_M)
#define    PAS_IOB_DMA_TXCH_RESET_PCNTRST	0x00000020
#define    PAS_IOB_DMA_TXCH_RESET_DCNTRST	0x00000010
#define    PAS_IOB_DMA_TXCH_RESET_TINTC		0x00000008
#define    PAS_IOB_DMA_TXCH_RESET_DINTC		0x00000004
#define    PAS_IOB_DMA_TXCH_RESET_SINTC		0x00000002
#define    PAS_IOB_DMA_TXCH_RESET_PINTC		0x00000001

#define PAS_IOB_DMA_COM_TIMEOUTCFG		0x1700
#define    PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M	0x00ffffff
#define    PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S	0
#define    PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x)	(((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \
						 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M)

/* Transmit descriptor fields */
#define	XCT_MACTX_T		0x8000000000000000ull
#define	XCT_MACTX_ST		0x4000000000000000ull
#define XCT_MACTX_NORES		0x0000000000000000ull
#define XCT_MACTX_8BRES		0x1000000000000000ull
#define XCT_MACTX_24BRES	0x2000000000000000ull
#define XCT_MACTX_40BRES	0x3000000000000000ull
#define XCT_MACTX_I		0x0800000000000000ull
#define XCT_MACTX_O		0x0400000000000000ull
#define XCT_MACTX_E		0x0200000000000000ull
#define XCT_MACTX_VLAN_M	0x0180000000000000ull
#define XCT_MACTX_VLAN_NOP	0x0000000000000000ull
#define XCT_MACTX_VLAN_REMOVE	0x0080000000000000ull
#define XCT_MACTX_VLAN_INSERT   0x0100000000000000ull
#define XCT_MACTX_VLAN_REPLACE  0x0180000000000000ull
#define XCT_MACTX_CRC_M		0x0060000000000000ull
#define XCT_MACTX_CRC_NOP	0x0000000000000000ull
#define XCT_MACTX_CRC_INSERT	0x0020000000000000ull
#define XCT_MACTX_CRC_PAD	0x0040000000000000ull
#define XCT_MACTX_CRC_REPLACE	0x0060000000000000ull
#define XCT_MACTX_SS		0x0010000000000000ull
#define XCT_MACTX_LLEN_M	0x00007fff00000000ull
#define XCT_MACTX_LLEN_S	32ull
#define XCT_MACTX_LLEN(x)	((((long)(x)) << XCT_MACTX_LLEN_S) & \
				 XCT_MACTX_LLEN_M)
#define XCT_MACTX_IPH_M		0x00000000f8000000ull
#define XCT_MACTX_IPH_S		27ull
#define XCT_MACTX_IPH(x)	((((long)(x)) << XCT_MACTX_IPH_S) & \
				 XCT_MACTX_IPH_M)
#define XCT_MACTX_IPO_M		0x0000000007c00000ull
#define XCT_MACTX_IPO_S		22ull
#define XCT_MACTX_IPO(x)	((((long)(x)) << XCT_MACTX_IPO_S) & \
				 XCT_MACTX_IPO_M)
#define XCT_MACTX_CSUM_M	0x0000000000000060ull
#define XCT_MACTX_CSUM_NOP	0x0000000000000000ull
#define XCT_MACTX_CSUM_TCP	0x0000000000000040ull
#define XCT_MACTX_CSUM_UDP	0x0000000000000060ull
#define XCT_MACTX_V6		0x0000000000000010ull
#define XCT_MACTX_C		0x0000000000000004ull
#define XCT_MACTX_AL2		0x0000000000000002ull

/* Receive descriptor fields */
#define	XCT_MACRX_T		0x8000000000000000ull
#define	XCT_MACRX_ST		0x4000000000000000ull
#define XCT_MACRX_RR_M		0x3000000000000000ull
#define XCT_MACRX_RR_NORES	0x0000000000000000ull
#define XCT_MACRX_RR_8BRES	0x1000000000000000ull
#define XCT_MACRX_O		0x0400000000000000ull
#define XCT_MACRX_E		0x0200000000000000ull
#define XCT_MACRX_FF		0x0100000000000000ull
#define XCT_MACRX_PF		0x0080000000000000ull
#define XCT_MACRX_OB		0x0040000000000000ull
#define XCT_MACRX_OD		0x0020000000000000ull
#define XCT_MACRX_FS		0x0010000000000000ull
#define XCT_MACRX_NB_M		0x000fc00000000000ull
#define XCT_MACRX_NB_S		46ULL
#define XCT_MACRX_NB(x)		((((long)(x)) << XCT_MACRX_NB_S) & \
				 XCT_MACRX_NB_M)
#define XCT_MACRX_LLEN_M	0x00003fff00000000ull
#define XCT_MACRX_LLEN_S	32ULL
#define XCT_MACRX_LLEN(x)	((((long)(x)) << XCT_MACRX_LLEN_S) & \
				 XCT_MACRX_LLEN_M)
#define XCT_MACRX_CRC		0x0000000080000000ull
#define XCT_MACRX_LEN_M		0x0000000060000000ull
#define XCT_MACRX_LEN_TOOSHORT	0x0000000020000000ull
#define XCT_MACRX_LEN_BELOWMIN	0x0000000040000000ull
#define XCT_MACRX_LEN_TRUNC	0x0000000060000000ull
#define XCT_MACRX_CAST_M	0x0000000018000000ull
#define XCT_MACRX_CAST_UNI	0x0000000000000000ull
#define XCT_MACRX_CAST_MULTI	0x0000000008000000ull
#define XCT_MACRX_CAST_BROAD	0x0000000010000000ull
#define XCT_MACRX_CAST_PAUSE	0x0000000018000000ull
#define XCT_MACRX_VLC_M		0x0000000006000000ull
#define XCT_MACRX_FM		0x0000000001000000ull
#define XCT_MACRX_HTY_M		0x0000000000c00000ull
#define XCT_MACRX_HTY_IPV4_OK	0x0000000000000000ull
#define XCT_MACRX_HTY_IPV6 	0x0000000000400000ull
#define XCT_MACRX_HTY_IPV4_BAD	0x0000000000800000ull
#define XCT_MACRX_HTY_NONIP	0x0000000000c00000ull
#define XCT_MACRX_IPP_M		0x00000000003f0000ull
#define XCT_MACRX_IPP_S		16
#define XCT_MACRX_CSUM_M	0x000000000000ffffull
#define XCT_MACRX_CSUM_S	0

#define XCT_PTR_T		0x8000000000000000ull
#define XCT_PTR_LEN_M		0x7ffff00000000000ull
#define XCT_PTR_LEN_S		44
#define XCT_PTR_LEN(x)		((((long)(x)) << XCT_PTR_LEN_S) & \
				 XCT_PTR_LEN_M)
#define XCT_PTR_ADDR_M		0x00000fffffffffffull
#define XCT_PTR_ADDR_S		0
#define XCT_PTR_ADDR(x)		((((long)(x)) << XCT_PTR_ADDR_S) & \
				 XCT_PTR_ADDR_M)

/* Receive interface 8byte result fields */
#define XCT_RXRES_8B_L4O_M	0xff00000000000000ull
#define XCT_RXRES_8B_L4O_S	56
#define XCT_RXRES_8B_RULE_M	0x00ffff0000000000ull
#define XCT_RXRES_8B_RULE_S	40
#define XCT_RXRES_8B_EVAL_M	0x000000ffff000000ull
#define XCT_RXRES_8B_EVAL_S	24
#define XCT_RXRES_8B_HTYPE_M	0x0000000000f00000ull
#define XCT_RXRES_8B_HASH_M	0x00000000000fffffull
#define XCT_RXRES_8B_HASH_S	0

/* Receive interface buffer fields */
#define XCT_RXB_LEN_M		0x0ffff00000000000ull
#define XCT_RXB_LEN_S		44
#define XCT_RXB_LEN(x)		((((long)(x)) << XCT_RXB_LEN_S) & \
				 XCT_RXB_LEN_M)
#define XCT_RXB_ADDR_M		0x00000fffffffffffull
#define XCT_RXB_ADDR_S		0
#define XCT_RXB_ADDR(x)		((((long)(x)) << XCT_RXB_ADDR_S) & \
				 XCT_RXB_ADDR_M)

/* Copy descriptor fields */
#define XCT_COPY_T		0x8000000000000000ull
#define XCT_COPY_ST		0x4000000000000000ull
#define XCT_COPY_RR_M		0x3000000000000000ull
#define XCT_COPY_RR_NORES	0x0000000000000000ull
#define XCT_COPY_RR_8BRES	0x1000000000000000ull
#define XCT_COPY_RR_24BRES	0x2000000000000000ull
#define XCT_COPY_RR_40BRES	0x3000000000000000ull
#define XCT_COPY_I		0x0800000000000000ull
#define XCT_COPY_O		0x0400000000000000ull
#define XCT_COPY_E		0x0200000000000000ull
#define XCT_COPY_STY_ZERO	0x01c0000000000000ull
#define XCT_COPY_DTY_PREF	0x0038000000000000ull
#define XCT_COPY_LLEN_M		0x0007ffff00000000ull
#define XCT_COPY_LLEN_S		32
#define XCT_COPY_LLEN(x)	((((long)(x)) << XCT_COPY_LLEN_S) & \
				 XCT_COPY_LLEN_M)
#define XCT_COPY_SE		0x0000000000000001ull

/* Control descriptor fields */
#define CTRL_CMD_T		0x8000000000000000ull
#define CTRL_CMD_META_EVT	0x2000000000000000ull
#define CTRL_CMD_O		0x0400000000000000ull
#define CTRL_CMD_REG_M		0x000000000000000full
#define CTRL_CMD_REG_S		0
#define CTRL_CMD_REG(x)		((((long)(x)) << CTRL_CMD_REG_S) & \
				 CTRL_CMD_REG_M)


#endif /* ASM_PASEMI_DMA_H */
Commit	Line	Data
40afa531 OJ	1	/*
	2	* Copyright (C) 2006 PA Semi, Inc
	3	*
	4	* Hardware register layout and descriptor formats for the on-board
	5	* DMA engine on PA Semi PWRficient. Used by ethernet, function and security
	6	* drivers.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21
	22	#ifndef ASM_PASEMI_DMA_H
	23	#define ASM_PASEMI_DMA_H
	24
	25	/* status register layout in IOB region, at 0xfb800000 */
	26	struct pasdma_status {
	27	u64 rx_sta[64]; /* RX channel status */
	28	u64 tx_sta[20]; /* TX channel status */
	29	};
	30
	31
	32	/* All these registers live in the PCI configuration space for the DMA PCI
	33	* device. Use the normal PCI config access functions for them.
	34	*/
	35	enum {
	36	PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */
	37	PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */
	38	PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */
	39	PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */
	40	};
	41	#define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */
	42	#define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */
	43	#define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */
	44	#define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */
	45
	46
	47	/* Per-interface and per-channel registers */
	48	#define _PAS_DMA_RXINT_STRIDE 0x20
	49	#define PAS_DMA_RXINT_RCMDSTA(i) (0x200+(i)*_PAS_DMA_RXINT_STRIDE)
	50	#define PAS_DMA_RXINT_RCMDSTA_EN 0x00000001
	51	#define PAS_DMA_RXINT_RCMDSTA_ST 0x00000002
	52	#define PAS_DMA_RXINT_RCMDSTA_MBT 0x00000008
	53	#define PAS_DMA_RXINT_RCMDSTA_MDR 0x00000010
	54	#define PAS_DMA_RXINT_RCMDSTA_MOO 0x00000020
	55	#define PAS_DMA_RXINT_RCMDSTA_MBP 0x00000040
	56	#define PAS_DMA_RXINT_RCMDSTA_BT 0x00000800
	57	#define PAS_DMA_RXINT_RCMDSTA_DR 0x00001000
	58	#define PAS_DMA_RXINT_RCMDSTA_OO 0x00002000
	59	#define PAS_DMA_RXINT_RCMDSTA_BP 0x00004000
	60	#define PAS_DMA_RXINT_RCMDSTA_TB 0x00008000
	61	#define PAS_DMA_RXINT_RCMDSTA_ACT 0x00010000
	62	#define PAS_DMA_RXINT_RCMDSTA_DROPS_M 0xfffe0000
	63	#define PAS_DMA_RXINT_RCMDSTA_DROPS_S 17
	64	#define PAS_DMA_RXINT_CFG(i) (0x204+(i)*_PAS_DMA_RXINT_STRIDE)
65	#define PAS_DMA_RXINT_CFG_RBP 0x80000000
66	#define PAS_DMA_RXINT_CFG_ITRR 0x40000000
67	#define PAS_DMA_RXINT_CFG_DHL_M 0x07000000
68	#define PAS_DMA_RXINT_CFG_DHL_S 24
69	#define PAS_DMA_RXINT_CFG_DHL(x) (((x) << PAS_DMA_RXINT_CFG_DHL_S) & \
70	PAS_DMA_RXINT_CFG_DHL_M)
71	#define PAS_DMA_RXINT_CFG_ITR 0x00400000
72	#define PAS_DMA_RXINT_CFG_LW 0x00200000
73	#define PAS_DMA_RXINT_CFG_L2 0x00100000
74	#define PAS_DMA_RXINT_CFG_HEN 0x00080000
75	#define PAS_DMA_RXINT_CFG_WIF 0x00000002
76	#define PAS_DMA_RXINT_CFG_WIL 0x00000001
77
78	#define PAS_DMA_RXINT_INCR(i) (0x210+(i)*_PAS_DMA_RXINT_STRIDE)
79	#define PAS_DMA_RXINT_INCR_INCR_M 0x0000ffff
80	#define PAS_DMA_RXINT_INCR_INCR_S 0
81	#define PAS_DMA_RXINT_INCR_INCR(x) ((x) & 0x0000ffff)
82	#define PAS_DMA_RXINT_BASEL(i) (0x218+(i)*_PAS_DMA_RXINT_STRIDE)
83	#define PAS_DMA_RXINT_BASEL_BRBL(x) ((x) & ~0x3f)
84	#define PAS_DMA_RXINT_BASEU(i) (0x21c+(i)*_PAS_DMA_RXINT_STRIDE)
85	#define PAS_DMA_RXINT_BASEU_BRBH(x) ((x) & 0xfff)
86	#define PAS_DMA_RXINT_BASEU_SIZ_M 0x3fff0000 /* # of cache lines worth of buffer ring */
87	#define PAS_DMA_RXINT_BASEU_SIZ_S 16 /* 0 = 16K */
88	#define PAS_DMA_RXINT_BASEU_SIZ(x) (((x) << PAS_DMA_RXINT_BASEU_SIZ_S) & \
89	PAS_DMA_RXINT_BASEU_SIZ_M)
90
91
92	#define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */
93	#define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */
94	#define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */
95	#define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */
96	#define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */
97	#define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */
98	#define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */
99	#define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */
100	#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE)
101	#define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */
102	#define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */
103	#define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */
104	#define PAS_DMA_TXCHAN_TCMDSTA_SZ 0x00000800
105	#define PAS_DMA_TXCHAN_TCMDSTA_DB 0x00000400
106	#define PAS_DMA_TXCHAN_TCMDSTA_DE 0x00000200
107	#define PAS_DMA_TXCHAN_TCMDSTA_DA 0x00000100
108	#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE)
109	#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */
110	#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c
111	#define PAS_DMA_TXCHAN_CFG_TATTR_S 2
112	#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \
113	PAS_DMA_TXCHAN_CFG_TATTR_M)
114	#define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0
115	#define PAS_DMA_TXCHAN_CFG_WT_S 6
116	#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \
117	PAS_DMA_TXCHAN_CFG_WT_M)
118	#define PAS_DMA_TXCHAN_CFG_TRD 0x00010000 /* translate data */
119	#define PAS_DMA_TXCHAN_CFG_TRR 0x00008000 /* translate rings */
120	#define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */
121	#define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */
122	#define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */
123	#define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE)
124	#define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE)
125	#define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0
126	#define PAS_DMA_TXCHAN_BASEL_BRBL_S 0
127	#define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \
128	PAS_DMA_TXCHAN_BASEL_BRBL_M)
129	#define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE)
130	#define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff
131	#define PAS_DMA_TXCHAN_BASEU_BRBH_S 0
132	#define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \
133	PAS_DMA_TXCHAN_BASEU_BRBH_M)
134	/* # of cache lines worth of buffer ring */
135	#define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000
136	#define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */
137	#define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \
138	PAS_DMA_TXCHAN_BASEU_SIZ_M)
139
140	#define _PAS_DMA_RXCHAN_STRIDE 0x20 /* Size per channel */
141	#define _PAS_DMA_RXCHAN_CCMDSTA 0x800 /* Command / Status */
142	#define _PAS_DMA_RXCHAN_CFG 0x804 /* Configuration */
143	#define _PAS_DMA_RXCHAN_INCR 0x810 /* Descriptor increment */
144	#define _PAS_DMA_RXCHAN_CNT 0x814 /* Descriptor count/offset */
145	#define _PAS_DMA_RXCHAN_BASEL 0x818 /* Descriptor ring base (low) */
146	#define _PAS_DMA_RXCHAN_BASEU 0x81c /* (high) */
147	#define PAS_DMA_RXCHAN_CCMDSTA(c) (0x800+(c)*_PAS_DMA_RXCHAN_STRIDE)
148	#define PAS_DMA_RXCHAN_CCMDSTA_EN 0x00000001 /* Enabled */
149	#define PAS_DMA_RXCHAN_CCMDSTA_ST 0x00000002 /* Stop interface */
150	#define PAS_DMA_RXCHAN_CCMDSTA_ACT 0x00010000 /* Active */
151	#define PAS_DMA_RXCHAN_CCMDSTA_DU 0x00020000
152	#define PAS_DMA_RXCHAN_CCMDSTA_OD 0x00002000
153	#define PAS_DMA_RXCHAN_CCMDSTA_FD 0x00001000
154	#define PAS_DMA_RXCHAN_CCMDSTA_DT 0x00000800
155	#define PAS_DMA_RXCHAN_CFG(c) (0x804+(c)*_PAS_DMA_RXCHAN_STRIDE)
156	#define PAS_DMA_RXCHAN_CFG_CTR 0x00000400
157	#define PAS_DMA_RXCHAN_CFG_HBU_M 0x00000380
158	#define PAS_DMA_RXCHAN_CFG_HBU_S 7
159	#define PAS_DMA_RXCHAN_CFG_HBU(x) (((x) << PAS_DMA_RXCHAN_CFG_HBU_S) & \
160	PAS_DMA_RXCHAN_CFG_HBU_M)
161	#define PAS_DMA_RXCHAN_INCR(c) (0x810+(c)*_PAS_DMA_RXCHAN_STRIDE)
162	#define PAS_DMA_RXCHAN_BASEL(c) (0x818+(c)*_PAS_DMA_RXCHAN_STRIDE)
163	#define PAS_DMA_RXCHAN_BASEL_BRBL_M 0xffffffc0
164	#define PAS_DMA_RXCHAN_BASEL_BRBL_S 0
165	#define PAS_DMA_RXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_RXCHAN_BASEL_BRBL_S) & \
166	PAS_DMA_RXCHAN_BASEL_BRBL_M)
167	#define PAS_DMA_RXCHAN_BASEU(c) (0x81c+(c)*_PAS_DMA_RXCHAN_STRIDE)
168	#define PAS_DMA_RXCHAN_BASEU_BRBH_M 0x00000fff
169	#define PAS_DMA_RXCHAN_BASEU_BRBH_S 0
170	#define PAS_DMA_RXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_RXCHAN_BASEU_BRBH_S) & \
171	PAS_DMA_RXCHAN_BASEU_BRBH_M)
172	/* # of cache lines worth of buffer ring */
173	#define PAS_DMA_RXCHAN_BASEU_SIZ_M 0x3fff0000
174	#define PAS_DMA_RXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */
175	#define PAS_DMA_RXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_RXCHAN_BASEU_SIZ_S) & \
176	PAS_DMA_RXCHAN_BASEU_SIZ_M)
177
178	#define PAS_STATUS_PCNT_M 0x000000000000ffffull
179	#define PAS_STATUS_PCNT_S 0
180	#define PAS_STATUS_DCNT_M 0x00000000ffff0000ull
181	#define PAS_STATUS_DCNT_S 16
182	#define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull
183	#define PAS_STATUS_BPCNT_S 32
184	#define PAS_STATUS_CAUSE_M 0xf000000000000000ull
185	#define PAS_STATUS_TIMER 0x1000000000000000ull
186	#define PAS_STATUS_ERROR 0x2000000000000000ull
187	#define PAS_STATUS_SOFT 0x4000000000000000ull
188	#define PAS_STATUS_INT 0x8000000000000000ull
189
190	#define PAS_IOB_COM_PKTHDRCNT 0x120
191	#define PAS_IOB_COM_PKTHDRCNT_PKTHDR1_M 0x0fff0000
192	#define PAS_IOB_COM_PKTHDRCNT_PKTHDR1_S 16
193	#define PAS_IOB_COM_PKTHDRCNT_PKTHDR0_M 0x00000fff
194	#define PAS_IOB_COM_PKTHDRCNT_PKTHDR0_S 0
195
196	#define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4)
197	#define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff
198	#define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0
199	#define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \
200	PAS_IOB_DMA_RXCH_CFG_CNTTH_M)
201	#define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4)
202	#define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff
203	#define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0
204	#define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \
205	PAS_IOB_DMA_TXCH_CFG_CNTTH_M)
206	#define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4)
207	#define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000
208	#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff
209	#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0
210	#define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\
211	PAS_IOB_DMA_RXCH_STAT_CNTDEL_M)
212	#define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4)
213	#define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000
214	#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff
215	#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0
216	#define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\
217	PAS_IOB_DMA_TXCH_STAT_CNTDEL_M)
218	#define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4)
219	#define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000
220	#define PAS_IOB_DMA_RXCH_RESET_PCNT_S 16
221	#define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \
222	PAS_IOB_DMA_RXCH_RESET_PCNT_M)
223	#define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020
224	#define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010
225	#define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008
226	#define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004
227	#define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002
228	#define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001
229	#define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4)
230	#define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000
231	#define PAS_IOB_DMA_TXCH_RESET_PCNT_S 16
232	#define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \
233	PAS_IOB_DMA_TXCH_RESET_PCNT_M)
234	#define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020
235	#define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010
236	#define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008
237	#define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004
238	#define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002
239	#define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001
240
241	#define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700
242	#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff
243	#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0
244	#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \
245	PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M)
246
247	/* Transmit descriptor fields */
248	#define XCT_MACTX_T 0x8000000000000000ull
249	#define XCT_MACTX_ST 0x4000000000000000ull
250	#define XCT_MACTX_NORES 0x0000000000000000ull
251	#define XCT_MACTX_8BRES 0x1000000000000000ull
252	#define XCT_MACTX_24BRES 0x2000000000000000ull
253	#define XCT_MACTX_40BRES 0x3000000000000000ull
254	#define XCT_MACTX_I 0x0800000000000000ull
255	#define XCT_MACTX_O 0x0400000000000000ull
256	#define XCT_MACTX_E 0x0200000000000000ull
257	#define XCT_MACTX_VLAN_M 0x0180000000000000ull
258	#define XCT_MACTX_VLAN_NOP 0x0000000000000000ull
259	#define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull
260	#define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull
261	#define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull
262	#define XCT_MACTX_CRC_M 0x0060000000000000ull
263	#define XCT_MACTX_CRC_NOP 0x0000000000000000ull
264	#define XCT_MACTX_CRC_INSERT 0x0020000000000000ull
265	#define XCT_MACTX_CRC_PAD 0x0040000000000000ull
266	#define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull
267	#define XCT_MACTX_SS 0x0010000000000000ull
268	#define XCT_MACTX_LLEN_M 0x00007fff00000000ull
269	#define XCT_MACTX_LLEN_S 32ull
270	#define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \
271	XCT_MACTX_LLEN_M)
272	#define XCT_MACTX_IPH_M 0x00000000f8000000ull
273	#define XCT_MACTX_IPH_S 27ull
274	#define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \
275	XCT_MACTX_IPH_M)
276	#define XCT_MACTX_IPO_M 0x0000000007c00000ull
277	#define XCT_MACTX_IPO_S 22ull
278	#define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \
279	XCT_MACTX_IPO_M)
280	#define XCT_MACTX_CSUM_M 0x0000000000000060ull
281	#define XCT_MACTX_CSUM_NOP 0x0000000000000000ull
282	#define XCT_MACTX_CSUM_TCP 0x0000000000000040ull
283	#define XCT_MACTX_CSUM_UDP 0x0000000000000060ull
284	#define XCT_MACTX_V6 0x0000000000000010ull
285	#define XCT_MACTX_C 0x0000000000000004ull
286	#define XCT_MACTX_AL2 0x0000000000000002ull
287
288	/* Receive descriptor fields */
289	#define XCT_MACRX_T 0x8000000000000000ull
290	#define XCT_MACRX_ST 0x4000000000000000ull
291	#define XCT_MACRX_RR_M 0x3000000000000000ull
292	#define XCT_MACRX_RR_NORES 0x0000000000000000ull
293	#define XCT_MACRX_RR_8BRES 0x1000000000000000ull
294	#define XCT_MACRX_O 0x0400000000000000ull
295	#define XCT_MACRX_E 0x0200000000000000ull
296	#define XCT_MACRX_FF 0x0100000000000000ull
297	#define XCT_MACRX_PF 0x0080000000000000ull
298	#define XCT_MACRX_OB 0x0040000000000000ull
299	#define XCT_MACRX_OD 0x0020000000000000ull
300	#define XCT_MACRX_FS 0x0010000000000000ull
301	#define XCT_MACRX_NB_M 0x000fc00000000000ull
302	#define XCT_MACRX_NB_S 46ULL
303	#define XCT_MACRX_NB(x) ((((long)(x)) << XCT_MACRX_NB_S) & \
304	XCT_MACRX_NB_M)
305	#define XCT_MACRX_LLEN_M 0x00003fff00000000ull
306	#define XCT_MACRX_LLEN_S 32ULL
307	#define XCT_MACRX_LLEN(x) ((((long)(x)) << XCT_MACRX_LLEN_S) & \
308	XCT_MACRX_LLEN_M)
309	#define XCT_MACRX_CRC 0x0000000080000000ull
310	#define XCT_MACRX_LEN_M 0x0000000060000000ull
311	#define XCT_MACRX_LEN_TOOSHORT 0x0000000020000000ull
312	#define XCT_MACRX_LEN_BELOWMIN 0x0000000040000000ull
313	#define XCT_MACRX_LEN_TRUNC 0x0000000060000000ull
314	#define XCT_MACRX_CAST_M 0x0000000018000000ull
315	#define XCT_MACRX_CAST_UNI 0x0000000000000000ull
316	#define XCT_MACRX_CAST_MULTI 0x0000000008000000ull
317	#define XCT_MACRX_CAST_BROAD 0x0000000010000000ull
318	#define XCT_MACRX_CAST_PAUSE 0x0000000018000000ull
319	#define XCT_MACRX_VLC_M 0x0000000006000000ull
320	#define XCT_MACRX_FM 0x0000000001000000ull
321	#define XCT_MACRX_HTY_M 0x0000000000c00000ull
322	#define XCT_MACRX_HTY_IPV4_OK 0x0000000000000000ull
323	#define XCT_MACRX_HTY_IPV6 0x0000000000400000ull
324	#define XCT_MACRX_HTY_IPV4_BAD 0x0000000000800000ull
325	#define XCT_MACRX_HTY_NONIP 0x0000000000c00000ull
326	#define XCT_MACRX_IPP_M 0x00000000003f0000ull
327	#define XCT_MACRX_IPP_S 16
328	#define XCT_MACRX_CSUM_M 0x000000000000ffffull
329	#define XCT_MACRX_CSUM_S 0
330
331	#define XCT_PTR_T 0x8000000000000000ull
332	#define XCT_PTR_LEN_M 0x7ffff00000000000ull
333	#define XCT_PTR_LEN_S 44
334	#define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \
335	XCT_PTR_LEN_M)
336	#define XCT_PTR_ADDR_M 0x00000fffffffffffull
337	#define XCT_PTR_ADDR_S 0
338	#define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \
339	XCT_PTR_ADDR_M)
340
341	/* Receive interface 8byte result fields */
342	#define XCT_RXRES_8B_L4O_M 0xff00000000000000ull
343	#define XCT_RXRES_8B_L4O_S 56
344	#define XCT_RXRES_8B_RULE_M 0x00ffff0000000000ull
345	#define XCT_RXRES_8B_RULE_S 40
346	#define XCT_RXRES_8B_EVAL_M 0x000000ffff000000ull
347	#define XCT_RXRES_8B_EVAL_S 24
348	#define XCT_RXRES_8B_HTYPE_M 0x0000000000f00000ull
349	#define XCT_RXRES_8B_HASH_M 0x00000000000fffffull
350	#define XCT_RXRES_8B_HASH_S 0
351
352	/* Receive interface buffer fields */
353	#define XCT_RXB_LEN_M 0x0ffff00000000000ull
354	#define XCT_RXB_LEN_S 44
355	#define XCT_RXB_LEN(x) ((((long)(x)) << XCT_RXB_LEN_S) & \
356	XCT_RXB_LEN_M)
357	#define XCT_RXB_ADDR_M 0x00000fffffffffffull
358	#define XCT_RXB_ADDR_S 0
359	#define XCT_RXB_ADDR(x) ((((long)(x)) << XCT_RXB_ADDR_S) & \
360	XCT_RXB_ADDR_M)
361
362	/* Copy descriptor fields */
363	#define XCT_COPY_T 0x8000000000000000ull
364	#define XCT_COPY_ST 0x4000000000000000ull
365	#define XCT_COPY_RR_M 0x3000000000000000ull
366	#define XCT_COPY_RR_NORES 0x0000000000000000ull
367	#define XCT_COPY_RR_8BRES 0x1000000000000000ull
368	#define XCT_COPY_RR_24BRES 0x2000000000000000ull
369	#define XCT_COPY_RR_40BRES 0x3000000000000000ull
370	#define XCT_COPY_I 0x0800000000000000ull
371	#define XCT_COPY_O 0x0400000000000000ull
372	#define XCT_COPY_E 0x0200000000000000ull
373	#define XCT_COPY_STY_ZERO 0x01c0000000000000ull
374	#define XCT_COPY_DTY_PREF 0x0038000000000000ull
375	#define XCT_COPY_LLEN_M 0x0007ffff00000000ull
376	#define XCT_COPY_LLEN_S 32
377	#define XCT_COPY_LLEN(x) ((((long)(x)) << XCT_COPY_LLEN_S) & \
378	XCT_COPY_LLEN_M)
379	#define XCT_COPY_SE 0x0000000000000001ull
380
381	/* Control descriptor fields */
382	#define CTRL_CMD_T 0x8000000000000000ull
383	#define CTRL_CMD_META_EVT 0x2000000000000000ull
384	#define CTRL_CMD_O 0x0400000000000000ull
385	#define CTRL_CMD_REG_M 0x000000000000000full
386	#define CTRL_CMD_REG_S 0
387	#define CTRL_CMD_REG(x) ((((long)(x)) << CTRL_CMD_REG_S) & \
388	CTRL_CMD_REG_M)
389
390
391	#endif /* ASM_PASEMI_DMA_H */