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da80d460 SR |
1 | #ifndef _ASM_POWERPC_PTRACE_H |
2 | #define _ASM_POWERPC_PTRACE_H | |
1da177e4 LT |
3 | |
4 | /* | |
5 | * Copyright (C) 2001 PPC64 Team, IBM Corp | |
6 | * | |
7 | * This struct defines the way the registers are stored on the | |
8 | * kernel stack during a system call or other kernel entry. | |
9 | * | |
10 | * this should only contain volatile regs | |
11 | * since we can keep non-volatile in the thread_struct | |
12 | * should set this up when only volatiles are saved | |
13 | * by intr code. | |
14 | * | |
15 | * Since this is going on the stack, *CARE MUST BE TAKEN* to insure | |
16 | * that the overall structure is a multiple of 16 bytes in length. | |
17 | * | |
18 | * Note that the offsets of the fields in this struct correspond with | |
da80d460 | 19 | * the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c. |
1da177e4 LT |
20 | * |
21 | * This program is free software; you can redistribute it and/or | |
22 | * modify it under the terms of the GNU General Public License | |
23 | * as published by the Free Software Foundation; either version | |
24 | * 2 of the License, or (at your option) any later version. | |
25 | */ | |
26 | ||
27 | #ifndef __ASSEMBLY__ | |
a0987224 | 28 | |
1da177e4 | 29 | struct pt_regs { |
a0987224 AB |
30 | unsigned long gpr[32]; |
31 | unsigned long nip; | |
32 | unsigned long msr; | |
da80d460 | 33 | unsigned long orig_gpr3; /* Used for restarting system calls */ |
a0987224 AB |
34 | unsigned long ctr; |
35 | unsigned long link; | |
36 | unsigned long xer; | |
37 | unsigned long ccr; | |
da80d460 SR |
38 | #ifdef __powerpc64__ |
39 | unsigned long softe; /* Soft enabled/disabled */ | |
40 | #else | |
41 | unsigned long mq; /* 601 only (not used at present) */ | |
42 | /* Used on APUS to hold IPL value. */ | |
43 | #endif | |
44 | unsigned long trap; /* Reason for being here */ | |
45 | /* N.B. for critical exceptions on 4xx, the dar and dsisr | |
46 | fields are overloaded to hold srr0 and srr1. */ | |
47 | unsigned long dar; /* Fault registers */ | |
48 | unsigned long dsisr; /* on 4xx/Book-E used for ESR */ | |
49 | unsigned long result; /* Result of a system call */ | |
1da177e4 LT |
50 | }; |
51 | ||
da80d460 | 52 | #endif /* __ASSEMBLY__ */ |
1da177e4 | 53 | |
a0987224 AB |
54 | #ifdef __KERNEL__ |
55 | ||
da80d460 SR |
56 | #ifdef __powerpc64__ |
57 | ||
58 | #define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */ | |
59 | ||
60 | /* Size of dummy stack frame allocated when calling signal handler. */ | |
61 | #define __SIGNAL_FRAMESIZE 128 | |
62 | #define __SIGNAL_FRAMESIZE32 64 | |
63 | ||
64 | #else /* __powerpc64__ */ | |
65 | ||
66 | #define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ | |
67 | ||
68 | /* Size of stack frame allocated when calling signal handler. */ | |
69 | #define __SIGNAL_FRAMESIZE 64 | |
70 | ||
71 | #endif /* __powerpc64__ */ | |
a0987224 | 72 | |
da80d460 SR |
73 | #ifndef __ASSEMBLY__ |
74 | ||
75 | #define instruction_pointer(regs) ((regs)->nip) | |
1da177e4 LT |
76 | #ifdef CONFIG_SMP |
77 | extern unsigned long profile_pc(struct pt_regs *regs); | |
78 | #else | |
79 | #define profile_pc(regs) instruction_pointer(regs) | |
80 | #endif | |
81 | ||
da80d460 | 82 | #ifdef __powerpc64__ |
1da177e4 | 83 | #define user_mode(regs) ((((regs)->msr) >> MSR_PR_LG) & 0x1) |
da80d460 SR |
84 | #else |
85 | #define user_mode(regs) (((regs)->msr & MSR_PR) != 0) | |
86 | #endif | |
1da177e4 LT |
87 | |
88 | #define force_successful_syscall_return() \ | |
da80d460 | 89 | do { \ |
401d1f02 | 90 | set_thread_flag(TIF_NOERROR); \ |
da80d460 | 91 | } while(0) |
1da177e4 LT |
92 | |
93 | /* | |
94 | * We use the least-significant bit of the trap field to indicate | |
95 | * whether we have saved the full set of registers, or only a | |
96 | * partial set. A 1 there means the partial set. | |
da80d460 SR |
97 | * On 4xx we use the next bit to indicate whether the exception |
98 | * is a critical exception (1 means it is). | |
1da177e4 LT |
99 | */ |
100 | #define FULL_REGS(regs) (((regs)->trap & 1) == 0) | |
da80d460 SR |
101 | #ifndef __powerpc64__ |
102 | #define IS_CRITICAL_EXC(regs) (((regs)->trap & 2) == 0) | |
103 | #endif /* ! __powerpc64__ */ | |
1da177e4 | 104 | #define TRAP(regs) ((regs)->trap & ~0xF) |
da80d460 | 105 | #ifdef __powerpc64__ |
1da177e4 | 106 | #define CHECK_FULL_REGS(regs) BUG_ON(regs->trap & 1) |
da80d460 SR |
107 | #else |
108 | #define CHECK_FULL_REGS(regs) \ | |
109 | do { \ | |
110 | if ((regs)->trap & 1) \ | |
111 | printk(KERN_CRIT "%s: partial register set\n", __FUNCTION__); \ | |
112 | } while (0) | |
113 | #endif /* __powerpc64__ */ | |
a0987224 AB |
114 | |
115 | #endif /* __ASSEMBLY__ */ | |
116 | ||
da80d460 | 117 | #endif /* __KERNEL__ */ |
a0987224 | 118 | |
1da177e4 LT |
119 | /* |
120 | * Offsets used by 'ptrace' system call interface. | |
da80d460 SR |
121 | * These can't be changed without breaking binary compatibility |
122 | * with MkLinux, etc. | |
1da177e4 LT |
123 | */ |
124 | #define PT_R0 0 | |
125 | #define PT_R1 1 | |
126 | #define PT_R2 2 | |
127 | #define PT_R3 3 | |
128 | #define PT_R4 4 | |
129 | #define PT_R5 5 | |
130 | #define PT_R6 6 | |
131 | #define PT_R7 7 | |
132 | #define PT_R8 8 | |
133 | #define PT_R9 9 | |
134 | #define PT_R10 10 | |
135 | #define PT_R11 11 | |
136 | #define PT_R12 12 | |
137 | #define PT_R13 13 | |
138 | #define PT_R14 14 | |
139 | #define PT_R15 15 | |
140 | #define PT_R16 16 | |
141 | #define PT_R17 17 | |
142 | #define PT_R18 18 | |
143 | #define PT_R19 19 | |
144 | #define PT_R20 20 | |
145 | #define PT_R21 21 | |
146 | #define PT_R22 22 | |
147 | #define PT_R23 23 | |
148 | #define PT_R24 24 | |
149 | #define PT_R25 25 | |
150 | #define PT_R26 26 | |
151 | #define PT_R27 27 | |
152 | #define PT_R28 28 | |
153 | #define PT_R29 29 | |
154 | #define PT_R30 30 | |
155 | #define PT_R31 31 | |
156 | ||
157 | #define PT_NIP 32 | |
158 | #define PT_MSR 33 | |
159 | #ifdef __KERNEL__ | |
160 | #define PT_ORIG_R3 34 | |
161 | #endif | |
162 | #define PT_CTR 35 | |
163 | #define PT_LNK 36 | |
164 | #define PT_XER 37 | |
165 | #define PT_CCR 38 | |
da80d460 SR |
166 | #ifndef __powerpc64__ |
167 | #define PT_MQ 39 | |
168 | #else | |
1da177e4 | 169 | #define PT_SOFTE 39 |
a0987224 AB |
170 | #define PT_TRAP 40 |
171 | #define PT_DAR 41 | |
172 | #define PT_DSISR 42 | |
1da177e4 | 173 | #define PT_RESULT 43 |
da80d460 | 174 | #endif |
1da177e4 | 175 | |
da80d460 SR |
176 | #define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ |
177 | ||
178 | #ifndef __powerpc64__ | |
179 | ||
180 | #define PT_FPR31 (PT_FPR0 + 2*31) | |
181 | #define PT_FPSCR (PT_FPR0 + 2*32 + 1) | |
182 | ||
183 | #else /* __powerpc64__ */ | |
1da177e4 | 184 | |
a0987224 | 185 | #define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */ |
1da177e4 LT |
186 | |
187 | #ifdef __KERNEL__ | |
a0987224 | 188 | #define PT_FPSCR32 (PT_FPR0 + 2*32 + 1) /* each FP reg occupies 2 32-bit userspace slots */ |
1da177e4 LT |
189 | #endif |
190 | ||
191 | #define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */ | |
192 | #define PT_VSCR (PT_VR0 + 32*2 + 1) | |
193 | #define PT_VRSAVE (PT_VR0 + 33*2) | |
194 | ||
195 | #ifdef __KERNEL__ | |
196 | #define PT_VR0_32 164 /* each Vector reg occupies 4 slots in 32-bit */ | |
197 | #define PT_VSCR_32 (PT_VR0 + 32*4 + 3) | |
198 | #define PT_VRSAVE_32 (PT_VR0 + 33*4) | |
199 | #endif | |
200 | ||
da80d460 SR |
201 | #endif /* __powerpc64__ */ |
202 | ||
1da177e4 | 203 | /* |
da80d460 SR |
204 | * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go. |
205 | * The transfer totals 34 quadword. Quadwords 0-31 contain the | |
206 | * corresponding vector registers. Quadword 32 contains the vscr as the | |
207 | * last word (offset 12) within that quadword. Quadword 33 contains the | |
1da177e4 LT |
208 | * vrsave as the first word (offset 0) within the quadword. |
209 | * | |
da80d460 SR |
210 | * This definition of the VMX state is compatible with the current PPC32 |
211 | * ptrace interface. This allows signal handling and ptrace to use the same | |
212 | * structures. This also simplifies the implementation of a bi-arch | |
1da177e4 LT |
213 | * (combined (32- and 64-bit) gdb. |
214 | */ | |
215 | #define PTRACE_GETVRREGS 18 | |
216 | #define PTRACE_SETVRREGS 19 | |
217 | ||
da80d460 SR |
218 | /* Get/set all the upper 32-bits of the SPE registers, accumulator, and |
219 | * spefscr, in one go */ | |
220 | #define PTRACE_GETEVRREGS 20 | |
221 | #define PTRACE_SETEVRREGS 21 | |
1da177e4 | 222 | |
a94d3085 AB |
223 | /* |
224 | * Get or set a debug register. The first 16 are DABR registers and the | |
225 | * second 16 are IABR registers. | |
226 | */ | |
227 | #define PTRACE_GET_DEBUGREG 25 | |
228 | #define PTRACE_SET_DEBUGREG 26 | |
229 | ||
a0987224 AB |
230 | /* Additional PTRACE requests implemented on PowerPC. */ |
231 | #define PPC_PTRACE_GETREGS 0x99 /* Get GPRs 0 - 31 */ | |
232 | #define PPC_PTRACE_SETREGS 0x98 /* Set GPRs 0 - 31 */ | |
233 | #define PPC_PTRACE_GETFPREGS 0x97 /* Get FPRs 0 - 31 */ | |
234 | #define PPC_PTRACE_SETFPREGS 0x96 /* Set FPRs 0 - 31 */ | |
235 | ||
236 | /* Calls to trace a 64bit program from a 32bit program */ | |
237 | #define PPC_PTRACE_PEEKTEXT_3264 0x95 | |
238 | #define PPC_PTRACE_PEEKDATA_3264 0x94 | |
239 | #define PPC_PTRACE_POKETEXT_3264 0x93 | |
240 | #define PPC_PTRACE_POKEDATA_3264 0x92 | |
241 | #define PPC_PTRACE_PEEKUSR_3264 0x91 | |
242 | #define PPC_PTRACE_POKEUSR_3264 0x90 | |
1da177e4 | 243 | |
da80d460 | 244 | #endif /* _ASM_POWERPC_PTRACE_H */ |