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67207b96 AB |
1 | /* |
2 | * SPU core / file system interface and HW structures | |
3 | * | |
4 | * (C) Copyright IBM Deutschland Entwicklung GmbH 2005 | |
5 | * | |
6 | * Author: Arnd Bergmann <arndb@de.ibm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #ifndef _SPU_H | |
24 | #define _SPU_H | |
25 | #include <linux/config.h> | |
26 | #include <linux/kref.h> | |
27 | #include <linux/workqueue.h> | |
28 | ||
29 | #define LS_ORDER (6) /* 256 kb */ | |
30 | ||
31 | #define LS_SIZE (PAGE_SIZE << LS_ORDER) | |
32 | ||
33 | struct spu { | |
34 | char *name; | |
35 | unsigned long local_store_phys; | |
36 | u8 *local_store; | |
37 | struct spu_problem __iomem *problem; | |
38 | struct spu_priv1 __iomem *priv1; | |
39 | struct spu_priv2 __iomem *priv2; | |
40 | struct list_head list; | |
41 | int number; | |
42 | u32 isrc; | |
43 | u32 node; | |
44 | struct kref kref; | |
45 | size_t ls_size; | |
46 | unsigned int slb_replace; | |
47 | struct mm_struct *mm; | |
48 | int class_0_pending; | |
49 | spinlock_t register_lock; | |
50 | ||
51 | u32 stop_code; | |
52 | wait_queue_head_t stop_wq; | |
53 | wait_queue_head_t ibox_wq; | |
54 | wait_queue_head_t wbox_wq; | |
55 | struct fasync_struct *ibox_fasync; | |
56 | struct fasync_struct *wbox_fasync; | |
57 | ||
58 | char irq_c0[8]; | |
59 | char irq_c1[8]; | |
60 | char irq_c2[8]; | |
61 | }; | |
62 | ||
63 | struct spu *spu_alloc(void); | |
64 | void spu_free(struct spu *spu); | |
65 | int spu_run(struct spu *spu); | |
66 | ||
67 | size_t spu_wbox_write(struct spu *spu, u32 data); | |
68 | size_t spu_ibox_read(struct spu *spu, u32 *data); | |
69 | ||
70 | extern struct spufs_calls { | |
71 | asmlinkage long (*create_thread)(const char __user *name, | |
72 | unsigned int flags, mode_t mode); | |
73 | asmlinkage long (*spu_run)(struct file *filp, __u32 __user *unpc, | |
74 | __u32 __user *ustatus); | |
75 | struct module *owner; | |
76 | } spufs_calls; | |
77 | ||
78 | #ifdef CONFIG_SPU_FS_MODULE | |
79 | int register_spu_syscalls(struct spufs_calls *calls); | |
80 | void unregister_spu_syscalls(struct spufs_calls *calls); | |
81 | #else | |
82 | static inline int register_spu_syscalls(struct spufs_calls *calls) | |
83 | { | |
84 | return 0; | |
85 | } | |
86 | static inline void unregister_spu_syscalls(struct spufs_calls *calls) | |
87 | { | |
88 | } | |
89 | #endif /* MODULE */ | |
90 | ||
91 | ||
92 | /* | |
93 | * This defines the Local Store, Problem Area and Privlege Area of an SPU. | |
94 | */ | |
95 | ||
96 | union mfc_tag_size_class_cmd { | |
97 | struct { | |
98 | u16 mfc_size; | |
99 | u16 mfc_tag; | |
100 | u8 pad; | |
101 | u8 mfc_rclassid; | |
102 | u16 mfc_cmd; | |
103 | } u; | |
104 | struct { | |
105 | u32 mfc_size_tag32; | |
106 | u32 mfc_class_cmd32; | |
107 | } by32; | |
108 | u64 all64; | |
109 | }; | |
110 | ||
111 | struct mfc_cq_sr { | |
112 | u64 mfc_cq_data0_RW; | |
113 | u64 mfc_cq_data1_RW; | |
114 | u64 mfc_cq_data2_RW; | |
115 | u64 mfc_cq_data3_RW; | |
116 | }; | |
117 | ||
118 | struct spu_problem { | |
119 | #define MS_SYNC_PENDING 1L | |
120 | u64 spc_mssync_RW; /* 0x0000 */ | |
121 | u8 pad_0x0008_0x3000[0x3000 - 0x0008]; | |
122 | ||
123 | /* DMA Area */ | |
124 | u8 pad_0x3000_0x3004[0x4]; /* 0x3000 */ | |
125 | u32 mfc_lsa_W; /* 0x3004 */ | |
126 | u64 mfc_ea_W; /* 0x3008 */ | |
127 | union mfc_tag_size_class_cmd mfc_union_W; /* 0x3010 */ | |
128 | u8 pad_0x3018_0x3104[0xec]; /* 0x3018 */ | |
129 | u32 dma_qstatus_R; /* 0x3104 */ | |
130 | u8 pad_0x3108_0x3204[0xfc]; /* 0x3108 */ | |
131 | u32 dma_querytype_RW; /* 0x3204 */ | |
132 | u8 pad_0x3208_0x321c[0x14]; /* 0x3208 */ | |
133 | u32 dma_querymask_RW; /* 0x321c */ | |
134 | u8 pad_0x3220_0x322c[0xc]; /* 0x3220 */ | |
135 | u32 dma_tagstatus_R; /* 0x322c */ | |
136 | #define DMA_TAGSTATUS_INTR_ANY 1u | |
137 | #define DMA_TAGSTATUS_INTR_ALL 2u | |
138 | u8 pad_0x3230_0x4000[0x4000 - 0x3230]; /* 0x3230 */ | |
139 | ||
140 | /* SPU Control Area */ | |
141 | u8 pad_0x4000_0x4004[0x4]; /* 0x4000 */ | |
142 | u32 pu_mb_R; /* 0x4004 */ | |
143 | u8 pad_0x4008_0x400c[0x4]; /* 0x4008 */ | |
144 | u32 spu_mb_W; /* 0x400c */ | |
145 | u8 pad_0x4010_0x4014[0x4]; /* 0x4010 */ | |
146 | u32 mb_stat_R; /* 0x4014 */ | |
147 | u8 pad_0x4018_0x401c[0x4]; /* 0x4018 */ | |
148 | u32 spu_runcntl_RW; /* 0x401c */ | |
149 | #define SPU_RUNCNTL_STOP 0L | |
150 | #define SPU_RUNCNTL_RUNNABLE 1L | |
151 | u8 pad_0x4020_0x4024[0x4]; /* 0x4020 */ | |
152 | u32 spu_status_R; /* 0x4024 */ | |
153 | #define SPU_STOP_STATUS_SHIFT 16 | |
154 | #define SPU_STATUS_STOPPED 0x0 | |
155 | #define SPU_STATUS_RUNNING 0x1 | |
156 | #define SPU_STATUS_STOPPED_BY_STOP 0x2 | |
157 | #define SPU_STATUS_STOPPED_BY_HALT 0x4 | |
158 | #define SPU_STATUS_WAITING_FOR_CHANNEL 0x8 | |
159 | #define SPU_STATUS_SINGLE_STEP 0x10 | |
160 | #define SPU_STATUS_INVALID_INSTR 0x20 | |
161 | #define SPU_STATUS_INVALID_CH 0x40 | |
162 | #define SPU_STATUS_ISOLATED_STATE 0x80 | |
163 | #define SPU_STATUS_ISOLATED_LOAD_STAUTUS 0x200 | |
164 | #define SPU_STATUS_ISOLATED_EXIT_STAUTUS 0x400 | |
165 | u8 pad_0x4028_0x402c[0x4]; /* 0x4028 */ | |
166 | u32 spu_spe_R; /* 0x402c */ | |
167 | u8 pad_0x4030_0x4034[0x4]; /* 0x4030 */ | |
168 | u32 spu_npc_RW; /* 0x4034 */ | |
169 | u8 pad_0x4038_0x14000[0x14000 - 0x4038]; /* 0x4038 */ | |
170 | ||
171 | /* Signal Notification Area */ | |
172 | u8 pad_0x14000_0x1400c[0xc]; /* 0x14000 */ | |
173 | u32 signal_notify1; /* 0x1400c */ | |
174 | u8 pad_0x14010_0x1c00c[0x7ffc]; /* 0x14010 */ | |
175 | u32 signal_notify2; /* 0x1c00c */ | |
176 | } __attribute__ ((aligned(0x20000))); | |
177 | ||
178 | /* SPU Privilege 2 State Area */ | |
179 | struct spu_priv2 { | |
180 | /* MFC Registers */ | |
181 | u8 pad_0x0000_0x1100[0x1100 - 0x0000]; /* 0x0000 */ | |
182 | ||
183 | /* SLB Management Registers */ | |
184 | u8 pad_0x1100_0x1108[0x8]; /* 0x1100 */ | |
185 | u64 slb_index_W; /* 0x1108 */ | |
186 | #define SLB_INDEX_MASK 0x7L | |
187 | u64 slb_esid_RW; /* 0x1110 */ | |
188 | u64 slb_vsid_RW; /* 0x1118 */ | |
189 | #define SLB_VSID_SUPERVISOR_STATE (0x1ull << 11) | |
190 | #define SLB_VSID_SUPERVISOR_STATE_MASK (0x1ull << 11) | |
191 | #define SLB_VSID_PROBLEM_STATE (0x1ull << 10) | |
192 | #define SLB_VSID_PROBLEM_STATE_MASK (0x1ull << 10) | |
193 | #define SLB_VSID_EXECUTE_SEGMENT (0x1ull << 9) | |
194 | #define SLB_VSID_NO_EXECUTE_SEGMENT (0x1ull << 9) | |
195 | #define SLB_VSID_EXECUTE_SEGMENT_MASK (0x1ull << 9) | |
196 | #define SLB_VSID_4K_PAGE (0x0 << 8) | |
197 | #define SLB_VSID_LARGE_PAGE (0x1ull << 8) | |
198 | #define SLB_VSID_PAGE_SIZE_MASK (0x1ull << 8) | |
199 | #define SLB_VSID_CLASS_MASK (0x1ull << 7) | |
200 | #define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6) | |
201 | u64 slb_invalidate_entry_W; /* 0x1120 */ | |
202 | u64 slb_invalidate_all_W; /* 0x1128 */ | |
203 | u8 pad_0x1130_0x2000[0x2000 - 0x1130]; /* 0x1130 */ | |
204 | ||
205 | /* Context Save / Restore Area */ | |
206 | struct mfc_cq_sr spuq[16]; /* 0x2000 */ | |
207 | struct mfc_cq_sr puq[8]; /* 0x2200 */ | |
208 | u8 pad_0x2300_0x3000[0x3000 - 0x2300]; /* 0x2300 */ | |
209 | ||
210 | /* MFC Control */ | |
211 | u64 mfc_control_RW; /* 0x3000 */ | |
212 | #define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0) | |
213 | #define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0) | |
214 | #define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0) | |
215 | #define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8) | |
216 | #define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8) | |
217 | #define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8) | |
218 | #define MFC_CNTL_SUSPEND_DMA_STATUS_MASK (3ull << 8) | |
219 | #define MFC_CNTL_DMA_QUEUES_EMPTY (1ull << 14) | |
220 | #define MFC_CNTL_DMA_QUEUES_EMPTY_MASK (1ull << 14) | |
221 | #define MFC_CNTL_PURGE_DMA_REQUEST (1ull << 15) | |
222 | #define MFC_CNTL_PURGE_DMA_IN_PROGRESS (1ull << 24) | |
223 | #define MFC_CNTL_PURGE_DMA_COMPLETE (3ull << 24) | |
224 | #define MFC_CNTL_PURGE_DMA_STATUS_MASK (3ull << 24) | |
225 | #define MFC_CNTL_RESTART_DMA_COMMAND (1ull << 32) | |
226 | #define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING (1ull << 32) | |
227 | #define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32) | |
228 | #define MFC_CNTL_MFC_PRIVILEGE_STATE (2ull << 33) | |
229 | #define MFC_CNTL_MFC_PROBLEM_STATE (3ull << 33) | |
230 | #define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK (3ull << 33) | |
231 | #define MFC_CNTL_DECREMENTER_HALTED (1ull << 35) | |
232 | #define MFC_CNTL_DECREMENTER_RUNNING (1ull << 40) | |
233 | #define MFC_CNTL_DECREMENTER_STATUS_MASK (1ull << 40) | |
234 | u8 pad_0x3008_0x4000[0x4000 - 0x3008]; /* 0x3008 */ | |
235 | ||
236 | /* Interrupt Mailbox */ | |
237 | u64 puint_mb_R; /* 0x4000 */ | |
238 | u8 pad_0x4008_0x4040[0x4040 - 0x4008]; /* 0x4008 */ | |
239 | ||
240 | /* SPU Control */ | |
241 | u64 spu_privcntl_RW; /* 0x4040 */ | |
242 | #define SPU_PRIVCNTL_MODE_NORMAL (0x0ull << 0) | |
243 | #define SPU_PRIVCNTL_MODE_SINGLE_STEP (0x1ull << 0) | |
244 | #define SPU_PRIVCNTL_MODE_MASK (0x1ull << 0) | |
245 | #define SPU_PRIVCNTL_NO_ATTENTION_EVENT (0x0ull << 1) | |
246 | #define SPU_PRIVCNTL_ATTENTION_EVENT (0x1ull << 1) | |
247 | #define SPU_PRIVCNTL_ATTENTION_EVENT_MASK (0x1ull << 1) | |
248 | #define SPU_PRIVCNT_LOAD_REQUEST_NORMAL (0x0ull << 2) | |
249 | #define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK (0x1ull << 2) | |
250 | u8 pad_0x4048_0x4058[0x10]; /* 0x4048 */ | |
251 | u64 spu_lslr_RW; /* 0x4058 */ | |
252 | u64 spu_chnlcntptr_RW; /* 0x4060 */ | |
253 | u64 spu_chnlcnt_RW; /* 0x4068 */ | |
254 | u64 spu_chnldata_RW; /* 0x4070 */ | |
255 | u64 spu_cfg_RW; /* 0x4078 */ | |
256 | u8 pad_0x4080_0x5000[0x5000 - 0x4080]; /* 0x4080 */ | |
257 | ||
258 | /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */ | |
259 | u64 spu_pm_trace_tag_status_RW; /* 0x5000 */ | |
260 | u64 spu_tag_status_query_RW; /* 0x5008 */ | |
261 | #define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32) | |
262 | #define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull) | |
263 | u64 spu_cmd_buf1_RW; /* 0x5010 */ | |
264 | #define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32) | |
265 | #define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull) | |
266 | u64 spu_cmd_buf2_RW; /* 0x5018 */ | |
267 | #define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32) | |
268 | #define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16) | |
269 | #define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full) | |
270 | u64 spu_atomic_status_RW; /* 0x5020 */ | |
271 | } __attribute__ ((aligned(0x20000))); | |
272 | ||
273 | /* SPU Privilege 1 State Area */ | |
274 | struct spu_priv1 { | |
275 | /* Control and Configuration Area */ | |
276 | u64 mfc_sr1_RW; /* 0x000 */ | |
277 | #define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK 0x01ull | |
278 | #define MFC_STATE1_BUS_TLBIE_MASK 0x02ull | |
279 | #define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull | |
280 | #define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull | |
281 | #define MFC_STATE1_RELOCATE_MASK 0x10ull | |
282 | #define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull | |
283 | u64 mfc_lpid_RW; /* 0x008 */ | |
284 | u64 spu_idr_RW; /* 0x010 */ | |
285 | u64 mfc_vr_RO; /* 0x018 */ | |
286 | #define MFC_VERSION_BITS (0xffff << 16) | |
287 | #define MFC_REVISION_BITS (0xffff) | |
288 | #define MFC_GET_VERSION_BITS(vr) (((vr) & MFC_VERSION_BITS) >> 16) | |
289 | #define MFC_GET_REVISION_BITS(vr) ((vr) & MFC_REVISION_BITS) | |
290 | u64 spu_vr_RO; /* 0x020 */ | |
291 | #define SPU_VERSION_BITS (0xffff << 16) | |
292 | #define SPU_REVISION_BITS (0xffff) | |
293 | #define SPU_GET_VERSION_BITS(vr) (vr & SPU_VERSION_BITS) >> 16 | |
294 | #define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS) | |
295 | u8 pad_0x28_0x100[0x100 - 0x28]; /* 0x28 */ | |
296 | ||
297 | ||
298 | /* Interrupt Area */ | |
299 | u64 int_mask_class0_RW; /* 0x100 */ | |
300 | #define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L | |
301 | #define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR 0x2L | |
302 | #define CLASS0_ENABLE_SPU_ERROR_INTR 0x4L | |
303 | #define CLASS0_ENABLE_MFC_FIR_INTR 0x8L | |
304 | u64 int_mask_class1_RW; /* 0x108 */ | |
305 | #define CLASS1_ENABLE_SEGMENT_FAULT_INTR 0x1L | |
306 | #define CLASS1_ENABLE_STORAGE_FAULT_INTR 0x2L | |
307 | #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L | |
308 | #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L | |
309 | u64 int_mask_class2_RW; /* 0x110 */ | |
310 | #define CLASS2_ENABLE_MAILBOX_INTR 0x1L | |
311 | #define CLASS2_ENABLE_SPU_STOP_INTR 0x2L | |
312 | #define CLASS2_ENABLE_SPU_HALT_INTR 0x4L | |
313 | #define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L | |
314 | u8 pad_0x118_0x140[0x28]; /* 0x118 */ | |
315 | u64 int_stat_class0_RW; /* 0x140 */ | |
316 | u64 int_stat_class1_RW; /* 0x148 */ | |
317 | u64 int_stat_class2_RW; /* 0x150 */ | |
318 | u8 pad_0x158_0x180[0x28]; /* 0x158 */ | |
319 | u64 int_route_RW; /* 0x180 */ | |
320 | ||
321 | /* Interrupt Routing */ | |
322 | u8 pad_0x188_0x200[0x200 - 0x188]; /* 0x188 */ | |
323 | ||
324 | /* Atomic Unit Control Area */ | |
325 | u64 mfc_atomic_flush_RW; /* 0x200 */ | |
326 | #define mfc_atomic_flush_enable 0x1L | |
327 | u8 pad_0x208_0x280[0x78]; /* 0x208 */ | |
328 | u64 resource_allocation_groupID_RW; /* 0x280 */ | |
329 | u64 resource_allocation_enable_RW; /* 0x288 */ | |
330 | u8 pad_0x290_0x3c8[0x3c8 - 0x290]; /* 0x290 */ | |
331 | ||
332 | /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */ | |
333 | ||
334 | u64 smf_sbi_signal_sel; /* 0x3c8 */ | |
335 | #define smf_sbi_mask_lsb 56 | |
336 | #define smf_sbi_shift (63 - smf_sbi_mask_lsb) | |
337 | #define smf_sbi_mask (0x301LL << smf_sbi_shift) | |
338 | #define smf_sbi_bus0_bits (0x001LL << smf_sbi_shift) | |
339 | #define smf_sbi_bus2_bits (0x100LL << smf_sbi_shift) | |
340 | #define smf_sbi2_bus0_bits (0x201LL << smf_sbi_shift) | |
341 | #define smf_sbi2_bus2_bits (0x300LL << smf_sbi_shift) | |
342 | u64 smf_ato_signal_sel; /* 0x3d0 */ | |
343 | #define smf_ato_mask_lsb 35 | |
344 | #define smf_ato_shift (63 - smf_ato_mask_lsb) | |
345 | #define smf_ato_mask (0x3LL << smf_ato_shift) | |
346 | #define smf_ato_bus0_bits (0x2LL << smf_ato_shift) | |
347 | #define smf_ato_bus2_bits (0x1LL << smf_ato_shift) | |
348 | u8 pad_0x3d8_0x400[0x400 - 0x3d8]; /* 0x3d8 */ | |
349 | ||
350 | /* TLB Management Registers */ | |
351 | u64 mfc_sdr_RW; /* 0x400 */ | |
352 | u8 pad_0x408_0x500[0xf8]; /* 0x408 */ | |
353 | u64 tlb_index_hint_RO; /* 0x500 */ | |
354 | u64 tlb_index_W; /* 0x508 */ | |
355 | u64 tlb_vpn_RW; /* 0x510 */ | |
356 | u64 tlb_rpn_RW; /* 0x518 */ | |
357 | u8 pad_0x520_0x540[0x20]; /* 0x520 */ | |
358 | u64 tlb_invalidate_entry_W; /* 0x540 */ | |
359 | u64 tlb_invalidate_all_W; /* 0x548 */ | |
360 | u8 pad_0x550_0x580[0x580 - 0x550]; /* 0x550 */ | |
361 | ||
362 | /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */ | |
363 | u64 smm_hid; /* 0x580 */ | |
364 | #define PAGE_SIZE_MASK 0xf000000000000000ull | |
365 | #define PAGE_SIZE_16MB_64KB 0x2000000000000000ull | |
366 | u8 pad_0x588_0x600[0x600 - 0x588]; /* 0x588 */ | |
367 | ||
368 | /* MFC Status/Control Area */ | |
369 | u64 mfc_accr_RW; /* 0x600 */ | |
370 | #define MFC_ACCR_EA_ACCESS_GET (1 << 0) | |
371 | #define MFC_ACCR_EA_ACCESS_PUT (1 << 1) | |
372 | #define MFC_ACCR_LS_ACCESS_GET (1 << 3) | |
373 | #define MFC_ACCR_LS_ACCESS_PUT (1 << 4) | |
374 | u8 pad_0x608_0x610[0x8]; /* 0x608 */ | |
375 | u64 mfc_dsisr_RW; /* 0x610 */ | |
376 | #define MFC_DSISR_PTE_NOT_FOUND (1 << 30) | |
377 | #define MFC_DSISR_ACCESS_DENIED (1 << 27) | |
378 | #define MFC_DSISR_ATOMIC (1 << 26) | |
379 | #define MFC_DSISR_ACCESS_PUT (1 << 25) | |
380 | #define MFC_DSISR_ADDR_MATCH (1 << 22) | |
381 | #define MFC_DSISR_LS (1 << 17) | |
382 | #define MFC_DSISR_L (1 << 16) | |
383 | #define MFC_DSISR_ADDRESS_OVERFLOW (1 << 0) | |
384 | u8 pad_0x618_0x620[0x8]; /* 0x618 */ | |
385 | u64 mfc_dar_RW; /* 0x620 */ | |
386 | u8 pad_0x628_0x700[0x700 - 0x628]; /* 0x628 */ | |
387 | ||
388 | /* Replacement Management Table (RMT) Area */ | |
389 | u64 rmt_index_RW; /* 0x700 */ | |
390 | u8 pad_0x708_0x710[0x8]; /* 0x708 */ | |
391 | u64 rmt_data1_RW; /* 0x710 */ | |
392 | u8 pad_0x718_0x800[0x800 - 0x718]; /* 0x718 */ | |
393 | ||
394 | /* Control/Configuration Registers */ | |
395 | u64 mfc_dsir_R; /* 0x800 */ | |
396 | #define MFC_DSIR_Q (1 << 31) | |
397 | #define MFC_DSIR_SPU_QUEUE MFC_DSIR_Q | |
398 | u64 mfc_lsacr_RW; /* 0x808 */ | |
399 | #define MFC_LSACR_COMPARE_MASK ((~0ull) << 32) | |
400 | #define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32) | |
401 | u64 mfc_lscrr_R; /* 0x810 */ | |
402 | #define MFC_LSCRR_Q (1 << 31) | |
403 | #define MFC_LSCRR_SPU_QUEUE MFC_LSCRR_Q | |
404 | #define MFC_LSCRR_QI_SHIFT 32 | |
405 | #define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT) | |
406 | u8 pad_0x818_0x820[0x8]; /* 0x818 */ | |
407 | u64 mfc_tclass_id_RW; /* 0x820 */ | |
408 | #define MFC_TCLASS_ID_ENABLE (1L << 0L) | |
409 | #define MFC_TCLASS_SLOT2_ENABLE (1L << 5L) | |
410 | #define MFC_TCLASS_SLOT1_ENABLE (1L << 6L) | |
411 | #define MFC_TCLASS_SLOT0_ENABLE (1L << 7L) | |
412 | #define MFC_TCLASS_QUOTA_2_SHIFT 8L | |
413 | #define MFC_TCLASS_QUOTA_1_SHIFT 16L | |
414 | #define MFC_TCLASS_QUOTA_0_SHIFT 24L | |
415 | #define MFC_TCLASS_QUOTA_2_MASK (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT) | |
416 | #define MFC_TCLASS_QUOTA_1_MASK (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT) | |
417 | #define MFC_TCLASS_QUOTA_0_MASK (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT) | |
418 | u8 pad_0x828_0x900[0x900 - 0x828]; /* 0x828 */ | |
419 | ||
420 | /* Real Mode Support Registers */ | |
421 | u64 mfc_rm_boundary; /* 0x900 */ | |
422 | u8 pad_0x908_0x938[0x30]; /* 0x908 */ | |
423 | u64 smf_dma_signal_sel; /* 0x938 */ | |
424 | #define mfc_dma1_mask_lsb 41 | |
425 | #define mfc_dma1_shift (63 - mfc_dma1_mask_lsb) | |
426 | #define mfc_dma1_mask (0x3LL << mfc_dma1_shift) | |
427 | #define mfc_dma1_bits (0x1LL << mfc_dma1_shift) | |
428 | #define mfc_dma2_mask_lsb 43 | |
429 | #define mfc_dma2_shift (63 - mfc_dma2_mask_lsb) | |
430 | #define mfc_dma2_mask (0x3LL << mfc_dma2_shift) | |
431 | #define mfc_dma2_bits (0x1LL << mfc_dma2_shift) | |
432 | u8 pad_0x940_0xa38[0xf8]; /* 0x940 */ | |
433 | u64 smm_signal_sel; /* 0xa38 */ | |
434 | #define smm_sig_mask_lsb 12 | |
435 | #define smm_sig_shift (63 - smm_sig_mask_lsb) | |
436 | #define smm_sig_mask (0x3LL << smm_sig_shift) | |
437 | #define smm_sig_bus0_bits (0x2LL << smm_sig_shift) | |
438 | #define smm_sig_bus2_bits (0x1LL << smm_sig_shift) | |
439 | u8 pad_0xa40_0xc00[0xc00 - 0xa40]; /* 0xa40 */ | |
440 | ||
441 | /* DMA Command Error Area */ | |
442 | u64 mfc_cer_R; /* 0xc00 */ | |
443 | #define MFC_CER_Q (1 << 31) | |
444 | #define MFC_CER_SPU_QUEUE MFC_CER_Q | |
445 | u8 pad_0xc08_0x1000[0x1000 - 0xc08]; /* 0xc08 */ | |
446 | ||
447 | /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */ | |
448 | /* DMA Command Error Area */ | |
449 | u64 spu_ecc_cntl_RW; /* 0x1000 */ | |
450 | #define SPU_ECC_CNTL_E (1ull << 0ull) | |
451 | #define SPU_ECC_CNTL_ENABLE SPU_ECC_CNTL_E | |
452 | #define SPU_ECC_CNTL_DISABLE (~SPU_ECC_CNTL_E & 1L) | |
453 | #define SPU_ECC_CNTL_S (1ull << 1ull) | |
454 | #define SPU_ECC_STOP_AFTER_ERROR SPU_ECC_CNTL_S | |
455 | #define SPU_ECC_CONTINUE_AFTER_ERROR (~SPU_ECC_CNTL_S & 2L) | |
456 | #define SPU_ECC_CNTL_B (1ull << 2ull) | |
457 | #define SPU_ECC_BACKGROUND_ENABLE SPU_ECC_CNTL_B | |
458 | #define SPU_ECC_BACKGROUND_DISABLE (~SPU_ECC_CNTL_B & 4L) | |
459 | #define SPU_ECC_CNTL_I_SHIFT 3ull | |
460 | #define SPU_ECC_CNTL_I_MASK (3ull << SPU_ECC_CNTL_I_SHIFT) | |
461 | #define SPU_ECC_WRITE_ALWAYS (~SPU_ECC_CNTL_I & 12L) | |
462 | #define SPU_ECC_WRITE_CORRECTABLE (1ull << SPU_ECC_CNTL_I_SHIFT) | |
463 | #define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT) | |
464 | #define SPU_ECC_CNTL_D (1ull << 5ull) | |
465 | #define SPU_ECC_DETECTION_ENABLE SPU_ECC_CNTL_D | |
466 | #define SPU_ECC_DETECTION_DISABLE (~SPU_ECC_CNTL_D & 32L) | |
467 | u64 spu_ecc_stat_RW; /* 0x1008 */ | |
468 | #define SPU_ECC_CORRECTED_ERROR (1ull << 0ul) | |
469 | #define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul) | |
470 | #define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul) | |
471 | #define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul) | |
472 | #define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul) | |
473 | #define SPU_ECC_DATA_ERROR (1ull << 5ul) | |
474 | #define SPU_ECC_DMA_ERROR (1ull << 6ul) | |
475 | #define SPU_ECC_STATUS_CNT_MASK (256ull << 8) | |
476 | u64 spu_ecc_addr_RW; /* 0x1010 */ | |
477 | u64 spu_err_mask_RW; /* 0x1018 */ | |
478 | #define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul) | |
479 | #define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul) | |
480 | u8 pad_0x1020_0x1028[0x1028 - 0x1020]; /* 0x1020 */ | |
481 | ||
482 | /* SPU Debug-Trace Bus (DTB) Selection Registers */ | |
483 | u64 spu_trig0_sel; /* 0x1028 */ | |
484 | u64 spu_trig1_sel; /* 0x1030 */ | |
485 | u64 spu_trig2_sel; /* 0x1038 */ | |
486 | u64 spu_trig3_sel; /* 0x1040 */ | |
487 | u64 spu_trace_sel; /* 0x1048 */ | |
488 | #define spu_trace_sel_mask 0x1f1fLL | |
489 | #define spu_trace_sel_bus0_bits 0x1000LL | |
490 | #define spu_trace_sel_bus2_bits 0x0010LL | |
491 | u64 spu_event0_sel; /* 0x1050 */ | |
492 | u64 spu_event1_sel; /* 0x1058 */ | |
493 | u64 spu_event2_sel; /* 0x1060 */ | |
494 | u64 spu_event3_sel; /* 0x1068 */ | |
495 | u64 spu_trace_cntl; /* 0x1070 */ | |
496 | } __attribute__ ((aligned(0x2000))); | |
497 | ||
498 | #endif |