[deliverable/linux.git] / include / asm-sparc64 / system.h

/* $Id: system.h,v 1.69 2002/02/09 19:49:31 davem Exp $ */
#ifndef __SPARC64_SYSTEM_H
#define __SPARC64_SYSTEM_H

#include <asm/ptrace.h>
#include <asm/processor.h>
#include <asm/visasm.h>

#ifndef __ASSEMBLY__

#include <linux/irqflags.h>

/*
 * Sparc (general) CPU types
 */
enum sparc_cpu {
  sun4        = 0x00,
  sun4c       = 0x01,
  sun4m       = 0x02,
  sun4d       = 0x03,
  sun4e       = 0x04,
  sun4u       = 0x05, /* V8 ploos ploos */
  sun_unknown = 0x06,
  ap1000      = 0x07, /* almost a sun4m */
};
                  
#define sparc_cpu_model sun4u

/* This cannot ever be a sun4c nor sun4 :) That's just history. */
#define ARCH_SUN4C_SUN4 0
#define ARCH_SUN4 0

/* These are here in an effort to more fully work around Spitfire Errata
 * #51.  Essentially, if a memory barrier occurs soon after a mispredicted
 * branch, the chip can stop executing instructions until a trap occurs.
 * Therefore, if interrupts are disabled, the chip can hang forever.
 *
 * It used to be believed that the memory barrier had to be right in the
 * delay slot, but a case has been traced recently wherein the memory barrier
 * was one instruction after the branch delay slot and the chip still hung.
 * The offending sequence was the following in sym_wakeup_done() of the
 * sym53c8xx_2 driver:
 *
 *	call	sym_ccb_from_dsa, 0
 *	 movge	%icc, 0, %l0
 *	brz,pn	%o0, .LL1303
 *	 mov	%o0, %l2
 *	membar	#LoadLoad
 *
 * The branch has to be mispredicted for the bug to occur.  Therefore, we put
 * the memory barrier explicitly into a "branch always, predicted taken"
 * delay slot to avoid the problem case.
 */
#define membar_safe(type) \
do {	__asm__ __volatile__("ba,pt	%%xcc, 1f\n\t" \
			     " membar	" type "\n" \
			     "1:\n" \
			     : : : "memory"); \
} while (0)

#define mb()	\
	membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
#define rmb()	\
	membar_safe("#LoadLoad")
#define wmb()	\
	membar_safe("#StoreStore")
#define membar_storeload() \
	membar_safe("#StoreLoad")
#define membar_storeload_storestore() \
	membar_safe("#StoreLoad | #StoreStore")
#define membar_storeload_loadload() \
	membar_safe("#StoreLoad | #LoadLoad")
#define membar_storestore_loadstore() \
	membar_safe("#StoreStore | #LoadStore")

#endif

#define nop() 		__asm__ __volatile__ ("nop")

#define read_barrier_depends()		do { } while(0)
#define set_mb(__var, __value) \
	do { __var = __value; membar_storeload_storestore(); } while(0)

#ifdef CONFIG_SMP
#define smp_mb()	mb()
#define smp_rmb()	rmb()
#define smp_wmb()	wmb()
#define smp_read_barrier_depends()	read_barrier_depends()
#else
#define smp_mb()	__asm__ __volatile__("":::"memory")
#define smp_rmb()	__asm__ __volatile__("":::"memory")
#define smp_wmb()	__asm__ __volatile__("":::"memory")
#define smp_read_barrier_depends()	do { } while(0)
#endif

#define flushi(addr)	__asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")

#define flushw_all()	__asm__ __volatile__("flushw")

/* Performance counter register access. */
#define read_pcr(__p)  __asm__ __volatile__("rd	%%pcr, %0" : "=r" (__p))
#define write_pcr(__p) __asm__ __volatile__("wr	%0, 0x0, %%pcr" : : "r" (__p))
#define read_pic(__p)  __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))

/* Blackbird errata workaround.  See commentary in
 * arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
 * for more information.
 */
#define reset_pic()    						\
	__asm__ __volatile__("ba,pt	%xcc, 99f\n\t"		\
			     ".align	64\n"			\
			  "99:wr	%g0, 0x0, %pic\n\t"	\
			     "rd	%pic, %g0")

#ifndef __ASSEMBLY__

extern void sun_do_break(void);
extern int serial_console;
extern int stop_a_enabled;

static __inline__ int con_is_present(void)
{
	return serial_console ? 0 : 1;
}

extern void synchronize_user_stack(void);

extern void __flushw_user(void);
#define flushw_user() __flushw_user()

#define flush_user_windows flushw_user
#define flush_register_windows flushw_all

/* Don't hold the runqueue lock over context switch */
#define __ARCH_WANT_UNLOCKED_CTXSW
#define prepare_arch_switch(next)		\
do {						\
	flushw_all();				\
} while (0)

	/* See what happens when you design the chip correctly?
	 *
	 * We tell gcc we clobber all non-fixed-usage registers except
	 * for l0/l1.  It will use one for 'next' and the other to hold
	 * the output value of 'last'.  'next' is not referenced again
	 * past the invocation of switch_to in the scheduler, so we need
	 * not preserve it's value.  Hairy, but it lets us remove 2 loads
	 * and 2 stores in this critical code path.  -DaveM
	 */
#define EXTRA_CLOBBER ,"%l1"
#define switch_to(prev, next, last)					\
do {	if (test_thread_flag(TIF_PERFCTR)) {				\
		unsigned long __tmp;					\
		read_pcr(__tmp);					\
		current_thread_info()->pcr_reg = __tmp;			\
		read_pic(__tmp);					\
		current_thread_info()->kernel_cntd0 += (unsigned int)(__tmp);\
		current_thread_info()->kernel_cntd1 += ((__tmp) >> 32);	\
	}								\
	flush_tlb_pending();						\
	save_and_clear_fpu();						\
	/* If you are tempted to conditionalize the following */	\
	/* so that ASI is only written if it changes, think again. */	\
	__asm__ __volatile__("wr %%g0, %0, %%asi"			\
	: : "r" (__thread_flag_byte_ptr(task_thread_info(next))[TI_FLAG_BYTE_CURRENT_DS]));\
	trap_block[current_thread_info()->cpu].thread =			\
		task_thread_info(next);					\
	__asm__ __volatile__(						\
	"mov	%%g4, %%g7\n\t"						\
	"stx	%%i6, [%%sp + 2047 + 0x70]\n\t"				\
	"stx	%%i7, [%%sp + 2047 + 0x78]\n\t"				\
	"rdpr	%%wstate, %%o5\n\t"					\
	"stx	%%o6, [%%g6 + %3]\n\t"					\
	"stb	%%o5, [%%g6 + %2]\n\t"					\
	"rdpr	%%cwp, %%o5\n\t"					\
	"stb	%%o5, [%%g6 + %5]\n\t"					\
	"mov	%1, %%g6\n\t"						\
	"ldub	[%1 + %5], %%g1\n\t"					\
	"wrpr	%%g1, %%cwp\n\t"					\
	"ldx	[%%g6 + %3], %%o6\n\t"					\
	"ldub	[%%g6 + %2], %%o5\n\t"					\
	"ldub	[%%g6 + %4], %%o7\n\t"					\
	"wrpr	%%o5, 0x0, %%wstate\n\t"				\
	"ldx	[%%sp + 2047 + 0x70], %%i6\n\t"				\
	"ldx	[%%sp + 2047 + 0x78], %%i7\n\t"				\
	"ldx	[%%g6 + %6], %%g4\n\t"					\
	"brz,pt %%o7, 1f\n\t"						\
	" mov	%%g7, %0\n\t"						\
	"b,a ret_from_syscall\n\t"					\
	"1:\n\t"							\
	: "=&r" (last)							\
	: "0" (task_thread_info(next)),					\
	  "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD),            \
	  "i" (TI_CWP), "i" (TI_TASK)					\
	: "cc",								\
	        "g1", "g2", "g3",                   "g7",		\
	              "l2", "l3", "l4", "l5", "l6", "l7",		\
	  "i0", "i1", "i2", "i3", "i4", "i5",				\
	  "o0", "o1", "o2", "o3", "o4", "o5",       "o7" EXTRA_CLOBBER);\
	/* If you fuck with this, update ret_from_syscall code too. */	\
	if (test_thread_flag(TIF_PERFCTR)) {				\
		write_pcr(current_thread_info()->pcr_reg);		\
		reset_pic();						\
	}								\
} while(0)

static inline unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val)
{
	unsigned long tmp1, tmp2;

	__asm__ __volatile__(
"	membar		#StoreLoad | #LoadLoad\n"
"	mov		%0, %1\n"
"1:	lduw		[%4], %2\n"
"	cas		[%4], %2, %0\n"
"	cmp		%2, %0\n"
"	bne,a,pn	%%icc, 1b\n"
"	 mov		%1, %0\n"
"	membar		#StoreLoad | #StoreStore\n"
	: "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
	: "0" (val), "r" (m)
	: "cc", "memory");
	return val;
}

static inline unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val)
{
	unsigned long tmp1, tmp2;

	__asm__ __volatile__(
"	membar		#StoreLoad | #LoadLoad\n"
"	mov		%0, %1\n"
"1:	ldx		[%4], %2\n"
"	casx		[%4], %2, %0\n"
"	cmp		%2, %0\n"
"	bne,a,pn	%%xcc, 1b\n"
"	 mov		%1, %0\n"
"	membar		#StoreLoad | #StoreStore\n"
	: "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
	: "0" (val), "r" (m)
	: "cc", "memory");
	return val;
}

#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))

extern void __xchg_called_with_bad_pointer(void);

static __inline__ unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
				       int size)
{
	switch (size) {
	case 4:
		return xchg32(ptr, x);
	case 8:
		return xchg64(ptr, x);
	};
	__xchg_called_with_bad_pointer();
	return x;
}

extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));

/* 
 * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 * store NEW in MEM.  Return the initial value in MEM.  Success is
 * indicated by comparing RETURN with OLD.
 */

#define __HAVE_ARCH_CMPXCHG 1

static __inline__ unsigned long
__cmpxchg_u32(volatile int *m, int old, int new)
{
	__asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
			     "cas [%2], %3, %0\n\t"
			     "membar #StoreLoad | #StoreStore"
			     : "=&r" (new)
			     : "0" (new), "r" (m), "r" (old)
			     : "memory");

	return new;
}

static __inline__ unsigned long
__cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
{
	__asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
			     "casx [%2], %3, %0\n\t"
			     "membar #StoreLoad | #StoreStore"
			     : "=&r" (new)
			     : "0" (new), "r" (m), "r" (old)
			     : "memory");

	return new;
}

/* This function doesn't exist, so you'll get a linker error
   if something tries to do an invalid cmpxchg().  */
extern void __cmpxchg_called_with_bad_pointer(void);

static __inline__ unsigned long
__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
{
	switch (size) {
		case 4:
			return __cmpxchg_u32(ptr, old, new);
		case 8:
			return __cmpxchg_u64(ptr, old, new);
	}
	__cmpxchg_called_with_bad_pointer();
	return old;
}

#define cmpxchg(ptr,o,n)						 \
  ({									 \
     __typeof__(*(ptr)) _o_ = (o);					 \
     __typeof__(*(ptr)) _n_ = (n);					 \
     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,		 \
				    (unsigned long)_n_, sizeof(*(ptr))); \
  })

#endif /* !(__ASSEMBLY__) */

#define arch_align_stack(x) (x)

#endif /* !(__SPARC64_SYSTEM_H) */
Commit	Line	Data
1da177e4 LT	1	/* $Id: system.h,v 1.69 2002/02/09 19:49:31 davem Exp $ */
	2	#ifndef __SPARC64_SYSTEM_H
	3	#define __SPARC64_SYSTEM_H
	4
1da177e4 LT	5	#include <asm/ptrace.h>
	6	#include <asm/processor.h>
	7	#include <asm/visasm.h>
	8
	9	#ifndef __ASSEMBLY__
10e26723 DM	10
	11	#include <linux/irqflags.h>
	12
1da177e4 LT	13	/*
	14	* Sparc (general) CPU types
	15	*/
	16	enum sparc_cpu {
	17	sun4 = 0x00,
	18	sun4c = 0x01,
	19	sun4m = 0x02,
	20	sun4d = 0x03,
	21	sun4e = 0x04,
	22	sun4u = 0x05, /* V8 ploos ploos */
	23	sun_unknown = 0x06,
	24	ap1000 = 0x07, /* almost a sun4m */
	25	};
	26
	27	#define sparc_cpu_model sun4u
	28
	29	/* This cannot ever be a sun4c nor sun4 :) That's just history. */
	30	#define ARCH_SUN4C_SUN4 0
	31	#define ARCH_SUN4 0
	32
4d803fcd DM	33	/* These are here in an effort to more fully work around Spitfire Errata
	34	* #51. Essentially, if a memory barrier occurs soon after a mispredicted
	35	* branch, the chip can stop executing instructions until a trap occurs.
	36	* Therefore, if interrupts are disabled, the chip can hang forever.
	37	*
	38	* It used to be believed that the memory barrier had to be right in the
	39	* delay slot, but a case has been traced recently wherein the memory barrier
	40	* was one instruction after the branch delay slot and the chip still hung.
	41	* The offending sequence was the following in sym_wakeup_done() of the
	42	* sym53c8xx_2 driver:
	43	*
	44	* call sym_ccb_from_dsa, 0
	45	* movge %icc, 0, %l0
	46	* brz,pn %o0, .LL1303
	47	* mov %o0, %l2
	48	* membar #LoadLoad
	49	*
	50	* The branch has to be mispredicted for the bug to occur. Therefore, we put
	51	* the memory barrier explicitly into a "branch always, predicted taken"
	52	* delay slot to avoid the problem case.
	53	*/
	54	#define membar_safe(type) \
	55	do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \
	56	" membar " type "\n" \
	57	"1:\n" \
	58	: : : "memory"); \
	59	} while (0)
	60
	61	#define mb() \
	62	membar_safe("#LoadLoad \| #LoadStore \| #StoreStore \| #StoreLoad")
	63	#define rmb() \
	64	membar_safe("#LoadLoad")
	65	#define wmb() \
	66	membar_safe("#StoreStore")
	67	#define membar_storeload() \
	68	membar_safe("#StoreLoad")
	69	#define membar_storeload_storestore() \
	70	membar_safe("#StoreLoad \| #StoreStore")
	71	#define membar_storeload_loadload() \
	72	membar_safe("#StoreLoad \| #LoadLoad")
	73	#define membar_storestore_loadstore() \
	74	membar_safe("#StoreStore \| #LoadStore")
4f07118f	75
1da177e4 LT	76	#endif
1da177e4 LT	77
1da177e4 LT	78	#define nop() __asm__ __volatile__ ("nop")
1da177e4 LT	79
1da177e4 LT	80	#define read_barrier_depends() do { } while(0)
1da177e4 LT	81	#define set_mb(__var, __value) \
4f07118f	82	do { __var = __value; membar_storeload_storestore(); } while(0)
1da177e4 LT	83
	84	#ifdef CONFIG_SMP
	85	#define smp_mb() mb()
	86	#define smp_rmb() rmb()
	87	#define smp_wmb() wmb()
	88	#define smp_read_barrier_depends() read_barrier_depends()
	89	#else
	90	#define smp_mb() __asm__ __volatile__("":::"memory")
	91	#define smp_rmb() __asm__ __volatile__("":::"memory")
	92	#define smp_wmb() __asm__ __volatile__("":::"memory")
	93	#define smp_read_barrier_depends() do { } while(0)
	94	#endif
	95
	96	#define flushi(addr) __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
	97
	98	#define flushw_all() __asm__ __volatile__("flushw")
	99
	100	/* Performance counter register access. */
	101	#define read_pcr(__p) __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p))
	102	#define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p))
	103	#define read_pic(__p) __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))
	104
	105	/* Blackbird errata workaround. See commentary in
	106	* arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
	107	* for more information.
	108	*/
	109	#define reset_pic() \
	110	__asm__ __volatile__("ba,pt %xcc, 99f\n\t" \
	111	".align 64\n" \
	112	"99:wr %g0, 0x0, %pic\n\t" \
	113	"rd %pic, %g0")
	114
	115	#ifndef __ASSEMBLY__
	116
	117	extern void sun_do_break(void);
	118	extern int serial_console;
	119	extern int stop_a_enabled;
	120
	121	static __inline__ int con_is_present(void)
	122	{
	123	return serial_console ? 0 : 1;
	124	}
	125
	126	extern void synchronize_user_stack(void);
	127
	128	extern void __flushw_user(void);
	129	#define flushw_user() __flushw_user()
	130
	131	#define flush_user_windows flushw_user
	132	#define flush_register_windows flushw_all
	133
4866cde0 NP	134	/* Don't hold the runqueue lock over context switch */
	135	#define __ARCH_WANT_UNLOCKED_CTXSW
	136	#define prepare_arch_switch(next) \
	137	do { \
1da177e4 LT	138	flushw_all(); \
	139	} while (0)
	140
1da177e4 LT	141	/* See what happens when you design the chip correctly?
	142	*
	143	* We tell gcc we clobber all non-fixed-usage registers except
	144	* for l0/l1. It will use one for 'next' and the other to hold
	145	* the output value of 'last'. 'next' is not referenced again
	146	* past the invocation of switch_to in the scheduler, so we need
	147	* not preserve it's value. Hairy, but it lets us remove 2 loads
	148	* and 2 stores in this critical code path. -DaveM
	149	*/
1da177e4	150	#define EXTRA_CLOBBER ,"%l1"
1da177e4 LT	151	#define switch_to(prev, next, last) \
	152	do { if (test_thread_flag(TIF_PERFCTR)) { \
	153	unsigned long __tmp; \
	154	read_pcr(__tmp); \
	155	current_thread_info()->pcr_reg = __tmp; \
	156	read_pic(__tmp); \
	157	current_thread_info()->kernel_cntd0 += (unsigned int)(__tmp);\
	158	current_thread_info()->kernel_cntd1 += ((__tmp) >> 32); \
	159	} \
	160	flush_tlb_pending(); \
	161	save_and_clear_fpu(); \
	162	/* If you are tempted to conditionalize the following */ \
	163	/* so that ASI is only written if it changes, think again. */ \
	164	__asm__ __volatile__("wr %%g0, %0, %%asi" \
f3169641	165	: : "r" (__thread_flag_byte_ptr(task_thread_info(next))[TI_FLAG_BYTE_CURRENT_DS]));\
56fb4df6 DM	166	trap_block[current_thread_info()->cpu].thread = \
56fb4df6 DM	167	task_thread_info(next); \
1da177e4 LT	168	__asm__ __volatile__( \
1da177e4 LT	169	"mov %%g4, %%g7\n\t" \
1da177e4 LT	170	"stx %%i6, [%%sp + 2047 + 0x70]\n\t" \
	171	"stx %%i7, [%%sp + 2047 + 0x78]\n\t" \
	172	"rdpr %%wstate, %%o5\n\t" \
	173	"stx %%o6, [%%g6 + %3]\n\t" \
	174	"stb %%o5, [%%g6 + %2]\n\t" \
	175	"rdpr %%cwp, %%o5\n\t" \
	176	"stb %%o5, [%%g6 + %5]\n\t" \
	177	"mov %1, %%g6\n\t" \
	178	"ldub [%1 + %5], %%g1\n\t" \
	179	"wrpr %%g1, %%cwp\n\t" \
	180	"ldx [%%g6 + %3], %%o6\n\t" \
	181	"ldub [%%g6 + %2], %%o5\n\t" \
db7d9a4e	182	"ldub [%%g6 + %4], %%o7\n\t" \
1da177e4 LT	183	"wrpr %%o5, 0x0, %%wstate\n\t" \
	184	"ldx [%%sp + 2047 + 0x70], %%i6\n\t" \
	185	"ldx [%%sp + 2047 + 0x78], %%i7\n\t" \
db7d9a4e	186	"ldx [%%g6 + %6], %%g4\n\t" \
db7d9a4e	187	"brz,pt %%o7, 1f\n\t" \
1da177e4 LT	188	" mov %%g7, %0\n\t" \
	189	"b,a ret_from_syscall\n\t" \
	190	"1:\n\t" \
	191	: "=&r" (last) \
f3169641	192	: "0" (task_thread_info(next)), \
db7d9a4e DM	193	"i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD), \
db7d9a4e DM	194	"i" (TI_CWP), "i" (TI_TASK) \
1da177e4 LT	195	: "cc", \
	196	"g1", "g2", "g3", "g7", \
	197	"l2", "l3", "l4", "l5", "l6", "l7", \
	198	"i0", "i1", "i2", "i3", "i4", "i5", \
	199	"o0", "o1", "o2", "o3", "o4", "o5", "o7" EXTRA_CLOBBER);\
	200	/* If you fuck with this, update ret_from_syscall code too. */ \
	201	if (test_thread_flag(TIF_PERFCTR)) { \
	202	write_pcr(current_thread_info()->pcr_reg); \
	203	reset_pic(); \
	204	} \
	205	} while(0)
	206
	207	static inline unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val)
	208	{
	209	unsigned long tmp1, tmp2;
	210
	211	__asm__ __volatile__(
	212	" membar #StoreLoad \| #LoadLoad\n"
	213	" mov %0, %1\n"
	214	"1: lduw [%4], %2\n"
	215	" cas [%4], %2, %0\n"
	216	" cmp %2, %0\n"
	217	" bne,a,pn %%icc, 1b\n"
	218	" mov %1, %0\n"
	219	" membar #StoreLoad \| #StoreStore\n"
	220	: "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
	221	: "0" (val), "r" (m)
	222	: "cc", "memory");
	223	return val;
	224	}
	225
	226	static inline unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val)
	227	{
	228	unsigned long tmp1, tmp2;
	229
	230	__asm__ __volatile__(
	231	" membar #StoreLoad \| #LoadLoad\n"
	232	" mov %0, %1\n"
	233	"1: ldx [%4], %2\n"
	234	" casx [%4], %2, %0\n"
	235	" cmp %2, %0\n"
	236	" bne,a,pn %%xcc, 1b\n"
	237	" mov %1, %0\n"
	238	" membar #StoreLoad \| #StoreStore\n"
	239	: "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
	240	: "0" (val), "r" (m)
	241	: "cc", "memory");
	242	return val;
	243	}
	244
	245	#define xchg(ptr,x) ((__typeof__((ptr)))__xchg((unsigned long)(x),(ptr),sizeof((ptr))))
1da177e4 LT	246
	247	extern void __xchg_called_with_bad_pointer(void);
	248
	249	static __inline__ unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
	250	int size)
	251	{
	252	switch (size) {
	253	case 4:
	254	return xchg32(ptr, x);
	255	case 8:
	256	return xchg64(ptr, x);
	257	};
	258	__xchg_called_with_bad_pointer();
	259	return x;
	260	}
	261
	262	extern void die_if_kernel(char str, struct pt_regs regs) __attribute__ ((noreturn));
	263
	264	/*
	265	* Atomic compare and exchange. Compare OLD with MEM, if identical,
	266	* store NEW in MEM. Return the initial value in MEM. Success is
	267	* indicated by comparing RETURN with OLD.
	268	*/
	269
	270	#define __HAVE_ARCH_CMPXCHG 1
	271
	272	static __inline__ unsigned long
	273	__cmpxchg_u32(volatile int *m, int old, int new)
	274	{
	275	__asm__ __volatile__("membar #StoreLoad \| #LoadLoad\n"
	276	"cas [%2], %3, %0\n\t"
	277	"membar #StoreLoad \| #StoreStore"
	278	: "=&r" (new)
	279	: "0" (new), "r" (m), "r" (old)
	280	: "memory");
	281
	282	return new;
	283	}
	284
	285	static __inline__ unsigned long
	286	__cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
	287	{
	288	__asm__ __volatile__("membar #StoreLoad \| #LoadLoad\n"
	289	"casx [%2], %3, %0\n\t"
	290	"membar #StoreLoad \| #StoreStore"
	291	: "=&r" (new)
	292	: "0" (new), "r" (m), "r" (old)
	293	: "memory");
	294
	295	return new;
	296	}
	297
	298	/* This function doesn't exist, so you'll get a linker error
	299	if something tries to do an invalid cmpxchg(). */
	300	extern void __cmpxchg_called_with_bad_pointer(void);
	301
	302	static __inline__ unsigned long
	303	__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
	304	{
	305	switch (size) {
	306	case 4:
	307	return __cmpxchg_u32(ptr, old, new);
	308	case 8:
	309	return __cmpxchg_u64(ptr, old, new);
310	}
311	__cmpxchg_called_with_bad_pointer();
312	return old;
313	}
314
315	#define cmpxchg(ptr,o,n) \
316	({ \
317	__typeof__(*(ptr)) _o_ = (o); \
318	__typeof__(*(ptr)) _n_ = (n); \
319	(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
320	(unsigned long)_n_, sizeof(*(ptr))); \
321	})
322
323	#endif /* !(__ASSEMBLY__) */
324
325	#define arch_align_stack(x) (x)
326
327	#endif /* !(__SPARC64_SYSTEM_H) */