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1 | #ifndef __ASM_IO_APIC_H |
2 | #define __ASM_IO_APIC_H | |
3 | ||
4 | #include <linux/config.h> | |
5 | #include <asm/types.h> | |
6 | #include <asm/mpspec.h> | |
7 | ||
8 | /* | |
9 | * Intel IO-APIC support for SMP and UP systems. | |
10 | * | |
11 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar | |
12 | */ | |
13 | ||
14 | #ifdef CONFIG_X86_IO_APIC | |
15 | ||
16 | #ifdef CONFIG_PCI_MSI | |
17 | static inline int use_pci_vector(void) {return 1;} | |
18 | static inline void disable_edge_ioapic_vector(unsigned int vector) { } | |
19 | static inline void mask_and_ack_level_ioapic_vector(unsigned int vector) { } | |
20 | static inline void end_edge_ioapic_vector (unsigned int vector) { } | |
21 | #define startup_level_ioapic startup_level_ioapic_vector | |
22 | #define shutdown_level_ioapic mask_IO_APIC_vector | |
23 | #define enable_level_ioapic unmask_IO_APIC_vector | |
24 | #define disable_level_ioapic mask_IO_APIC_vector | |
25 | #define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_vector | |
26 | #define end_level_ioapic end_level_ioapic_vector | |
27 | #define set_ioapic_affinity set_ioapic_affinity_vector | |
28 | ||
29 | #define startup_edge_ioapic startup_edge_ioapic_vector | |
30 | #define shutdown_edge_ioapic disable_edge_ioapic_vector | |
31 | #define enable_edge_ioapic unmask_IO_APIC_vector | |
32 | #define disable_edge_ioapic disable_edge_ioapic_vector | |
33 | #define ack_edge_ioapic ack_edge_ioapic_vector | |
34 | #define end_edge_ioapic end_edge_ioapic_vector | |
35 | #else | |
36 | static inline int use_pci_vector(void) {return 0;} | |
37 | static inline void disable_edge_ioapic_irq(unsigned int irq) { } | |
38 | static inline void mask_and_ack_level_ioapic_irq(unsigned int irq) { } | |
39 | static inline void end_edge_ioapic_irq (unsigned int irq) { } | |
40 | #define startup_level_ioapic startup_level_ioapic_irq | |
41 | #define shutdown_level_ioapic mask_IO_APIC_irq | |
42 | #define enable_level_ioapic unmask_IO_APIC_irq | |
43 | #define disable_level_ioapic mask_IO_APIC_irq | |
44 | #define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_irq | |
45 | #define end_level_ioapic end_level_ioapic_irq | |
46 | #define set_ioapic_affinity set_ioapic_affinity_irq | |
47 | ||
48 | #define startup_edge_ioapic startup_edge_ioapic_irq | |
49 | #define shutdown_edge_ioapic disable_edge_ioapic_irq | |
50 | #define enable_edge_ioapic unmask_IO_APIC_irq | |
51 | #define disable_edge_ioapic disable_edge_ioapic_irq | |
52 | #define ack_edge_ioapic ack_edge_ioapic_irq | |
53 | #define end_edge_ioapic end_edge_ioapic_irq | |
54 | #endif | |
55 | ||
56 | #define APIC_MISMATCH_DEBUG | |
57 | ||
58 | #define IO_APIC_BASE(idx) \ | |
59 | ((volatile int *)(__fix_to_virt(FIX_IO_APIC_BASE_0 + idx) \ | |
60 | + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK))) | |
61 | ||
62 | /* | |
63 | * The structure of the IO-APIC: | |
64 | */ | |
65 | union IO_APIC_reg_00 { | |
66 | u32 raw; | |
67 | struct { | |
68 | u32 __reserved_2 : 14, | |
69 | LTS : 1, | |
70 | delivery_type : 1, | |
71 | __reserved_1 : 8, | |
72 | ID : 8; | |
73 | } __attribute__ ((packed)) bits; | |
74 | }; | |
75 | ||
76 | union IO_APIC_reg_01 { | |
77 | u32 raw; | |
78 | struct { | |
79 | u32 version : 8, | |
80 | __reserved_2 : 7, | |
81 | PRQ : 1, | |
82 | entries : 8, | |
83 | __reserved_1 : 8; | |
84 | } __attribute__ ((packed)) bits; | |
85 | }; | |
86 | ||
87 | union IO_APIC_reg_02 { | |
88 | u32 raw; | |
89 | struct { | |
90 | u32 __reserved_2 : 24, | |
91 | arbitration : 4, | |
92 | __reserved_1 : 4; | |
93 | } __attribute__ ((packed)) bits; | |
94 | }; | |
95 | ||
96 | union IO_APIC_reg_03 { | |
97 | u32 raw; | |
98 | struct { | |
99 | u32 boot_DT : 1, | |
100 | __reserved_1 : 31; | |
101 | } __attribute__ ((packed)) bits; | |
102 | }; | |
103 | ||
104 | /* | |
105 | * # of IO-APICs and # of IRQ routing registers | |
106 | */ | |
107 | extern int nr_ioapics; | |
108 | extern int nr_ioapic_registers[MAX_IO_APICS]; | |
109 | ||
110 | enum ioapic_irq_destination_types { | |
111 | dest_Fixed = 0, | |
112 | dest_LowestPrio = 1, | |
113 | dest_SMI = 2, | |
114 | dest__reserved_1 = 3, | |
115 | dest_NMI = 4, | |
116 | dest_INIT = 5, | |
117 | dest__reserved_2 = 6, | |
118 | dest_ExtINT = 7 | |
119 | }; | |
120 | ||
121 | struct IO_APIC_route_entry { | |
122 | __u32 vector : 8, | |
123 | delivery_mode : 3, /* 000: FIXED | |
124 | * 001: lowest prio | |
125 | * 111: ExtINT | |
126 | */ | |
127 | dest_mode : 1, /* 0: physical, 1: logical */ | |
128 | delivery_status : 1, | |
129 | polarity : 1, | |
130 | irr : 1, | |
131 | trigger : 1, /* 0: edge, 1: level */ | |
132 | mask : 1, /* 0: enabled, 1: disabled */ | |
133 | __reserved_2 : 15; | |
134 | ||
135 | union { struct { __u32 | |
136 | __reserved_1 : 24, | |
137 | physical_dest : 4, | |
138 | __reserved_2 : 4; | |
139 | } physical; | |
140 | ||
141 | struct { __u32 | |
142 | __reserved_1 : 24, | |
143 | logical_dest : 8; | |
144 | } logical; | |
145 | } dest; | |
146 | ||
147 | } __attribute__ ((packed)); | |
148 | ||
149 | /* | |
150 | * MP-BIOS irq configuration table structures: | |
151 | */ | |
152 | ||
153 | /* I/O APIC entries */ | |
154 | extern struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; | |
155 | ||
156 | /* # of MP IRQ source entries */ | |
157 | extern int mp_irq_entries; | |
158 | ||
159 | /* MP IRQ source entries */ | |
160 | extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; | |
161 | ||
162 | /* non-0 if default (table-less) MP configuration */ | |
163 | extern int mpc_default_type; | |
164 | ||
165 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
166 | { | |
167 | *IO_APIC_BASE(apic) = reg; | |
168 | return *(IO_APIC_BASE(apic)+4); | |
169 | } | |
170 | ||
171 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
172 | { | |
173 | *IO_APIC_BASE(apic) = reg; | |
174 | *(IO_APIC_BASE(apic)+4) = value; | |
175 | } | |
176 | ||
177 | /* | |
178 | * Re-write a value: to be used for read-modify-write | |
179 | * cycles where the read already set up the index register. | |
180 | */ | |
181 | static inline void io_apic_modify(unsigned int apic, unsigned int value) | |
182 | { | |
183 | *(IO_APIC_BASE(apic)+4) = value; | |
184 | } | |
185 | ||
186 | /* | |
187 | * Synchronize the IO-APIC and the CPU by doing | |
188 | * a dummy read from the IO-APIC | |
189 | */ | |
190 | static inline void io_apic_sync(unsigned int apic) | |
191 | { | |
192 | (void) *(IO_APIC_BASE(apic)+4); | |
193 | } | |
194 | ||
195 | /* 1 if "noapic" boot option passed */ | |
196 | extern int skip_ioapic_setup; | |
197 | ||
198 | /* | |
199 | * If we use the IO-APIC for IRQ routing, disable automatic | |
200 | * assignment of PCI IRQ's. | |
201 | */ | |
202 | #define io_apic_assign_pci_irqs (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs) | |
203 | ||
888ba6c6 | 204 | #ifdef CONFIG_ACPI |
1da177e4 LT |
205 | extern int io_apic_get_version (int ioapic); |
206 | extern int io_apic_get_redir_entries (int ioapic); | |
207 | extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int, int); | |
208 | #endif | |
209 | ||
210 | extern int sis_apic_bug; /* dummy */ | |
211 | ||
212 | #else /* !CONFIG_X86_IO_APIC */ | |
213 | #define io_apic_assign_pci_irqs 0 | |
214 | #endif | |
215 | ||
216 | extern int assign_irq_vector(int irq); | |
217 | ||
218 | void enable_NMI_through_LVT0 (void * dummy); | |
219 | ||
306e440d IM |
220 | extern spinlock_t i8259A_lock; |
221 | ||
1da177e4 | 222 | #endif |