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1da177e4 LT |
1 | #ifndef __ASM_SMP_H |
2 | #define __ASM_SMP_H | |
3 | ||
4 | /* | |
5 | * We need the APIC definitions automatically as part of 'smp.h' | |
6 | */ | |
7 | #ifndef __ASSEMBLY__ | |
8 | #include <linux/config.h> | |
9 | #include <linux/threads.h> | |
10 | #include <linux/cpumask.h> | |
11 | #include <linux/bitops.h> | |
12 | extern int disable_apic; | |
13 | #endif | |
14 | ||
15 | #ifdef CONFIG_X86_LOCAL_APIC | |
16 | #ifndef __ASSEMBLY__ | |
17 | #include <asm/fixmap.h> | |
18 | #include <asm/mpspec.h> | |
19 | #ifdef CONFIG_X86_IO_APIC | |
20 | #include <asm/io_apic.h> | |
21 | #endif | |
22 | #include <asm/apic.h> | |
23 | #include <asm/thread_info.h> | |
24 | #endif | |
25 | #endif | |
26 | ||
27 | #ifdef CONFIG_SMP | |
28 | #ifndef ASSEMBLY | |
29 | ||
30 | #include <asm/pda.h> | |
31 | ||
32 | struct pt_regs; | |
33 | ||
a8ab26fe AK |
34 | extern cpumask_t cpu_present_mask; |
35 | extern cpumask_t cpu_possible_map; | |
36 | extern cpumask_t cpu_online_map; | |
37 | extern cpumask_t cpu_callout_map; | |
3c021751 | 38 | extern cpumask_t cpu_initialized; |
a8ab26fe | 39 | |
1da177e4 LT |
40 | /* |
41 | * Private routines/data | |
42 | */ | |
43 | ||
44 | extern void smp_alloc_memory(void); | |
1da177e4 LT |
45 | extern volatile unsigned long smp_invalidate_needed; |
46 | extern int pic_mode; | |
884d9e40 AR |
47 | extern void lock_ipi_call_lock(void); |
48 | extern void unlock_ipi_call_lock(void); | |
1da177e4 | 49 | extern int smp_num_siblings; |
1da177e4 | 50 | extern void smp_send_reschedule(int cpu); |
1da177e4 | 51 | void smp_stop_cpu(void); |
3d483f47 EB |
52 | extern int smp_call_function_single(int cpuid, void (*func) (void *info), |
53 | void *info, int retry, int wait); | |
54 | ||
1da177e4 | 55 | extern cpumask_t cpu_sibling_map[NR_CPUS]; |
3dd9d514 | 56 | extern cpumask_t cpu_core_map[NR_CPUS]; |
1da177e4 | 57 | extern u8 phys_proc_id[NR_CPUS]; |
3dd9d514 | 58 | extern u8 cpu_core_id[NR_CPUS]; |
1da177e4 LT |
59 | |
60 | #define SMP_TRAMPOLINE_BASE 0x6000 | |
61 | ||
62 | /* | |
63 | * On x86 all CPUs are mapped 1:1 to the APIC space. | |
64 | * This simplifies scheduling and IPI sending and | |
65 | * compresses data structures. | |
66 | */ | |
67 | ||
1da177e4 LT |
68 | static inline int num_booting_cpus(void) |
69 | { | |
70 | return cpus_weight(cpu_callout_map); | |
71 | } | |
72 | ||
39c715b7 | 73 | #define raw_smp_processor_id() read_pda(cpunumber) |
1da177e4 | 74 | |
9c0aa0f9 | 75 | static inline int hard_smp_processor_id(void) |
1da177e4 LT |
76 | { |
77 | /* we don't want to mark this access volatile - bad code generation */ | |
78 | return GET_APIC_ID(*(unsigned int *)(APIC_BASE+APIC_ID)); | |
79 | } | |
80 | ||
a8ab26fe | 81 | extern int safe_smp_processor_id(void); |
76e4f660 AR |
82 | extern int __cpu_disable(void); |
83 | extern void __cpu_die(unsigned int cpu); | |
421c7ce6 | 84 | extern void prefill_possible_map(void); |
420f8f68 AK |
85 | extern unsigned num_processors; |
86 | extern unsigned disabled_cpus; | |
1da177e4 LT |
87 | |
88 | #endif /* !ASSEMBLY */ | |
89 | ||
90 | #define NO_PROC_ID 0xFF /* No processor magic marker */ | |
91 | ||
92 | #endif | |
93 | ||
94 | #ifndef ASSEMBLY | |
95 | /* | |
96 | * Some lowlevel functions might want to know about | |
97 | * the real APIC ID <-> CPU # mapping. | |
98 | */ | |
99 | extern u8 x86_cpu_to_apicid[NR_CPUS]; /* physical ID */ | |
100 | extern u8 x86_cpu_to_log_apicid[NR_CPUS]; | |
101 | extern u8 bios_cpu_apicid[]; | |
102 | ||
103 | static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask) | |
104 | { | |
105 | return cpus_addr(cpumask)[0]; | |
106 | } | |
107 | ||
1da177e4 LT |
108 | static inline int cpu_present_to_apicid(int mps_cpu) |
109 | { | |
110 | if (mps_cpu < NR_CPUS) | |
111 | return (int)bios_cpu_apicid[mps_cpu]; | |
112 | else | |
113 | return BAD_APICID; | |
114 | } | |
115 | ||
116 | #endif /* !ASSEMBLY */ | |
117 | ||
118 | #ifndef CONFIG_SMP | |
119 | #define stack_smp_processor_id() 0 | |
120 | #define safe_smp_processor_id() 0 | |
121 | #define cpu_logical_map(x) (x) | |
122 | #else | |
123 | #include <asm/thread_info.h> | |
124 | #define stack_smp_processor_id() \ | |
125 | ({ \ | |
126 | struct thread_info *ti; \ | |
127 | __asm__("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK)); \ | |
128 | ti->cpu; \ | |
129 | }) | |
130 | #endif | |
131 | ||
132 | #ifndef __ASSEMBLY__ | |
133 | static __inline int logical_smp_processor_id(void) | |
134 | { | |
135 | /* we don't want to mark this access volatile - bad code generation */ | |
136 | return GET_APIC_LOGICAL_ID(*(unsigned long *)(APIC_BASE+APIC_LDR)); | |
137 | } | |
138 | #endif | |
139 | ||
b4033c17 AR |
140 | #ifdef CONFIG_SMP |
141 | #define cpu_physical_id(cpu) x86_cpu_to_apicid[cpu] | |
142 | #else | |
143 | #define cpu_physical_id(cpu) boot_cpu_id | |
144 | #endif | |
145 | ||
1da177e4 LT |
146 | #endif |
147 |