[deliverable/linux.git] / include / dt-bindings / clock / imx6qdl-clock.h

/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
#define __DT_BINDINGS_CLOCK_IMX6QDL_H

#define IMX6QDL_CLK_DUMMY			0
#define IMX6QDL_CLK_CKIL			1
#define IMX6QDL_CLK_CKIH			2
#define IMX6QDL_CLK_OSC				3
#define IMX6QDL_CLK_PLL2_PFD0_352M		4
#define IMX6QDL_CLK_PLL2_PFD1_594M		5
#define IMX6QDL_CLK_PLL2_PFD2_396M		6
#define IMX6QDL_CLK_PLL3_PFD0_720M		7
#define IMX6QDL_CLK_PLL3_PFD1_540M		8
#define IMX6QDL_CLK_PLL3_PFD2_508M		9
#define IMX6QDL_CLK_PLL3_PFD3_454M		10
#define IMX6QDL_CLK_PLL2_198M			11
#define IMX6QDL_CLK_PLL3_120M			12
#define IMX6QDL_CLK_PLL3_80M			13
#define IMX6QDL_CLK_PLL3_60M			14
#define IMX6QDL_CLK_TWD				15
#define IMX6QDL_CLK_STEP			16
#define IMX6QDL_CLK_PLL1_SW			17
#define IMX6QDL_CLK_PERIPH_PRE			18
#define IMX6QDL_CLK_PERIPH2_PRE			19
#define IMX6QDL_CLK_PERIPH_CLK2_SEL		20
#define IMX6QDL_CLK_PERIPH2_CLK2_SEL		21
#define IMX6QDL_CLK_AXI_SEL			22
#define IMX6QDL_CLK_ESAI_SEL			23
#define IMX6QDL_CLK_ASRC_SEL			24
#define IMX6QDL_CLK_SPDIF_SEL			25
#define IMX6QDL_CLK_GPU2D_AXI			26
#define IMX6QDL_CLK_GPU3D_AXI			27
#define IMX6QDL_CLK_GPU2D_CORE_SEL		28
#define IMX6QDL_CLK_GPU3D_CORE_SEL		29
#define IMX6QDL_CLK_GPU3D_SHADER_SEL		30
#define IMX6QDL_CLK_IPU1_SEL			31
#define IMX6QDL_CLK_IPU2_SEL			32
#define IMX6QDL_CLK_LDB_DI0_SEL			33
#define IMX6QDL_CLK_LDB_DI1_SEL			34
#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL		35
#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL		36
#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL		37
#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL		38
#define IMX6QDL_CLK_IPU1_DI0_SEL		39
#define IMX6QDL_CLK_IPU1_DI1_SEL		40
#define IMX6QDL_CLK_IPU2_DI0_SEL		41
#define IMX6QDL_CLK_IPU2_DI1_SEL		42
#define IMX6QDL_CLK_HSI_TX_SEL			43
#define IMX6QDL_CLK_PCIE_AXI_SEL		44
#define IMX6QDL_CLK_SSI1_SEL			45
#define IMX6QDL_CLK_SSI2_SEL			46
#define IMX6QDL_CLK_SSI3_SEL			47
#define IMX6QDL_CLK_USDHC1_SEL			48
#define IMX6QDL_CLK_USDHC2_SEL			49
#define IMX6QDL_CLK_USDHC3_SEL			50
#define IMX6QDL_CLK_USDHC4_SEL			51
#define IMX6QDL_CLK_ENFC_SEL			52
#define IMX6QDL_CLK_EMI_SEL			53
#define IMX6QDL_CLK_EMI_SLOW_SEL		54
#define IMX6QDL_CLK_VDO_AXI_SEL			55
#define IMX6QDL_CLK_VPU_AXI_SEL			56
#define IMX6QDL_CLK_CKO1_SEL			57
#define IMX6QDL_CLK_PERIPH			58
#define IMX6QDL_CLK_PERIPH2			59
#define IMX6QDL_CLK_PERIPH_CLK2			60
#define IMX6QDL_CLK_PERIPH2_CLK2		61
#define IMX6QDL_CLK_IPG				62
#define IMX6QDL_CLK_IPG_PER			63
#define IMX6QDL_CLK_ESAI_PRED			64
#define IMX6QDL_CLK_ESAI_PODF			65
#define IMX6QDL_CLK_ASRC_PRED			66
#define IMX6QDL_CLK_ASRC_PODF			67
#define IMX6QDL_CLK_SPDIF_PRED			68
#define IMX6QDL_CLK_SPDIF_PODF			69
#define IMX6QDL_CLK_CAN_ROOT			70
#define IMX6QDL_CLK_ECSPI_ROOT			71
#define IMX6QDL_CLK_GPU2D_CORE_PODF		72
#define IMX6QDL_CLK_GPU3D_CORE_PODF		73
#define IMX6QDL_CLK_GPU3D_SHADER		74
#define IMX6QDL_CLK_IPU1_PODF			75
#define IMX6QDL_CLK_IPU2_PODF			76
#define IMX6QDL_CLK_LDB_DI0_PODF		77
#define IMX6QDL_CLK_LDB_DI1_PODF		78
#define IMX6QDL_CLK_IPU1_DI0_PRE		79
#define IMX6QDL_CLK_IPU1_DI1_PRE		80
#define IMX6QDL_CLK_IPU2_DI0_PRE		81
#define IMX6QDL_CLK_IPU2_DI1_PRE		82
#define IMX6QDL_CLK_HSI_TX_PODF			83
#define IMX6QDL_CLK_SSI1_PRED			84
#define IMX6QDL_CLK_SSI1_PODF			85
#define IMX6QDL_CLK_SSI2_PRED			86
#define IMX6QDL_CLK_SSI2_PODF			87
#define IMX6QDL_CLK_SSI3_PRED			88
#define IMX6QDL_CLK_SSI3_PODF			89
#define IMX6QDL_CLK_UART_SERIAL_PODF		90
#define IMX6QDL_CLK_USDHC1_PODF			91
#define IMX6QDL_CLK_USDHC2_PODF			92
#define IMX6QDL_CLK_USDHC3_PODF			93
#define IMX6QDL_CLK_USDHC4_PODF			94
#define IMX6QDL_CLK_ENFC_PRED			95
#define IMX6QDL_CLK_ENFC_PODF			96
#define IMX6QDL_CLK_EMI_PODF			97
#define IMX6QDL_CLK_EMI_SLOW_PODF		98
#define IMX6QDL_CLK_VPU_AXI_PODF		99
#define IMX6QDL_CLK_CKO1_PODF			100
#define IMX6QDL_CLK_AXI				101
#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF		102
#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF		103
#define IMX6QDL_CLK_ARM				104
#define IMX6QDL_CLK_AHB				105
#define IMX6QDL_CLK_APBH_DMA			106
#define IMX6QDL_CLK_ASRC			107
#define IMX6QDL_CLK_CAN1_IPG			108
#define IMX6QDL_CLK_CAN1_SERIAL			109
#define IMX6QDL_CLK_CAN2_IPG			110
#define IMX6QDL_CLK_CAN2_SERIAL			111
#define IMX6QDL_CLK_ECSPI1			112
#define IMX6QDL_CLK_ECSPI2			113
#define IMX6QDL_CLK_ECSPI3			114
#define IMX6QDL_CLK_ECSPI4			115
#define IMX6Q_CLK_ECSPI5			116
#define IMX6DL_CLK_I2C4				116
#define IMX6QDL_CLK_ENET			117
#define IMX6QDL_CLK_ESAI_EXTAL			118
#define IMX6QDL_CLK_GPT_IPG			119
#define IMX6QDL_CLK_GPT_IPG_PER			120
#define IMX6QDL_CLK_GPU2D_CORE			121
#define IMX6QDL_CLK_GPU3D_CORE			122
#define IMX6QDL_CLK_HDMI_IAHB			123
#define IMX6QDL_CLK_HDMI_ISFR			124
#define IMX6QDL_CLK_I2C1			125
#define IMX6QDL_CLK_I2C2			126
#define IMX6QDL_CLK_I2C3			127
#define IMX6QDL_CLK_IIM				128
#define IMX6QDL_CLK_ENFC			129
#define IMX6QDL_CLK_IPU1			130
#define IMX6QDL_CLK_IPU1_DI0			131
#define IMX6QDL_CLK_IPU1_DI1			132
#define IMX6QDL_CLK_IPU2			133
#define IMX6QDL_CLK_IPU2_DI0			134
#define IMX6QDL_CLK_LDB_DI0			135
#define IMX6QDL_CLK_LDB_DI1			136
#define IMX6QDL_CLK_IPU2_DI1			137
#define IMX6QDL_CLK_HSI_TX			138
#define IMX6QDL_CLK_MLB				139
#define IMX6QDL_CLK_MMDC_CH0_AXI		140
#define IMX6QDL_CLK_MMDC_CH1_AXI		141
#define IMX6QDL_CLK_OCRAM			142
#define IMX6QDL_CLK_OPENVG_AXI			143
#define IMX6QDL_CLK_PCIE_AXI			144
#define IMX6QDL_CLK_PWM1			145
#define IMX6QDL_CLK_PWM2			146
#define IMX6QDL_CLK_PWM3			147
#define IMX6QDL_CLK_PWM4			148
#define IMX6QDL_CLK_PER1_BCH			149
#define IMX6QDL_CLK_GPMI_BCH_APB		150
#define IMX6QDL_CLK_GPMI_BCH			151
#define IMX6QDL_CLK_GPMI_IO			152
#define IMX6QDL_CLK_GPMI_APB			153
#define IMX6QDL_CLK_SATA			154
#define IMX6QDL_CLK_SDMA			155
#define IMX6QDL_CLK_SPBA			156
#define IMX6QDL_CLK_SSI1			157
#define IMX6QDL_CLK_SSI2			158
#define IMX6QDL_CLK_SSI3			159
#define IMX6QDL_CLK_UART_IPG			160
#define IMX6QDL_CLK_UART_SERIAL			161
#define IMX6QDL_CLK_USBOH3			162
#define IMX6QDL_CLK_USDHC1			163
#define IMX6QDL_CLK_USDHC2			164
#define IMX6QDL_CLK_USDHC3			165
#define IMX6QDL_CLK_USDHC4			166
#define IMX6QDL_CLK_VDO_AXI			167
#define IMX6QDL_CLK_VPU_AXI			168
#define IMX6QDL_CLK_CKO1			169
#define IMX6QDL_CLK_PLL1_SYS			170
#define IMX6QDL_CLK_PLL2_BUS			171
#define IMX6QDL_CLK_PLL3_USB_OTG		172
#define IMX6QDL_CLK_PLL4_AUDIO			173
#define IMX6QDL_CLK_PLL5_VIDEO			174
#define IMX6QDL_CLK_PLL8_MLB			175
#define IMX6QDL_CLK_PLL7_USB_HOST		176
#define IMX6QDL_CLK_PLL6_ENET			177
#define IMX6QDL_CLK_SSI1_IPG			178
#define IMX6QDL_CLK_SSI2_IPG			179
#define IMX6QDL_CLK_SSI3_IPG			180
#define IMX6QDL_CLK_ROM				181
#define IMX6QDL_CLK_USBPHY1			182
#define IMX6QDL_CLK_USBPHY2			183
#define IMX6QDL_CLK_LDB_DI0_DIV_3_5		184
#define IMX6QDL_CLK_LDB_DI1_DIV_3_5		185
#define IMX6QDL_CLK_SATA_REF			186
#define IMX6QDL_CLK_SATA_REF_100M		187
#define IMX6QDL_CLK_PCIE_REF			188
#define IMX6QDL_CLK_PCIE_REF_125M		189
#define IMX6QDL_CLK_ENET_REF			190
#define IMX6QDL_CLK_USBPHY1_GATE		191
#define IMX6QDL_CLK_USBPHY2_GATE		192
#define IMX6QDL_CLK_PLL4_POST_DIV		193
#define IMX6QDL_CLK_PLL5_POST_DIV		194
#define IMX6QDL_CLK_PLL5_VIDEO_DIV		195
#define IMX6QDL_CLK_EIM_SLOW			196
#define IMX6QDL_CLK_SPDIF			197
#define IMX6QDL_CLK_CKO2_SEL			198
#define IMX6QDL_CLK_CKO2_PODF			199
#define IMX6QDL_CLK_CKO2			200
#define IMX6QDL_CLK_CKO				201
#define IMX6QDL_CLK_VDOA			202
#define IMX6QDL_CLK_PLL4_AUDIO_DIV		203
#define IMX6QDL_CLK_LVDS1_SEL			204
#define IMX6QDL_CLK_LVDS2_SEL			205
#define IMX6QDL_CLK_LVDS1_GATE			206
#define IMX6QDL_CLK_LVDS2_GATE			207
#define IMX6QDL_CLK_ESAI_IPG			208
#define IMX6QDL_CLK_ESAI_MEM			209
#define IMX6QDL_CLK_ASRC_IPG			210
#define IMX6QDL_CLK_ASRC_MEM			211
#define IMX6QDL_CLK_LVDS1_IN			212
#define IMX6QDL_CLK_LVDS2_IN			213
#define IMX6QDL_CLK_ANACLK1			214
#define IMX6QDL_CLK_ANACLK2			215
#define IMX6QDL_PLL1_BYPASS_SRC			216
#define IMX6QDL_PLL2_BYPASS_SRC			217
#define IMX6QDL_PLL3_BYPASS_SRC			218
#define IMX6QDL_PLL4_BYPASS_SRC			219
#define IMX6QDL_PLL5_BYPASS_SRC			220
#define IMX6QDL_PLL6_BYPASS_SRC			221
#define IMX6QDL_PLL7_BYPASS_SRC			222
#define IMX6QDL_CLK_PLL1			223
#define IMX6QDL_CLK_PLL2			224
#define IMX6QDL_CLK_PLL3			225
#define IMX6QDL_CLK_PLL4			226
#define IMX6QDL_CLK_PLL5			227
#define IMX6QDL_CLK_PLL6			228
#define IMX6QDL_CLK_PLL7			229
#define IMX6QDL_PLL1_BYPASS			230
#define IMX6QDL_PLL2_BYPASS			231
#define IMX6QDL_PLL3_BYPASS			232
#define IMX6QDL_PLL4_BYPASS			233
#define IMX6QDL_PLL5_BYPASS			234
#define IMX6QDL_PLL6_BYPASS			235
#define IMX6QDL_PLL7_BYPASS			236
#define IMX6QDL_CLK_GPT_3M			237
#define IMX6QDL_CLK_END				238

#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
Commit	Line	Data
d2d2e54d SG	1	/*
	2	* Copyright 2014 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
	10	#define __DT_BINDINGS_CLOCK_IMX6QDL_H
	11
	12	#define IMX6QDL_CLK_DUMMY 0
	13	#define IMX6QDL_CLK_CKIL 1
	14	#define IMX6QDL_CLK_CKIH 2
	15	#define IMX6QDL_CLK_OSC 3
	16	#define IMX6QDL_CLK_PLL2_PFD0_352M 4
	17	#define IMX6QDL_CLK_PLL2_PFD1_594M 5
	18	#define IMX6QDL_CLK_PLL2_PFD2_396M 6
	19	#define IMX6QDL_CLK_PLL3_PFD0_720M 7
	20	#define IMX6QDL_CLK_PLL3_PFD1_540M 8
	21	#define IMX6QDL_CLK_PLL3_PFD2_508M 9
	22	#define IMX6QDL_CLK_PLL3_PFD3_454M 10
	23	#define IMX6QDL_CLK_PLL2_198M 11
	24	#define IMX6QDL_CLK_PLL3_120M 12
	25	#define IMX6QDL_CLK_PLL3_80M 13
	26	#define IMX6QDL_CLK_PLL3_60M 14
	27	#define IMX6QDL_CLK_TWD 15
	28	#define IMX6QDL_CLK_STEP 16
	29	#define IMX6QDL_CLK_PLL1_SW 17
	30	#define IMX6QDL_CLK_PERIPH_PRE 18
	31	#define IMX6QDL_CLK_PERIPH2_PRE 19
	32	#define IMX6QDL_CLK_PERIPH_CLK2_SEL 20
	33	#define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21
	34	#define IMX6QDL_CLK_AXI_SEL 22
	35	#define IMX6QDL_CLK_ESAI_SEL 23
	36	#define IMX6QDL_CLK_ASRC_SEL 24
	37	#define IMX6QDL_CLK_SPDIF_SEL 25
	38	#define IMX6QDL_CLK_GPU2D_AXI 26
	39	#define IMX6QDL_CLK_GPU3D_AXI 27
	40	#define IMX6QDL_CLK_GPU2D_CORE_SEL 28
	41	#define IMX6QDL_CLK_GPU3D_CORE_SEL 29
	42	#define IMX6QDL_CLK_GPU3D_SHADER_SEL 30
	43	#define IMX6QDL_CLK_IPU1_SEL 31
	44	#define IMX6QDL_CLK_IPU2_SEL 32
	45	#define IMX6QDL_CLK_LDB_DI0_SEL 33
	46	#define IMX6QDL_CLK_LDB_DI1_SEL 34
	47	#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35
	48	#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36
	49	#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37
	50	#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38
	51	#define IMX6QDL_CLK_IPU1_DI0_SEL 39
	52	#define IMX6QDL_CLK_IPU1_DI1_SEL 40
	53	#define IMX6QDL_CLK_IPU2_DI0_SEL 41
	54	#define IMX6QDL_CLK_IPU2_DI1_SEL 42
	55	#define IMX6QDL_CLK_HSI_TX_SEL 43
	56	#define IMX6QDL_CLK_PCIE_AXI_SEL 44
	57	#define IMX6QDL_CLK_SSI1_SEL 45
	58	#define IMX6QDL_CLK_SSI2_SEL 46
	59	#define IMX6QDL_CLK_SSI3_SEL 47
	60	#define IMX6QDL_CLK_USDHC1_SEL 48
	61	#define IMX6QDL_CLK_USDHC2_SEL 49
	62	#define IMX6QDL_CLK_USDHC3_SEL 50
	63	#define IMX6QDL_CLK_USDHC4_SEL 51
	64	#define IMX6QDL_CLK_ENFC_SEL 52
65	#define IMX6QDL_CLK_EMI_SEL 53
66	#define IMX6QDL_CLK_EMI_SLOW_SEL 54
67	#define IMX6QDL_CLK_VDO_AXI_SEL 55
68	#define IMX6QDL_CLK_VPU_AXI_SEL 56
69	#define IMX6QDL_CLK_CKO1_SEL 57
70	#define IMX6QDL_CLK_PERIPH 58
71	#define IMX6QDL_CLK_PERIPH2 59
72	#define IMX6QDL_CLK_PERIPH_CLK2 60
73	#define IMX6QDL_CLK_PERIPH2_CLK2 61
74	#define IMX6QDL_CLK_IPG 62
75	#define IMX6QDL_CLK_IPG_PER 63
76	#define IMX6QDL_CLK_ESAI_PRED 64
77	#define IMX6QDL_CLK_ESAI_PODF 65
78	#define IMX6QDL_CLK_ASRC_PRED 66
79	#define IMX6QDL_CLK_ASRC_PODF 67
80	#define IMX6QDL_CLK_SPDIF_PRED 68
81	#define IMX6QDL_CLK_SPDIF_PODF 69
82	#define IMX6QDL_CLK_CAN_ROOT 70
83	#define IMX6QDL_CLK_ECSPI_ROOT 71
84	#define IMX6QDL_CLK_GPU2D_CORE_PODF 72
85	#define IMX6QDL_CLK_GPU3D_CORE_PODF 73
86	#define IMX6QDL_CLK_GPU3D_SHADER 74
87	#define IMX6QDL_CLK_IPU1_PODF 75
88	#define IMX6QDL_CLK_IPU2_PODF 76
89	#define IMX6QDL_CLK_LDB_DI0_PODF 77
90	#define IMX6QDL_CLK_LDB_DI1_PODF 78
91	#define IMX6QDL_CLK_IPU1_DI0_PRE 79
92	#define IMX6QDL_CLK_IPU1_DI1_PRE 80
93	#define IMX6QDL_CLK_IPU2_DI0_PRE 81
94	#define IMX6QDL_CLK_IPU2_DI1_PRE 82
95	#define IMX6QDL_CLK_HSI_TX_PODF 83
96	#define IMX6QDL_CLK_SSI1_PRED 84
97	#define IMX6QDL_CLK_SSI1_PODF 85
98	#define IMX6QDL_CLK_SSI2_PRED 86
99	#define IMX6QDL_CLK_SSI2_PODF 87
100	#define IMX6QDL_CLK_SSI3_PRED 88
101	#define IMX6QDL_CLK_SSI3_PODF 89
102	#define IMX6QDL_CLK_UART_SERIAL_PODF 90
103	#define IMX6QDL_CLK_USDHC1_PODF 91
104	#define IMX6QDL_CLK_USDHC2_PODF 92
105	#define IMX6QDL_CLK_USDHC3_PODF 93
106	#define IMX6QDL_CLK_USDHC4_PODF 94
107	#define IMX6QDL_CLK_ENFC_PRED 95
108	#define IMX6QDL_CLK_ENFC_PODF 96
109	#define IMX6QDL_CLK_EMI_PODF 97
110	#define IMX6QDL_CLK_EMI_SLOW_PODF 98
111	#define IMX6QDL_CLK_VPU_AXI_PODF 99
112	#define IMX6QDL_CLK_CKO1_PODF 100
113	#define IMX6QDL_CLK_AXI 101
114	#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102
115	#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103
116	#define IMX6QDL_CLK_ARM 104
117	#define IMX6QDL_CLK_AHB 105
118	#define IMX6QDL_CLK_APBH_DMA 106
119	#define IMX6QDL_CLK_ASRC 107
120	#define IMX6QDL_CLK_CAN1_IPG 108
121	#define IMX6QDL_CLK_CAN1_SERIAL 109
122	#define IMX6QDL_CLK_CAN2_IPG 110
123	#define IMX6QDL_CLK_CAN2_SERIAL 111
124	#define IMX6QDL_CLK_ECSPI1 112
125	#define IMX6QDL_CLK_ECSPI2 113
126	#define IMX6QDL_CLK_ECSPI3 114
127	#define IMX6QDL_CLK_ECSPI4 115
128	#define IMX6Q_CLK_ECSPI5 116
129	#define IMX6DL_CLK_I2C4 116
130	#define IMX6QDL_CLK_ENET 117
7bce3d23	131	#define IMX6QDL_CLK_ESAI_EXTAL 118
d2d2e54d SG	132	#define IMX6QDL_CLK_GPT_IPG 119
	133	#define IMX6QDL_CLK_GPT_IPG_PER 120
	134	#define IMX6QDL_CLK_GPU2D_CORE 121
	135	#define IMX6QDL_CLK_GPU3D_CORE 122
	136	#define IMX6QDL_CLK_HDMI_IAHB 123
	137	#define IMX6QDL_CLK_HDMI_ISFR 124
	138	#define IMX6QDL_CLK_I2C1 125
	139	#define IMX6QDL_CLK_I2C2 126
	140	#define IMX6QDL_CLK_I2C3 127
	141	#define IMX6QDL_CLK_IIM 128
	142	#define IMX6QDL_CLK_ENFC 129
	143	#define IMX6QDL_CLK_IPU1 130
	144	#define IMX6QDL_CLK_IPU1_DI0 131
	145	#define IMX6QDL_CLK_IPU1_DI1 132
	146	#define IMX6QDL_CLK_IPU2 133
	147	#define IMX6QDL_CLK_IPU2_DI0 134
	148	#define IMX6QDL_CLK_LDB_DI0 135
	149	#define IMX6QDL_CLK_LDB_DI1 136
	150	#define IMX6QDL_CLK_IPU2_DI1 137
	151	#define IMX6QDL_CLK_HSI_TX 138
	152	#define IMX6QDL_CLK_MLB 139
	153	#define IMX6QDL_CLK_MMDC_CH0_AXI 140
	154	#define IMX6QDL_CLK_MMDC_CH1_AXI 141
	155	#define IMX6QDL_CLK_OCRAM 142
	156	#define IMX6QDL_CLK_OPENVG_AXI 143
	157	#define IMX6QDL_CLK_PCIE_AXI 144
	158	#define IMX6QDL_CLK_PWM1 145
	159	#define IMX6QDL_CLK_PWM2 146
	160	#define IMX6QDL_CLK_PWM3 147
	161	#define IMX6QDL_CLK_PWM4 148
	162	#define IMX6QDL_CLK_PER1_BCH 149
	163	#define IMX6QDL_CLK_GPMI_BCH_APB 150
	164	#define IMX6QDL_CLK_GPMI_BCH 151
	165	#define IMX6QDL_CLK_GPMI_IO 152
	166	#define IMX6QDL_CLK_GPMI_APB 153
	167	#define IMX6QDL_CLK_SATA 154
	168	#define IMX6QDL_CLK_SDMA 155
	169	#define IMX6QDL_CLK_SPBA 156
	170	#define IMX6QDL_CLK_SSI1 157
	171	#define IMX6QDL_CLK_SSI2 158
	172	#define IMX6QDL_CLK_SSI3 159
	173	#define IMX6QDL_CLK_UART_IPG 160
	174	#define IMX6QDL_CLK_UART_SERIAL 161
	175	#define IMX6QDL_CLK_USBOH3 162
	176	#define IMX6QDL_CLK_USDHC1 163
	177	#define IMX6QDL_CLK_USDHC2 164
	178	#define IMX6QDL_CLK_USDHC3 165
	179	#define IMX6QDL_CLK_USDHC4 166
	180	#define IMX6QDL_CLK_VDO_AXI 167
	181	#define IMX6QDL_CLK_VPU_AXI 168
	182	#define IMX6QDL_CLK_CKO1 169
	183	#define IMX6QDL_CLK_PLL1_SYS 170
	184	#define IMX6QDL_CLK_PLL2_BUS 171
	185	#define IMX6QDL_CLK_PLL3_USB_OTG 172
	186	#define IMX6QDL_CLK_PLL4_AUDIO 173
	187	#define IMX6QDL_CLK_PLL5_VIDEO 174
	188	#define IMX6QDL_CLK_PLL8_MLB 175
	189	#define IMX6QDL_CLK_PLL7_USB_HOST 176
	190	#define IMX6QDL_CLK_PLL6_ENET 177
	191	#define IMX6QDL_CLK_SSI1_IPG 178
	192	#define IMX6QDL_CLK_SSI2_IPG 179
	193	#define IMX6QDL_CLK_SSI3_IPG 180
	194	#define IMX6QDL_CLK_ROM 181
	195	#define IMX6QDL_CLK_USBPHY1 182
196	#define IMX6QDL_CLK_USBPHY2 183
197	#define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184
198	#define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185
199	#define IMX6QDL_CLK_SATA_REF 186
200	#define IMX6QDL_CLK_SATA_REF_100M 187
201	#define IMX6QDL_CLK_PCIE_REF 188
202	#define IMX6QDL_CLK_PCIE_REF_125M 189
203	#define IMX6QDL_CLK_ENET_REF 190
204	#define IMX6QDL_CLK_USBPHY1_GATE 191
205	#define IMX6QDL_CLK_USBPHY2_GATE 192
206	#define IMX6QDL_CLK_PLL4_POST_DIV 193
207	#define IMX6QDL_CLK_PLL5_POST_DIV 194
208	#define IMX6QDL_CLK_PLL5_VIDEO_DIV 195
209	#define IMX6QDL_CLK_EIM_SLOW 196
210	#define IMX6QDL_CLK_SPDIF 197
211	#define IMX6QDL_CLK_CKO2_SEL 198
212	#define IMX6QDL_CLK_CKO2_PODF 199
213	#define IMX6QDL_CLK_CKO2 200
214	#define IMX6QDL_CLK_CKO 201
215	#define IMX6QDL_CLK_VDOA 202
216	#define IMX6QDL_CLK_PLL4_AUDIO_DIV 203
217	#define IMX6QDL_CLK_LVDS1_SEL 204
218	#define IMX6QDL_CLK_LVDS2_SEL 205
219	#define IMX6QDL_CLK_LVDS1_GATE 206
220	#define IMX6QDL_CLK_LVDS2_GATE 207
7bce3d23 SW	221	#define IMX6QDL_CLK_ESAI_IPG 208
7bce3d23 SW	222	#define IMX6QDL_CLK_ESAI_MEM 209
aec247d4 SW	223	#define IMX6QDL_CLK_ASRC_IPG 210
aec247d4 SW	224	#define IMX6QDL_CLK_ASRC_MEM 211
b1f156db SG	225	#define IMX6QDL_CLK_LVDS1_IN 212
	226	#define IMX6QDL_CLK_LVDS2_IN 213
	227	#define IMX6QDL_CLK_ANACLK1 214
	228	#define IMX6QDL_CLK_ANACLK2 215
	229	#define IMX6QDL_PLL1_BYPASS_SRC 216
	230	#define IMX6QDL_PLL2_BYPASS_SRC 217
	231	#define IMX6QDL_PLL3_BYPASS_SRC 218
	232	#define IMX6QDL_PLL4_BYPASS_SRC 219
	233	#define IMX6QDL_PLL5_BYPASS_SRC 220
	234	#define IMX6QDL_PLL6_BYPASS_SRC 221
	235	#define IMX6QDL_PLL7_BYPASS_SRC 222
	236	#define IMX6QDL_CLK_PLL1 223
	237	#define IMX6QDL_CLK_PLL2 224
	238	#define IMX6QDL_CLK_PLL3 225
	239	#define IMX6QDL_CLK_PLL4 226
	240	#define IMX6QDL_CLK_PLL5 227
	241	#define IMX6QDL_CLK_PLL6 228
	242	#define IMX6QDL_CLK_PLL7 229
	243	#define IMX6QDL_PLL1_BYPASS 230
	244	#define IMX6QDL_PLL2_BYPASS 231
	245	#define IMX6QDL_PLL3_BYPASS 232
	246	#define IMX6QDL_PLL4_BYPASS 233
	247	#define IMX6QDL_PLL5_BYPASS 234
	248	#define IMX6QDL_PLL6_BYPASS 235
	249	#define IMX6QDL_PLL7_BYPASS 236
6f11c69d AH	250	#define IMX6QDL_CLK_GPT_3M 237
6f11c69d AH	251	#define IMX6QDL_CLK_END 238
d2d2e54d SG	252
d2d2e54d SG	253	#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */