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6171de8f | 1 | /* |
2edb90ae | 2 | * include/linux/clk/at91_pmc.h |
6171de8f AV |
3 | * |
4 | * Copyright (C) 2005 Ivan Kokshaysky | |
5 | * Copyright (C) SAN People | |
6 | * | |
7 | * Power Management Controller (PMC) - System peripherals registers. | |
8 | * Based on AT91RM9200 datasheet revision E. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | */ | |
15 | ||
16 | #ifndef AT91_PMC_H | |
17 | #define AT91_PMC_H | |
18 | ||
b5514952 JCPV |
19 | #define AT91_PMC_SCER 0x00 /* System Clock Enable Register */ |
20 | #define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */ | |
21 | ||
22 | #define AT91_PMC_SCSR 0x08 /* System Clock Status Register */ | |
6171de8f AV |
23 | #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ |
24 | #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ | |
25 | #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ | |
26 | #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ | |
27 | #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ | |
28 | #define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ | |
29 | #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ | |
30 | #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ | |
31 | #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ | |
32 | #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ | |
5e38efae | 33 | #define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */ |
6171de8f AV |
34 | #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ |
35 | #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ | |
36 | ||
b5514952 JCPV |
37 | #define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */ |
38 | #define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ | |
39 | #define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */ | |
6171de8f | 40 | |
b5514952 | 41 | #define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */ |
53d71680 SP |
42 | #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ |
43 | #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ | |
44 | #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ | |
6d0485a9 | 45 | #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ |
9ebbec27 | 46 | |
b5514952 | 47 | #define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */ |
cbd5c78e NF |
48 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ |
49 | #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */ | |
50 | #define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */ | |
51 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ | |
52 | #define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */ | |
53 | #define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */ | |
54 | #define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */ | |
6171de8f | 55 | |
b5514952 | 56 | #define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */ |
6171de8f AV |
57 | #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ |
58 | #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ | |
59 | ||
b5514952 JCPV |
60 | #define AT91_CKGR_PLLAR 0x28 /* PLL A Register */ |
61 | #define AT91_CKGR_PLLBR 0x2c /* PLL B Register */ | |
6171de8f AV |
62 | #define AT91_PMC_DIV (0xff << 0) /* Divider */ |
63 | #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ | |
64 | #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ | |
65 | #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ | |
8f4b4794 LD |
66 | #define AT91_PMC_MUL_GET(n) ((n) >> 16 & 0x7ff) |
67 | #define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */ | |
68 | #define AT91_PMC3_MUL_GET(n) ((n) >> 18 & 0x7f) | |
2b3b3516 AV |
69 | #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ |
70 | #define AT91_PMC_USBDIV_1 (0 << 28) | |
71 | #define AT91_PMC_USBDIV_2 (1 << 28) | |
72 | #define AT91_PMC_USBDIV_4 (2 << 28) | |
6171de8f AV |
73 | #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ |
74 | ||
b5514952 | 75 | #define AT91_PMC_MCKR 0x30 /* Master Clock Register */ |
6171de8f AV |
76 | #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ |
77 | #define AT91_PMC_CSS_SLOW (0 << 0) | |
78 | #define AT91_PMC_CSS_MAIN (1 << 0) | |
79 | #define AT91_PMC_CSS_PLLA (2 << 0) | |
80 | #define AT91_PMC_CSS_PLLB (3 << 0) | |
6d0485a9 | 81 | #define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ |
cbd5c78e NF |
82 | #define PMC_PRES_OFFSET 2 |
83 | #define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */ | |
84 | #define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET) | |
85 | #define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET) | |
86 | #define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET) | |
87 | #define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET) | |
88 | #define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET) | |
89 | #define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET) | |
90 | #define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET) | |
91 | #define PMC_ALT_PRES_OFFSET 4 | |
92 | #define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */ | |
93 | #define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET) | |
94 | #define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET) | |
95 | #define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET) | |
96 | #define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET) | |
97 | #define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET) | |
98 | #define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET) | |
99 | #define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET) | |
6171de8f | 100 | #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ |
32b1216d AV |
101 | #define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ |
102 | #define AT91RM9200_PMC_MDIV_2 (1 << 8) | |
103 | #define AT91RM9200_PMC_MDIV_3 (2 << 8) | |
104 | #define AT91RM9200_PMC_MDIV_4 (3 << 8) | |
9918ceaf | 105 | #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */ |
32b1216d AV |
106 | #define AT91SAM9_PMC_MDIV_2 (1 << 8) |
107 | #define AT91SAM9_PMC_MDIV_4 (2 << 8) | |
6d0485a9 NF |
108 | #define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ |
109 | #define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ | |
32b1216d AV |
110 | #define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ |
111 | #define AT91_PMC_PDIV_1 (0 << 12) | |
112 | #define AT91_PMC_PDIV_2 (1 << 12) | |
6d0485a9 NF |
113 | #define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ |
114 | #define AT91_PMC_PLLADIV2_OFF (0 << 12) | |
115 | #define AT91_PMC_PLLADIV2_ON (1 << 12) | |
bcc5fd49 | 116 | #define AT91_PMC_H32MXDIV BIT(24) |
6171de8f | 117 | |
b5514952 | 118 | #define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */ |
6d0485a9 NF |
119 | #define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ |
120 | #define AT91_PMC_USBS_PLLA (0 << 0) | |
121 | #define AT91_PMC_USBS_UPLL (1 << 0) | |
d04e5b69 | 122 | #define AT91_PMC_USBS_PLLB (1 << 0) /* [AT91SAMN12 only] */ |
6d0485a9 | 123 | #define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ |
d04e5b69 NF |
124 | #define AT91_PMC_OHCIUSBDIV_1 (0x0 << 8) |
125 | #define AT91_PMC_OHCIUSBDIV_2 (0x1 << 8) | |
6d0485a9 | 126 | |
b5514952 | 127 | #define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */ |
cbd5c78e NF |
128 | #define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */ |
129 | #define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */ | |
130 | #define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV) | |
131 | ||
b5514952 | 132 | #define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ |
cbd5c78e NF |
133 | #define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */ |
134 | #define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */ | |
6d0485a9 NF |
135 | #define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ |
136 | #define AT91_PMC_CSSMCK_CSS (0 << 8) | |
137 | #define AT91_PMC_CSSMCK_MCK (1 << 8) | |
6171de8f | 138 | |
b5514952 JCPV |
139 | #define AT91_PMC_IER 0x60 /* Interrupt Enable Register */ |
140 | #define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */ | |
141 | #define AT91_PMC_SR 0x68 /* Status Register */ | |
6171de8f AV |
142 | #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ |
143 | #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ | |
144 | #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ | |
145 | #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ | |
9918ceaf | 146 | #define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */ |
80eded6c | 147 | #define AT91_PMC_OSCSEL (1 << 7) /* Slow Oscillator Selection [some SAM9] */ |
6171de8f AV |
148 | #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ |
149 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ | |
150 | #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ | |
151 | #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ | |
cbd5c78e NF |
152 | #define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */ |
153 | #define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */ | |
154 | #define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ | |
a5752e57 | 155 | #define AT91_PMC_GCKRDY (1 << 24) /* Generated Clocks */ |
b5514952 | 156 | #define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ |
6171de8f | 157 | |
1a748d2b BB |
158 | #define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */ |
159 | ||
b5514952 | 160 | #define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ |
cbd5c78e NF |
161 | #define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */ |
162 | #define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */ | |
163 | #define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */ | |
164 | ||
b5514952 | 165 | #define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */ |
cbd5c78e NF |
166 | #define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ |
167 | #define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ | |
7be90a6b | 168 | |
8f4b4794 LD |
169 | #define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/ |
170 | #define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */ | |
171 | #define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */ | |
172 | ||
173 | #define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */ | |
96ef36e9 | 174 | #define AT91_PMC_PCR_PID_MASK 0x3f |
df70aeef NF |
175 | #define AT91_PMC_PCR_GCKCSS_OFFSET 8 |
176 | #define AT91_PMC_PCR_GCKCSS_MASK (0x7 << AT91_PMC_PCR_GCKCSS_OFFSET) | |
177 | #define AT91_PMC_PCR_GCKCSS(n) ((n) << AT91_PMC_PCR_GCKCSS_OFFSET) /* GCK Clock Source Selection */ | |
96ef36e9 NF |
178 | #define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ |
179 | #define AT91_PMC_PCR_DIV_OFFSET 16 | |
180 | #define AT91_PMC_PCR_DIV_MASK (0x3 << AT91_PMC_PCR_DIV_OFFSET) | |
181 | #define AT91_PMC_PCR_DIV(n) ((n) << AT91_PMC_PCR_DIV_OFFSET) /* Divisor Value */ | |
df70aeef NF |
182 | #define AT91_PMC_PCR_GCKDIV_OFFSET 20 |
183 | #define AT91_PMC_PCR_GCKDIV_MASK (0xff << AT91_PMC_PCR_GCKDIV_OFFSET) | |
184 | #define AT91_PMC_PCR_GCKDIV(n) ((n) << AT91_PMC_PCR_GCKDIV_OFFSET) /* Generated Clock Divisor Value */ | |
96ef36e9 | 185 | #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ |
df70aeef | 186 | #define AT91_PMC_PCR_GCKEN (0x1 << 29) /* GCK Enable */ |
7be90a6b | 187 | |
6171de8f | 188 | #endif |