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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX4_DEVICE_H | |
34 | #define MLX4_DEVICE_H | |
35 | ||
574e2af7 | 36 | #include <linux/if_ether.h> |
225c7b1f RD |
37 | #include <linux/pci.h> |
38 | #include <linux/completion.h> | |
39 | #include <linux/radix-tree.h> | |
d9236c3f | 40 | #include <linux/cpu_rmap.h> |
225c7b1f | 41 | |
60063497 | 42 | #include <linux/atomic.h> |
225c7b1f | 43 | |
ec693d47 AV |
44 | #include <linux/clocksource.h> |
45 | ||
0b7ca5a9 YP |
46 | #define MAX_MSIX_P_PORT 17 |
47 | #define MAX_MSIX 64 | |
48 | #define MSIX_LEGACY_SZ 4 | |
49 | #define MIN_MSIX_P_PORT 5 | |
50 | ||
6ee51a4e | 51 | #define MLX4_ROCE_MAX_GIDS 128 |
b6ffaeff | 52 | #define MLX4_ROCE_PF_GIDS 16 |
6ee51a4e | 53 | |
225c7b1f RD |
54 | enum { |
55 | MLX4_FLAG_MSI_X = 1 << 0, | |
5ae2a7a8 | 56 | MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, |
623ed84b JM |
57 | MLX4_FLAG_MASTER = 1 << 2, |
58 | MLX4_FLAG_SLAVE = 1 << 3, | |
59 | MLX4_FLAG_SRIOV = 1 << 4, | |
acddd5dd | 60 | MLX4_FLAG_OLD_REG_MAC = 1 << 6, |
225c7b1f RD |
61 | }; |
62 | ||
efcd235d JM |
63 | enum { |
64 | MLX4_PORT_CAP_IS_SM = 1 << 1, | |
65 | MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, | |
66 | }; | |
67 | ||
225c7b1f | 68 | enum { |
fc06573d JM |
69 | MLX4_MAX_PORTS = 2, |
70 | MLX4_MAX_PORT_PKEYS = 128 | |
225c7b1f RD |
71 | }; |
72 | ||
396f2feb JM |
73 | /* base qkey for use in sriov tunnel-qp/proxy-qp communication. |
74 | * These qkeys must not be allowed for general use. This is a 64k range, | |
75 | * and to test for violation, we use the mask (protect against future chg). | |
76 | */ | |
77 | #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) | |
78 | #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) | |
79 | ||
cd9281d8 JM |
80 | enum { |
81 | MLX4_BOARD_ID_LEN = 64 | |
82 | }; | |
83 | ||
623ed84b JM |
84 | enum { |
85 | MLX4_MAX_NUM_PF = 16, | |
86 | MLX4_MAX_NUM_VF = 64, | |
1ab95d37 | 87 | MLX4_MAX_NUM_VF_P_PORT = 64, |
623ed84b | 88 | MLX4_MFUNC_MAX = 80, |
3fc929e2 | 89 | MLX4_MAX_EQ_NUM = 1024, |
623ed84b JM |
90 | MLX4_MFUNC_EQ_NUM = 4, |
91 | MLX4_MFUNC_MAX_EQES = 8, | |
92 | MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) | |
93 | }; | |
94 | ||
0ff1fb65 HHZ |
95 | /* Driver supports 3 diffrent device methods to manage traffic steering: |
96 | * -device managed - High level API for ib and eth flow steering. FW is | |
97 | * managing flow steering tables. | |
c96d97f4 HHZ |
98 | * - B0 steering mode - Common low level API for ib and (if supported) eth. |
99 | * - A0 steering mode - Limited low level API for eth. In case of IB, | |
100 | * B0 mode is in use. | |
101 | */ | |
102 | enum { | |
103 | MLX4_STEERING_MODE_A0, | |
0ff1fb65 HHZ |
104 | MLX4_STEERING_MODE_B0, |
105 | MLX4_STEERING_MODE_DEVICE_MANAGED | |
c96d97f4 HHZ |
106 | }; |
107 | ||
108 | static inline const char *mlx4_steering_mode_str(int steering_mode) | |
109 | { | |
110 | switch (steering_mode) { | |
111 | case MLX4_STEERING_MODE_A0: | |
112 | return "A0 steering"; | |
113 | ||
114 | case MLX4_STEERING_MODE_B0: | |
115 | return "B0 steering"; | |
0ff1fb65 HHZ |
116 | |
117 | case MLX4_STEERING_MODE_DEVICE_MANAGED: | |
118 | return "Device managed flow steering"; | |
119 | ||
c96d97f4 HHZ |
120 | default: |
121 | return "Unrecognize steering mode"; | |
122 | } | |
123 | } | |
124 | ||
7ffdf726 OG |
125 | enum { |
126 | MLX4_TUNNEL_OFFLOAD_MODE_NONE, | |
127 | MLX4_TUNNEL_OFFLOAD_MODE_VXLAN | |
128 | }; | |
129 | ||
225c7b1f | 130 | enum { |
52eafc68 OG |
131 | MLX4_DEV_CAP_FLAG_RC = 1LL << 0, |
132 | MLX4_DEV_CAP_FLAG_UC = 1LL << 1, | |
133 | MLX4_DEV_CAP_FLAG_UD = 1LL << 2, | |
012a8ff5 | 134 | MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, |
52eafc68 OG |
135 | MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, |
136 | MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, | |
137 | MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, | |
138 | MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, | |
139 | MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, | |
140 | MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, | |
141 | MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, | |
142 | MLX4_DEV_CAP_FLAG_APM = 1LL << 17, | |
143 | MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, | |
144 | MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, | |
145 | MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, | |
146 | MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, | |
ccf86321 OG |
147 | MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, |
148 | MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, | |
f3a9d1f2 | 149 | MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, |
559a9f1d OD |
150 | MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, |
151 | MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, | |
ccf86321 OG |
152 | MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, |
153 | MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, | |
f2a3f6a3 | 154 | MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, |
58a60168 | 155 | MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, |
540b3a39 | 156 | MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, |
00f5ce99 JM |
157 | MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, |
158 | MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, | |
08ff3235 OG |
159 | MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, |
160 | MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 | |
225c7b1f RD |
161 | }; |
162 | ||
b3416f44 SP |
163 | enum { |
164 | MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, | |
165 | MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, | |
0ff1fb65 | 166 | MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, |
955154fa | 167 | MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, |
5930e8d0 | 168 | MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4, |
3f7fb021 | 169 | MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, |
e6b6a231 | 170 | MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, |
b01978ca | 171 | MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, |
4de65803 | 172 | MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8, |
4ba9920e LT |
173 | MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9, |
174 | MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, | |
b3416f44 SP |
175 | }; |
176 | ||
08ff3235 OG |
177 | enum { |
178 | MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, | |
179 | MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1 | |
180 | }; | |
181 | ||
182 | enum { | |
183 | MLX4_USER_DEV_CAP_64B_CQE = 1L << 0 | |
184 | }; | |
185 | ||
186 | enum { | |
187 | MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0 | |
188 | }; | |
189 | ||
190 | ||
97285b78 MA |
191 | #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) |
192 | ||
95d04f07 | 193 | enum { |
804d6a89 | 194 | MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, |
95d04f07 RD |
195 | MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, |
196 | MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, | |
197 | MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, | |
198 | MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, | |
199 | MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, | |
200 | }; | |
201 | ||
225c7b1f RD |
202 | enum mlx4_event { |
203 | MLX4_EVENT_TYPE_COMP = 0x00, | |
204 | MLX4_EVENT_TYPE_PATH_MIG = 0x01, | |
205 | MLX4_EVENT_TYPE_COMM_EST = 0x02, | |
206 | MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, | |
207 | MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, | |
208 | MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, | |
209 | MLX4_EVENT_TYPE_CQ_ERROR = 0x04, | |
210 | MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
211 | MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, | |
212 | MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, | |
213 | MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, | |
214 | MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, | |
215 | MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, | |
216 | MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, | |
217 | MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, | |
218 | MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, | |
219 | MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, | |
623ed84b JM |
220 | MLX4_EVENT_TYPE_CMD = 0x0a, |
221 | MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, | |
222 | MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, | |
fe6f700d | 223 | MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, |
5984be90 | 224 | MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, |
623ed84b | 225 | MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, |
00f5ce99 | 226 | MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, |
623ed84b | 227 | MLX4_EVENT_TYPE_NONE = 0xff, |
225c7b1f RD |
228 | }; |
229 | ||
230 | enum { | |
231 | MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, | |
232 | MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 | |
233 | }; | |
234 | ||
5984be90 JM |
235 | enum { |
236 | MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, | |
237 | }; | |
238 | ||
993c401e JM |
239 | enum slave_port_state { |
240 | SLAVE_PORT_DOWN = 0, | |
241 | SLAVE_PENDING_UP, | |
242 | SLAVE_PORT_UP, | |
243 | }; | |
244 | ||
245 | enum slave_port_gen_event { | |
246 | SLAVE_PORT_GEN_EVENT_DOWN = 0, | |
247 | SLAVE_PORT_GEN_EVENT_UP, | |
248 | SLAVE_PORT_GEN_EVENT_NONE, | |
249 | }; | |
250 | ||
251 | enum slave_port_state_event { | |
252 | MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, | |
253 | MLX4_PORT_STATE_DEV_EVENT_PORT_UP, | |
254 | MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, | |
255 | MLX4_PORT_STATE_IB_EVENT_GID_INVALID, | |
256 | }; | |
257 | ||
225c7b1f RD |
258 | enum { |
259 | MLX4_PERM_LOCAL_READ = 1 << 10, | |
260 | MLX4_PERM_LOCAL_WRITE = 1 << 11, | |
261 | MLX4_PERM_REMOTE_READ = 1 << 12, | |
262 | MLX4_PERM_REMOTE_WRITE = 1 << 13, | |
804d6a89 SM |
263 | MLX4_PERM_ATOMIC = 1 << 14, |
264 | MLX4_PERM_BIND_MW = 1 << 15, | |
225c7b1f RD |
265 | }; |
266 | ||
267 | enum { | |
268 | MLX4_OPCODE_NOP = 0x00, | |
269 | MLX4_OPCODE_SEND_INVAL = 0x01, | |
270 | MLX4_OPCODE_RDMA_WRITE = 0x08, | |
271 | MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, | |
272 | MLX4_OPCODE_SEND = 0x0a, | |
273 | MLX4_OPCODE_SEND_IMM = 0x0b, | |
274 | MLX4_OPCODE_LSO = 0x0e, | |
275 | MLX4_OPCODE_RDMA_READ = 0x10, | |
276 | MLX4_OPCODE_ATOMIC_CS = 0x11, | |
277 | MLX4_OPCODE_ATOMIC_FA = 0x12, | |
6fa8f719 VS |
278 | MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, |
279 | MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, | |
225c7b1f RD |
280 | MLX4_OPCODE_BIND_MW = 0x18, |
281 | MLX4_OPCODE_FMR = 0x19, | |
282 | MLX4_OPCODE_LOCAL_INVAL = 0x1b, | |
283 | MLX4_OPCODE_CONFIG_CMD = 0x1f, | |
284 | ||
285 | MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, | |
286 | MLX4_RECV_OPCODE_SEND = 0x01, | |
287 | MLX4_RECV_OPCODE_SEND_IMM = 0x02, | |
288 | MLX4_RECV_OPCODE_SEND_INVAL = 0x03, | |
289 | ||
290 | MLX4_CQE_OPCODE_ERROR = 0x1e, | |
291 | MLX4_CQE_OPCODE_RESIZE = 0x16, | |
292 | }; | |
293 | ||
294 | enum { | |
295 | MLX4_STAT_RATE_OFFSET = 5 | |
296 | }; | |
297 | ||
da995a8a | 298 | enum mlx4_protocol { |
0345584e YP |
299 | MLX4_PROT_IB_IPV6 = 0, |
300 | MLX4_PROT_ETH, | |
301 | MLX4_PROT_IB_IPV4, | |
302 | MLX4_PROT_FCOE | |
da995a8a AS |
303 | }; |
304 | ||
29bdc883 VS |
305 | enum { |
306 | MLX4_MTT_FLAG_PRESENT = 1 | |
307 | }; | |
308 | ||
93fc9e1b YP |
309 | enum mlx4_qp_region { |
310 | MLX4_QP_REGION_FW = 0, | |
311 | MLX4_QP_REGION_ETH_ADDR, | |
312 | MLX4_QP_REGION_FC_ADDR, | |
313 | MLX4_QP_REGION_FC_EXCH, | |
314 | MLX4_NUM_QP_REGION | |
315 | }; | |
316 | ||
7ff93f8b | 317 | enum mlx4_port_type { |
623ed84b | 318 | MLX4_PORT_TYPE_NONE = 0, |
27bf91d6 YP |
319 | MLX4_PORT_TYPE_IB = 1, |
320 | MLX4_PORT_TYPE_ETH = 2, | |
321 | MLX4_PORT_TYPE_AUTO = 3 | |
7ff93f8b YP |
322 | }; |
323 | ||
2a2336f8 YP |
324 | enum mlx4_special_vlan_idx { |
325 | MLX4_NO_VLAN_IDX = 0, | |
326 | MLX4_VLAN_MISS_IDX, | |
327 | MLX4_VLAN_REGULAR | |
328 | }; | |
329 | ||
0345584e YP |
330 | enum mlx4_steer_type { |
331 | MLX4_MC_STEER = 0, | |
332 | MLX4_UC_STEER, | |
333 | MLX4_NUM_STEERS | |
334 | }; | |
335 | ||
93fc9e1b YP |
336 | enum { |
337 | MLX4_NUM_FEXCH = 64 * 1024, | |
338 | }; | |
339 | ||
5a0fd094 EC |
340 | enum { |
341 | MLX4_MAX_FAST_REG_PAGES = 511, | |
342 | }; | |
343 | ||
00f5ce99 JM |
344 | enum { |
345 | MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, | |
346 | MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, | |
347 | MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, | |
348 | }; | |
349 | ||
350 | /* Port mgmt change event handling */ | |
351 | enum { | |
352 | MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, | |
353 | MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, | |
354 | MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, | |
355 | MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, | |
356 | MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, | |
357 | }; | |
358 | ||
359 | #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ | |
360 | MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) | |
361 | ||
ea54b10c JM |
362 | static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) |
363 | { | |
364 | return (major << 32) | (minor << 16) | subminor; | |
365 | } | |
366 | ||
3fc929e2 | 367 | struct mlx4_phys_caps { |
6634961c JM |
368 | u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; |
369 | u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; | |
3fc929e2 | 370 | u32 num_phys_eqs; |
47605df9 JM |
371 | u32 base_sqpn; |
372 | u32 base_proxy_sqpn; | |
373 | u32 base_tunnel_sqpn; | |
3fc929e2 MA |
374 | }; |
375 | ||
225c7b1f RD |
376 | struct mlx4_caps { |
377 | u64 fw_ver; | |
623ed84b | 378 | u32 function; |
225c7b1f | 379 | int num_ports; |
5ae2a7a8 | 380 | int vl_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 | 381 | int ib_mtu_cap[MLX4_MAX_PORTS + 1]; |
9a5aa622 | 382 | __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 YP |
383 | u64 def_mac[MLX4_MAX_PORTS + 1]; |
384 | int eth_mtu_cap[MLX4_MAX_PORTS + 1]; | |
5ae2a7a8 RD |
385 | int gid_table_len[MLX4_MAX_PORTS + 1]; |
386 | int pkey_table_len[MLX4_MAX_PORTS + 1]; | |
7699517d YP |
387 | int trans_type[MLX4_MAX_PORTS + 1]; |
388 | int vendor_oui[MLX4_MAX_PORTS + 1]; | |
389 | int wavelength[MLX4_MAX_PORTS + 1]; | |
390 | u64 trans_code[MLX4_MAX_PORTS + 1]; | |
225c7b1f RD |
391 | int local_ca_ack_delay; |
392 | int num_uars; | |
f5311ac1 | 393 | u32 uar_page_size; |
225c7b1f RD |
394 | int bf_reg_size; |
395 | int bf_regs_per_page; | |
396 | int max_sq_sg; | |
397 | int max_rq_sg; | |
398 | int num_qps; | |
399 | int max_wqes; | |
400 | int max_sq_desc_sz; | |
401 | int max_rq_desc_sz; | |
402 | int max_qp_init_rdma; | |
403 | int max_qp_dest_rdma; | |
99ec41d0 | 404 | u32 *qp0_qkey; |
47605df9 JM |
405 | u32 *qp0_proxy; |
406 | u32 *qp1_proxy; | |
407 | u32 *qp0_tunnel; | |
408 | u32 *qp1_tunnel; | |
225c7b1f RD |
409 | int num_srqs; |
410 | int max_srq_wqes; | |
411 | int max_srq_sge; | |
412 | int reserved_srqs; | |
413 | int num_cqs; | |
414 | int max_cqes; | |
415 | int reserved_cqs; | |
416 | int num_eqs; | |
417 | int reserved_eqs; | |
b8dd786f | 418 | int num_comp_vectors; |
0b7ca5a9 | 419 | int comp_pool; |
225c7b1f | 420 | int num_mpts; |
a5bbe892 | 421 | int max_fmr_maps; |
2b8fb286 | 422 | int num_mtts; |
225c7b1f RD |
423 | int fmr_reserved_mtts; |
424 | int reserved_mtts; | |
425 | int reserved_mrws; | |
426 | int reserved_uars; | |
427 | int num_mgms; | |
428 | int num_amgms; | |
429 | int reserved_mcgs; | |
430 | int num_qp_per_mgm; | |
c96d97f4 | 431 | int steering_mode; |
0ff1fb65 | 432 | int fs_log_max_ucast_qp_range_size; |
225c7b1f RD |
433 | int num_pds; |
434 | int reserved_pds; | |
012a8ff5 SH |
435 | int max_xrcds; |
436 | int reserved_xrcds; | |
225c7b1f | 437 | int mtt_entry_sz; |
149983af | 438 | u32 max_msg_sz; |
225c7b1f | 439 | u32 page_size_cap; |
52eafc68 | 440 | u64 flags; |
b3416f44 | 441 | u64 flags2; |
95d04f07 RD |
442 | u32 bmme_flags; |
443 | u32 reserved_lkey; | |
225c7b1f | 444 | u16 stat_rate_support; |
5ae2a7a8 | 445 | u8 port_width_cap[MLX4_MAX_PORTS + 1]; |
b832be1e | 446 | int max_gso_sz; |
b3416f44 | 447 | int max_rss_tbl_sz; |
93fc9e1b YP |
448 | int reserved_qps_cnt[MLX4_NUM_QP_REGION]; |
449 | int reserved_qps; | |
450 | int reserved_qps_base[MLX4_NUM_QP_REGION]; | |
451 | int log_num_macs; | |
452 | int log_num_vlans; | |
7ff93f8b YP |
453 | enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; |
454 | u8 supported_type[MLX4_MAX_PORTS + 1]; | |
8d0fc7b6 YP |
455 | u8 suggested_type[MLX4_MAX_PORTS + 1]; |
456 | u8 default_sense[MLX4_MAX_PORTS + 1]; | |
65dab25d | 457 | u32 port_mask[MLX4_MAX_PORTS + 1]; |
27bf91d6 | 458 | enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; |
f2a3f6a3 | 459 | u32 max_counters; |
096335b3 | 460 | u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; |
1ffeb2eb | 461 | u16 sqp_demux; |
08ff3235 OG |
462 | u32 eqe_size; |
463 | u32 cqe_size; | |
464 | u8 eqe_factor; | |
465 | u32 userspace_caps; /* userspace must be aware of these */ | |
466 | u32 function_caps; /* VFs must be aware of these */ | |
ddd8a6c1 | 467 | u16 hca_core_clock; |
8e1a28e8 | 468 | u64 phys_port_id[MLX4_MAX_PORTS + 1]; |
7ffdf726 | 469 | int tunnel_offload_mode; |
225c7b1f RD |
470 | }; |
471 | ||
472 | struct mlx4_buf_list { | |
473 | void *buf; | |
474 | dma_addr_t map; | |
475 | }; | |
476 | ||
477 | struct mlx4_buf { | |
b57aacfa RD |
478 | struct mlx4_buf_list direct; |
479 | struct mlx4_buf_list *page_list; | |
225c7b1f RD |
480 | int nbufs; |
481 | int npages; | |
482 | int page_shift; | |
483 | }; | |
484 | ||
485 | struct mlx4_mtt { | |
2b8fb286 | 486 | u32 offset; |
225c7b1f RD |
487 | int order; |
488 | int page_shift; | |
489 | }; | |
490 | ||
6296883c YP |
491 | enum { |
492 | MLX4_DB_PER_PAGE = PAGE_SIZE / 4 | |
493 | }; | |
494 | ||
495 | struct mlx4_db_pgdir { | |
496 | struct list_head list; | |
497 | DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); | |
498 | DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); | |
499 | unsigned long *bits[2]; | |
500 | __be32 *db_page; | |
501 | dma_addr_t db_dma; | |
502 | }; | |
503 | ||
504 | struct mlx4_ib_user_db_page; | |
505 | ||
506 | struct mlx4_db { | |
507 | __be32 *db; | |
508 | union { | |
509 | struct mlx4_db_pgdir *pgdir; | |
510 | struct mlx4_ib_user_db_page *user_page; | |
511 | } u; | |
512 | dma_addr_t dma; | |
513 | int index; | |
514 | int order; | |
515 | }; | |
516 | ||
38ae6a53 YP |
517 | struct mlx4_hwq_resources { |
518 | struct mlx4_db db; | |
519 | struct mlx4_mtt mtt; | |
520 | struct mlx4_buf buf; | |
521 | }; | |
522 | ||
225c7b1f RD |
523 | struct mlx4_mr { |
524 | struct mlx4_mtt mtt; | |
525 | u64 iova; | |
526 | u64 size; | |
527 | u32 key; | |
528 | u32 pd; | |
529 | u32 access; | |
530 | int enabled; | |
531 | }; | |
532 | ||
804d6a89 SM |
533 | enum mlx4_mw_type { |
534 | MLX4_MW_TYPE_1 = 1, | |
535 | MLX4_MW_TYPE_2 = 2, | |
536 | }; | |
537 | ||
538 | struct mlx4_mw { | |
539 | u32 key; | |
540 | u32 pd; | |
541 | enum mlx4_mw_type type; | |
542 | int enabled; | |
543 | }; | |
544 | ||
8ad11fb6 JM |
545 | struct mlx4_fmr { |
546 | struct mlx4_mr mr; | |
547 | struct mlx4_mpt_entry *mpt; | |
548 | __be64 *mtts; | |
549 | dma_addr_t dma_handle; | |
550 | int max_pages; | |
551 | int max_maps; | |
552 | int maps; | |
553 | u8 page_shift; | |
554 | }; | |
555 | ||
225c7b1f RD |
556 | struct mlx4_uar { |
557 | unsigned long pfn; | |
558 | int index; | |
c1b43dca EC |
559 | struct list_head bf_list; |
560 | unsigned free_bf_bmap; | |
561 | void __iomem *map; | |
562 | void __iomem *bf_map; | |
563 | }; | |
564 | ||
565 | struct mlx4_bf { | |
566 | unsigned long offset; | |
567 | int buf_size; | |
568 | struct mlx4_uar *uar; | |
569 | void __iomem *reg; | |
225c7b1f RD |
570 | }; |
571 | ||
572 | struct mlx4_cq { | |
573 | void (*comp) (struct mlx4_cq *); | |
574 | void (*event) (struct mlx4_cq *, enum mlx4_event); | |
575 | ||
576 | struct mlx4_uar *uar; | |
577 | ||
578 | u32 cons_index; | |
579 | ||
2eacc23c YA |
580 | u16 irq; |
581 | bool irq_affinity_change; | |
582 | ||
225c7b1f RD |
583 | __be32 *set_ci_db; |
584 | __be32 *arm_db; | |
585 | int arm_sn; | |
586 | ||
587 | int cqn; | |
b8dd786f | 588 | unsigned vector; |
225c7b1f RD |
589 | |
590 | atomic_t refcount; | |
591 | struct completion free; | |
592 | }; | |
593 | ||
594 | struct mlx4_qp { | |
595 | void (*event) (struct mlx4_qp *, enum mlx4_event); | |
596 | ||
597 | int qpn; | |
598 | ||
599 | atomic_t refcount; | |
600 | struct completion free; | |
601 | }; | |
602 | ||
603 | struct mlx4_srq { | |
604 | void (*event) (struct mlx4_srq *, enum mlx4_event); | |
605 | ||
606 | int srqn; | |
607 | int max; | |
608 | int max_gs; | |
609 | int wqe_shift; | |
610 | ||
611 | atomic_t refcount; | |
612 | struct completion free; | |
613 | }; | |
614 | ||
615 | struct mlx4_av { | |
616 | __be32 port_pd; | |
617 | u8 reserved1; | |
618 | u8 g_slid; | |
619 | __be16 dlid; | |
620 | u8 reserved2; | |
621 | u8 gid_index; | |
622 | u8 stat_rate; | |
623 | u8 hop_limit; | |
624 | __be32 sl_tclass_flowlabel; | |
625 | u8 dgid[16]; | |
626 | }; | |
627 | ||
fa417f7b EC |
628 | struct mlx4_eth_av { |
629 | __be32 port_pd; | |
630 | u8 reserved1; | |
631 | u8 smac_idx; | |
632 | u16 reserved2; | |
633 | u8 reserved3; | |
634 | u8 gid_index; | |
635 | u8 stat_rate; | |
636 | u8 hop_limit; | |
637 | __be32 sl_tclass_flowlabel; | |
638 | u8 dgid[16]; | |
5ea8bbfc JM |
639 | u8 s_mac[6]; |
640 | u8 reserved4[2]; | |
fa417f7b | 641 | __be16 vlan; |
574e2af7 | 642 | u8 mac[ETH_ALEN]; |
fa417f7b EC |
643 | }; |
644 | ||
645 | union mlx4_ext_av { | |
646 | struct mlx4_av ib; | |
647 | struct mlx4_eth_av eth; | |
648 | }; | |
649 | ||
f2a3f6a3 OG |
650 | struct mlx4_counter { |
651 | u8 reserved1[3]; | |
652 | u8 counter_mode; | |
653 | __be32 num_ifc; | |
654 | u32 reserved2[2]; | |
655 | __be64 rx_frames; | |
656 | __be64 rx_bytes; | |
657 | __be64 tx_frames; | |
658 | __be64 tx_bytes; | |
659 | }; | |
660 | ||
5a0d0a61 JM |
661 | struct mlx4_quotas { |
662 | int qp; | |
663 | int cq; | |
664 | int srq; | |
665 | int mpt; | |
666 | int mtt; | |
667 | int counter; | |
668 | int xrcd; | |
669 | }; | |
670 | ||
1ab95d37 MB |
671 | struct mlx4_vf_dev { |
672 | u8 min_port; | |
673 | u8 n_ports; | |
674 | }; | |
675 | ||
225c7b1f RD |
676 | struct mlx4_dev { |
677 | struct pci_dev *pdev; | |
678 | unsigned long flags; | |
623ed84b | 679 | unsigned long num_slaves; |
225c7b1f | 680 | struct mlx4_caps caps; |
3fc929e2 | 681 | struct mlx4_phys_caps phys_caps; |
5a0d0a61 | 682 | struct mlx4_quotas quotas; |
225c7b1f | 683 | struct radix_tree_root qp_table_tree; |
725c8999 | 684 | u8 rev_id; |
cd9281d8 | 685 | char board_id[MLX4_BOARD_ID_LEN]; |
ab9c17a0 | 686 | int num_vfs; |
6e7136ed | 687 | int numa_node; |
3c439b55 | 688 | int oper_log_mgm_entry_size; |
592e49dd HHZ |
689 | u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; |
690 | u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; | |
1ab95d37 | 691 | struct mlx4_vf_dev *dev_vfs; |
225c7b1f RD |
692 | }; |
693 | ||
00f5ce99 JM |
694 | struct mlx4_eqe { |
695 | u8 reserved1; | |
696 | u8 type; | |
697 | u8 reserved2; | |
698 | u8 subtype; | |
699 | union { | |
700 | u32 raw[6]; | |
701 | struct { | |
702 | __be32 cqn; | |
703 | } __packed comp; | |
704 | struct { | |
705 | u16 reserved1; | |
706 | __be16 token; | |
707 | u32 reserved2; | |
708 | u8 reserved3[3]; | |
709 | u8 status; | |
710 | __be64 out_param; | |
711 | } __packed cmd; | |
712 | struct { | |
713 | __be32 qpn; | |
714 | } __packed qp; | |
715 | struct { | |
716 | __be32 srqn; | |
717 | } __packed srq; | |
718 | struct { | |
719 | __be32 cqn; | |
720 | u32 reserved1; | |
721 | u8 reserved2[3]; | |
722 | u8 syndrome; | |
723 | } __packed cq_err; | |
724 | struct { | |
725 | u32 reserved1[2]; | |
726 | __be32 port; | |
727 | } __packed port_change; | |
728 | struct { | |
729 | #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 | |
730 | u32 reserved; | |
731 | u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; | |
732 | } __packed comm_channel_arm; | |
733 | struct { | |
734 | u8 port; | |
735 | u8 reserved[3]; | |
736 | __be64 mac; | |
737 | } __packed mac_update; | |
738 | struct { | |
739 | __be32 slave_id; | |
740 | } __packed flr_event; | |
741 | struct { | |
742 | __be16 current_temperature; | |
743 | __be16 warning_threshold; | |
744 | } __packed warming; | |
745 | struct { | |
746 | u8 reserved[3]; | |
747 | u8 port; | |
748 | union { | |
749 | struct { | |
750 | __be16 mstr_sm_lid; | |
751 | __be16 port_lid; | |
752 | __be32 changed_attr; | |
753 | u8 reserved[3]; | |
754 | u8 mstr_sm_sl; | |
755 | __be64 gid_prefix; | |
756 | } __packed port_info; | |
757 | struct { | |
758 | __be32 block_ptr; | |
759 | __be32 tbl_entries_mask; | |
760 | } __packed tbl_change_info; | |
761 | } params; | |
762 | } __packed port_mgmt_change; | |
763 | } event; | |
764 | u8 slave_id; | |
765 | u8 reserved3[2]; | |
766 | u8 owner; | |
767 | } __packed; | |
768 | ||
225c7b1f RD |
769 | struct mlx4_init_port_param { |
770 | int set_guid0; | |
771 | int set_node_guid; | |
772 | int set_si_guid; | |
773 | u16 mtu; | |
774 | int port_width_cap; | |
775 | u16 vl_cap; | |
776 | u16 max_gid; | |
777 | u16 max_pkey; | |
778 | u64 guid0; | |
779 | u64 node_guid; | |
780 | u64 si_guid; | |
781 | }; | |
782 | ||
7ff93f8b YP |
783 | #define mlx4_foreach_port(port, dev, type) \ |
784 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
65dab25d | 785 | if ((type) == (dev)->caps.port_mask[(port)]) |
7ff93f8b | 786 | |
026149cb JM |
787 | #define mlx4_foreach_non_ib_transport_port(port, dev) \ |
788 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
789 | if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB)) | |
790 | ||
65dab25d JM |
791 | #define mlx4_foreach_ib_transport_port(port, dev) \ |
792 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
793 | if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ | |
794 | ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) | |
623ed84b | 795 | |
752a50ca JM |
796 | #define MLX4_INVALID_SLAVE_ID 0xFF |
797 | ||
00f5ce99 JM |
798 | void handle_port_mgmt_change_event(struct work_struct *work); |
799 | ||
2aca1172 JM |
800 | static inline int mlx4_master_func_num(struct mlx4_dev *dev) |
801 | { | |
802 | return dev->caps.function; | |
803 | } | |
804 | ||
623ed84b JM |
805 | static inline int mlx4_is_master(struct mlx4_dev *dev) |
806 | { | |
807 | return dev->flags & MLX4_FLAG_MASTER; | |
808 | } | |
809 | ||
5a0d0a61 JM |
810 | static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) |
811 | { | |
812 | return dev->phys_caps.base_sqpn + 8 + | |
813 | 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); | |
814 | } | |
815 | ||
623ed84b JM |
816 | static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) |
817 | { | |
47605df9 | 818 | return (qpn < dev->phys_caps.base_sqpn + 8 + |
e2c76824 JM |
819 | 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev)); |
820 | } | |
821 | ||
822 | static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) | |
823 | { | |
47605df9 | 824 | int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; |
e2c76824 | 825 | |
47605df9 | 826 | if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) |
e2c76824 JM |
827 | return 1; |
828 | ||
829 | return 0; | |
623ed84b | 830 | } |
fa417f7b | 831 | |
623ed84b JM |
832 | static inline int mlx4_is_mfunc(struct mlx4_dev *dev) |
833 | { | |
834 | return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); | |
835 | } | |
836 | ||
837 | static inline int mlx4_is_slave(struct mlx4_dev *dev) | |
838 | { | |
839 | return dev->flags & MLX4_FLAG_SLAVE; | |
840 | } | |
fa417f7b | 841 | |
225c7b1f | 842 | int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, |
40f2287b | 843 | struct mlx4_buf *buf, gfp_t gfp); |
225c7b1f | 844 | void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); |
1c69fc2a RD |
845 | static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) |
846 | { | |
313abe55 | 847 | if (BITS_PER_LONG == 64 || buf->nbufs == 1) |
b57aacfa | 848 | return buf->direct.buf + offset; |
1c69fc2a | 849 | else |
b57aacfa | 850 | return buf->page_list[offset >> PAGE_SHIFT].buf + |
1c69fc2a RD |
851 | (offset & (PAGE_SIZE - 1)); |
852 | } | |
225c7b1f RD |
853 | |
854 | int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); | |
855 | void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); | |
012a8ff5 SH |
856 | int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); |
857 | void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); | |
225c7b1f RD |
858 | |
859 | int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
860 | void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
163561a4 | 861 | int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); |
c1b43dca | 862 | void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); |
225c7b1f RD |
863 | |
864 | int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, | |
865 | struct mlx4_mtt *mtt); | |
866 | void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
867 | u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
868 | ||
869 | int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, | |
870 | int npages, int page_shift, struct mlx4_mr *mr); | |
61083720 | 871 | int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); |
225c7b1f | 872 | int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); |
804d6a89 SM |
873 | int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, |
874 | struct mlx4_mw *mw); | |
875 | void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); | |
876 | int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); | |
225c7b1f RD |
877 | int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
878 | int start_index, int npages, u64 *page_list); | |
879 | int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
40f2287b | 880 | struct mlx4_buf *buf, gfp_t gfp); |
225c7b1f | 881 | |
40f2287b JK |
882 | int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order, |
883 | gfp_t gfp); | |
6296883c YP |
884 | void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); |
885 | ||
38ae6a53 YP |
886 | int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, |
887 | int size, int max_direct); | |
888 | void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, | |
889 | int size); | |
890 | ||
225c7b1f | 891 | int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, |
e463c7b1 | 892 | struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, |
ec693d47 | 893 | unsigned vector, int collapsed, int timestamp_en); |
225c7b1f RD |
894 | void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); |
895 | ||
a3cdcbfa YP |
896 | int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base); |
897 | void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); | |
898 | ||
40f2287b JK |
899 | int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp, |
900 | gfp_t gfp); | |
225c7b1f RD |
901 | void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); |
902 | ||
18abd5ea SH |
903 | int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, |
904 | struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); | |
225c7b1f RD |
905 | void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); |
906 | int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); | |
65541cb7 | 907 | int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); |
225c7b1f | 908 | |
5ae2a7a8 | 909 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); |
225c7b1f RD |
910 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); |
911 | ||
ffe455ad EE |
912 | int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
913 | int block_mcast_loopback, enum mlx4_protocol prot); | |
914 | int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | |
915 | enum mlx4_protocol prot); | |
521e575b | 916 | int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
0ff1fb65 HHZ |
917 | u8 port, int block_mcast_loopback, |
918 | enum mlx4_protocol protocol, u64 *reg_id); | |
da995a8a | 919 | int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
0ff1fb65 HHZ |
920 | enum mlx4_protocol protocol, u64 reg_id); |
921 | ||
922 | enum { | |
923 | MLX4_DOMAIN_UVERBS = 0x1000, | |
924 | MLX4_DOMAIN_ETHTOOL = 0x2000, | |
925 | MLX4_DOMAIN_RFS = 0x3000, | |
926 | MLX4_DOMAIN_NIC = 0x5000, | |
927 | }; | |
928 | ||
929 | enum mlx4_net_trans_rule_id { | |
930 | MLX4_NET_TRANS_RULE_ID_ETH = 0, | |
931 | MLX4_NET_TRANS_RULE_ID_IB, | |
932 | MLX4_NET_TRANS_RULE_ID_IPV6, | |
933 | MLX4_NET_TRANS_RULE_ID_IPV4, | |
934 | MLX4_NET_TRANS_RULE_ID_TCP, | |
935 | MLX4_NET_TRANS_RULE_ID_UDP, | |
7ffdf726 | 936 | MLX4_NET_TRANS_RULE_ID_VXLAN, |
0ff1fb65 HHZ |
937 | MLX4_NET_TRANS_RULE_NUM, /* should be last */ |
938 | }; | |
939 | ||
a8edc3bf HHZ |
940 | extern const u16 __sw_id_hw[]; |
941 | ||
7fb40f87 HHZ |
942 | static inline int map_hw_to_sw_id(u16 header_id) |
943 | { | |
944 | ||
945 | int i; | |
946 | for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { | |
947 | if (header_id == __sw_id_hw[i]) | |
948 | return i; | |
949 | } | |
950 | return -EINVAL; | |
951 | } | |
952 | ||
0ff1fb65 | 953 | enum mlx4_net_trans_promisc_mode { |
f9162539 HHZ |
954 | MLX4_FS_REGULAR = 1, |
955 | MLX4_FS_ALL_DEFAULT, | |
956 | MLX4_FS_MC_DEFAULT, | |
957 | MLX4_FS_UC_SNIFFER, | |
958 | MLX4_FS_MC_SNIFFER, | |
c2c19dc3 | 959 | MLX4_FS_MODE_NUM, /* should be last */ |
0ff1fb65 HHZ |
960 | }; |
961 | ||
962 | struct mlx4_spec_eth { | |
574e2af7 JP |
963 | u8 dst_mac[ETH_ALEN]; |
964 | u8 dst_mac_msk[ETH_ALEN]; | |
965 | u8 src_mac[ETH_ALEN]; | |
966 | u8 src_mac_msk[ETH_ALEN]; | |
0ff1fb65 HHZ |
967 | u8 ether_type_enable; |
968 | __be16 ether_type; | |
969 | __be16 vlan_id_msk; | |
970 | __be16 vlan_id; | |
971 | }; | |
972 | ||
973 | struct mlx4_spec_tcp_udp { | |
974 | __be16 dst_port; | |
975 | __be16 dst_port_msk; | |
976 | __be16 src_port; | |
977 | __be16 src_port_msk; | |
978 | }; | |
979 | ||
980 | struct mlx4_spec_ipv4 { | |
981 | __be32 dst_ip; | |
982 | __be32 dst_ip_msk; | |
983 | __be32 src_ip; | |
984 | __be32 src_ip_msk; | |
985 | }; | |
986 | ||
987 | struct mlx4_spec_ib { | |
ba60a356 | 988 | __be32 l3_qpn; |
0ff1fb65 HHZ |
989 | __be32 qpn_msk; |
990 | u8 dst_gid[16]; | |
991 | u8 dst_gid_msk[16]; | |
992 | }; | |
993 | ||
7ffdf726 OG |
994 | struct mlx4_spec_vxlan { |
995 | __be32 vni; | |
996 | __be32 vni_mask; | |
997 | ||
998 | }; | |
999 | ||
0ff1fb65 HHZ |
1000 | struct mlx4_spec_list { |
1001 | struct list_head list; | |
1002 | enum mlx4_net_trans_rule_id id; | |
1003 | union { | |
1004 | struct mlx4_spec_eth eth; | |
1005 | struct mlx4_spec_ib ib; | |
1006 | struct mlx4_spec_ipv4 ipv4; | |
1007 | struct mlx4_spec_tcp_udp tcp_udp; | |
7ffdf726 | 1008 | struct mlx4_spec_vxlan vxlan; |
0ff1fb65 HHZ |
1009 | }; |
1010 | }; | |
1011 | ||
1012 | enum mlx4_net_trans_hw_rule_queue { | |
1013 | MLX4_NET_TRANS_Q_FIFO, | |
1014 | MLX4_NET_TRANS_Q_LIFO, | |
1015 | }; | |
1016 | ||
1017 | struct mlx4_net_trans_rule { | |
1018 | struct list_head list; | |
1019 | enum mlx4_net_trans_hw_rule_queue queue_mode; | |
1020 | bool exclusive; | |
1021 | bool allow_loopback; | |
1022 | enum mlx4_net_trans_promisc_mode promisc_mode; | |
1023 | u8 port; | |
1024 | u16 priority; | |
1025 | u32 qpn; | |
1026 | }; | |
1027 | ||
3cd0e178 | 1028 | struct mlx4_net_trans_rule_hw_ctrl { |
bcf37297 HHZ |
1029 | __be16 prio; |
1030 | u8 type; | |
1031 | u8 flags; | |
3cd0e178 HHZ |
1032 | u8 rsvd1; |
1033 | u8 funcid; | |
1034 | u8 vep; | |
1035 | u8 port; | |
1036 | __be32 qpn; | |
1037 | __be32 rsvd2; | |
1038 | }; | |
1039 | ||
1040 | struct mlx4_net_trans_rule_hw_ib { | |
1041 | u8 size; | |
1042 | u8 rsvd1; | |
1043 | __be16 id; | |
1044 | u32 rsvd2; | |
ba60a356 | 1045 | __be32 l3_qpn; |
3cd0e178 HHZ |
1046 | __be32 qpn_mask; |
1047 | u8 dst_gid[16]; | |
1048 | u8 dst_gid_msk[16]; | |
1049 | } __packed; | |
1050 | ||
1051 | struct mlx4_net_trans_rule_hw_eth { | |
1052 | u8 size; | |
1053 | u8 rsvd; | |
1054 | __be16 id; | |
1055 | u8 rsvd1[6]; | |
1056 | u8 dst_mac[6]; | |
1057 | u16 rsvd2; | |
1058 | u8 dst_mac_msk[6]; | |
1059 | u16 rsvd3; | |
1060 | u8 src_mac[6]; | |
1061 | u16 rsvd4; | |
1062 | u8 src_mac_msk[6]; | |
1063 | u8 rsvd5; | |
1064 | u8 ether_type_enable; | |
1065 | __be16 ether_type; | |
ba60a356 HHZ |
1066 | __be16 vlan_tag_msk; |
1067 | __be16 vlan_tag; | |
3cd0e178 HHZ |
1068 | } __packed; |
1069 | ||
1070 | struct mlx4_net_trans_rule_hw_tcp_udp { | |
1071 | u8 size; | |
1072 | u8 rsvd; | |
1073 | __be16 id; | |
1074 | __be16 rsvd1[3]; | |
1075 | __be16 dst_port; | |
1076 | __be16 rsvd2; | |
1077 | __be16 dst_port_msk; | |
1078 | __be16 rsvd3; | |
1079 | __be16 src_port; | |
1080 | __be16 rsvd4; | |
1081 | __be16 src_port_msk; | |
1082 | } __packed; | |
1083 | ||
1084 | struct mlx4_net_trans_rule_hw_ipv4 { | |
1085 | u8 size; | |
1086 | u8 rsvd; | |
1087 | __be16 id; | |
1088 | __be32 rsvd1; | |
1089 | __be32 dst_ip; | |
1090 | __be32 dst_ip_msk; | |
1091 | __be32 src_ip; | |
1092 | __be32 src_ip_msk; | |
1093 | } __packed; | |
1094 | ||
7ffdf726 OG |
1095 | struct mlx4_net_trans_rule_hw_vxlan { |
1096 | u8 size; | |
1097 | u8 rsvd; | |
1098 | __be16 id; | |
1099 | __be32 rsvd1; | |
1100 | __be32 vni; | |
1101 | __be32 vni_mask; | |
1102 | } __packed; | |
1103 | ||
3cd0e178 HHZ |
1104 | struct _rule_hw { |
1105 | union { | |
1106 | struct { | |
1107 | u8 size; | |
1108 | u8 rsvd; | |
1109 | __be16 id; | |
1110 | }; | |
1111 | struct mlx4_net_trans_rule_hw_eth eth; | |
1112 | struct mlx4_net_trans_rule_hw_ib ib; | |
1113 | struct mlx4_net_trans_rule_hw_ipv4 ipv4; | |
1114 | struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; | |
7ffdf726 | 1115 | struct mlx4_net_trans_rule_hw_vxlan vxlan; |
3cd0e178 HHZ |
1116 | }; |
1117 | }; | |
1118 | ||
7ffdf726 OG |
1119 | enum { |
1120 | VXLAN_STEER_BY_OUTER_MAC = 1 << 0, | |
1121 | VXLAN_STEER_BY_OUTER_VLAN = 1 << 1, | |
1122 | VXLAN_STEER_BY_VSID_VNI = 1 << 2, | |
1123 | VXLAN_STEER_BY_INNER_MAC = 1 << 3, | |
1124 | VXLAN_STEER_BY_INNER_VLAN = 1 << 4, | |
1125 | }; | |
1126 | ||
1127 | ||
592e49dd HHZ |
1128 | int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, |
1129 | enum mlx4_net_trans_promisc_mode mode); | |
1130 | int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, | |
1131 | enum mlx4_net_trans_promisc_mode mode); | |
1679200f YP |
1132 | int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); |
1133 | int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
1134 | int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); | |
1135 | int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
1136 | int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); | |
1137 | ||
ffe455ad EE |
1138 | int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); |
1139 | void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); | |
16a10ffd YB |
1140 | int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); |
1141 | int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); | |
93ece0c1 | 1142 | void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap); |
9a9a232a YP |
1143 | int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, |
1144 | u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); | |
1145 | int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, | |
1146 | u8 promisc); | |
e5395e92 AV |
1147 | int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc); |
1148 | int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, | |
1149 | u8 *pg, u16 *ratelimit); | |
1b136de1 | 1150 | int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable); |
dd5f03be | 1151 | int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); |
4c3eb3ca | 1152 | int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); |
2a2336f8 | 1153 | int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); |
2009d005 | 1154 | void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); |
2a2336f8 | 1155 | |
8ad11fb6 JM |
1156 | int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, |
1157 | int npages, u64 iova, u32 *lkey, u32 *rkey); | |
1158 | int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, | |
1159 | int max_maps, u8 page_shift, struct mlx4_fmr *fmr); | |
1160 | int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
1161 | void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, | |
1162 | u32 *lkey, u32 *rkey); | |
1163 | int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
1164 | int mlx4_SYNC_TPT(struct mlx4_dev *dev); | |
e7c1c2c4 | 1165 | int mlx4_test_interrupts(struct mlx4_dev *dev); |
d9236c3f AV |
1166 | int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap, |
1167 | int *vector); | |
0b7ca5a9 | 1168 | void mlx4_release_eq(struct mlx4_dev *dev, int vec); |
8ad11fb6 | 1169 | |
8e1a28e8 | 1170 | int mlx4_get_phys_port_id(struct mlx4_dev *dev); |
14c07b13 YP |
1171 | int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); |
1172 | int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); | |
1173 | ||
f2a3f6a3 OG |
1174 | int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); |
1175 | void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); | |
1176 | ||
0ff1fb65 HHZ |
1177 | int mlx4_flow_attach(struct mlx4_dev *dev, |
1178 | struct mlx4_net_trans_rule *rule, u64 *reg_id); | |
1179 | int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); | |
c2c19dc3 HHZ |
1180 | int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, |
1181 | enum mlx4_net_trans_promisc_mode flow_type); | |
1182 | int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, | |
1183 | enum mlx4_net_trans_rule_id id); | |
1184 | int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); | |
0ff1fb65 | 1185 | |
54679e14 JM |
1186 | void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, |
1187 | int i, int val); | |
1188 | ||
396f2feb JM |
1189 | int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); |
1190 | ||
993c401e JM |
1191 | int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); |
1192 | int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); | |
1193 | int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); | |
1194 | int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); | |
1195 | int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); | |
1196 | enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); | |
1197 | int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); | |
1198 | ||
afa8fd1d JM |
1199 | void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); |
1200 | __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); | |
9cd59352 JM |
1201 | |
1202 | int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, | |
1203 | int *slave_id); | |
1204 | int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, | |
1205 | u8 *gid); | |
993c401e | 1206 | |
4de65803 MB |
1207 | int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, |
1208 | u32 max_range_qpn); | |
1209 | ||
ec693d47 AV |
1210 | cycle_t mlx4_read_clock(struct mlx4_dev *dev); |
1211 | ||
f74462ac MB |
1212 | struct mlx4_active_ports { |
1213 | DECLARE_BITMAP(ports, MLX4_MAX_PORTS); | |
1214 | }; | |
1215 | /* Returns a bitmap of the physical ports which are assigned to slave */ | |
1216 | struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave); | |
1217 | ||
1218 | /* Returns the physical port that represents the virtual port of the slave, */ | |
1219 | /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */ | |
1220 | /* mapping is returned. */ | |
1221 | int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port); | |
1222 | ||
1223 | struct mlx4_slaves_pport { | |
1224 | DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX); | |
1225 | }; | |
1226 | /* Returns a bitmap of all slaves that are assigned to port. */ | |
1227 | struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev, | |
1228 | int port); | |
1229 | ||
1230 | /* Returns a bitmap of all slaves that are assigned exactly to all the */ | |
1231 | /* the ports that are set in crit_ports. */ | |
1232 | struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv( | |
1233 | struct mlx4_dev *dev, | |
1234 | const struct mlx4_active_ports *crit_ports); | |
1235 | ||
1236 | /* Returns the slave's virtual port that represents the physical port. */ | |
1237 | int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port); | |
1238 | ||
449fc488 | 1239 | int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port); |
d18f141a OG |
1240 | |
1241 | int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port); | |
97982f5a | 1242 | int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port); |
65fed8a8 JM |
1243 | int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port); |
1244 | int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port, | |
1245 | int enable); | |
225c7b1f | 1246 | #endif /* MLX4_DEVICE_H */ |