Commit | Line | Data |
---|---|---|
f8381cba TG |
1 | /* |
2 | * linux/kernel/time/tick-broadcast.c | |
3 | * | |
4 | * This file contains functions which emulate a local clock-event | |
5 | * device via a broadcast event source. | |
6 | * | |
7 | * Copyright(C) 2005-2006, Thomas Gleixner <tglx@linutronix.de> | |
8 | * Copyright(C) 2005-2007, Red Hat, Inc., Ingo Molnar | |
9 | * Copyright(C) 2006-2007, Timesys Corp., Thomas Gleixner | |
10 | * | |
11 | * This code is licenced under the GPL version 2. For details see | |
12 | * kernel-base/COPYING. | |
13 | */ | |
14 | #include <linux/cpu.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/hrtimer.h> | |
d7b90689 | 17 | #include <linux/interrupt.h> |
f8381cba TG |
18 | #include <linux/percpu.h> |
19 | #include <linux/profile.h> | |
20 | #include <linux/sched.h> | |
12ad1000 | 21 | #include <linux/smp.h> |
f8381cba TG |
22 | |
23 | #include "tick-internal.h" | |
24 | ||
25 | /* | |
26 | * Broadcast support for broken x86 hardware, where the local apic | |
27 | * timer stops in C3 state. | |
28 | */ | |
29 | ||
a52f5c56 | 30 | static struct tick_device tick_broadcast_device; |
6b954823 RR |
31 | /* FIXME: Use cpumask_var_t. */ |
32 | static DECLARE_BITMAP(tick_broadcast_mask, NR_CPUS); | |
33 | static DECLARE_BITMAP(tmpmask, NR_CPUS); | |
b5f91da0 | 34 | static DEFINE_RAW_SPINLOCK(tick_broadcast_lock); |
aa276e1c | 35 | static int tick_broadcast_force; |
f8381cba | 36 | |
5590a536 TG |
37 | #ifdef CONFIG_TICK_ONESHOT |
38 | static void tick_broadcast_clear_oneshot(int cpu); | |
39 | #else | |
40 | static inline void tick_broadcast_clear_oneshot(int cpu) { } | |
41 | #endif | |
42 | ||
289f480a IM |
43 | /* |
44 | * Debugging: see timer_list.c | |
45 | */ | |
46 | struct tick_device *tick_get_broadcast_device(void) | |
47 | { | |
48 | return &tick_broadcast_device; | |
49 | } | |
50 | ||
6b954823 | 51 | struct cpumask *tick_get_broadcast_mask(void) |
289f480a | 52 | { |
6b954823 | 53 | return to_cpumask(tick_broadcast_mask); |
289f480a IM |
54 | } |
55 | ||
f8381cba TG |
56 | /* |
57 | * Start the device in periodic mode | |
58 | */ | |
59 | static void tick_broadcast_start_periodic(struct clock_event_device *bc) | |
60 | { | |
18de5bc4 | 61 | if (bc) |
f8381cba TG |
62 | tick_setup_periodic(bc, 1); |
63 | } | |
64 | ||
65 | /* | |
66 | * Check, if the device can be utilized as broadcast device: | |
67 | */ | |
68 | int tick_check_broadcast_device(struct clock_event_device *dev) | |
69 | { | |
a7dc19b8 MR |
70 | if ((dev->features & CLOCK_EVT_FEAT_DUMMY) || |
71 | (tick_broadcast_device.evtdev && | |
4a93232d VP |
72 | tick_broadcast_device.evtdev->rating >= dev->rating) || |
73 | (dev->features & CLOCK_EVT_FEAT_C3STOP)) | |
f8381cba TG |
74 | return 0; |
75 | ||
c1be8430 | 76 | clockevents_exchange_device(tick_broadcast_device.evtdev, dev); |
f8381cba | 77 | tick_broadcast_device.evtdev = dev; |
6b954823 | 78 | if (!cpumask_empty(tick_get_broadcast_mask())) |
f8381cba TG |
79 | tick_broadcast_start_periodic(dev); |
80 | return 1; | |
81 | } | |
82 | ||
83 | /* | |
84 | * Check, if the device is the broadcast device | |
85 | */ | |
86 | int tick_is_broadcast_device(struct clock_event_device *dev) | |
87 | { | |
88 | return (dev && tick_broadcast_device.evtdev == dev); | |
89 | } | |
90 | ||
12ad1000 MR |
91 | static void err_broadcast(const struct cpumask *mask) |
92 | { | |
93 | pr_crit_once("Failed to broadcast timer tick. Some CPUs may be unresponsive.\n"); | |
94 | } | |
95 | ||
5d1d9a29 MR |
96 | static void tick_device_setup_broadcast_func(struct clock_event_device *dev) |
97 | { | |
98 | if (!dev->broadcast) | |
99 | dev->broadcast = tick_broadcast; | |
100 | if (!dev->broadcast) { | |
101 | pr_warn_once("%s depends on broadcast, but no broadcast function available\n", | |
102 | dev->name); | |
103 | dev->broadcast = err_broadcast; | |
104 | } | |
105 | } | |
106 | ||
f8381cba TG |
107 | /* |
108 | * Check, if the device is disfunctional and a place holder, which | |
109 | * needs to be handled by the broadcast device. | |
110 | */ | |
111 | int tick_device_uses_broadcast(struct clock_event_device *dev, int cpu) | |
112 | { | |
113 | unsigned long flags; | |
114 | int ret = 0; | |
115 | ||
b5f91da0 | 116 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
f8381cba TG |
117 | |
118 | /* | |
119 | * Devices might be registered with both periodic and oneshot | |
120 | * mode disabled. This signals, that the device needs to be | |
121 | * operated from the broadcast device and is a placeholder for | |
122 | * the cpu local device. | |
123 | */ | |
124 | if (!tick_device_is_functional(dev)) { | |
125 | dev->event_handler = tick_handle_periodic; | |
5d1d9a29 | 126 | tick_device_setup_broadcast_func(dev); |
6b954823 | 127 | cpumask_set_cpu(cpu, tick_get_broadcast_mask()); |
f8381cba TG |
128 | tick_broadcast_start_periodic(tick_broadcast_device.evtdev); |
129 | ret = 1; | |
5590a536 TG |
130 | } else { |
131 | /* | |
132 | * When the new device is not affected by the stop | |
133 | * feature and the cpu is marked in the broadcast mask | |
134 | * then clear the broadcast bit. | |
135 | */ | |
136 | if (!(dev->features & CLOCK_EVT_FEAT_C3STOP)) { | |
137 | int cpu = smp_processor_id(); | |
6b954823 | 138 | cpumask_clear_cpu(cpu, tick_get_broadcast_mask()); |
5590a536 | 139 | tick_broadcast_clear_oneshot(cpu); |
5d1d9a29 MR |
140 | } else { |
141 | tick_device_setup_broadcast_func(dev); | |
5590a536 TG |
142 | } |
143 | } | |
b5f91da0 | 144 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
f8381cba TG |
145 | return ret; |
146 | } | |
147 | ||
12572dbb MR |
148 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
149 | int tick_receive_broadcast(void) | |
150 | { | |
151 | struct tick_device *td = this_cpu_ptr(&tick_cpu_device); | |
152 | struct clock_event_device *evt = td->evtdev; | |
153 | ||
154 | if (!evt) | |
155 | return -ENODEV; | |
156 | ||
157 | if (!evt->event_handler) | |
158 | return -EINVAL; | |
159 | ||
160 | evt->event_handler(evt); | |
161 | return 0; | |
162 | } | |
163 | #endif | |
164 | ||
f8381cba | 165 | /* |
6b954823 | 166 | * Broadcast the event to the cpus, which are set in the mask (mangled). |
f8381cba | 167 | */ |
6b954823 | 168 | static void tick_do_broadcast(struct cpumask *mask) |
f8381cba | 169 | { |
186e3cb8 | 170 | int cpu = smp_processor_id(); |
f8381cba TG |
171 | struct tick_device *td; |
172 | ||
173 | /* | |
174 | * Check, if the current cpu is in the mask | |
175 | */ | |
6b954823 RR |
176 | if (cpumask_test_cpu(cpu, mask)) { |
177 | cpumask_clear_cpu(cpu, mask); | |
f8381cba TG |
178 | td = &per_cpu(tick_cpu_device, cpu); |
179 | td->evtdev->event_handler(td->evtdev); | |
f8381cba TG |
180 | } |
181 | ||
6b954823 | 182 | if (!cpumask_empty(mask)) { |
f8381cba TG |
183 | /* |
184 | * It might be necessary to actually check whether the devices | |
185 | * have different broadcast functions. For now, just use the | |
186 | * one of the first device. This works as long as we have this | |
187 | * misfeature only on x86 (lapic) | |
188 | */ | |
6b954823 RR |
189 | td = &per_cpu(tick_cpu_device, cpumask_first(mask)); |
190 | td->evtdev->broadcast(mask); | |
f8381cba | 191 | } |
f8381cba TG |
192 | } |
193 | ||
194 | /* | |
195 | * Periodic broadcast: | |
196 | * - invoke the broadcast handlers | |
197 | */ | |
198 | static void tick_do_periodic_broadcast(void) | |
199 | { | |
b5f91da0 | 200 | raw_spin_lock(&tick_broadcast_lock); |
f8381cba | 201 | |
6b954823 RR |
202 | cpumask_and(to_cpumask(tmpmask), |
203 | cpu_online_mask, tick_get_broadcast_mask()); | |
204 | tick_do_broadcast(to_cpumask(tmpmask)); | |
f8381cba | 205 | |
b5f91da0 | 206 | raw_spin_unlock(&tick_broadcast_lock); |
f8381cba TG |
207 | } |
208 | ||
209 | /* | |
210 | * Event handler for periodic broadcast ticks | |
211 | */ | |
212 | static void tick_handle_periodic_broadcast(struct clock_event_device *dev) | |
213 | { | |
d4496b39 TG |
214 | ktime_t next; |
215 | ||
f8381cba TG |
216 | tick_do_periodic_broadcast(); |
217 | ||
218 | /* | |
219 | * The device is in periodic mode. No reprogramming necessary: | |
220 | */ | |
221 | if (dev->mode == CLOCK_EVT_MODE_PERIODIC) | |
222 | return; | |
223 | ||
224 | /* | |
225 | * Setup the next period for devices, which do not have | |
d4496b39 | 226 | * periodic mode. We read dev->next_event first and add to it |
698f9315 | 227 | * when the event already expired. clockevents_program_event() |
d4496b39 TG |
228 | * sets dev->next_event only when the event is really |
229 | * programmed to the device. | |
f8381cba | 230 | */ |
d4496b39 TG |
231 | for (next = dev->next_event; ;) { |
232 | next = ktime_add(next, tick_period); | |
f8381cba | 233 | |
d1748302 | 234 | if (!clockevents_program_event(dev, next, false)) |
f8381cba TG |
235 | return; |
236 | tick_do_periodic_broadcast(); | |
237 | } | |
238 | } | |
239 | ||
240 | /* | |
241 | * Powerstate information: The system enters/leaves a state, where | |
242 | * affected devices might stop | |
243 | */ | |
f833bab8 | 244 | static void tick_do_broadcast_on_off(unsigned long *reason) |
f8381cba TG |
245 | { |
246 | struct clock_event_device *bc, *dev; | |
247 | struct tick_device *td; | |
f833bab8 | 248 | unsigned long flags; |
9c17bcda | 249 | int cpu, bc_stopped; |
f8381cba | 250 | |
b5f91da0 | 251 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
f8381cba TG |
252 | |
253 | cpu = smp_processor_id(); | |
254 | td = &per_cpu(tick_cpu_device, cpu); | |
255 | dev = td->evtdev; | |
256 | bc = tick_broadcast_device.evtdev; | |
257 | ||
258 | /* | |
1595f452 | 259 | * Is the device not affected by the powerstate ? |
f8381cba | 260 | */ |
1595f452 | 261 | if (!dev || !(dev->features & CLOCK_EVT_FEAT_C3STOP)) |
f8381cba TG |
262 | goto out; |
263 | ||
3dfbc884 TG |
264 | if (!tick_device_is_functional(dev)) |
265 | goto out; | |
1595f452 | 266 | |
6b954823 | 267 | bc_stopped = cpumask_empty(tick_get_broadcast_mask()); |
9c17bcda | 268 | |
1595f452 TG |
269 | switch (*reason) { |
270 | case CLOCK_EVT_NOTIFY_BROADCAST_ON: | |
271 | case CLOCK_EVT_NOTIFY_BROADCAST_FORCE: | |
6b954823 RR |
272 | if (!cpumask_test_cpu(cpu, tick_get_broadcast_mask())) { |
273 | cpumask_set_cpu(cpu, tick_get_broadcast_mask()); | |
07454bff TG |
274 | if (tick_broadcast_device.mode == |
275 | TICKDEV_MODE_PERIODIC) | |
2344abbc | 276 | clockevents_shutdown(dev); |
f8381cba | 277 | } |
3dfbc884 | 278 | if (*reason == CLOCK_EVT_NOTIFY_BROADCAST_FORCE) |
aa276e1c | 279 | tick_broadcast_force = 1; |
1595f452 TG |
280 | break; |
281 | case CLOCK_EVT_NOTIFY_BROADCAST_OFF: | |
aa276e1c | 282 | if (!tick_broadcast_force && |
6b954823 RR |
283 | cpumask_test_cpu(cpu, tick_get_broadcast_mask())) { |
284 | cpumask_clear_cpu(cpu, tick_get_broadcast_mask()); | |
07454bff TG |
285 | if (tick_broadcast_device.mode == |
286 | TICKDEV_MODE_PERIODIC) | |
f8381cba TG |
287 | tick_setup_periodic(dev, 0); |
288 | } | |
1595f452 | 289 | break; |
f8381cba TG |
290 | } |
291 | ||
6b954823 | 292 | if (cpumask_empty(tick_get_broadcast_mask())) { |
9c17bcda | 293 | if (!bc_stopped) |
2344abbc | 294 | clockevents_shutdown(bc); |
9c17bcda | 295 | } else if (bc_stopped) { |
f8381cba TG |
296 | if (tick_broadcast_device.mode == TICKDEV_MODE_PERIODIC) |
297 | tick_broadcast_start_periodic(bc); | |
79bf2bb3 TG |
298 | else |
299 | tick_broadcast_setup_oneshot(bc); | |
f8381cba TG |
300 | } |
301 | out: | |
b5f91da0 | 302 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
f8381cba TG |
303 | } |
304 | ||
305 | /* | |
306 | * Powerstate information: The system enters/leaves a state, where | |
307 | * affected devices might stop. | |
308 | */ | |
309 | void tick_broadcast_on_off(unsigned long reason, int *oncpu) | |
310 | { | |
6b954823 | 311 | if (!cpumask_test_cpu(*oncpu, cpu_online_mask)) |
833df317 | 312 | printk(KERN_ERR "tick-broadcast: ignoring broadcast for " |
72fcde96 | 313 | "offline CPU #%d\n", *oncpu); |
bf020cb7 | 314 | else |
f833bab8 | 315 | tick_do_broadcast_on_off(&reason); |
f8381cba TG |
316 | } |
317 | ||
318 | /* | |
319 | * Set the periodic handler depending on broadcast on/off | |
320 | */ | |
321 | void tick_set_periodic_handler(struct clock_event_device *dev, int broadcast) | |
322 | { | |
323 | if (!broadcast) | |
324 | dev->event_handler = tick_handle_periodic; | |
325 | else | |
326 | dev->event_handler = tick_handle_periodic_broadcast; | |
327 | } | |
328 | ||
329 | /* | |
330 | * Remove a CPU from broadcasting | |
331 | */ | |
332 | void tick_shutdown_broadcast(unsigned int *cpup) | |
333 | { | |
334 | struct clock_event_device *bc; | |
335 | unsigned long flags; | |
336 | unsigned int cpu = *cpup; | |
337 | ||
b5f91da0 | 338 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
f8381cba TG |
339 | |
340 | bc = tick_broadcast_device.evtdev; | |
6b954823 | 341 | cpumask_clear_cpu(cpu, tick_get_broadcast_mask()); |
f8381cba TG |
342 | |
343 | if (tick_broadcast_device.mode == TICKDEV_MODE_PERIODIC) { | |
6b954823 | 344 | if (bc && cpumask_empty(tick_get_broadcast_mask())) |
2344abbc | 345 | clockevents_shutdown(bc); |
f8381cba TG |
346 | } |
347 | ||
b5f91da0 | 348 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
f8381cba | 349 | } |
79bf2bb3 | 350 | |
6321dd60 TG |
351 | void tick_suspend_broadcast(void) |
352 | { | |
353 | struct clock_event_device *bc; | |
354 | unsigned long flags; | |
355 | ||
b5f91da0 | 356 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
6321dd60 TG |
357 | |
358 | bc = tick_broadcast_device.evtdev; | |
18de5bc4 | 359 | if (bc) |
2344abbc | 360 | clockevents_shutdown(bc); |
6321dd60 | 361 | |
b5f91da0 | 362 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
6321dd60 TG |
363 | } |
364 | ||
365 | int tick_resume_broadcast(void) | |
366 | { | |
367 | struct clock_event_device *bc; | |
368 | unsigned long flags; | |
369 | int broadcast = 0; | |
370 | ||
b5f91da0 | 371 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
6321dd60 TG |
372 | |
373 | bc = tick_broadcast_device.evtdev; | |
6321dd60 | 374 | |
cd05a1f8 | 375 | if (bc) { |
18de5bc4 TG |
376 | clockevents_set_mode(bc, CLOCK_EVT_MODE_RESUME); |
377 | ||
cd05a1f8 TG |
378 | switch (tick_broadcast_device.mode) { |
379 | case TICKDEV_MODE_PERIODIC: | |
6b954823 | 380 | if (!cpumask_empty(tick_get_broadcast_mask())) |
cd05a1f8 | 381 | tick_broadcast_start_periodic(bc); |
6b954823 RR |
382 | broadcast = cpumask_test_cpu(smp_processor_id(), |
383 | tick_get_broadcast_mask()); | |
cd05a1f8 TG |
384 | break; |
385 | case TICKDEV_MODE_ONESHOT: | |
a6371f80 SS |
386 | if (!cpumask_empty(tick_get_broadcast_mask())) |
387 | broadcast = tick_resume_broadcast_oneshot(bc); | |
cd05a1f8 TG |
388 | break; |
389 | } | |
6321dd60 | 390 | } |
b5f91da0 | 391 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
6321dd60 TG |
392 | |
393 | return broadcast; | |
394 | } | |
395 | ||
396 | ||
79bf2bb3 TG |
397 | #ifdef CONFIG_TICK_ONESHOT |
398 | ||
6b954823 RR |
399 | /* FIXME: use cpumask_var_t. */ |
400 | static DECLARE_BITMAP(tick_broadcast_oneshot_mask, NR_CPUS); | |
79bf2bb3 | 401 | |
289f480a | 402 | /* |
6b954823 | 403 | * Exposed for debugging: see timer_list.c |
289f480a | 404 | */ |
6b954823 | 405 | struct cpumask *tick_get_broadcast_oneshot_mask(void) |
289f480a | 406 | { |
6b954823 | 407 | return to_cpumask(tick_broadcast_oneshot_mask); |
289f480a IM |
408 | } |
409 | ||
79bf2bb3 TG |
410 | static int tick_broadcast_set_event(ktime_t expires, int force) |
411 | { | |
412 | struct clock_event_device *bc = tick_broadcast_device.evtdev; | |
1fb9b7d2 | 413 | |
b9a6a235 TG |
414 | if (bc->mode != CLOCK_EVT_MODE_ONESHOT) |
415 | clockevents_set_mode(bc, CLOCK_EVT_MODE_ONESHOT); | |
416 | ||
d1748302 | 417 | return clockevents_program_event(bc, expires, force); |
79bf2bb3 TG |
418 | } |
419 | ||
cd05a1f8 TG |
420 | int tick_resume_broadcast_oneshot(struct clock_event_device *bc) |
421 | { | |
422 | clockevents_set_mode(bc, CLOCK_EVT_MODE_ONESHOT); | |
b7e113dc | 423 | return 0; |
cd05a1f8 TG |
424 | } |
425 | ||
fb02fbc1 TG |
426 | /* |
427 | * Called from irq_enter() when idle was interrupted to reenable the | |
428 | * per cpu device. | |
429 | */ | |
430 | void tick_check_oneshot_broadcast(int cpu) | |
431 | { | |
6b954823 | 432 | if (cpumask_test_cpu(cpu, to_cpumask(tick_broadcast_oneshot_mask))) { |
fb02fbc1 TG |
433 | struct tick_device *td = &per_cpu(tick_cpu_device, cpu); |
434 | ||
435 | clockevents_set_mode(td->evtdev, CLOCK_EVT_MODE_ONESHOT); | |
436 | } | |
437 | } | |
438 | ||
79bf2bb3 TG |
439 | /* |
440 | * Handle oneshot mode broadcasting | |
441 | */ | |
442 | static void tick_handle_oneshot_broadcast(struct clock_event_device *dev) | |
443 | { | |
444 | struct tick_device *td; | |
cdc6f27d | 445 | ktime_t now, next_event; |
79bf2bb3 TG |
446 | int cpu; |
447 | ||
b5f91da0 | 448 | raw_spin_lock(&tick_broadcast_lock); |
79bf2bb3 TG |
449 | again: |
450 | dev->next_event.tv64 = KTIME_MAX; | |
cdc6f27d | 451 | next_event.tv64 = KTIME_MAX; |
6b954823 | 452 | cpumask_clear(to_cpumask(tmpmask)); |
79bf2bb3 TG |
453 | now = ktime_get(); |
454 | /* Find all expired events */ | |
6b954823 | 455 | for_each_cpu(cpu, tick_get_broadcast_oneshot_mask()) { |
79bf2bb3 TG |
456 | td = &per_cpu(tick_cpu_device, cpu); |
457 | if (td->evtdev->next_event.tv64 <= now.tv64) | |
6b954823 | 458 | cpumask_set_cpu(cpu, to_cpumask(tmpmask)); |
cdc6f27d TG |
459 | else if (td->evtdev->next_event.tv64 < next_event.tv64) |
460 | next_event.tv64 = td->evtdev->next_event.tv64; | |
79bf2bb3 TG |
461 | } |
462 | ||
463 | /* | |
cdc6f27d TG |
464 | * Wakeup the cpus which have an expired event. |
465 | */ | |
6b954823 | 466 | tick_do_broadcast(to_cpumask(tmpmask)); |
cdc6f27d TG |
467 | |
468 | /* | |
469 | * Two reasons for reprogram: | |
470 | * | |
471 | * - The global event did not expire any CPU local | |
472 | * events. This happens in dyntick mode, as the maximum PIT | |
473 | * delta is quite small. | |
474 | * | |
475 | * - There are pending events on sleeping CPUs which were not | |
476 | * in the event mask | |
79bf2bb3 | 477 | */ |
cdc6f27d | 478 | if (next_event.tv64 != KTIME_MAX) { |
79bf2bb3 | 479 | /* |
cdc6f27d TG |
480 | * Rearm the broadcast device. If event expired, |
481 | * repeat the above | |
79bf2bb3 | 482 | */ |
cdc6f27d | 483 | if (tick_broadcast_set_event(next_event, 0)) |
79bf2bb3 TG |
484 | goto again; |
485 | } | |
b5f91da0 | 486 | raw_spin_unlock(&tick_broadcast_lock); |
79bf2bb3 TG |
487 | } |
488 | ||
489 | /* | |
490 | * Powerstate information: The system enters/leaves a state, where | |
491 | * affected devices might stop | |
492 | */ | |
493 | void tick_broadcast_oneshot_control(unsigned long reason) | |
494 | { | |
495 | struct clock_event_device *bc, *dev; | |
496 | struct tick_device *td; | |
497 | unsigned long flags; | |
498 | int cpu; | |
499 | ||
79bf2bb3 TG |
500 | /* |
501 | * Periodic mode does not care about the enter/exit of power | |
502 | * states | |
503 | */ | |
504 | if (tick_broadcast_device.mode == TICKDEV_MODE_PERIODIC) | |
7372b0b1 | 505 | return; |
79bf2bb3 | 506 | |
7372b0b1 AK |
507 | /* |
508 | * We are called with preemtion disabled from the depth of the | |
509 | * idle code, so we can't be moved away. | |
510 | */ | |
79bf2bb3 TG |
511 | cpu = smp_processor_id(); |
512 | td = &per_cpu(tick_cpu_device, cpu); | |
513 | dev = td->evtdev; | |
514 | ||
515 | if (!(dev->features & CLOCK_EVT_FEAT_C3STOP)) | |
7372b0b1 AK |
516 | return; |
517 | ||
518 | bc = tick_broadcast_device.evtdev; | |
79bf2bb3 | 519 | |
7372b0b1 | 520 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
79bf2bb3 | 521 | if (reason == CLOCK_EVT_NOTIFY_BROADCAST_ENTER) { |
6b954823 RR |
522 | if (!cpumask_test_cpu(cpu, tick_get_broadcast_oneshot_mask())) { |
523 | cpumask_set_cpu(cpu, tick_get_broadcast_oneshot_mask()); | |
79bf2bb3 TG |
524 | clockevents_set_mode(dev, CLOCK_EVT_MODE_SHUTDOWN); |
525 | if (dev->next_event.tv64 < bc->next_event.tv64) | |
526 | tick_broadcast_set_event(dev->next_event, 1); | |
527 | } | |
528 | } else { | |
6b954823 RR |
529 | if (cpumask_test_cpu(cpu, tick_get_broadcast_oneshot_mask())) { |
530 | cpumask_clear_cpu(cpu, | |
531 | tick_get_broadcast_oneshot_mask()); | |
79bf2bb3 TG |
532 | clockevents_set_mode(dev, CLOCK_EVT_MODE_ONESHOT); |
533 | if (dev->next_event.tv64 != KTIME_MAX) | |
534 | tick_program_event(dev->next_event, 1); | |
535 | } | |
536 | } | |
b5f91da0 | 537 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
79bf2bb3 TG |
538 | } |
539 | ||
5590a536 TG |
540 | /* |
541 | * Reset the one shot broadcast for a cpu | |
542 | * | |
543 | * Called with tick_broadcast_lock held | |
544 | */ | |
545 | static void tick_broadcast_clear_oneshot(int cpu) | |
546 | { | |
6b954823 | 547 | cpumask_clear_cpu(cpu, tick_get_broadcast_oneshot_mask()); |
5590a536 TG |
548 | } |
549 | ||
6b954823 RR |
550 | static void tick_broadcast_init_next_event(struct cpumask *mask, |
551 | ktime_t expires) | |
7300711e TG |
552 | { |
553 | struct tick_device *td; | |
554 | int cpu; | |
555 | ||
5db0e1e9 | 556 | for_each_cpu(cpu, mask) { |
7300711e TG |
557 | td = &per_cpu(tick_cpu_device, cpu); |
558 | if (td->evtdev) | |
559 | td->evtdev->next_event = expires; | |
560 | } | |
561 | } | |
562 | ||
79bf2bb3 | 563 | /** |
8dce39c2 | 564 | * tick_broadcast_setup_oneshot - setup the broadcast device |
79bf2bb3 TG |
565 | */ |
566 | void tick_broadcast_setup_oneshot(struct clock_event_device *bc) | |
567 | { | |
07f4beb0 TG |
568 | int cpu = smp_processor_id(); |
569 | ||
9c17bcda TG |
570 | /* Set it up only once ! */ |
571 | if (bc->event_handler != tick_handle_oneshot_broadcast) { | |
7300711e | 572 | int was_periodic = bc->mode == CLOCK_EVT_MODE_PERIODIC; |
7300711e | 573 | |
9c17bcda | 574 | bc->event_handler = tick_handle_oneshot_broadcast; |
7300711e TG |
575 | |
576 | /* Take the do_timer update */ | |
577 | tick_do_timer_cpu = cpu; | |
578 | ||
579 | /* | |
580 | * We must be careful here. There might be other CPUs | |
581 | * waiting for periodic broadcast. We need to set the | |
582 | * oneshot_mask bits for those and program the | |
583 | * broadcast device to fire. | |
584 | */ | |
6b954823 RR |
585 | cpumask_copy(to_cpumask(tmpmask), tick_get_broadcast_mask()); |
586 | cpumask_clear_cpu(cpu, to_cpumask(tmpmask)); | |
587 | cpumask_or(tick_get_broadcast_oneshot_mask(), | |
588 | tick_get_broadcast_oneshot_mask(), | |
589 | to_cpumask(tmpmask)); | |
590 | ||
591 | if (was_periodic && !cpumask_empty(to_cpumask(tmpmask))) { | |
b435092f | 592 | clockevents_set_mode(bc, CLOCK_EVT_MODE_ONESHOT); |
6b954823 RR |
593 | tick_broadcast_init_next_event(to_cpumask(tmpmask), |
594 | tick_next_period); | |
7300711e TG |
595 | tick_broadcast_set_event(tick_next_period, 1); |
596 | } else | |
597 | bc->next_event.tv64 = KTIME_MAX; | |
07f4beb0 TG |
598 | } else { |
599 | /* | |
600 | * The first cpu which switches to oneshot mode sets | |
601 | * the bit for all other cpus which are in the general | |
602 | * (periodic) broadcast mask. So the bit is set and | |
603 | * would prevent the first broadcast enter after this | |
604 | * to program the bc device. | |
605 | */ | |
606 | tick_broadcast_clear_oneshot(cpu); | |
9c17bcda | 607 | } |
79bf2bb3 TG |
608 | } |
609 | ||
610 | /* | |
611 | * Select oneshot operating mode for the broadcast device | |
612 | */ | |
613 | void tick_broadcast_switch_to_oneshot(void) | |
614 | { | |
615 | struct clock_event_device *bc; | |
616 | unsigned long flags; | |
617 | ||
b5f91da0 | 618 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
fa4da365 SS |
619 | |
620 | tick_broadcast_device.mode = TICKDEV_MODE_ONESHOT; | |
79bf2bb3 TG |
621 | bc = tick_broadcast_device.evtdev; |
622 | if (bc) | |
623 | tick_broadcast_setup_oneshot(bc); | |
77b0d60c | 624 | |
b5f91da0 | 625 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
79bf2bb3 TG |
626 | } |
627 | ||
628 | ||
629 | /* | |
630 | * Remove a dead CPU from broadcasting | |
631 | */ | |
632 | void tick_shutdown_broadcast_oneshot(unsigned int *cpup) | |
633 | { | |
79bf2bb3 TG |
634 | unsigned long flags; |
635 | unsigned int cpu = *cpup; | |
636 | ||
b5f91da0 | 637 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
79bf2bb3 | 638 | |
31d9b393 TG |
639 | /* |
640 | * Clear the broadcast mask flag for the dead cpu, but do not | |
641 | * stop the broadcast device! | |
642 | */ | |
6b954823 | 643 | cpumask_clear_cpu(cpu, tick_get_broadcast_oneshot_mask()); |
79bf2bb3 | 644 | |
b5f91da0 | 645 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
79bf2bb3 TG |
646 | } |
647 | ||
27ce4cb4 TG |
648 | /* |
649 | * Check, whether the broadcast device is in one shot mode | |
650 | */ | |
651 | int tick_broadcast_oneshot_active(void) | |
652 | { | |
653 | return tick_broadcast_device.mode == TICKDEV_MODE_ONESHOT; | |
654 | } | |
655 | ||
3a142a06 TG |
656 | /* |
657 | * Check whether the broadcast device supports oneshot. | |
658 | */ | |
659 | bool tick_broadcast_oneshot_available(void) | |
660 | { | |
661 | struct clock_event_device *bc = tick_broadcast_device.evtdev; | |
662 | ||
663 | return bc ? bc->features & CLOCK_EVT_FEAT_ONESHOT : false; | |
664 | } | |
665 | ||
79bf2bb3 | 666 | #endif |