Commit | Line | Data |
---|---|---|
5b872f7d JB |
1 | 2020-07-06 Jan Beulich <jbeulich@suse.com> |
2 | ||
3 | * i386-dis.c (safe-ctype.h): Include. | |
4 | (EXdScalar, EXqScalar): Delete. | |
5 | (d_scalar_mode, q_scalar_mode): Delete. | |
6 | (prefix_table, vex_len_table): Use EXxmm_md in place of | |
7 | EXdScalar and EXxmm_mq in place of EXqScalar. | |
8 | (intel_operand_size, OP_E_memory, OP_EX): Remove uses of | |
9 | d_scalar_mode and q_scalar_mode. | |
10 | * i386-dis-evex-w.h (vmovss): Use EXxmm_md. | |
11 | (vmovsd): Use EXxmm_mq. | |
12 | ||
ddc73fa9 NC |
13 | 2020-07-06 Yuri Chornoivan <yurchor@ukr.net> |
14 | ||
15 | PR 26204 | |
16 | * arc-dis.c: Fix spelling mistake. | |
17 | * po/opcodes.pot: Regenerate. | |
18 | ||
17550be7 NC |
19 | 2020-07-06 Nick Clifton <nickc@redhat.com> |
20 | ||
21 | * po/pt_BR.po: Updated Brazilian Portugugese translation. | |
22 | * po/uk.po: Updated Ukranian translation. | |
23 | ||
b19d852d NC |
24 | 2020-07-04 Nick Clifton <nickc@redhat.com> |
25 | ||
26 | * configure: Regenerate. | |
27 | * po/opcodes.pot: Regenerate. | |
28 | ||
b115b9fd NC |
29 | 2020-07-04 Nick Clifton <nickc@redhat.com> |
30 | ||
31 | Binutils 2.35 branch created. | |
32 | ||
c2ecccb3 L |
33 | 2020-07-02 H.J. Lu <hongjiu.lu@intel.com> |
34 | ||
35 | * i386-gen.c (opcode_modifiers): Add VexSwapSources. | |
36 | * i386-opc.h (VexSwapSources): New. | |
37 | (i386_opcode_modifier): Add vexswapsources. | |
38 | * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions | |
39 | with two source operands swapped. | |
40 | * i386-tbl.h: Regenerated. | |
41 | ||
08ccfccf NC |
42 | 2020-06-30 Nelson Chu <nelson.chu@sifive.com> |
43 | ||
44 | * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the | |
45 | unprivileged CSR can also be initialized. | |
46 | ||
279edac5 AM |
47 | 2020-06-29 Alan Modra <amodra@gmail.com> |
48 | ||
49 | * arm-dis.c: Use C style comments. | |
50 | * cr16-opc.c: Likewise. | |
51 | * ft32-dis.c: Likewise. | |
52 | * moxie-opc.c: Likewise. | |
53 | * tic54x-dis.c: Likewise. | |
54 | * s12z-opc.c: Remove useless comment. | |
55 | * xgate-dis.c: Likewise. | |
56 | ||
e978ad62 L |
57 | 2020-06-26 H.J. Lu <hongjiu.lu@intel.com> |
58 | ||
59 | * i386-opc.tbl: Add a blank line. | |
60 | ||
63112cd6 L |
61 | 2020-06-26 H.J. Lu <hongjiu.lu@intel.com> |
62 | ||
63 | * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB. | |
64 | (VecSIB128): Renamed to ... | |
65 | (VECSIB128): This. | |
66 | (VecSIB256): Renamed to ... | |
67 | (VECSIB256): This. | |
68 | (VecSIB512): Renamed to ... | |
69 | (VECSIB512): This. | |
70 | (VecSIB): Renamed to ... | |
71 | (SIB): This. | |
72 | (i386_opcode_modifier): Replace vecsib with sib. | |
79b32e73 | 73 | * i386-opc.tbl (VecSIB128): New. |
63112cd6 L |
74 | (VecSIB256): Likewise. |
75 | (VecSIB512): Likewise. | |
79b32e73 | 76 | Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256 |
63112cd6 L |
77 | and VecSIB512, respectively. |
78 | ||
d1c36125 JB |
79 | 2020-06-26 Jan Beulich <jbeulich@suse.com> |
80 | ||
81 | * i386-dis.c: Adjust description of I macro. | |
82 | (x86_64_table): Drop use of I. | |
83 | (float_mem): Replace use of I. | |
84 | (putop): Remove handling of I. Adjust setting/clearing of "alt". | |
85 | ||
2a1bb84c JB |
86 | 2020-06-26 Jan Beulich <jbeulich@suse.com> |
87 | ||
88 | * i386-dis.c: (print_insn): Avoid straight assignment to | |
89 | priv.orig_sizeflag when processing -M sub-options. | |
90 | ||
8f570d62 JB |
91 | 2020-06-25 Jan Beulich <jbeulich@suse.com> |
92 | ||
93 | * i386-dis.c: Adjust description of J macro. | |
94 | (dis386, x86_64_table, mod_table): Replace J. | |
95 | (putop): Remove handling of J. | |
96 | ||
464dc4af JB |
97 | 2020-06-25 Jan Beulich <jbeulich@suse.com> |
98 | ||
99 | * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt. | |
100 | ||
589958d6 JB |
101 | 2020-06-25 Jan Beulich <jbeulich@suse.com> |
102 | ||
103 | * i386-dis.c: Adjust description of "LQ" macro. | |
104 | (dis386_twobyte): Use LQ for sysret. | |
105 | (putop): Adjust handling of LQ. | |
106 | ||
39ff0b81 NC |
107 | 2020-06-22 Nelson Chu <nelson.chu@sifive.com> |
108 | ||
109 | * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c. | |
110 | * riscv-dis.c: Include elfxx-riscv.h. | |
111 | ||
d27c357a JB |
112 | 2020-06-18 H.J. Lu <hongjiu.lu@intel.com> |
113 | ||
114 | * i386-dis.c (prefix_table): Revert the last vmgexit change. | |
115 | ||
6fde587f CL |
116 | 2020-06-17 Lili Cui <lili.cui@intel.com> |
117 | ||
118 | * i386-dis.c (prefix_table): Delete the incorrect vmgexit. | |
119 | ||
efe30057 L |
120 | 2020-06-14 H.J. Lu <hongjiu.lu@intel.com> |
121 | ||
122 | PR gas/26115 | |
123 | * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk. | |
124 | * i386-opc.tbl: Likewise. | |
125 | * i386-tbl.h: Regenerated. | |
126 | ||
d8af286f NC |
127 | 2020-06-12 Nelson Chu <nelson.chu@sifive.com> |
128 | ||
129 | * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9. | |
130 | ||
14962256 AC |
131 | 2020-06-11 Alex Coplan <alex.coplan@arm.com> |
132 | ||
133 | * aarch64-opc.c (SYSREG): New macro for describing system registers. | |
134 | (SR_CORE): Likewise. | |
135 | (SR_FEAT): Likewise. | |
136 | (SR_RNG): Likewise. | |
137 | (SR_V8_1): Likewise. | |
138 | (SR_V8_2): Likewise. | |
139 | (SR_V8_3): Likewise. | |
140 | (SR_V8_4): Likewise. | |
141 | (SR_PAN): Likewise. | |
142 | (SR_RAS): Likewise. | |
143 | (SR_SSBS): Likewise. | |
144 | (SR_SVE): Likewise. | |
145 | (SR_ID_PFR2): Likewise. | |
146 | (SR_PROFILE): Likewise. | |
147 | (SR_MEMTAG): Likewise. | |
148 | (SR_SCXTNUM): Likewise. | |
149 | (aarch64_sys_regs): Refactor to store feature information in the table. | |
150 | (aarch64_sys_reg_supported_p): Collapse logic for system registers | |
151 | that now describe their own features. | |
152 | (aarch64_pstatefield_supported_p): Likewise. | |
153 | ||
f9630fa6 L |
154 | 2020-06-09 H.J. Lu <hongjiu.lu@intel.com> |
155 | ||
156 | * i386-dis.c (prefix_table): Fix a typo in comments. | |
157 | ||
73239888 JB |
158 | 2020-06-09 Jan Beulich <jbeulich@suse.com> |
159 | ||
160 | * i386-dis.c (rex_ignored): Delete. | |
161 | (ckprefix): Drop rex_ignored initialization. | |
162 | (get_valid_dis386): Drop setting of rex_ignored. | |
163 | (print_insn): Drop checking of rex_ignored. Don't record data | |
164 | size prefix as used with VEX-and-alike encodings. | |
165 | ||
18897deb JB |
166 | 2020-06-09 Jan Beulich <jbeulich@suse.com> |
167 | ||
168 | * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2, | |
169 | MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators. | |
170 | (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete. | |
171 | (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define. | |
172 | (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16, | |
173 | VEX_0F12, and VEX_0F16. | |
174 | (vex_len_table): Use X for vmovlp* and vmovh*s. Drop | |
175 | VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries. | |
176 | (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE | |
177 | from movlps and movhlps. New MOD_0F12_PREFIX_2, | |
178 | MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and | |
179 | MOD_VEX_0F16_PREFIX_2 entries. | |
180 | ||
97e6786a JB |
181 | 2020-06-09 Jan Beulich <jbeulich@suse.com> |
182 | ||
183 | * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13, | |
184 | MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators. | |
185 | (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, | |
186 | PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, | |
187 | PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, | |
188 | PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6, | |
189 | EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0, | |
190 | EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2, | |
191 | EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, | |
192 | EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, | |
193 | EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, | |
194 | EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, | |
195 | EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, | |
196 | EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, | |
197 | EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, | |
198 | EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, | |
199 | EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, | |
200 | EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, | |
201 | EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, | |
202 | EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, | |
203 | EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, | |
204 | EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, | |
205 | EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, | |
206 | EVEX_W_0FC6_P_2): Delete. | |
207 | (print_insn): Add EVEX.W vs embedded prefix consistency check | |
208 | to prefix validation. | |
209 | * i386-dis-evex.h (evex_table): Don't further descend for | |
210 | vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX, | |
211 | and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17, | |
212 | and 0F2B. | |
213 | * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries. | |
214 | * i386-dis-evex-prefix.h: Don't further descend for vmovupX, | |
215 | vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX, | |
216 | vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases | |
217 | 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29. | |
218 | Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, | |
219 | PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B, | |
220 | PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56, | |
221 | PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries. | |
222 | * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, | |
223 | EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, | |
224 | EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, | |
225 | EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, | |
226 | EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, | |
227 | EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, | |
228 | EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, | |
229 | EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, | |
230 | EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, | |
231 | EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2, | |
232 | EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0, | |
233 | EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, | |
234 | EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0, | |
235 | EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2, | |
236 | EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0, | |
237 | EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2, | |
238 | EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0, | |
239 | EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries. | |
240 | ||
bf926894 JB |
241 | 2020-06-09 Jan Beulich <jbeulich@suse.com> |
242 | ||
243 | * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX, | |
244 | vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX. | |
245 | (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and | |
246 | vmovmskpX. | |
247 | (print_insn): Drop pointless check against bad_opcode. Split | |
248 | prefix validation into legacy and VEX-and-alike parts. | |
249 | (putop): Re-work 'X' macro handling. | |
250 | ||
a5aaedb9 JB |
251 | 2020-06-09 Jan Beulich <jbeulich@suse.com> |
252 | ||
253 | * i386-dis.c (MOD_0F51): Rename to ... | |
254 | (MOD_0F50): ... this. | |
255 | ||
26417f19 AC |
256 | 2020-06-08 Alex Coplan <alex.coplan@arm.com> |
257 | ||
258 | * arm-dis.c (arm_opcodes): Add dfb. | |
259 | (thumb32_opcodes): Add dfb. | |
260 | ||
8a6fb3f9 JB |
261 | 2020-06-08 Jan Beulich <jbeulich@suse.com> |
262 | ||
263 | * i386-opc.h (reg_entry): Const-qualify reg_name field. | |
264 | ||
1424c35d AM |
265 | 2020-06-06 Alan Modra <amodra@gmail.com> |
266 | ||
267 | * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10. | |
268 | ||
d3d1cc7b AM |
269 | 2020-06-05 Alan Modra <amodra@gmail.com> |
270 | ||
271 | * cgen-dis.c (hash_insn_array): Increase size of buf. Assert | |
272 | size is large enough. | |
273 | ||
d8740be1 JM |
274 | 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> |
275 | ||
276 | * disassemble.c (disassemble_init_for_target): Set endian_code for | |
277 | bpf targets. | |
278 | * bpf-desc.c: Regenerate. | |
279 | * bpf-opc.c: Likewise. | |
280 | * bpf-dis.c: Likewise. | |
281 | ||
e9bffec9 JM |
282 | 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com> |
283 | ||
284 | * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument. | |
285 | (cgen_put_insn_value): Likewise. | |
286 | (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value. | |
287 | * cgen-dis.in (print_insn): Likewise. | |
288 | * cgen-ibld.in (insert_1): Likewise. | |
289 | (insert_1): Likewise. | |
290 | (insert_insn_normal): Likewise. | |
291 | (extract_1): Likewise. | |
292 | * bpf-dis.c: Regenerate. | |
293 | * bpf-ibld.c: Likewise. | |
294 | * bpf-ibld.c: Likewise. | |
295 | * cgen-dis.in: Likewise. | |
296 | * cgen-ibld.in: Likewise. | |
297 | * cgen-opc.c: Likewise. | |
298 | * epiphany-dis.c: Likewise. | |
299 | * epiphany-ibld.c: Likewise. | |
300 | * fr30-dis.c: Likewise. | |
301 | * fr30-ibld.c: Likewise. | |
302 | * frv-dis.c: Likewise. | |
303 | * frv-ibld.c: Likewise. | |
304 | * ip2k-dis.c: Likewise. | |
305 | * ip2k-ibld.c: Likewise. | |
306 | * iq2000-dis.c: Likewise. | |
307 | * iq2000-ibld.c: Likewise. | |
308 | * lm32-dis.c: Likewise. | |
309 | * lm32-ibld.c: Likewise. | |
310 | * m32c-dis.c: Likewise. | |
311 | * m32c-ibld.c: Likewise. | |
312 | * m32r-dis.c: Likewise. | |
313 | * m32r-ibld.c: Likewise. | |
314 | * mep-dis.c: Likewise. | |
315 | * mep-ibld.c: Likewise. | |
316 | * mt-dis.c: Likewise. | |
317 | * mt-ibld.c: Likewise. | |
318 | * or1k-dis.c: Likewise. | |
319 | * or1k-ibld.c: Likewise. | |
320 | * xc16x-dis.c: Likewise. | |
321 | * xc16x-ibld.c: Likewise. | |
322 | * xstormy16-dis.c: Likewise. | |
323 | * xstormy16-ibld.c: Likewise. | |
324 | ||
b3db6d07 JM |
325 | 2020-06-04 Jose E. Marchesi <jemarch@gnu.org> |
326 | ||
327 | * cgen-dis.in (cpu_desc_list): New field `insn_endian'. | |
328 | (print_insn_): Handle instruction endian. | |
329 | * bpf-dis.c: Regenerate. | |
330 | * bpf-desc.c: Regenerate. | |
331 | * epiphany-dis.c: Likewise. | |
332 | * epiphany-desc.c: Likewise. | |
333 | * fr30-dis.c: Likewise. | |
334 | * fr30-desc.c: Likewise. | |
335 | * frv-dis.c: Likewise. | |
336 | * frv-desc.c: Likewise. | |
337 | * ip2k-dis.c: Likewise. | |
338 | * ip2k-desc.c: Likewise. | |
339 | * iq2000-dis.c: Likewise. | |
340 | * iq2000-desc.c: Likewise. | |
341 | * lm32-dis.c: Likewise. | |
342 | * lm32-desc.c: Likewise. | |
343 | * m32c-dis.c: Likewise. | |
344 | * m32c-desc.c: Likewise. | |
345 | * m32r-dis.c: Likewise. | |
346 | * m32r-desc.c: Likewise. | |
347 | * mep-dis.c: Likewise. | |
348 | * mep-desc.c: Likewise. | |
349 | * mt-dis.c: Likewise. | |
350 | * mt-desc.c: Likewise. | |
351 | * or1k-dis.c: Likewise. | |
352 | * or1k-desc.c: Likewise. | |
353 | * xc16x-dis.c: Likewise. | |
354 | * xc16x-desc.c: Likewise. | |
355 | * xstormy16-dis.c: Likewise. | |
356 | * xstormy16-desc.c: Likewise. | |
357 | ||
4ee4189f NC |
358 | 2020-06-03 Nick Clifton <nickc@redhat.com> |
359 | ||
360 | * po/sr.po: Updated Serbian translation. | |
361 | ||
44730156 NC |
362 | 2020-06-03 Nelson Chu <nelson.chu@sifive.com> |
363 | ||
364 | * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int. | |
365 | (riscv_get_priv_spec_class): Likewise. | |
366 | ||
3c3d0376 AM |
367 | 2020-06-01 Alan Modra <amodra@gmail.com> |
368 | ||
369 | * bpf-desc.c: Regenerate. | |
370 | ||
78c1c354 JM |
371 | 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com> |
372 | David Faust <david.faust@oracle.com> | |
373 | ||
374 | * bpf-desc.c: Regenerate. | |
375 | * bpf-opc.h: Likewise. | |
376 | * bpf-opc.c: Likewise. | |
377 | * bpf-dis.c: Likewise. | |
378 | ||
efcf5fb5 AM |
379 | 2020-05-28 Alan Modra <amodra@gmail.com> |
380 | ||
381 | * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative | |
382 | values. | |
383 | ||
ab382d64 AM |
384 | 2020-05-28 Alan Modra <amodra@gmail.com> |
385 | ||
386 | * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for | |
387 | immediates. | |
388 | (print_insn_ns32k): Revert last change. | |
389 | ||
151f5de4 NC |
390 | 2020-05-28 Nick Clifton <nickc@redhat.com> |
391 | ||
392 | * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to | |
393 | static. | |
394 | ||
25e1eca8 SL |
395 | 2020-05-26 Sandra Loosemore <sandra@codesourcery.com> |
396 | ||
397 | Fix extraction of signed constants in nios2 disassembler (again). | |
398 | ||
399 | * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to | |
400 | extractions of signed fields. | |
401 | ||
57b17940 SSF |
402 | 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> |
403 | ||
404 | * s390-opc.txt: Relocate vector load/store instructions with | |
405 | additional alignment parameter and change architecture level | |
406 | constraint from z14 to z13. | |
407 | ||
d96bf37b AM |
408 | 2020-05-21 Alan Modra <amodra@gmail.com> |
409 | ||
410 | * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout. | |
411 | * sparc-dis.c: Likewise. | |
412 | * tic4x-dis.c: Likewise. | |
413 | * xtensa-dis.c: Likewise. | |
414 | * bpf-desc.c: Regenerate. | |
415 | * epiphany-desc.c: Regenerate. | |
416 | * fr30-desc.c: Regenerate. | |
417 | * frv-desc.c: Regenerate. | |
418 | * ip2k-desc.c: Regenerate. | |
419 | * iq2000-desc.c: Regenerate. | |
420 | * lm32-desc.c: Regenerate. | |
421 | * m32c-desc.c: Regenerate. | |
422 | * m32r-desc.c: Regenerate. | |
423 | * mep-asm.c: Regenerate. | |
424 | * mep-desc.c: Regenerate. | |
425 | * mt-desc.c: Regenerate. | |
426 | * or1k-desc.c: Regenerate. | |
427 | * xc16x-desc.c: Regenerate. | |
428 | * xstormy16-desc.c: Regenerate. | |
429 | ||
8f595e9b NC |
430 | 2020-05-20 Nelson Chu <nelson.chu@sifive.com> |
431 | ||
432 | * riscv-opc.c (riscv_ext_version_table): The table used to store | |
433 | all information about the supported spec and the corresponding ISA | |
434 | versions. Currently, only Zicsr is supported to verify the | |
435 | correctness of Z sub extension settings. Others will be supported | |
436 | in the future patches. | |
437 | (struct isa_spec_t, isa_specs): List for all supported ISA spec | |
438 | classes and the corresponding strings. | |
439 | (riscv_get_isa_spec_class): New function. Get the corresponding ISA | |
440 | spec class by giving a ISA spec string. | |
441 | * riscv-opc.c (struct priv_spec_t): New structure. | |
442 | (struct priv_spec_t priv_specs): List for all supported privilege spec | |
443 | classes and the corresponding strings. | |
444 | (riscv_get_priv_spec_class): New function. Get the corresponding | |
445 | privilege spec class by giving a spec string. | |
446 | (riscv_get_priv_spec_name): New function. Get the corresponding | |
447 | privilege spec string by giving a CSR version class. | |
448 | * riscv-dis.c: Updated since DECLARE_CSR is changed. | |
449 | * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR | |
450 | according to the chosen version. Build a hash table riscv_csr_hash to | |
451 | store the valid CSR for the chosen pirv verison. Dump the direct | |
452 | CSR address rather than it's name if it is invalid. | |
453 | (parse_riscv_dis_option_without_args): New function. Parse the options | |
454 | without arguments. | |
455 | (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to | |
456 | parse the options without arguments first, and then handle the options | |
457 | with arguments. Add the new option -Mpriv-spec, which has argument. | |
458 | * riscv-dis.c (print_riscv_disassembler_options): Add description | |
459 | about the new OBJDUMP option. | |
460 | ||
3d205eb4 PB |
461 | 2020-05-19 Peter Bergner <bergner@linux.ibm.com> |
462 | ||
463 | * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new | |
464 | WC values on POWER10 sync, dcbf and wait instructions. | |
465 | (insert_pl, extract_pl): New functions. | |
466 | (L2OPT, LS, WC): Use insert_ls and extract_ls. | |
467 | (LS3): New , 3-bit L for sync. | |
468 | (LS3, L3OPT): New, 3-bit L for sync and dcbf. | |
469 | (SC2, PL): New, 2-bit SC and PL for sync and wait. | |
470 | (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks. | |
471 | (XOPL3, XWCPL, XSYNCLS): New opcode macros. | |
472 | (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync, | |
473 | plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics. | |
474 | <wait>: Enable PL operand on POWER10. | |
475 | <dcbf>: Enable L3OPT operand on POWER10. | |
476 | <sync>: Enable SC2 operand on POWER10. | |
477 | ||
a501eb44 SH |
478 | 2020-05-19 Stafford Horne <shorne@gmail.com> |
479 | ||
480 | PR 25184 | |
481 | * or1k-asm.c: Regenerate. | |
482 | * or1k-desc.c: Regenerate. | |
483 | * or1k-desc.h: Regenerate. | |
484 | * or1k-dis.c: Regenerate. | |
485 | * or1k-ibld.c: Regenerate. | |
486 | * or1k-opc.c: Regenerate. | |
487 | * or1k-opc.h: Regenerate. | |
488 | * or1k-opinst.c: Regenerate. | |
489 | ||
3b646889 AM |
490 | 2020-05-11 Alan Modra <amodra@gmail.com> |
491 | ||
492 | * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp, | |
493 | xsmaxcqp, xsmincqp. | |
494 | ||
9cc4ce88 AM |
495 | 2020-05-11 Alan Modra <amodra@gmail.com> |
496 | ||
497 | * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx, | |
498 | stxvrbx, stxvrhx, stxvrwx, stxvrdx. | |
499 | ||
5d57bc3f AM |
500 | 2020-05-11 Alan Modra <amodra@gmail.com> |
501 | ||
502 | * ppc-opc.c (powerpc_opcodes): Add xvtlsbb. | |
503 | ||
66ef5847 AM |
504 | 2020-05-11 Alan Modra <amodra@gmail.com> |
505 | ||
506 | * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr, | |
507 | vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr.. | |
508 | ||
4f3e9537 PB |
509 | 2020-05-11 Peter Bergner <bergner@linux.ibm.com> |
510 | ||
511 | * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New | |
512 | mnemonics. | |
513 | ||
ec40e91c AM |
514 | 2020-05-11 Alan Modra <amodra@gmail.com> |
515 | ||
516 | * ppc-opc.c (UIM8, P_U8XX4_MASK): Define. | |
517 | (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm, | |
518 | vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm. | |
519 | (prefix_opcodes): Add xxeval. | |
520 | ||
d7e97a76 AM |
521 | 2020-05-11 Alan Modra <amodra@gmail.com> |
522 | ||
523 | * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm, | |
524 | xxgenpcvwm, xxgenpcvdm. | |
525 | ||
fdefed7c AM |
526 | 2020-05-11 Alan Modra <amodra@gmail.com> |
527 | ||
528 | * ppc-opc.c (MP, VXVAM_MASK): Define. | |
529 | (VXVAPS_MASK): Use VXVA_MASK. | |
530 | (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm, | |
531 | vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm, | |
532 | vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm, | |
533 | vcntmbb, vcntmbh, vcntmbw, vcntmbd. | |
534 | ||
aa3c112f AM |
535 | 2020-05-11 Alan Modra <amodra@gmail.com> |
536 | Peter Bergner <bergner@linux.ibm.com> | |
537 | ||
538 | * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a): | |
539 | New functions. | |
540 | (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK, | |
541 | YMSK2, XA6a, XA6ap, XB6a entries. | |
542 | (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define | |
543 | (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define. | |
544 | (PPCVSX4): Define. | |
545 | (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz, | |
546 | xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, | |
547 | xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, | |
548 | xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np, | |
549 | xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp, | |
550 | xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn, | |
551 | xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16. | |
552 | (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp, | |
553 | pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8, | |
554 | pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2, | |
555 | pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp, | |
556 | pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp, | |
557 | pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn, | |
558 | pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn. | |
559 | ||
6edbfd3b AM |
560 | 2020-05-11 Alan Modra <amodra@gmail.com> |
561 | ||
562 | * ppc-opc.c (insert_imm32, extract_imm32): New functions. | |
563 | (insert_xts, extract_xts): New functions. | |
564 | (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define. | |
565 | (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define. | |
566 | (VXRC_MASK, VXSH_MASK): Define. | |
567 | (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx, | |
568 | vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx, | |
569 | vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx, | |
570 | vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx, | |
571 | vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq. | |
572 | (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb, | |
573 | xxblendvh, xxblendvw, xxblendvd, xxpermx. | |
574 | ||
c7d7aea2 AM |
575 | 2020-05-11 Alan Modra <amodra@gmail.com> |
576 | ||
577 | * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi, | |
578 | vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd, | |
579 | vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd, | |
580 | vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz, | |
581 | xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq. | |
582 | ||
94ba9882 AM |
583 | 2020-05-11 Alan Modra <amodra@gmail.com> |
584 | ||
585 | * ppc-opc.c (insert_xtp, extract_xtp): New functions. | |
586 | (XTP, DQXP, DQXP_MASK): Define. | |
587 | (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx. | |
588 | (prefix_opcodes): Add plxvp and pstxvp. | |
589 | ||
f4791f1a AM |
590 | 2020-05-11 Alan Modra <amodra@gmail.com> |
591 | ||
592 | * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld, | |
593 | vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw, | |
594 | vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd. | |
595 | ||
3ff0a5ba PB |
596 | 2020-05-11 Peter Bergner <bergner@linux.ibm.com> |
597 | ||
598 | * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics. | |
599 | ||
afef4fe9 PB |
600 | 2020-05-11 Peter Bergner <bergner@linux.ibm.com> |
601 | ||
602 | * ppc-opc.c (insert_l1opt, extract_l1opt): New functions. | |
603 | (L1OPT): Define. | |
604 | (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10. | |
605 | ||
1224c05d PB |
606 | 2020-05-11 Peter Bergner <bergner@linux.ibm.com> |
607 | ||
608 | * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand. | |
609 | ||
6bbb0c05 AM |
610 | 2020-05-11 Alan Modra <amodra@gmail.com> |
611 | ||
612 | * ppc-dis.c (powerpc_init_dialect): Default to "power10". | |
613 | ||
7c1f4227 AM |
614 | 2020-05-11 Alan Modra <amodra@gmail.com> |
615 | ||
616 | * ppc-dis.c (ppc_opts): Add "power10" entry. | |
617 | (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming. | |
618 | * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses. | |
619 | ||
73199c2b NC |
620 | 2020-05-11 Nick Clifton <nickc@redhat.com> |
621 | ||
622 | * po/fr.po: Updated French translation. | |
623 | ||
09c1e68a AC |
624 | 2020-04-30 Alex Coplan <alex.coplan@arm.com> |
625 | ||
626 | * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2. | |
627 | * aarch64-opc.c (fields): Add entry for FLD_imm16_2. | |
628 | (operand_general_constraint_met_p): validate | |
629 | AARCH64_OPND_UNDEFINED. | |
630 | * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry | |
631 | for FLD_imm16_2. | |
632 | * aarch64-asm-2.c: Regenerated. | |
633 | * aarch64-dis-2.c: Regenerated. | |
634 | * aarch64-opc-2.c: Regenerated. | |
635 | ||
9654d51a NC |
636 | 2020-04-29 Nick Clifton <nickc@redhat.com> |
637 | ||
638 | PR 22699 | |
639 | * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC | |
640 | and SETRC insns. | |
641 | ||
c2e71e57 NC |
642 | 2020-04-29 Nick Clifton <nickc@redhat.com> |
643 | ||
644 | * po/sv.po: Updated Swedish translation. | |
645 | ||
5c936ef5 NC |
646 | 2020-04-29 Nick Clifton <nickc@redhat.com> |
647 | ||
648 | PR 22699 | |
649 | * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use | |
650 | IMM0_8S for arithmetic insns and IMM0_8U for logical insns. | |
651 | * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add | |
652 | IMM0_8U case. | |
653 | ||
bb2a1453 AS |
654 | 2020-04-21 Andreas Schwab <schwab@linux-m68k.org> |
655 | ||
656 | PR 25848 | |
657 | * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of | |
658 | cmpi only on m68020up and cpu32. | |
659 | ||
c2e5c986 SD |
660 | 2020-04-20 Sudakshina Das <sudi.das@arm.com> |
661 | ||
662 | * aarch64-asm.c (aarch64_ins_none): New. | |
663 | * aarch64-asm.h (ins_none): New declaration. | |
664 | * aarch64-dis.c (aarch64_ext_none): New. | |
665 | * aarch64-dis.h (ext_none): New declaration. | |
666 | * aarch64-opc.c (aarch64_print_operand): Update case for | |
667 | AARCH64_OPND_BARRIER_PSB. | |
668 | * aarch64-tbl.h (aarch64_opcode_table): Add tsb. | |
669 | (AARCH64_OPERANDS): Update inserter/extracter for | |
670 | AARCH64_OPND_BARRIER_PSB to use new dummy functions. | |
671 | * aarch64-asm-2.c: Regenerated. | |
672 | * aarch64-dis-2.c: Regenerated. | |
673 | * aarch64-opc-2.c: Regenerated. | |
674 | ||
8a6e1d1d SD |
675 | 2020-04-20 Sudakshina Das <sudi.das@arm.com> |
676 | ||
677 | * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove. | |
678 | (aarch64_feature_ras, RAS): Likewise. | |
679 | (aarch64_feature_stat_profile, STAT_PROFILE): Likewise. | |
680 | (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716, | |
681 | autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp, | |
682 | autiaz, autiasp, autibz, autibsp to be CORE_INSN. | |
683 | * aarch64-asm-2.c: Regenerated. | |
684 | * aarch64-dis-2.c: Regenerated. | |
685 | * aarch64-opc-2.c: Regenerated. | |
686 | ||
e409955d FS |
687 | 2020-04-17 Fredrik Strupe <fredrik@strupe.net> |
688 | ||
689 | * arm-dis.c (neon_opcodes): Fix VDUP instruction masks. | |
690 | (print_insn_neon): Support disassembly of conditional | |
691 | instructions. | |
692 | ||
c54a9b56 DF |
693 | 2020-02-16 David Faust <david.faust@oracle.com> |
694 | ||
695 | * bpf-desc.c: Regenerate. | |
696 | * bpf-desc.h: Likewise. | |
697 | * bpf-opc.c: Regenerate. | |
698 | * bpf-opc.h: Likewise. | |
699 | ||
bb651e8b CL |
700 | 2020-04-07 Lili Cui <lili.cui@intel.com> |
701 | ||
702 | * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1, | |
703 | (prefix_table): New instructions (see prefixes above). | |
704 | (rm_table): Likewise | |
705 | * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS, | |
706 | CPU_ANY_TSXLDTRK_FLAGS. | |
707 | (cpu_flags): Add CpuTSXLDTRK. | |
708 | * i386-opc.h (enum): Add CpuTSXLDTRK. | |
709 | (i386_cpu_flags): Add cputsxldtrk. | |
710 | * i386-opc.tbl: Add XSUSPLDTRK insns. | |
711 | * i386-init.h: Regenerate. | |
712 | * i386-tbl.h: Likewise. | |
713 | ||
4b27d27c L |
714 | 2020-04-02 Lili Cui <lili.cui@intel.com> |
715 | ||
716 | * i386-dis.c (prefix_table): New instructions serialize. | |
717 | * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS, | |
718 | CPU_ANY_SERIALIZE_FLAGS. | |
719 | (cpu_flags): Add CpuSERIALIZE. | |
720 | * i386-opc.h (enum): Add CpuSERIALIZE. | |
721 | (i386_cpu_flags): Add cpuserialize. | |
722 | * i386-opc.tbl: Add SERIALIZE insns. | |
723 | * i386-init.h: Regenerate. | |
724 | * i386-tbl.h: Likewise. | |
725 | ||
832a5807 AM |
726 | 2020-03-26 Alan Modra <amodra@gmail.com> |
727 | ||
728 | * disassemble.h (opcodes_assert): Declare. | |
729 | (OPCODES_ASSERT): Define. | |
730 | * disassemble.c: Don't include assert.h. Include opintl.h. | |
731 | (opcodes_assert): New function. | |
732 | * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT. | |
733 | (bfd_h8_disassemble): Reduce size of data array. Correctly | |
734 | calculate maxlen. Omit insn decoding when insn length exceeds | |
735 | maxlen. Exit from nibble loop when looking for E, before | |
736 | accessing next data byte. Move processing of E outside loop. | |
737 | Replace tests of maxlen in loop with assertions. | |
738 | ||
4c4addbe AM |
739 | 2020-03-26 Alan Modra <amodra@gmail.com> |
740 | ||
741 | * arc-dis.c (find_format): Init needs_limm. Simplify use of limm. | |
742 | ||
a18cd0ca AM |
743 | 2020-03-25 Alan Modra <amodra@gmail.com> |
744 | ||
745 | * z80-dis.c (suffix): Init mybuf. | |
746 | ||
57cb32b3 AM |
747 | 2020-03-22 Alan Modra <amodra@gmail.com> |
748 | ||
749 | * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that | |
750 | successflly read from section. | |
751 | ||
beea5cc1 AM |
752 | 2020-03-22 Alan Modra <amodra@gmail.com> |
753 | ||
754 | * arc-dis.c (find_format): Use ISO C string concatenation rather | |
755 | than line continuation within a string. Don't access needs_limm | |
756 | before testing opcode != NULL. | |
757 | ||
03704c77 AM |
758 | 2020-03-22 Alan Modra <amodra@gmail.com> |
759 | ||
760 | * ns32k-dis.c (print_insn_arg): Update comment. | |
761 | (print_insn_ns32k): Reduce size of index_offset array, and | |
762 | initialize, passing -1 to print_insn_arg for args that are not | |
763 | an index. Don't exit arg loop early. Abort on bad arg number. | |
764 | ||
d1023b5d AM |
765 | 2020-03-22 Alan Modra <amodra@gmail.com> |
766 | ||
767 | * s12z-dis.c (abstract_read_memory): Don't print error on EOI. | |
768 | * s12z-opc.c: Formatting. | |
769 | (operands_f): Return an int. | |
770 | (opr_n_bytes_p1): Return -1 on reaching buffer memory limit. | |
771 | (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes), | |
772 | (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes), | |
773 | (exg_sex_discrim): Likewise. | |
774 | (create_immediate_operand, create_bitfield_operand), | |
775 | (create_register_operand_with_size, create_register_all_operand), | |
776 | (create_register_all16_operand, create_simple_memory_operand), | |
777 | (create_memory_operand, create_memory_auto_operand): Don't | |
778 | segfault on malloc failure. | |
779 | (z_ext24_decode): Return an int status, negative on fail, zero | |
780 | on success. | |
781 | (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2), | |
782 | (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base), | |
783 | (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7), | |
784 | (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x), | |
785 | (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode), | |
786 | (mov_imm_opr, ld_18bit_decode, exg_sex_decode), | |
787 | (loop_primitive_decode, shift_decode, psh_pul_decode), | |
788 | (bit_field_decode): Similarly. | |
789 | (z_decode_signed_value, decode_signed_value): Similarly. Add arg | |
790 | to return value, update callers. | |
791 | (x_opr_decode_with_size): Check all reads, returning NULL on fail. | |
792 | Don't segfault on NULL operand. | |
793 | (decode_operation): Return OP_INVALID on first fail. | |
794 | (decode_s12z): Check all reads, returning -1 on fail. | |
795 | ||
340f3ac8 AM |
796 | 2020-03-20 Alan Modra <amodra@gmail.com> |
797 | ||
798 | * metag-dis.c (print_insn_metag): Don't ignore status from | |
799 | read_memory_func. | |
800 | ||
fe90ae8a AM |
801 | 2020-03-20 Alan Modra <amodra@gmail.com> |
802 | ||
803 | * nds32-dis.c (print_insn_nds32): Remove unnecessary casts. | |
804 | Initialize parts of buffer not written when handling a possible | |
805 | 2-byte insn at end of section. Don't attempt decoding of such | |
806 | an insn by the 4-byte machinery. | |
807 | ||
833d919c AM |
808 | 2020-03-20 Alan Modra <amodra@gmail.com> |
809 | ||
810 | * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of | |
811 | partially filled buffer. Prevent lookup of 4-byte insns when | |
812 | only VLE 2-byte insns are possible due to section size. Print | |
813 | ".word" rather than ".long" for 2-byte leftovers. | |
814 | ||
327ef784 NC |
815 | 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com> |
816 | ||
817 | PR 25641 | |
818 | * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes. | |
819 | ||
1673df32 JB |
820 | 2020-03-13 Jan Beulich <jbeulich@suse.com> |
821 | ||
822 | * i386-dis.c (X86_64_0D): Rename to ... | |
823 | (X86_64_0E): ... this. | |
824 | ||
384f3689 L |
825 | 2020-03-09 H.J. Lu <hongjiu.lu@intel.com> |
826 | ||
827 | * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP). | |
828 | * Makefile.in: Regenerated. | |
829 | ||
865e2027 JB |
830 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
831 | ||
832 | * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp* | |
833 | 3-operand pseudos. | |
834 | * i386-tbl.h: Re-generate. | |
835 | ||
2f13234b JB |
836 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
837 | ||
838 | * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*, | |
839 | vprot*, vpsha*, and vpshl*. | |
840 | * i386-tbl.h: Re-generate. | |
841 | ||
3fabc179 JB |
842 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
843 | ||
844 | * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps, | |
845 | vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops. | |
846 | * i386-tbl.h: Re-generate. | |
847 | ||
3677e4c1 JB |
848 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
849 | ||
850 | * i386-gen.c (set_bitfield): Ignore zero-length field names. | |
851 | * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps, | |
852 | cmpss, cmppd, and cmpsd 2-operand pseudo-ops. | |
853 | * i386-tbl.h: Re-generate. | |
854 | ||
4c4898e8 JB |
855 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
856 | ||
857 | * i386-gen.c (struct template_arg, struct template_instance, | |
858 | struct template_param, struct template, templates, | |
859 | parse_template, expand_templates): New. | |
860 | (process_i386_opcodes): Various local variables moved to | |
861 | expand_templates. Call parse_template and expand_templates. | |
862 | * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc. | |
863 | * i386-tbl.h: Re-generate. | |
864 | ||
bc49bfd8 JB |
865 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
866 | ||
867 | * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph, | |
868 | vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate | |
869 | register and memory source templates. Replace VexW= by VexW* | |
870 | where applicable. | |
871 | * i386-tbl.h: Re-generate. | |
872 | ||
4873e243 JB |
873 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
874 | ||
875 | * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace | |
876 | VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable. | |
877 | * i386-tbl.h: Re-generate. | |
878 | ||
672a349b JB |
879 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
880 | ||
881 | * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax. | |
882 | * i386-tbl.h: Re-generate. | |
883 | ||
4ed21b58 JB |
884 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
885 | ||
886 | * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants. | |
887 | (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps, | |
888 | pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use | |
889 | VexW0 on SSE2AVX variants. | |
890 | (vmovq): Drop NoRex64 from XMM/XMM variants. | |
891 | (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb, | |
892 | vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where | |
893 | applicable use VexW0. | |
894 | * i386-tbl.h: Re-generate. | |
895 | ||
643bb870 JB |
896 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
897 | ||
898 | * i386-gen.c (opcode_modifiers): Remove Rex64 field. | |
899 | * i386-opc.h (Rex64): Delete. | |
900 | (struct i386_opcode_modifier): Remove rex64 field. | |
901 | * i386-opc.tbl (crc32): Drop Rex64. | |
902 | Replace Rex64 with Size64 everywhere else. | |
903 | * i386-tbl.h: Re-generate. | |
904 | ||
a23b33b3 JB |
905 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
906 | ||
907 | * i386-dis.c (OP_E_memory): Exclude recording of used address | |
908 | prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit | |
909 | addressed memory operands for MPX insns. | |
910 | ||
a0497384 JB |
911 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
912 | ||
913 | * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept, | |
914 | invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx, | |
915 | adox, mwaitx, rdpid, movdiri): Add IgnoreSize. | |
916 | (ptwrite): Split into non-64-bit and 64-bit forms. | |
917 | * i386-tbl.h: Re-generate. | |
918 | ||
b630c145 JB |
919 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
920 | ||
921 | * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand | |
922 | template. | |
923 | * i386-tbl.h: Re-generate. | |
924 | ||
a847e322 JB |
925 | 2020-03-04 Jan Beulich <jbeulich@suse.com> |
926 | ||
927 | * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New. | |
928 | (prefix_table): Move vmmcall here. Add vmgexit. | |
929 | (rm_table): Replace vmmcall entry by prefix_table[] escape. | |
930 | * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry. | |
931 | (cpu_flags): Add CpuSEV_ES entry. | |
932 | * i386-opc.h (CpuSEV_ES): New. | |
933 | (union i386_cpu_flags): Add cpusev_es field. | |
934 | * i386-opc.tbl (vmgexit): New. | |
935 | * i386-init.h, i386-tbl.h: Re-generate. | |
936 | ||
3cd7f3e3 L |
937 | 2020-03-03 H.J. Lu <hongjiu.lu@intel.com> |
938 | ||
939 | * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize | |
940 | with MnemonicSize. | |
941 | * i386-opc.h (IGNORESIZE): New. | |
942 | (DEFAULTSIZE): Likewise. | |
943 | (IgnoreSize): Removed. | |
944 | (DefaultSize): Likewise. | |
945 | (MnemonicSize): New. | |
946 | (i386_opcode_modifier): Replace ignoresize/defaultsize with | |
947 | mnemonicsize. | |
948 | * i386-opc.tbl (IgnoreSize): New. | |
949 | (DefaultSize): Likewise. | |
950 | * i386-tbl.h: Regenerated. | |
951 | ||
b8ba1385 SB |
952 | 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com> |
953 | ||
954 | PR 25627 | |
955 | * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX | |
956 | instructions. | |
957 | ||
10d97a0f L |
958 | 2020-03-03 H.J. Lu <hongjiu.lu@intel.com> |
959 | ||
960 | PR gas/25622 | |
961 | * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd, | |
962 | vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax. | |
963 | * i386-tbl.h: Regenerated. | |
964 | ||
dc1e8a47 AM |
965 | 2020-02-26 Alan Modra <amodra@gmail.com> |
966 | ||
967 | * aarch64-asm.c: Indent labels correctly. | |
968 | * aarch64-dis.c: Likewise. | |
969 | * aarch64-gen.c: Likewise. | |
970 | * aarch64-opc.c: Likewise. | |
971 | * alpha-dis.c: Likewise. | |
972 | * i386-dis.c: Likewise. | |
973 | * nds32-asm.c: Likewise. | |
974 | * nfp-dis.c: Likewise. | |
975 | * visium-dis.c: Likewise. | |
976 | ||
265b4673 CZ |
977 | 2020-02-25 Claudiu Zissulescu <claziss@gmail.com> |
978 | ||
979 | * arc-regs.h (int_vector_base): Make it available for all ARC | |
980 | CPUs. | |
981 | ||
bd0cf5a6 NC |
982 | 2020-02-20 Nelson Chu <nelson.chu@sifive.com> |
983 | ||
984 | * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is | |
985 | changed. | |
986 | ||
fa164239 JW |
987 | 2020-02-19 Nelson Chu <nelson.chu@sifive.com> |
988 | ||
989 | * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed | |
990 | c.mv/c.li if rs1 is zero. | |
991 | ||
272a84b1 L |
992 | 2020-02-17 H.J. Lu <hongjiu.lu@intel.com> |
993 | ||
994 | * i386-gen.c (cpu_flag_init): Replace CpuABM with | |
995 | CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add | |
996 | CPU_POPCNT_FLAGS. | |
997 | (cpu_flags): Remove CpuABM. Add CpuPOPCNT. | |
998 | * i386-opc.h (CpuABM): Removed. | |
999 | (CpuPOPCNT): New. | |
1000 | (i386_cpu_flags): Remove cpuabm. Add cpupopcnt. | |
1001 | * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on | |
1002 | popcnt. Remove CpuABM from lzcnt. | |
1003 | * i386-init.h: Regenerated. | |
1004 | * i386-tbl.h: Likewise. | |
1005 | ||
1f730c46 JB |
1006 | 2020-02-17 Jan Beulich <jbeulich@suse.com> |
1007 | ||
1008 | * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss): | |
1009 | Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/ | |
1010 | VexW1 instead of open-coding them. | |
1011 | * i386-tbl.h: Re-generate. | |
1012 | ||
c8f8eebc JB |
1013 | 2020-02-17 Jan Beulich <jbeulich@suse.com> |
1014 | ||
1015 | * i386-opc.tbl (AddrPrefixOpReg): Define. | |
1016 | (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx, | |
1017 | umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64 | |
1018 | templates. Drop NoRex64. | |
1019 | * i386-tbl.h: Re-generate. | |
1020 | ||
b9915cbc JB |
1021 | 2020-02-17 Jan Beulich <jbeulich@suse.com> |
1022 | ||
1023 | PR gas/6518 | |
1024 | * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq, | |
1025 | vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms | |
1026 | into Intel syntax instance (with Unpsecified) and AT&T one | |
1027 | (without). | |
1028 | (vcvtneps2bf16): Likewise, along with folding the two so far | |
1029 | separate ones. | |
1030 | * i386-tbl.h: Re-generate. | |
1031 | ||
ce504911 L |
1032 | 2020-02-16 H.J. Lu <hongjiu.lu@intel.com> |
1033 | ||
1034 | * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from | |
1035 | CPU_ANY_SSE4A_FLAGS. | |
1036 | ||
dabec65d AM |
1037 | 2020-02-17 Alan Modra <amodra@gmail.com> |
1038 | ||
1039 | * i386-gen.c (cpu_flag_init): Correct last change. | |
1040 | ||
af5c13b0 L |
1041 | 2020-02-16 H.J. Lu <hongjiu.lu@intel.com> |
1042 | ||
1043 | * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove | |
1044 | CPU_ANY_SSE4_FLAGS. | |
1045 | ||
6867aac0 L |
1046 | 2020-02-14 H.J. Lu <hongjiu.lu@intel.com> |
1047 | ||
1048 | * i386-opc.tbl (movsx): Remove Intel syntax comments. | |
1049 | (movzx): Likewise. | |
1050 | ||
65fca059 JB |
1051 | 2020-02-14 Jan Beulich <jbeulich@suse.com> |
1052 | ||
1053 | PR gas/25438 | |
1054 | * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as | |
1055 | destination for Cpu64-only variant. | |
1056 | (movzx): Fold patterns. | |
1057 | * i386-tbl.h: Re-generate. | |
1058 | ||
7deea9aa JB |
1059 | 2020-02-13 Jan Beulich <jbeulich@suse.com> |
1060 | ||
1061 | * i386-gen.c (cpu_flag_init): Move CpuSSE4a from | |
1062 | CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add | |
1063 | CPU_ANY_SSE4_FLAGS entry. | |
1064 | * i386-init.h: Re-generate. | |
1065 | ||
6c0946d0 JB |
1066 | 2020-02-12 Jan Beulich <jbeulich@suse.com> |
1067 | ||
1068 | * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form | |
1069 | with Unspecified, making the present one AT&T syntax only. | |
1070 | * i386-tbl.h: Re-generate. | |
1071 | ||
ddb56fe6 JB |
1072 | 2020-02-12 Jan Beulich <jbeulich@suse.com> |
1073 | ||
1074 | * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants. | |
1075 | * i386-tbl.h: Re-generate. | |
1076 | ||
5990e377 JB |
1077 | 2020-02-12 Jan Beulich <jbeulich@suse.com> |
1078 | ||
1079 | PR gas/24546 | |
1080 | * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode. | |
1081 | * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into | |
1082 | Amd64 and Intel64 templates. | |
1083 | (call, jmp): Likewise for far indirect variants. Dro | |
1084 | Unspecified. | |
1085 | * i386-tbl.h: Re-generate. | |
1086 | ||
50128d0c JB |
1087 | 2020-02-11 Jan Beulich <jbeulich@suse.com> |
1088 | ||
1089 | * i386-gen.c (opcode_modifiers): Remove ShortForm entry. | |
1090 | * i386-opc.h (ShortForm): Delete. | |
1091 | (struct i386_opcode_modifier): Remove shortform field. | |
1092 | * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld, | |
1093 | fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub, | |
1094 | fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp, | |
1095 | ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq): | |
1096 | Drop ShortForm. | |
1097 | * i386-tbl.h: Re-generate. | |
1098 | ||
1e05b5c4 JB |
1099 | 2020-02-11 Jan Beulich <jbeulich@suse.com> |
1100 | ||
1101 | * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip, | |
1102 | fucompi): Drop ShortForm from operand-less templates. | |
1103 | * i386-tbl.h: Re-generate. | |
1104 | ||
2f5dd314 AM |
1105 | 2020-02-11 Alan Modra <amodra@gmail.com> |
1106 | ||
1107 | * cgen-ibld.in (extract_normal): Set *valuep on all return paths. | |
1108 | * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c, | |
1109 | * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c, | |
1110 | * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c, | |
1111 | * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate. | |
1112 | ||
5aae9ae9 MM |
1113 | 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com> |
1114 | ||
1115 | * arm-dis.c (print_insn_cde): Define 'V' parse character. | |
1116 | (cde_opcodes): Add VCX* instructions. | |
1117 | ||
4934a27c MM |
1118 | 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> |
1119 | Matthew Malcomson <matthew.malcomson@arm.com> | |
1120 | ||
1121 | * arm-dis.c (struct cdeopcode32): New. | |
1122 | (CDE_OPCODE): New macro. | |
1123 | (cde_opcodes): New disassembly table. | |
1124 | (regnames): New option to table. | |
1125 | (cde_coprocs): New global variable. | |
1126 | (print_insn_cde): New | |
1127 | (print_insn_thumb32): Use print_insn_cde. | |
1128 | (parse_arm_disassembler_options): Parse coprocN args. | |
1129 | ||
4b5aaf5f L |
1130 | 2020-02-10 H.J. Lu <hongjiu.lu@intel.com> |
1131 | ||
1132 | PR gas/25516 | |
1133 | * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64 | |
1134 | with ISA64. | |
1135 | * i386-opc.h (AMD64): Removed. | |
1136 | (Intel64): Likewose. | |
1137 | (AMD64): New. | |
1138 | (INTEL64): Likewise. | |
1139 | (INTEL64ONLY): Likewise. | |
1140 | (i386_opcode_modifier): Replace amd64 and intel64 with isa64. | |
1141 | * i386-opc.tbl (Amd64): New. | |
1142 | (Intel64): Likewise. | |
1143 | (Intel64Only): Likewise. | |
1144 | Replace AMD64 with Amd64. Update sysenter/sysenter with | |
1145 | Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter. | |
1146 | * i386-tbl.h: Regenerated. | |
1147 | ||
9fc0b501 SB |
1148 | 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com> |
1149 | ||
1150 | PR 25469 | |
1151 | * z80-dis.c: Add support for GBZ80 opcodes. | |
1152 | ||
c5d7be0c AM |
1153 | 2020-02-04 Alan Modra <amodra@gmail.com> |
1154 | ||
1155 | * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned. | |
1156 | ||
44e4546f AM |
1157 | 2020-02-03 Alan Modra <amodra@gmail.com> |
1158 | ||
1159 | * m32c-ibld.c: Regenerate. | |
1160 | ||
b2b1453a AM |
1161 | 2020-02-01 Alan Modra <amodra@gmail.com> |
1162 | ||
1163 | * frv-ibld.c: Regenerate. | |
1164 | ||
4102be5c JB |
1165 | 2020-01-31 Jan Beulich <jbeulich@suse.com> |
1166 | ||
1167 | * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete. | |
1168 | (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label. | |
1169 | (OP_E_memory): Replace xmm_mdq_mode case label by | |
1170 | vex_scalar_w_dq_mode one. | |
1171 | * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar. | |
1172 | ||
825bd36c JB |
1173 | 2020-01-31 Jan Beulich <jbeulich@suse.com> |
1174 | ||
1175 | * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete. | |
1176 | (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode, | |
1177 | vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments. | |
1178 | (intel_operand_size): Drop vex_w_dq_mode case label. | |
1179 | ||
c3036ed0 RS |
1180 | 2020-01-31 Richard Sandiford <richard.sandiford@arm.com> |
1181 | ||
1182 | * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt. | |
1183 | Remove C_SCAN_MOVPRFX for SVE bfcvtnt. | |
1184 | ||
0c115f84 AM |
1185 | 2020-01-30 Alan Modra <amodra@gmail.com> |
1186 | ||
1187 | * m32c-ibld.c: Regenerate. | |
1188 | ||
bd434cc4 JM |
1189 | 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> |
1190 | ||
1191 | * bpf-opc.c: Regenerate. | |
1192 | ||
aeab2b26 JB |
1193 | 2020-01-30 Jan Beulich <jbeulich@suse.com> |
1194 | ||
1195 | * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators. | |
1196 | (dis386): Use them to replace C2/C3 table entries. | |
1197 | (x86_64_table): Add X86_64_C2 and X86_64_C3 entries. | |
1198 | * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64 | |
1199 | ones. Use Size64 instead of DefaultSize on Intel64 ones. | |
1200 | * i386-tbl.h: Re-generate. | |
1201 | ||
62b3f548 JB |
1202 | 2020-01-30 Jan Beulich <jbeulich@suse.com> |
1203 | ||
1204 | * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword | |
1205 | forms. | |
1206 | (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop | |
1207 | DefaultSize. | |
1208 | * i386-tbl.h: Re-generate. | |
1209 | ||
1bd8ae10 AM |
1210 | 2020-01-30 Alan Modra <amodra@gmail.com> |
1211 | ||
1212 | * tic4x-dis.c (tic4x_dp): Make unsigned. | |
1213 | ||
bc31405e L |
1214 | 2020-01-27 H.J. Lu <hongjiu.lu@intel.com> |
1215 | Jan Beulich <jbeulich@suse.com> | |
1216 | ||
1217 | PR binutils/25445 | |
1218 | * i386-dis.c (MOVSXD_Fixup): New function. | |
1219 | (movsxd_mode): New enum. | |
1220 | (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd. | |
1221 | (intel_operand_size): Handle movsxd_mode. | |
1222 | (OP_E_register): Likewise. | |
1223 | (OP_G): Likewise. | |
1224 | * i386-opc.tbl: Remove Rex64 and allow 32-bit destination | |
1225 | register on movsxd. Add movsxd with 16-bit destination register | |
1226 | for AMD64 and Intel64 ISAs. | |
1227 | * i386-tbl.h: Regenerated. | |
1228 | ||
7568c93b TC |
1229 | 2020-01-27 Tamar Christina <tamar.christina@arm.com> |
1230 | ||
1231 | PR 25403 | |
1232 | * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv. | |
1233 | * aarch64-asm-2.c: Regenerate | |
1234 | * aarch64-dis-2.c: Likewise. | |
1235 | * aarch64-opc-2.c: Likewise. | |
1236 | ||
c006a730 JB |
1237 | 2020-01-21 Jan Beulich <jbeulich@suse.com> |
1238 | ||
1239 | * i386-opc.tbl (sysret): Drop DefaultSize. | |
1240 | * i386-tbl.h: Re-generate. | |
1241 | ||
c906a69a JB |
1242 | 2020-01-21 Jan Beulich <jbeulich@suse.com> |
1243 | ||
1244 | * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and | |
1245 | Dword. | |
1246 | (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword. | |
1247 | * i386-tbl.h: Re-generate. | |
1248 | ||
26916852 NC |
1249 | 2020-01-20 Nick Clifton <nickc@redhat.com> |
1250 | ||
1251 | * po/de.po: Updated German translation. | |
1252 | * po/pt_BR.po: Updated Brazilian Portuguese translation. | |
1253 | * po/uk.po: Updated Ukranian translation. | |
1254 | ||
4d6cbb64 AM |
1255 | 2020-01-20 Alan Modra <amodra@gmail.com> |
1256 | ||
1257 | * hppa-dis.c (fput_const): Remove useless cast. | |
1258 | ||
2bddb71a AM |
1259 | 2020-01-20 Alan Modra <amodra@gmail.com> |
1260 | ||
1261 | * arm-dis.c (print_insn_arm): Wrap 'T' value. | |
1262 | ||
1b1bb2c6 NC |
1263 | 2020-01-18 Nick Clifton <nickc@redhat.com> |
1264 | ||
1265 | * configure: Regenerate. | |
1266 | * po/opcodes.pot: Regenerate. | |
1267 | ||
ae774686 NC |
1268 | 2020-01-18 Nick Clifton <nickc@redhat.com> |
1269 | ||
1270 | Binutils 2.34 branch created. | |
1271 | ||
07f1f3aa CB |
1272 | 2020-01-17 Christian Biesinger <cbiesinger@google.com> |
1273 | ||
1274 | * opintl.h: Fix spelling error (seperate). | |
1275 | ||
42e04b36 L |
1276 | 2020-01-17 H.J. Lu <hongjiu.lu@intel.com> |
1277 | ||
1278 | * i386-opc.tbl: Add {vex} pseudo prefix. | |
1279 | * i386-tbl.h: Regenerated. | |
1280 | ||
2da2eaf4 AV |
1281 | 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
1282 | ||
1283 | PR 25376 | |
1284 | * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits. | |
1285 | (neon_opcodes): Likewise. | |
1286 | (select_arm_features): Make sure we enable MVE bits when selecting | |
1287 | armv8.1-m.main. Make sure we do not enable MVE bits when not selecting | |
1288 | any architecture. | |
1289 | ||
d0849eed JB |
1290 | 2020-01-16 Jan Beulich <jbeulich@suse.com> |
1291 | ||
1292 | * i386-opc.tbl: Drop stale comment from XOP section. | |
1293 | ||
9cf70a44 JB |
1294 | 2020-01-16 Jan Beulich <jbeulich@suse.com> |
1295 | ||
1296 | * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms. | |
1297 | (extractps): Add VexWIG to SSE2AVX forms. | |
1298 | * i386-tbl.h: Re-generate. | |
1299 | ||
4814632e JB |
1300 | 2020-01-16 Jan Beulich <jbeulich@suse.com> |
1301 | ||
1302 | * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop | |
1303 | Size64 from and use VexW1 on SSE2AVX forms. | |
1304 | (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from | |
1305 | VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1. | |
1306 | * i386-tbl.h: Re-generate. | |
1307 | ||
aad09917 AM |
1308 | 2020-01-15 Alan Modra <amodra@gmail.com> |
1309 | ||
1310 | * tic4x-dis.c (tic4x_version): Make unsigned long. | |
1311 | (optab, optab_special, registernames): New file scope vars. | |
1312 | (tic4x_print_register): Set up registernames rather than | |
1313 | malloc'd registertable. | |
1314 | (tic4x_disassemble): Delete optable and optable_special. Use | |
1315 | optab and optab_special instead. Throw away old optab, | |
1316 | optab_special and registernames when info->mach changes. | |
1317 | ||
7a6bf3be SB |
1318 | 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com> |
1319 | ||
1320 | PR 25377 | |
1321 | * z80-dis.c (suffix): Use .db instruction to generate double | |
1322 | prefix. | |
1323 | ||
ca1eaac0 AM |
1324 | 2020-01-14 Alan Modra <amodra@gmail.com> |
1325 | ||
1326 | * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short | |
1327 | values to unsigned before shifting. | |
1328 | ||
1d67fe3b TT |
1329 | 2020-01-13 Thomas Troeger <tstroege@gmx.de> |
1330 | ||
1331 | * arm-dis.c (print_insn_arm): Fill in insn info fields for control | |
1332 | flow instructions. | |
1333 | (print_insn_thumb16, print_insn_thumb32): Likewise. | |
1334 | (print_insn): Initialize the insn info. | |
1335 | * i386-dis.c (print_insn): Initialize the insn info fields, and | |
1336 | detect jumps. | |
1337 | ||
5e4f7e05 CZ |
1338 | 2012-01-13 Claudiu Zissulescu <claziss@gmail.com> |
1339 | ||
1340 | * arc-opc.c (C_NE): Make it required. | |
1341 | ||
b9fe6b8a CZ |
1342 | 2012-01-13 Claudiu Zissulescu <claziss@gmail.com> |
1343 | ||
1344 | * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo | |
1345 | reserved register name. | |
1346 | ||
90dee485 AM |
1347 | 2020-01-13 Alan Modra <amodra@gmail.com> |
1348 | ||
1349 | * ns32k-dis.c (Is_gen): Use strchr, add 'f'. | |
1350 | (print_insn_ns32k): Adjust ioffset for 'f' index_offset. | |
1351 | ||
febda64f AM |
1352 | 2020-01-13 Alan Modra <amodra@gmail.com> |
1353 | ||
1354 | * wasm32-dis.c (print_insn_wasm32): Localise variables. Store | |
1355 | result of wasm_read_leb128 in a uint64_t and check that bits | |
1356 | are not lost when copying to other locals. Use uint32_t for | |
1357 | most locals. Use PRId64 when printing int64_t. | |
1358 | ||
df08b588 AM |
1359 | 2020-01-13 Alan Modra <amodra@gmail.com> |
1360 | ||
1361 | * score-dis.c: Formatting. | |
1362 | * score7-dis.c: Formatting. | |
1363 | ||
b2c759ce AM |
1364 | 2020-01-13 Alan Modra <amodra@gmail.com> |
1365 | ||
1366 | * score-dis.c (print_insn_score48): Use unsigned variables for | |
1367 | unsigned values. Don't left shift negative values. | |
1368 | (print_insn_score32): Likewise. | |
1369 | * score7-dis.c (print_insn_score32, print_insn_score16): Likewise. | |
1370 | ||
5496abe1 AM |
1371 | 2020-01-13 Alan Modra <amodra@gmail.com> |
1372 | ||
1373 | * tic4x-dis.c (tic4x_print_register): Remove dead code. | |
1374 | ||
202e762b AM |
1375 | 2020-01-13 Alan Modra <amodra@gmail.com> |
1376 | ||
1377 | * fr30-ibld.c: Regenerate. | |
1378 | ||
7ef412cf AM |
1379 | 2020-01-13 Alan Modra <amodra@gmail.com> |
1380 | ||
1381 | * xgate-dis.c (print_insn): Don't left shift signed value. | |
1382 | (ripBits): Formatting, use 1u. | |
1383 | ||
7f578b95 AM |
1384 | 2020-01-10 Alan Modra <amodra@gmail.com> |
1385 | ||
1386 | * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned. | |
1387 | * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval. | |
1388 | ||
441af85b AM |
1389 | 2020-01-10 Alan Modra <amodra@gmail.com> |
1390 | ||
1391 | * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG, | |
1392 | and XRREG value earlier to avoid a shift with negative exponent. | |
1393 | * m10200-dis.c (disassemble): Similarly. | |
1394 | ||
bce58db4 NC |
1395 | 2020-01-09 Nick Clifton <nickc@redhat.com> |
1396 | ||
1397 | PR 25224 | |
1398 | * z80-dis.c (ld_ii_ii): Use correct cast. | |
1399 | ||
40c75bc8 SB |
1400 | 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com> |
1401 | ||
1402 | PR 25224 | |
1403 | * z80-dis.c (ld_ii_ii): Use character constant when checking | |
1404 | opcode byte value. | |
1405 | ||
d835a58b JB |
1406 | 2020-01-09 Jan Beulich <jbeulich@suse.com> |
1407 | ||
1408 | * i386-dis.c (SEP_Fixup): New. | |
1409 | (SEP): Define. | |
1410 | (dis386_twobyte): Use it for sysenter/sysexit. | |
1411 | (enum x86_64_isa): Change amd64 enumerator to value 1. | |
1412 | (OP_J): Compare isa64 against intel64 instead of amd64. | |
1413 | * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64 | |
1414 | forms. | |
1415 | * i386-tbl.h: Re-generate. | |
1416 | ||
030a2e78 AM |
1417 | 2020-01-08 Alan Modra <amodra@gmail.com> |
1418 | ||
1419 | * z8k-dis.c: Include libiberty.h | |
1420 | (instr_data_s): Make max_fetched unsigned. | |
1421 | (z8k_lookup_instr): Make nibl_index and tabl_index unsigned. | |
1422 | Don't exceed byte_info bounds. | |
1423 | (output_instr): Make num_bytes unsigned. | |
1424 | (unpack_instr): Likewise for nibl_count and loop. | |
1425 | * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and | |
1426 | idx unsigned. | |
1427 | * z8k-opc.h: Regenerate. | |
1428 | ||
bb82aefe SV |
1429 | 2020-01-07 Shahab Vahedi <shahab@synopsys.com> |
1430 | ||
1431 | * arc-tbl.h (llock): Use 'LLOCK' as class. | |
1432 | (llockd): Likewise. | |
1433 | (scond): Use 'SCOND' as class. | |
1434 | (scondd): Likewise. | |
1435 | (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit. | |
1436 | (scondd): Likewise. | |
1437 | ||
cc6aa1a6 AM |
1438 | 2020-01-06 Alan Modra <amodra@gmail.com> |
1439 | ||
1440 | * m32c-ibld.c: Regenerate. | |
1441 | ||
660e62b1 AM |
1442 | 2020-01-06 Alan Modra <amodra@gmail.com> |
1443 | ||
1444 | PR 25344 | |
1445 | * z80-dis.c (suffix): Don't use a local struct buffer copy. | |
1446 | Peek at next byte to prevent recursion on repeated prefix bytes. | |
1447 | Ensure uninitialised "mybuf" is not accessed. | |
1448 | (print_insn_z80): Don't zero n_fetch and n_used here,.. | |
1449 | (print_insn_z80_buf): ..do it here instead. | |
1450 | ||
c9ae58fe AM |
1451 | 2020-01-04 Alan Modra <amodra@gmail.com> |
1452 | ||
1453 | * m32r-ibld.c: Regenerate. | |
1454 | ||
5f57d4ec AM |
1455 | 2020-01-04 Alan Modra <amodra@gmail.com> |
1456 | ||
1457 | * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value. | |
1458 | ||
2c5c1196 AM |
1459 | 2020-01-04 Alan Modra <amodra@gmail.com> |
1460 | ||
1461 | * crx-dis.c (match_opcode): Avoid shift left of signed value. | |
1462 | ||
2e98c6c5 AM |
1463 | 2020-01-04 Alan Modra <amodra@gmail.com> |
1464 | ||
1465 | * d30v-dis.c (print_insn): Avoid signed overflow in left shift. | |
1466 | ||
567dfba2 JB |
1467 | 2020-01-03 Jan Beulich <jbeulich@suse.com> |
1468 | ||
5437a02a JB |
1469 | * aarch64-tbl.h (aarch64_opcode_table): Use |
1470 | SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}. | |
1471 | ||
1472 | 2020-01-03 Jan Beulich <jbeulich@suse.com> | |
1473 | ||
1474 | * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD | |
567dfba2 JB |
1475 | forms of SUDOT and USDOT. |
1476 | ||
8c45011a JB |
1477 | 2020-01-03 Jan Beulich <jbeulich@suse.com> |
1478 | ||
5437a02a | 1479 | * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from |
8c45011a JB |
1480 | uzip{1,2}. |
1481 | * opcodes/aarch64-dis-2.c: Re-generate. | |
1482 | ||
f4950f76 JB |
1483 | 2020-01-03 Jan Beulich <jbeulich@suse.com> |
1484 | ||
5437a02a | 1485 | * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit |
f4950f76 JB |
1486 | FMMLA encoding. |
1487 | * opcodes/aarch64-dis-2.c: Re-generate. | |
1488 | ||
6655dba2 SB |
1489 | 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com> |
1490 | ||
1491 | * z80-dis.c: Add support for eZ80 and Z80 instructions. | |
1492 | ||
b14ce8bf AM |
1493 | 2020-01-01 Alan Modra <amodra@gmail.com> |
1494 | ||
1495 | Update year range in copyright notice of all files. | |
1496 | ||
0b114740 | 1497 | For older changes see ChangeLog-2019 |
3499769a | 1498 | \f |
0b114740 | 1499 | Copyright (C) 2020 Free Software Foundation, Inc. |
3499769a AM |
1500 | |
1501 | Copying and distribution of this file, with or without modification, | |
1502 | are permitted in any medium without royalty provided the copyright | |
1503 | notice and this notice are preserved. | |
1504 | ||
1505 | Local Variables: | |
1506 | mode: change-log | |
1507 | left-margin: 8 | |
1508 | fill-column: 74 | |
1509 | version-control: never | |
1510 | End: |