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[AArch64] Fix bogus MOVPRFX warning for GPR form of CPY
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
89418844
RS		 12019-07-02 Richard Sandiford <richard.sandiford@arm.com>
2
3 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
4 registers in an instruction prefixed by MOVPRFX.
5
41be57ca
MM		 62019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
7
8 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
9 sve_size_13 icode to account for variant behaviour of
10 pmull{t,b}.
11 * aarch64-dis-2.c: Regenerate.
12 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
13 sve_size_13 icode to account for variant behaviour of
14 pmull{t,b}.
15 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
16 (OP_SVE_VVV_Q_D): Add new qualifier.
17 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
18 (struct aarch64_opcode): Split pmull{t,b} into those requiring
19 AES and those not.
20
9d3bf266
JB		 212019-07-01 Jan Beulich <jbeulich@suse.com>
22
23 * opcodes/i386-gen.c (operand_type_init): Remove
24 OPERAND_TYPE_VEC_IMM4 entry.
25 (operand_types): Remove Vec_Imm4.
26 * opcodes/i386-opc.h (Vec_Imm4): Delete.
27 (union i386_operand_type): Remove vec_imm4.
28 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
29 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
30
c3949f43
JB		 312019-07-01 Jan Beulich <jbeulich@suse.com>
32
33 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
34 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
35 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
36 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
37 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
38 monitorx, mwaitx): Drop ImmExt from operand-less forms.
39 * i386-tbl.h: Re-generate.
40
5641ec01
JB		 412019-07-01 Jan Beulich <jbeulich@suse.com>
42
43 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
44 register operands.
45 * i386-tbl.h: Re-generate.
46
79dec6b7
JB		 472019-07-01 Jan Beulich <jbeulich@suse.com>
48
49 * i386-opc.tbl (C): New.
50 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
51 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
52 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
53 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
54 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
55 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
56 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
57 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
58 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
59 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
60 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
61 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
62 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
63 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
64 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
65 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
66 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
67 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
68 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
69 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
70 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
71 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
72 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
73 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
74 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
75 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
76 flavors.
77 * i386-tbl.h: Re-generate.
78
a0a1771e
JB		 792019-07-01 Jan Beulich <jbeulich@suse.com>
80
81 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
82 register operands.
83 * i386-tbl.h: Re-generate.
84
cd546e7b
JB		 852019-07-01 Jan Beulich <jbeulich@suse.com>
86
87 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
88 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
89 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
90 * i386-tbl.h: Re-generate.
91
e3bba3fc
JB		 922019-07-01 Jan Beulich <jbeulich@suse.com>
93
94 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
95 Disp8MemShift from register only templates.
96 * i386-tbl.h: Re-generate.
97
36cc073e
JB		 982019-07-01 Jan Beulich <jbeulich@suse.com>
99
100 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
101 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
102 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
103 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
104 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
105 EVEX_W_0F11_P_3_M_1): Delete.
106 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
107 EVEX_W_0F11_P_3): New.
108 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
109 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
110 MOD_EVEX_0F11_PREFIX_3 table entries.
111 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
112 PREFIX_EVEX_0F11 table entries.
113 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
114 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
115 EVEX_W_0F11_P_3_M_{0,1} table entries.
116
219920a7
JB		 1172019-07-01 Jan Beulich <jbeulich@suse.com>
118
119 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
120 Delete.
121
e395f487
L		 1222019-06-27 H.J. Lu <hongjiu.lu@intel.com>
123
124 PR binutils/24719
125 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
126 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
127 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
128 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
129 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
130 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
131 EVEX_LEN_0F38C7_R_6_P_2_W_1.
132 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
133 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
134 PREFIX_EVEX_0F38C6_REG_6 entries.
135 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
136 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
137 EVEX_W_0F38C7_R_6_P_2 entries.
138 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
139 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
140 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
141 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
142 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
143 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
144 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
145
2b7bcc87
JB		 1462019-06-27 Jan Beulich <jbeulich@suse.com>
147
148 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
149 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
150 VEX_LEN_0F2D_P_3): Delete.
151 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
152 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
153 (prefix_table): ... here.
154
c1dc7af5
JB		 1552019-06-27 Jan Beulich <jbeulich@suse.com>
156
157 * i386-dis.c (Iq): Delete.
158 (Id): New.
159 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
160 TBM insns.
161 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
162 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
163 (OP_E_memory): Also honor needindex when deciding whether an
164 address size prefix needs printing.
165 (OP_I): Remove handling of q_mode. Add handling of d_mode.
166
d7560e2d
JW		 1672019-06-26 Jim Wilson <jimw@sifive.com>
168
169 PR binutils/24739
170 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
171 Set info->display_endian to info->endian_code.
172
2c703856
JB		 1732019-06-25 Jan Beulich <jbeulich@suse.com>
174
175 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
176 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
177 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
178 OPERAND_TYPE_ACC64 entries.
179 * i386-init.h: Re-generate.
180
54fbadc0
JB		 1812019-06-25 Jan Beulich <jbeulich@suse.com>
182
183 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
184 Delete.
185 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
186 of dqa_mode.
187 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
188 entries here.
189 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
190 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
191
a280ab8e
JB		 1922019-06-25 Jan Beulich <jbeulich@suse.com>
193
194 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
195 variables.
196
e1a1babd
JB		 1972019-06-25 Jan Beulich <jbeulich@suse.com>
198
199 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
200 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
201 movnti.
d7560e2d 202 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 203 * i386-tbl.h: Re-generate.
204
b8364fa7
JB		 2052019-06-25 Jan Beulich <jbeulich@suse.com>
206
207 * i386-opc.tbl (and): Mark Imm8S form for optimization.
208 * i386-tbl.h: Re-generate.
209
ad692897
L		 2102019-06-21 H.J. Lu <hongjiu.lu@intel.com>
211
212 * i386-dis-evex.h: Break into ...
213 * i386-dis-evex-len.h: New file.
214 * i386-dis-evex-mod.h: Likewise.
215 * i386-dis-evex-prefix.h: Likewise.
216 * i386-dis-evex-reg.h: Likewise.
217 * i386-dis-evex-w.h: Likewise.
218 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
219 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
220 i386-dis-evex-mod.h.
221
f0a6222e
L		 2222019-06-19 H.J. Lu <hongjiu.lu@intel.com>
223
224 PR binutils/24700
225 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
226 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
227 EVEX_W_0F385B_P_2.
228 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
229 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
230 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
231 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
232 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
233 EVEX_LEN_0F385B_P_2_W_1.
234 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
235 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
236 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
237 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
238 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
239 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
240 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
241 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
242 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
243 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
244
6e1c90b7
L		 2452019-06-17 H.J. Lu <hongjiu.lu@intel.com>
246
247 PR binutils/24691
248 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
249 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
250 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
251 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
252 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
253 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
254 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
255 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
256 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
257 EVEX_LEN_0F3A43_P_2_W_1.
258 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
259 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
260 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
261 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
262 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
263 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
264 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
265 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
266 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
267 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
268 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
269 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
270
bcc5a6eb
NC		 2712019-06-14 Nick Clifton <nickc@redhat.com>
272
273 * po/fr.po; Updated French translation.
274
e4c4ac46
SH		 2752019-06-13 Stafford Horne <shorne@gmail.com>
276
277 * or1k-asm.c: Regenerated.
278 * or1k-desc.c: Regenerated.
279 * or1k-desc.h: Regenerated.
280 * or1k-dis.c: Regenerated.
281 * or1k-ibld.c: Regenerated.
282 * or1k-opc.c: Regenerated.
283 * or1k-opc.h: Regenerated.
284 * or1k-opinst.c: Regenerated.
285
a0e44ef5
PB		 2862019-06-12 Peter Bergner <bergner@linux.ibm.com>
287
288 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
289
12efd68d
L		 2902019-06-05 H.J. Lu <hongjiu.lu@intel.com>
291
292 PR binutils/24633
293 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
294 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
295 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
296 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
297 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
298 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
299 EVEX_LEN_0F3A1B_P_2_W_1.
300 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
301 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
302 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
303 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
304 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
305 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
306 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
307 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
308
63c6fc6c
L		 3092019-06-04 H.J. Lu <hongjiu.lu@intel.com>
310
311 PR binutils/24626
312 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
313 EVEX.vvvv when disassembling VEX and EVEX instructions.
314 (OP_VEX): Set vex.register_specifier to 0 after readding
315 vex.register_specifier.
316 (OP_Vex_2src_1): Likewise.
317 (OP_Vex_2src_2): Likewise.
318 (OP_LWP_E): Likewise.
319 (OP_EX_Vex): Don't check vex.register_specifier.
320 (OP_XMM_Vex): Likewise.
321
9186c494
L		 3222019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
323 Lili Cui <lili.cui@intel.com>
324
325 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
326 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
327 instructions.
328 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
329 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
330 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
331 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
332 (i386_cpu_flags): Add cpuavx512_vp2intersect.
333 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
334 * i386-init.h: Regenerated.
335 * i386-tbl.h: Likewise.
336
5d79adc4
L		 3372019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
338 Lili Cui <lili.cui@intel.com>
339
340 * doc/c-i386.texi: Document enqcmd.
341 * testsuite/gas/i386/enqcmd-intel.d: New file.
342 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
343 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
344 * testsuite/gas/i386/enqcmd.d: Likewise.
345 * testsuite/gas/i386/enqcmd.s: Likewise.
346 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
347 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
348 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
349 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
350 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
351 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
352 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
353 and x86-64-enqcmd.
354
a9d96ab9
AH		 3552019-06-04 Alan Hayward <alan.hayward@arm.com>
356
357 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
358
4f6d070a
AM		 3592019-06-03 Alan Modra <amodra@gmail.com>
360
361 * ppc-dis.c (prefix_opcd_indices): Correct size.
362
a2f4b66c
L		 3632019-05-28 H.J. Lu <hongjiu.lu@intel.com>
364
365 PR gas/24625
366 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
367 Disp8ShiftVL.
368 * i386-tbl.h: Regenerated.
369
405b5bd8
AM		 3702019-05-24 Alan Modra <amodra@gmail.com>
371
372 * po/POTFILES.in: Regenerate.
373
8acf1435
PB		 3742019-05-24 Peter Bergner <bergner@linux.ibm.com>
375 Alan Modra <amodra@gmail.com>
376
377 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
378 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
379 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
380 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
381 XTOP>): Define and add entries.
382 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
383 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
384 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
385 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
386
dd7efa79
PB		 3872019-05-24 Peter Bergner <bergner@linux.ibm.com>
388 Alan Modra <amodra@gmail.com>
389
390 * ppc-dis.c (ppc_opts): Add "future" entry.
391 (PREFIX_OPCD_SEGS): Define.
392 (prefix_opcd_indices): New array.
393 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
394 (lookup_prefix): New function.
395 (print_insn_powerpc): Handle 64-bit prefix instructions.
396 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
397 (PMRR, POWERXX): Define.
398 (prefix_opcodes): New instruction table.
399 (prefix_num_opcodes): New constant.
400
79472b45
JM		 4012019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
402
403 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
404 * configure: Regenerated.
405 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
406 and cpu/bpf.opc.
407 (HFILES): Add bpf-desc.h and bpf-opc.h.
408 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
409 bpf-ibld.c and bpf-opc.c.
410 (BPF_DEPS): Define.
411 * Makefile.in: Regenerated.
412 * disassemble.c (ARCH_bpf): Define.
413 (disassembler): Add case for bfd_arch_bpf.
414 (disassemble_init_for_target): Likewise.
415 (enum epbf_isa_attr): Define.
416 * disassemble.h: extern print_insn_bpf.
417 * bpf-asm.c: Generated.
418 * bpf-opc.h: Likewise.
419 * bpf-opc.c: Likewise.
420 * bpf-ibld.c: Likewise.
421 * bpf-dis.c: Likewise.
422 * bpf-desc.h: Likewise.
423 * bpf-desc.c: Likewise.
424
ba6cd17f
SD		 4252019-05-21 Sudakshina Das <sudi.das@arm.com>
426
427 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
428 and VMSR with the new operands.
429
e39c1607
SD		 4302019-05-21 Sudakshina Das <sudi.das@arm.com>
431
432 * arm-dis.c (enum mve_instructions): New enum
433 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
434 and cneg.
435 (mve_opcodes): New instructions as above.
436 (is_mve_encoding_conflict): Add cases for csinc, csinv,
437 csneg and csel.
438 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
439
23d00a41
SD		 4402019-05-21 Sudakshina Das <sudi.das@arm.com>
441
442 * arm-dis.c (emun mve_instructions): Updated for new instructions.
443 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
444 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
445 uqshl, urshrl and urshr.
446 (is_mve_okay_in_it): Add new instructions to TRUE list.
447 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
448 (print_insn_mve): Updated to accept new %j,
449 %<bitfield>m and %<bitfield>n patterns.
450
cd4797ee
FS		 4512019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
452
453 * mips-opc.c (mips_builtin_opcodes): Change source register
454 constraint for DAUI.
455
999b073b
NC		 4562019-05-20 Nick Clifton <nickc@redhat.com>
457
458 * po/fr.po: Updated French translation.
459
14b456f2
AV		 4602019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
461 Michael Collison <michael.collison@arm.com>
462
463 * arm-dis.c (thumb32_opcodes): Add new instructions.
464 (enum mve_instructions): Likewise.
465 (enum mve_undefined): Add new reasons.
466 (is_mve_encoding_conflict): Handle new instructions.
467 (is_mve_undefined): Likewise.
468 (is_mve_unpredictable): Likewise.
469 (print_mve_undefined): Likewise.
470 (print_mve_size): Likewise.
471
f49bb598
AV		 4722019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
473 Michael Collison <michael.collison@arm.com>
474
475 * arm-dis.c (thumb32_opcodes): Add new instructions.
476 (enum mve_instructions): Likewise.
477 (is_mve_encoding_conflict): Handle new instructions.
478 (is_mve_undefined): Likewise.
479 (is_mve_unpredictable): Likewise.
480 (print_mve_size): Likewise.
481
56858bea
AV		 4822019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
483 Michael Collison <michael.collison@arm.com>
484
485 * arm-dis.c (thumb32_opcodes): Add new instructions.
486 (enum mve_instructions): Likewise.
487 (is_mve_encoding_conflict): Likewise.
488 (is_mve_unpredictable): Likewise.
489 (print_mve_size): Likewise.
490
e523f101
AV		 4912019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
492 Michael Collison <michael.collison@arm.com>
493
494 * arm-dis.c (thumb32_opcodes): Add new instructions.
495 (enum mve_instructions): Likewise.
496 (is_mve_encoding_conflict): Handle new instructions.
497 (is_mve_undefined): Likewise.
498 (is_mve_unpredictable): Likewise.
499 (print_mve_size): Likewise.
500
66dcaa5d
AV		 5012019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
502 Michael Collison <michael.collison@arm.com>
503
504 * arm-dis.c (thumb32_opcodes): Add new instructions.
505 (enum mve_instructions): Likewise.
506 (is_mve_encoding_conflict): Handle new instructions.
507 (is_mve_undefined): Likewise.
508 (is_mve_unpredictable): Likewise.
509 (print_mve_size): Likewise.
510 (print_insn_mve): Likewise.
511
d052b9b7
AV		 5122019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
513 Michael Collison <michael.collison@arm.com>
514
515 * arm-dis.c (thumb32_opcodes): Add new instructions.
516 (print_insn_thumb32): Handle new instructions.
517
ed63aa17
AV		 5182019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
519 Michael Collison <michael.collison@arm.com>
520
521 * arm-dis.c (enum mve_instructions): Add new instructions.
522 (enum mve_undefined): Add new reasons.
523 (is_mve_encoding_conflict): Handle new instructions.
524 (is_mve_undefined): Likewise.
525 (is_mve_unpredictable): Likewise.
526 (print_mve_undefined): Likewise.
527 (print_mve_size): Likewise.
528 (print_mve_shift_n): Likewise.
529 (print_insn_mve): Likewise.
530
897b9bbc
AV		 5312019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
532 Michael Collison <michael.collison@arm.com>
533
534 * arm-dis.c (enum mve_instructions): Add new instructions.
535 (is_mve_encoding_conflict): Handle new instructions.
536 (is_mve_unpredictable): Likewise.
537 (print_mve_rotate): Likewise.
538 (print_mve_size): Likewise.
539 (print_insn_mve): Likewise.
540
1c8f2df8
AV		 5412019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
542 Michael Collison <michael.collison@arm.com>
543
544 * arm-dis.c (enum mve_instructions): Add new instructions.
545 (is_mve_encoding_conflict): Handle new instructions.
546 (is_mve_unpredictable): Likewise.
547 (print_mve_size): Likewise.
548 (print_insn_mve): Likewise.
549
d3b63143
AV		 5502019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
551 Michael Collison <michael.collison@arm.com>
552
553 * arm-dis.c (enum mve_instructions): Add new instructions.
554 (enum mve_undefined): Add new reasons.
555 (is_mve_encoding_conflict): Handle new instructions.
556 (is_mve_undefined): Likewise.
557 (is_mve_unpredictable): Likewise.
558 (print_mve_undefined): Likewise.
559 (print_mve_size): Likewise.
560 (print_insn_mve): Likewise.
561
14925797
AV		 5622019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
563 Michael Collison <michael.collison@arm.com>
564
565 * arm-dis.c (enum mve_instructions): Add new instructions.
566 (is_mve_encoding_conflict): Handle new instructions.
567 (is_mve_undefined): Likewise.
568 (is_mve_unpredictable): Likewise.
569 (print_mve_size): Likewise.
570 (print_insn_mve): Likewise.
571
c507f10b
AV		 5722019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
573 Michael Collison <michael.collison@arm.com>
574
575 * arm-dis.c (enum mve_instructions): Add new instructions.
576 (enum mve_unpredictable): Add new reasons.
577 (enum mve_undefined): Likewise.
578 (is_mve_okay_in_it): Handle new isntructions.
579 (is_mve_encoding_conflict): Likewise.
580 (is_mve_undefined): Likewise.
581 (is_mve_unpredictable): Likewise.
582 (print_mve_vmov_index): Likewise.
583 (print_simd_imm8): Likewise.
584 (print_mve_undefined): Likewise.
585 (print_mve_unpredictable): Likewise.
586 (print_mve_size): Likewise.
587 (print_insn_mve): Likewise.
588
bf0b396d
AV		 5892019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
590 Michael Collison <michael.collison@arm.com>
591
592 * arm-dis.c (enum mve_instructions): Add new instructions.
593 (enum mve_unpredictable): Add new reasons.
594 (enum mve_undefined): Likewise.
595 (is_mve_encoding_conflict): Handle new instructions.
596 (is_mve_undefined): Likewise.
597 (is_mve_unpredictable): Likewise.
598 (print_mve_undefined): Likewise.
599 (print_mve_unpredictable): Likewise.
600 (print_mve_rounding_mode): Likewise.
601 (print_mve_vcvt_size): Likewise.
602 (print_mve_size): Likewise.
603 (print_insn_mve): Likewise.
604
ef1576a1
AV		 6052019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
606 Michael Collison <michael.collison@arm.com>
607
608 * arm-dis.c (enum mve_instructions): Add new instructions.
609 (enum mve_unpredictable): Add new reasons.
610 (enum mve_undefined): Likewise.
611 (is_mve_undefined): Handle new instructions.
612 (is_mve_unpredictable): Likewise.
613 (print_mve_undefined): Likewise.
614 (print_mve_unpredictable): Likewise.
615 (print_mve_size): Likewise.
616 (print_insn_mve): Likewise.
617
aef6d006
AV		 6182019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
619 Michael Collison <michael.collison@arm.com>
620
621 * arm-dis.c (enum mve_instructions): Add new instructions.
622 (enum mve_undefined): Add new reasons.
623 (insns): Add new instructions.
624 (is_mve_encoding_conflict):
625 (print_mve_vld_str_addr): New print function.
626 (is_mve_undefined): Handle new instructions.
627 (is_mve_unpredictable): Likewise.
628 (print_mve_undefined): Likewise.
629 (print_mve_size): Likewise.
630 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
631 (print_insn_mve): Handle new operands.
632
04d54ace
AV		 6332019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
634 Michael Collison <michael.collison@arm.com>
635
636 * arm-dis.c (enum mve_instructions): Add new instructions.
637 (enum mve_unpredictable): Add new reasons.
638 (is_mve_encoding_conflict): Handle new instructions.
639 (is_mve_unpredictable): Likewise.
640 (mve_opcodes): Add new instructions.
641 (print_mve_unpredictable): Handle new reasons.
642 (print_mve_register_blocks): New print function.
643 (print_mve_size): Handle new instructions.
644 (print_insn_mve): Likewise.
645
9743db03
AV		 6462019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
647 Michael Collison <michael.collison@arm.com>
648
649 * arm-dis.c (enum mve_instructions): Add new instructions.
650 (enum mve_unpredictable): Add new reasons.
651 (enum mve_undefined): Likewise.
652 (is_mve_encoding_conflict): Handle new instructions.
653 (is_mve_undefined): Likewise.
654 (is_mve_unpredictable): Likewise.
655 (coprocessor_opcodes): Move NEON VDUP from here...
656 (neon_opcodes): ... to here.
657 (mve_opcodes): Add new instructions.
658 (print_mve_undefined): Handle new reasons.
659 (print_mve_unpredictable): Likewise.
660 (print_mve_size): Handle new instructions.
661 (print_insn_neon): Handle vdup.
662 (print_insn_mve): Handle new operands.
663
143275ea
AV		 6642019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
665 Michael Collison <michael.collison@arm.com>
666
667 * arm-dis.c (enum mve_instructions): Add new instructions.
668 (enum mve_unpredictable): Add new values.
669 (mve_opcodes): Add new instructions.
670 (vec_condnames): New array with vector conditions.
671 (mve_predicatenames): New array with predicate suffixes.
672 (mve_vec_sizename): New array with vector sizes.
673 (enum vpt_pred_state): New enum with vector predication states.
674 (struct vpt_block): New struct type for vpt blocks.
675 (vpt_block_state): Global struct to keep track of state.
676 (mve_extract_pred_mask): New helper function.
677 (num_instructions_vpt_block): Likewise.
678 (mark_outside_vpt_block): Likewise.
679 (mark_inside_vpt_block): Likewise.
680 (invert_next_predicate_state): Likewise.
681 (update_next_predicate_state): Likewise.
682 (update_vpt_block_state): Likewise.
683 (is_vpt_instruction): Likewise.
684 (is_mve_encoding_conflict): Add entries for new instructions.
685 (is_mve_unpredictable): Likewise.
686 (print_mve_unpredictable): Handle new cases.
687 (print_instruction_predicate): Likewise.
688 (print_mve_size): New function.
689 (print_vec_condition): New function.
690 (print_insn_mve): Handle vpt blocks and new print operands.
691
f08d8ce3
AV		 6922019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
693
694 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
695 8, 14 and 15 for Armv8.1-M Mainline.
696
73cd51e5
AV		 6972019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
698 Michael Collison <michael.collison@arm.com>
699
700 * arm-dis.c (enum mve_instructions): New enum.
701 (enum mve_unpredictable): Likewise.
702 (enum mve_undefined): Likewise.
703 (struct mopcode32): New struct.
704 (is_mve_okay_in_it): New function.
705 (is_mve_architecture): Likewise.
706 (arm_decode_field): Likewise.
707 (arm_decode_field_multiple): Likewise.
708 (is_mve_encoding_conflict): Likewise.
709 (is_mve_undefined): Likewise.
710 (is_mve_unpredictable): Likewise.
711 (print_mve_undefined): Likewise.
712 (print_mve_unpredictable): Likewise.
713 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
714 (print_insn_mve): New function.
715 (print_insn_thumb32): Handle MVE architecture.
716 (select_arm_features): Force thumb for Armv8.1-m Mainline.
717
3076e594
NC		 7182019-05-10 Nick Clifton <nickc@redhat.com>
719
720 PR 24538
721 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
722 end of the table prematurely.
723
387e7624
FS		 7242019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
725
726 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
727 macros for R6.
728
0067be51
AM		 7292019-05-11 Alan Modra <amodra@gmail.com>
730
731 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
732 when -Mraw is in effect.
733
42e6288f
MM		 7342019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
735
736 * aarch64-dis-2.c: Regenerate.
737 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
738 (OP_SVE_BBB): New variant set.
739 (OP_SVE_DDDD): New variant set.
740 (OP_SVE_HHH): New variant set.
741 (OP_SVE_HHHU): New variant set.
742 (OP_SVE_SSS): New variant set.
743 (OP_SVE_SSSU): New variant set.
744 (OP_SVE_SHH): New variant set.
745 (OP_SVE_SBBU): New variant set.
746 (OP_SVE_DSS): New variant set.
747 (OP_SVE_DHHU): New variant set.
748 (OP_SVE_VMV_HSD_BHS): New variant set.
749 (OP_SVE_VVU_HSD_BHS): New variant set.
750 (OP_SVE_VVVU_SD_BH): New variant set.
751 (OP_SVE_VVVU_BHSD): New variant set.
752 (OP_SVE_VVV_QHD_DBS): New variant set.
753 (OP_SVE_VVV_HSD_BHS): New variant set.
754 (OP_SVE_VVV_HSD_BHS2): New variant set.
755 (OP_SVE_VVV_BHS_HSD): New variant set.
756 (OP_SVE_VV_BHS_HSD): New variant set.
757 (OP_SVE_VVV_SD): New variant set.
758 (OP_SVE_VVU_BHS_HSD): New variant set.
759 (OP_SVE_VZVV_SD): New variant set.
760 (OP_SVE_VZVV_BH): New variant set.
761 (OP_SVE_VZV_SD): New variant set.
762 (aarch64_opcode_table): Add sve2 instructions.
763
28ed815a
MM		 7642019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
765
766 * aarch64-asm-2.c: Regenerated.
767 * aarch64-dis-2.c: Regenerated.
768 * aarch64-opc-2.c: Regenerated.
769 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
770 for SVE_SHLIMM_UNPRED_22.
771 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
772 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
773 operand.
774
fd1dc4a0
MM		 7752019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
776
777 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
778 sve_size_tsz_bhs iclass encode.
779 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
780 sve_size_tsz_bhs iclass decode.
781
31e36ab3
MM		 7822019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
783
784 * aarch64-asm-2.c: Regenerated.
785 * aarch64-dis-2.c: Regenerated.
786 * aarch64-opc-2.c: Regenerated.
787 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
788 for SVE_Zm4_11_INDEX.
789 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
790 (fields): Handle SVE_i2h field.
791 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
792 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
793
1be5f94f
MM		 7942019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
795
796 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
797 sve_shift_tsz_bhsd iclass encode.
798 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
799 sve_shift_tsz_bhsd iclass decode.
800
3c17238b
MM		 8012019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
802
803 * aarch64-asm-2.c: Regenerated.
804 * aarch64-dis-2.c: Regenerated.
805 * aarch64-opc-2.c: Regenerated.
806 * aarch64-asm.c (aarch64_ins_sve_shrimm):
807 (aarch64_encode_variant_using_iclass): Handle
808 sve_shift_tsz_hsd iclass encode.
809 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
810 sve_shift_tsz_hsd iclass decode.
811 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
812 for SVE_SHRIMM_UNPRED_22.
813 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
814 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
815 operand.
816
cd50a87a
MM		 8172019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
818
819 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
820 sve_size_013 iclass encode.
821 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
822 sve_size_013 iclass decode.
823
3c705960
MM		 8242019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
825
826 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
827 sve_size_bh iclass encode.
828 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
829 sve_size_bh iclass decode.
830
0a57e14f
MM		 8312019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
832
833 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
834 sve_size_sd2 iclass encode.
835 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
836 sve_size_sd2 iclass decode.
837 * aarch64-opc.c (fields): Handle SVE_sz2 field.
838 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
839
c469c864
MM		 8402019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
841
842 * aarch64-asm-2.c: Regenerated.
843 * aarch64-dis-2.c: Regenerated.
844 * aarch64-opc-2.c: Regenerated.
845 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
846 for SVE_ADDR_ZX.
847 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
848 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
849
116adc27
MM		 8502019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
851
852 * aarch64-asm-2.c: Regenerated.
853 * aarch64-dis-2.c: Regenerated.
854 * aarch64-opc-2.c: Regenerated.
855 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
856 for SVE_Zm3_11_INDEX.
857 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
858 (fields): Handle SVE_i3l and SVE_i3h2 fields.
859 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
860 fields.
861 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
862
3bd82c86
MM		 8632019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
864
865 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
866 sve_size_hsd2 iclass encode.
867 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
868 sve_size_hsd2 iclass decode.
869 * aarch64-opc.c (fields): Handle SVE_size field.
870 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
871
adccc507
MM		 8722019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
873
874 * aarch64-asm-2.c: Regenerated.
875 * aarch64-dis-2.c: Regenerated.
876 * aarch64-opc-2.c: Regenerated.
877 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
878 for SVE_IMM_ROT3.
879 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
880 (fields): Handle SVE_rot3 field.
881 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
882 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
883
5cd99750
MM		 8842019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
885
886 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
887 instructions.
888
7ce2460a
MM		 8892019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
890
891 * aarch64-tbl.h
892 (aarch64_feature_sve2, aarch64_feature_sve2aes,
893 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
894 aarch64_feature_sve2bitperm): New feature sets.
895 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
896 for feature set addresses.
897 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
898 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
899
41cee089
FS		 9002019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
901 Faraz Shahbazker <fshahbazker@wavecomp.com>
902
903 * mips-dis.c (mips_calculate_combination_ases): Add ISA
904 argument and set ASE_EVA_R6 appropriately.
905 (set_default_mips_dis_options): Pass ISA to above.
906 (parse_mips_dis_option): Likewise.
907 * mips-opc.c (EVAR6): New macro.
908 (mips_builtin_opcodes): Add llwpe, scwpe.
909
b83b4b13
SD		 9102019-05-01 Sudakshina Das <sudi.das@arm.com>
911
912 * aarch64-asm-2.c: Regenerated.
913 * aarch64-dis-2.c: Regenerated.
914 * aarch64-opc-2.c: Regenerated.
915 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
916 AARCH64_OPND_TME_UIMM16.
917 (aarch64_print_operand): Likewise.
918 * aarch64-tbl.h (QL_IMM_NIL): New.
919 (TME): New.
920 (_TME_INSN): New.
921 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
922
4a90ce95
JD		 9232019-04-29 John Darrington <john@darrington.wattle.id.au>
924
925 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
926
a45328b9
AB		 9272019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
928 Faraz Shahbazker <fshahbazker@wavecomp.com>
929
930 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
931
d10be0cb
JD		 9322019-04-24 John Darrington <john@darrington.wattle.id.au>
933
934 * s12z-opc.h: Add extern "C" bracketing to help
935 users who wish to use this interface in c++ code.
936
a679f24e
JD		 9372019-04-24 John Darrington <john@darrington.wattle.id.au>
938
939 * s12z-opc.c (bm_decode): Handle bit map operations with the
940 "reserved0" mode.
941
32c36c3c
AV		 9422019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
943
944 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
945 specifier. Add entries for VLDR and VSTR of system registers.
946 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
947 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
948 of %J and %K format specifier.
949
efd6b359
AV		 9502019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
951
952 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
953 Add new entries for VSCCLRM instruction.
954 (print_insn_coprocessor): Handle new %C format control code.
955
6b0dd094
AV		 9562019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
957
958 * arm-dis.c (enum isa): New enum.
959 (struct sopcode32): New structure.
960 (coprocessor_opcodes): change type of entries to struct sopcode32 and
961 set isa field of all current entries to ANY.
962 (print_insn_coprocessor): Change type of insn to struct sopcode32.
963 Only match an entry if its isa field allows the current mode.
964
4b5a202f
AV		 9652019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
966
967 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
968 CLRM.
969 (print_insn_thumb32): Add logic to print %n CLRM register list.
970
60f993ce
AV		 9712019-04-15 Sudakshina Das <sudi.das@arm.com>
972
973 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
974 and %Q patterns.
975
f6b2b12d
AV		 9762019-04-15 Sudakshina Das <sudi.das@arm.com>
977
978 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
979 (print_insn_thumb32): Edit the switch case for %Z.
980
1889da70
AV		 9812019-04-15 Sudakshina Das <sudi.das@arm.com>
982
983 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
984
65d1bc05
AV		 9852019-04-15 Sudakshina Das <sudi.das@arm.com>
986
987 * arm-dis.c (thumb32_opcodes): New instruction bfl.
988
1caf72a5
AV		 9892019-04-15 Sudakshina Das <sudi.das@arm.com>
990
991 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
992
f1c7f421
AV		 9932019-04-15 Sudakshina Das <sudi.das@arm.com>
994
995 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
996 Arm register with r13 and r15 unpredictable.
997 (thumb32_opcodes): New instructions for bfx and bflx.
998
4389b29a
AV		 9992019-04-15 Sudakshina Das <sudi.das@arm.com>
1000
1001 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1002
e5d6e09e
AV		 10032019-04-15 Sudakshina Das <sudi.das@arm.com>
1004
1005 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1006
e12437dc
AV		 10072019-04-15 Sudakshina Das <sudi.das@arm.com>
1008
1009 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1010
031254f2
AV		 10112019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1012
1013 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1014
e5a557ac
JD		 10152019-04-12 John Darrington <john@darrington.wattle.id.au>
1016
1017 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1018 "optr". ("operator" is a reserved word in c++).
1019
bd7ceb8d
SD		 10202019-04-11 Sudakshina Das <sudi.das@arm.com>
1021
1022 * aarch64-opc.c (aarch64_print_operand): Add case for
1023 AARCH64_OPND_Rt_SP.
1024 (verify_constraints): Likewise.
1025 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1026 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1027 to accept Rt|SP as first operand.
1028 (AARCH64_OPERANDS): Add new Rt_SP.
1029 * aarch64-asm-2.c: Regenerated.
1030 * aarch64-dis-2.c: Regenerated.
1031 * aarch64-opc-2.c: Regenerated.
1032
e54010f1
SD		 10332019-04-11 Sudakshina Das <sudi.das@arm.com>
1034
1035 * aarch64-asm-2.c: Regenerated.
1036 * aarch64-dis-2.c: Likewise.
1037 * aarch64-opc-2.c: Likewise.
1038 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1039
7e96e219
RS		 10402019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1041
1042 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1043
6f2791d5
L		 10442019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1045
1046 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1047 * i386-init.h: Regenerated.
1048
e392bad3
AM		 10492019-04-07 Alan Modra <amodra@gmail.com>
1050
1051 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1052 op_separator to control printing of spaces, comma and parens
1053 rather than need_comma, need_paren and spaces vars.
1054
dffaa15c
AM		 10552019-04-07 Alan Modra <amodra@gmail.com>
1056
1057 PR 24421
1058 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1059 (print_insn_neon, print_insn_arm): Likewise.
1060
d6aab7a1
XG		 10612019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1062
1063 * i386-dis-evex.h (evex_table): Updated to support BF16
1064 instructions.
1065 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1066 and EVEX_W_0F3872_P_3.
1067 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1068 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1069 * i386-opc.h (enum): Add CpuAVX512_BF16.
1070 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1071 * i386-opc.tbl: Add AVX512 BF16 instructions.
1072 * i386-init.h: Regenerated.
1073 * i386-tbl.h: Likewise.
1074
66e85460
AM		 10752019-04-05 Alan Modra <amodra@gmail.com>
1076
1077 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1078 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1079 to favour printing of "-" branch hint when using the "y" bit.
1080 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1081
c2b1c275
AM		 10822019-04-05 Alan Modra <amodra@gmail.com>
1083
1084 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1085 opcode until first operand is output.
1086
aae9718e
PB		 10872019-04-04 Peter Bergner <bergner@linux.ibm.com>
1088
1089 PR gas/24349
1090 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1091 (valid_bo_post_v2): Add support for 'at' branch hints.
1092 (insert_bo): Only error on branch on ctr.
1093 (get_bo_hint_mask): New function.
1094 (insert_boe): Add new 'branch_taken' formal argument. Add support
1095 for inserting 'at' branch hints.
1096 (extract_boe): Add new 'branch_taken' formal argument. Add support
1097 for extracting 'at' branch hints.
1098 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1099 (BOE): Delete operand.
1100 (BOM, BOP): New operands.
1101 (RM): Update value.
1102 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1103 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1104 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1105 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1106 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1107 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1108 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1109 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1110 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1111 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1112 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1113 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1114 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1115 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1116 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1117 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1118 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1119 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1120 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1121 bttarl+>: New extended mnemonics.
1122
96a86c01
AM		 11232019-03-28 Alan Modra <amodra@gmail.com>
1124
1125 PR 24390
1126 * ppc-opc.c (BTF): Define.
1127 (powerpc_opcodes): Use for mtfsb*.
1128 * ppc-dis.c (print_insn_powerpc): Print fields with both
1129 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1130
796d6298
TC		 11312019-03-25 Tamar Christina <tamar.christina@arm.com>
1132
1133 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1134 (mapping_symbol_for_insn): Implement new algorithm.
1135 (print_insn): Remove duplicate code.
1136
60df3720
TC		 11372019-03-25 Tamar Christina <tamar.christina@arm.com>
1138
1139 * aarch64-dis.c (print_insn_aarch64):
1140 Implement override.
1141
51457761
TC		 11422019-03-25 Tamar Christina <tamar.christina@arm.com>
1143
1144 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1145 order.
1146
53b2f36b
TC		 11472019-03-25 Tamar Christina <tamar.christina@arm.com>
1148
1149 * aarch64-dis.c (last_stop_offset): New.
1150 (print_insn_aarch64): Use stop_offset.
1151
89199bb5
L		 11522019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1153
1154 PR gas/24359
1155 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1156 CPU_ANY_AVX2_FLAGS.
1157 * i386-init.h: Regenerated.
1158
97ed31ae
L		 11592019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1160
1161 PR gas/24348
1162 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1163 vmovdqu16, vmovdqu32 and vmovdqu64.
1164 * i386-tbl.h: Regenerated.
1165
0919bfe9
AK		 11662019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1167
1168 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1169 from vstrszb, vstrszh, and vstrszf.
1170
11712019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1172
1173 * s390-opc.txt: Add instruction descriptions.
1174
21820ebe
JW		 11752019-02-08 Jim Wilson <jimw@sifive.com>
1176
1177 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1178 <bne>: Likewise.
1179
f7dd2fb2
TC		 11802019-02-07 Tamar Christina <tamar.christina@arm.com>
1181
1182 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1183
6456d318
TC		 11842019-02-07 Tamar Christina <tamar.christina@arm.com>
1185
1186 PR binutils/23212
1187 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1188 * aarch64-opc.c (verify_elem_sd): New.
1189 (fields): Add FLD_sz entr.
1190 * aarch64-tbl.h (_SIMD_INSN): New.
1191 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1192 fmulx scalar and vector by element isns.
1193
4a83b610
NC		 11942019-02-07 Nick Clifton <nickc@redhat.com>
1195
1196 * po/sv.po: Updated Swedish translation.
1197
fc60b8c8
AK		 11982019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1199
1200 * s390-mkopc.c (main): Accept arch13 as cpu string.
1201 * s390-opc.c: Add new instruction formats and instruction opcode
1202 masks.
1203 * s390-opc.txt: Add new arch13 instructions.
1204
e10620d3
TC		 12052019-01-25 Sudakshina Das <sudi.das@arm.com>
1206
1207 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1208 (aarch64_opcode): Change encoding for stg, stzg
1209 st2g and st2zg.
1210 * aarch64-asm-2.c: Regenerated.
1211 * aarch64-dis-2.c: Regenerated.
1212 * aarch64-opc-2.c: Regenerated.
1213
20a4ca55
SD		 12142019-01-25 Sudakshina Das <sudi.das@arm.com>
1215
1216 * aarch64-asm-2.c: Regenerated.
1217 * aarch64-dis-2.c: Likewise.
1218 * aarch64-opc-2.c: Likewise.
1219 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1220
550fd7bf
SD		 12212019-01-25 Sudakshina Das <sudi.das@arm.com>
1222 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1223
1224 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1225 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1226 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1227 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1228 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1229 case for ldstgv_indexed.
1230 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1231 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1232 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1233 * aarch64-asm-2.c: Regenerated.
1234 * aarch64-dis-2.c: Regenerated.
1235 * aarch64-opc-2.c: Regenerated.
1236
d9938630
NC		 12372019-01-23 Nick Clifton <nickc@redhat.com>
1238
1239 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1240
375cd423
NC		 12412019-01-21 Nick Clifton <nickc@redhat.com>
1242
1243 * po/de.po: Updated German translation.
1244 * po/uk.po: Updated Ukranian translation.
1245
57299f48
CX		 12462019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1247 * mips-dis.c (mips_arch_choices): Fix typo in
1248 gs464, gs464e and gs264e descriptors.
1249
f48dfe41
NC		 12502019-01-19 Nick Clifton <nickc@redhat.com>
1251
1252 * configure: Regenerate.
1253 * po/opcodes.pot: Regenerate.
1254
f974f26c
NC		 12552018-06-24 Nick Clifton <nickc@redhat.com>
1256
1257 2.32 branch created.
1258
39f286cd
JD		 12592019-01-09 John Darrington <john@darrington.wattle.id.au>
1260
448b8ca8
JD		 1261 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1262 if it is null.
1263 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1264 zero.
1265
3107326d
AP		 12662019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1267
1268 * configure: Regenerate.
1269
7e9ca91e
AM		 12702019-01-07 Alan Modra <amodra@gmail.com>
1271
1272 * configure: Regenerate.
1273 * po/POTFILES.in: Regenerate.
1274
ef1ad42b
JD		 12752019-01-03 John Darrington <john@darrington.wattle.id.au>
1276
1277 * s12z-opc.c: New file.
1278 * s12z-opc.h: New file.
1279 * s12z-dis.c: Removed all code not directly related to display
1280 of instructions. Used the interface provided by the new files
1281 instead.
1282 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1283 * Makefile.in: Regenerate.
ef1ad42b 1284 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1285 * configure: Regenerate.
ef1ad42b 1286
82704155
AM		 12872019-01-01 Alan Modra <amodra@gmail.com>
1288
1289 Update year range in copyright notice of all files.
1290
d5c04e1b 1291For older changes see ChangeLog-2018
3499769a 1292\f
d5c04e1b 1293Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1294
1295Copying and distribution of this file, with or without modification,
1296are permitted in any medium without royalty provided the copyright
1297notice and this notice are preserved.
1298
1299Local Variables:
1300mode: change-log
1301left-margin: 8
1302fill-column: 74
1303version-control: never
1304End:
GDB Binutils - Deliverables
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