Commit | Line | Data |
---|---|---|
c2ecccb3 L |
1 | 2020-07-02 H.J. Lu <hongjiu.lu@intel.com> |
2 | ||
3 | * i386-gen.c (opcode_modifiers): Add VexSwapSources. | |
4 | * i386-opc.h (VexSwapSources): New. | |
5 | (i386_opcode_modifier): Add vexswapsources. | |
6 | * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions | |
7 | with two source operands swapped. | |
8 | * i386-tbl.h: Regenerated. | |
9 | ||
08ccfccf NC |
10 | 2020-06-30 Nelson Chu <nelson.chu@sifive.com> |
11 | ||
12 | * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the | |
13 | unprivileged CSR can also be initialized. | |
14 | ||
279edac5 AM |
15 | 2020-06-29 Alan Modra <amodra@gmail.com> |
16 | ||
17 | * arm-dis.c: Use C style comments. | |
18 | * cr16-opc.c: Likewise. | |
19 | * ft32-dis.c: Likewise. | |
20 | * moxie-opc.c: Likewise. | |
21 | * tic54x-dis.c: Likewise. | |
22 | * s12z-opc.c: Remove useless comment. | |
23 | * xgate-dis.c: Likewise. | |
24 | ||
e978ad62 L |
25 | 2020-06-26 H.J. Lu <hongjiu.lu@intel.com> |
26 | ||
27 | * i386-opc.tbl: Add a blank line. | |
28 | ||
63112cd6 L |
29 | 2020-06-26 H.J. Lu <hongjiu.lu@intel.com> |
30 | ||
31 | * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB. | |
32 | (VecSIB128): Renamed to ... | |
33 | (VECSIB128): This. | |
34 | (VecSIB256): Renamed to ... | |
35 | (VECSIB256): This. | |
36 | (VecSIB512): Renamed to ... | |
37 | (VECSIB512): This. | |
38 | (VecSIB): Renamed to ... | |
39 | (SIB): This. | |
40 | (i386_opcode_modifier): Replace vecsib with sib. | |
79b32e73 | 41 | * i386-opc.tbl (VecSIB128): New. |
63112cd6 L |
42 | (VecSIB256): Likewise. |
43 | (VecSIB512): Likewise. | |
79b32e73 | 44 | Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256 |
63112cd6 L |
45 | and VecSIB512, respectively. |
46 | ||
d1c36125 JB |
47 | 2020-06-26 Jan Beulich <jbeulich@suse.com> |
48 | ||
49 | * i386-dis.c: Adjust description of I macro. | |
50 | (x86_64_table): Drop use of I. | |
51 | (float_mem): Replace use of I. | |
52 | (putop): Remove handling of I. Adjust setting/clearing of "alt". | |
53 | ||
2a1bb84c JB |
54 | 2020-06-26 Jan Beulich <jbeulich@suse.com> |
55 | ||
56 | * i386-dis.c: (print_insn): Avoid straight assignment to | |
57 | priv.orig_sizeflag when processing -M sub-options. | |
58 | ||
8f570d62 JB |
59 | 2020-06-25 Jan Beulich <jbeulich@suse.com> |
60 | ||
61 | * i386-dis.c: Adjust description of J macro. | |
62 | (dis386, x86_64_table, mod_table): Replace J. | |
63 | (putop): Remove handling of J. | |
64 | ||
464dc4af JB |
65 | 2020-06-25 Jan Beulich <jbeulich@suse.com> |
66 | ||
67 | * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt. | |
68 | ||
589958d6 JB |
69 | 2020-06-25 Jan Beulich <jbeulich@suse.com> |
70 | ||
71 | * i386-dis.c: Adjust description of "LQ" macro. | |
72 | (dis386_twobyte): Use LQ for sysret. | |
73 | (putop): Adjust handling of LQ. | |
74 | ||
39ff0b81 NC |
75 | 2020-06-22 Nelson Chu <nelson.chu@sifive.com> |
76 | ||
77 | * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c. | |
78 | * riscv-dis.c: Include elfxx-riscv.h. | |
79 | ||
d27c357a JB |
80 | 2020-06-18 H.J. Lu <hongjiu.lu@intel.com> |
81 | ||
82 | * i386-dis.c (prefix_table): Revert the last vmgexit change. | |
83 | ||
6fde587f CL |
84 | 2020-06-17 Lili Cui <lili.cui@intel.com> |
85 | ||
86 | * i386-dis.c (prefix_table): Delete the incorrect vmgexit. | |
87 | ||
efe30057 L |
88 | 2020-06-14 H.J. Lu <hongjiu.lu@intel.com> |
89 | ||
90 | PR gas/26115 | |
91 | * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk. | |
92 | * i386-opc.tbl: Likewise. | |
93 | * i386-tbl.h: Regenerated. | |
94 | ||
d8af286f NC |
95 | 2020-06-12 Nelson Chu <nelson.chu@sifive.com> |
96 | ||
97 | * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9. | |
98 | ||
14962256 AC |
99 | 2020-06-11 Alex Coplan <alex.coplan@arm.com> |
100 | ||
101 | * aarch64-opc.c (SYSREG): New macro for describing system registers. | |
102 | (SR_CORE): Likewise. | |
103 | (SR_FEAT): Likewise. | |
104 | (SR_RNG): Likewise. | |
105 | (SR_V8_1): Likewise. | |
106 | (SR_V8_2): Likewise. | |
107 | (SR_V8_3): Likewise. | |
108 | (SR_V8_4): Likewise. | |
109 | (SR_PAN): Likewise. | |
110 | (SR_RAS): Likewise. | |
111 | (SR_SSBS): Likewise. | |
112 | (SR_SVE): Likewise. | |
113 | (SR_ID_PFR2): Likewise. | |
114 | (SR_PROFILE): Likewise. | |
115 | (SR_MEMTAG): Likewise. | |
116 | (SR_SCXTNUM): Likewise. | |
117 | (aarch64_sys_regs): Refactor to store feature information in the table. | |
118 | (aarch64_sys_reg_supported_p): Collapse logic for system registers | |
119 | that now describe their own features. | |
120 | (aarch64_pstatefield_supported_p): Likewise. | |
121 | ||
f9630fa6 L |
122 | 2020-06-09 H.J. Lu <hongjiu.lu@intel.com> |
123 | ||
124 | * i386-dis.c (prefix_table): Fix a typo in comments. | |
125 | ||
73239888 JB |
126 | 2020-06-09 Jan Beulich <jbeulich@suse.com> |
127 | ||
128 | * i386-dis.c (rex_ignored): Delete. | |
129 | (ckprefix): Drop rex_ignored initialization. | |
130 | (get_valid_dis386): Drop setting of rex_ignored. | |
131 | (print_insn): Drop checking of rex_ignored. Don't record data | |
132 | size prefix as used with VEX-and-alike encodings. | |
133 | ||
18897deb JB |
134 | 2020-06-09 Jan Beulich <jbeulich@suse.com> |
135 | ||
136 | * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2, | |
137 | MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators. | |
138 | (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete. | |
139 | (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define. | |
140 | (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16, | |
141 | VEX_0F12, and VEX_0F16. | |
142 | (vex_len_table): Use X for vmovlp* and vmovh*s. Drop | |
143 | VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries. | |
144 | (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE | |
145 | from movlps and movhlps. New MOD_0F12_PREFIX_2, | |
146 | MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and | |
147 | MOD_VEX_0F16_PREFIX_2 entries. | |
148 | ||
97e6786a JB |
149 | 2020-06-09 Jan Beulich <jbeulich@suse.com> |
150 | ||
151 | * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13, | |
152 | MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators. | |
153 | (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, | |
154 | PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, | |
155 | PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, | |
156 | PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6, | |
157 | EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0, | |
158 | EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2, | |
159 | EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, | |
160 | EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, | |
161 | EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, | |
162 | EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, | |
163 | EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, | |
164 | EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, | |
165 | EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, | |
166 | EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, | |
167 | EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, | |
168 | EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, | |
169 | EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, | |
170 | EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, | |
171 | EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, | |
172 | EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, | |
173 | EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, | |
174 | EVEX_W_0FC6_P_2): Delete. | |
175 | (print_insn): Add EVEX.W vs embedded prefix consistency check | |
176 | to prefix validation. | |
177 | * i386-dis-evex.h (evex_table): Don't further descend for | |
178 | vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX, | |
179 | and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17, | |
180 | and 0F2B. | |
181 | * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries. | |
182 | * i386-dis-evex-prefix.h: Don't further descend for vmovupX, | |
183 | vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX, | |
184 | vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases | |
185 | 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29. | |
186 | Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, | |
187 | PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B, | |
188 | PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56, | |
189 | PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries. | |
190 | * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, | |
191 | EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, | |
192 | EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, | |
193 | EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, | |
194 | EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, | |
195 | EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, | |
196 | EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, | |
197 | EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, | |
198 | EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, | |
199 | EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2, | |
200 | EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0, | |
201 | EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, | |
202 | EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0, | |
203 | EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2, | |
204 | EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0, | |
205 | EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2, | |
206 | EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0, | |
207 | EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries. | |
208 | ||
bf926894 JB |
209 | 2020-06-09 Jan Beulich <jbeulich@suse.com> |
210 | ||
211 | * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX, | |
212 | vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX. | |
213 | (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and | |
214 | vmovmskpX. | |
215 | (print_insn): Drop pointless check against bad_opcode. Split | |
216 | prefix validation into legacy and VEX-and-alike parts. | |
217 | (putop): Re-work 'X' macro handling. | |
218 | ||
a5aaedb9 JB |
219 | 2020-06-09 Jan Beulich <jbeulich@suse.com> |
220 | ||
221 | * i386-dis.c (MOD_0F51): Rename to ... | |
222 | (MOD_0F50): ... this. | |
223 | ||
26417f19 AC |
224 | 2020-06-08 Alex Coplan <alex.coplan@arm.com> |
225 | ||
226 | * arm-dis.c (arm_opcodes): Add dfb. | |
227 | (thumb32_opcodes): Add dfb. | |
228 | ||
8a6fb3f9 JB |
229 | 2020-06-08 Jan Beulich <jbeulich@suse.com> |
230 | ||
231 | * i386-opc.h (reg_entry): Const-qualify reg_name field. | |
232 | ||
1424c35d AM |
233 | 2020-06-06 Alan Modra <amodra@gmail.com> |
234 | ||
235 | * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10. | |
236 | ||
d3d1cc7b AM |
237 | 2020-06-05 Alan Modra <amodra@gmail.com> |
238 | ||
239 | * cgen-dis.c (hash_insn_array): Increase size of buf. Assert | |
240 | size is large enough. | |
241 | ||
d8740be1 JM |
242 | 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> |
243 | ||
244 | * disassemble.c (disassemble_init_for_target): Set endian_code for | |
245 | bpf targets. | |
246 | * bpf-desc.c: Regenerate. | |
247 | * bpf-opc.c: Likewise. | |
248 | * bpf-dis.c: Likewise. | |
249 | ||
e9bffec9 JM |
250 | 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com> |
251 | ||
252 | * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument. | |
253 | (cgen_put_insn_value): Likewise. | |
254 | (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value. | |
255 | * cgen-dis.in (print_insn): Likewise. | |
256 | * cgen-ibld.in (insert_1): Likewise. | |
257 | (insert_1): Likewise. | |
258 | (insert_insn_normal): Likewise. | |
259 | (extract_1): Likewise. | |
260 | * bpf-dis.c: Regenerate. | |
261 | * bpf-ibld.c: Likewise. | |
262 | * bpf-ibld.c: Likewise. | |
263 | * cgen-dis.in: Likewise. | |
264 | * cgen-ibld.in: Likewise. | |
265 | * cgen-opc.c: Likewise. | |
266 | * epiphany-dis.c: Likewise. | |
267 | * epiphany-ibld.c: Likewise. | |
268 | * fr30-dis.c: Likewise. | |
269 | * fr30-ibld.c: Likewise. | |
270 | * frv-dis.c: Likewise. | |
271 | * frv-ibld.c: Likewise. | |
272 | * ip2k-dis.c: Likewise. | |
273 | * ip2k-ibld.c: Likewise. | |
274 | * iq2000-dis.c: Likewise. | |
275 | * iq2000-ibld.c: Likewise. | |
276 | * lm32-dis.c: Likewise. | |
277 | * lm32-ibld.c: Likewise. | |
278 | * m32c-dis.c: Likewise. | |
279 | * m32c-ibld.c: Likewise. | |
280 | * m32r-dis.c: Likewise. | |
281 | * m32r-ibld.c: Likewise. | |
282 | * mep-dis.c: Likewise. | |
283 | * mep-ibld.c: Likewise. | |
284 | * mt-dis.c: Likewise. | |
285 | * mt-ibld.c: Likewise. | |
286 | * or1k-dis.c: Likewise. | |
287 | * or1k-ibld.c: Likewise. | |
288 | * xc16x-dis.c: Likewise. | |
289 | * xc16x-ibld.c: Likewise. | |
290 | * xstormy16-dis.c: Likewise. | |
291 | * xstormy16-ibld.c: Likewise. | |
292 | ||
b3db6d07 JM |
293 | 2020-06-04 Jose E. Marchesi <jemarch@gnu.org> |
294 | ||
295 | * cgen-dis.in (cpu_desc_list): New field `insn_endian'. | |
296 | (print_insn_): Handle instruction endian. | |
297 | * bpf-dis.c: Regenerate. | |
298 | * bpf-desc.c: Regenerate. | |
299 | * epiphany-dis.c: Likewise. | |
300 | * epiphany-desc.c: Likewise. | |
301 | * fr30-dis.c: Likewise. | |
302 | * fr30-desc.c: Likewise. | |
303 | * frv-dis.c: Likewise. | |
304 | * frv-desc.c: Likewise. | |
305 | * ip2k-dis.c: Likewise. | |
306 | * ip2k-desc.c: Likewise. | |
307 | * iq2000-dis.c: Likewise. | |
308 | * iq2000-desc.c: Likewise. | |
309 | * lm32-dis.c: Likewise. | |
310 | * lm32-desc.c: Likewise. | |
311 | * m32c-dis.c: Likewise. | |
312 | * m32c-desc.c: Likewise. | |
313 | * m32r-dis.c: Likewise. | |
314 | * m32r-desc.c: Likewise. | |
315 | * mep-dis.c: Likewise. | |
316 | * mep-desc.c: Likewise. | |
317 | * mt-dis.c: Likewise. | |
318 | * mt-desc.c: Likewise. | |
319 | * or1k-dis.c: Likewise. | |
320 | * or1k-desc.c: Likewise. | |
321 | * xc16x-dis.c: Likewise. | |
322 | * xc16x-desc.c: Likewise. | |
323 | * xstormy16-dis.c: Likewise. | |
324 | * xstormy16-desc.c: Likewise. | |
325 | ||
4ee4189f NC |
326 | 2020-06-03 Nick Clifton <nickc@redhat.com> |
327 | ||
328 | * po/sr.po: Updated Serbian translation. | |
329 | ||
44730156 NC |
330 | 2020-06-03 Nelson Chu <nelson.chu@sifive.com> |
331 | ||
332 | * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int. | |
333 | (riscv_get_priv_spec_class): Likewise. | |
334 | ||
3c3d0376 AM |
335 | 2020-06-01 Alan Modra <amodra@gmail.com> |
336 | ||
337 | * bpf-desc.c: Regenerate. | |
338 | ||
78c1c354 JM |
339 | 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com> |
340 | David Faust <david.faust@oracle.com> | |
341 | ||
342 | * bpf-desc.c: Regenerate. | |
343 | * bpf-opc.h: Likewise. | |
344 | * bpf-opc.c: Likewise. | |
345 | * bpf-dis.c: Likewise. | |
346 | ||
efcf5fb5 AM |
347 | 2020-05-28 Alan Modra <amodra@gmail.com> |
348 | ||
349 | * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative | |
350 | values. | |
351 | ||
ab382d64 AM |
352 | 2020-05-28 Alan Modra <amodra@gmail.com> |
353 | ||
354 | * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for | |
355 | immediates. | |
356 | (print_insn_ns32k): Revert last change. | |
357 | ||
151f5de4 NC |
358 | 2020-05-28 Nick Clifton <nickc@redhat.com> |
359 | ||
360 | * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to | |
361 | static. | |
362 | ||
25e1eca8 SL |
363 | 2020-05-26 Sandra Loosemore <sandra@codesourcery.com> |
364 | ||
365 | Fix extraction of signed constants in nios2 disassembler (again). | |
366 | ||
367 | * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to | |
368 | extractions of signed fields. | |
369 | ||
57b17940 SSF |
370 | 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> |
371 | ||
372 | * s390-opc.txt: Relocate vector load/store instructions with | |
373 | additional alignment parameter and change architecture level | |
374 | constraint from z14 to z13. | |
375 | ||
d96bf37b AM |
376 | 2020-05-21 Alan Modra <amodra@gmail.com> |
377 | ||
378 | * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout. | |
379 | * sparc-dis.c: Likewise. | |
380 | * tic4x-dis.c: Likewise. | |
381 | * xtensa-dis.c: Likewise. | |
382 | * bpf-desc.c: Regenerate. | |
383 | * epiphany-desc.c: Regenerate. | |
384 | * fr30-desc.c: Regenerate. | |
385 | * frv-desc.c: Regenerate. | |
386 | * ip2k-desc.c: Regenerate. | |
387 | * iq2000-desc.c: Regenerate. | |
388 | * lm32-desc.c: Regenerate. | |
389 | * m32c-desc.c: Regenerate. | |
390 | * m32r-desc.c: Regenerate. | |
391 | * mep-asm.c: Regenerate. | |
392 | * mep-desc.c: Regenerate. | |
393 | * mt-desc.c: Regenerate. | |
394 | * or1k-desc.c: Regenerate. | |
395 | * xc16x-desc.c: Regenerate. | |
396 | * xstormy16-desc.c: Regenerate. | |
397 | ||
8f595e9b NC |
398 | 2020-05-20 Nelson Chu <nelson.chu@sifive.com> |
399 | ||
400 | * riscv-opc.c (riscv_ext_version_table): The table used to store | |
401 | all information about the supported spec and the corresponding ISA | |
402 | versions. Currently, only Zicsr is supported to verify the | |
403 | correctness of Z sub extension settings. Others will be supported | |
404 | in the future patches. | |
405 | (struct isa_spec_t, isa_specs): List for all supported ISA spec | |
406 | classes and the corresponding strings. | |
407 | (riscv_get_isa_spec_class): New function. Get the corresponding ISA | |
408 | spec class by giving a ISA spec string. | |
409 | * riscv-opc.c (struct priv_spec_t): New structure. | |
410 | (struct priv_spec_t priv_specs): List for all supported privilege spec | |
411 | classes and the corresponding strings. | |
412 | (riscv_get_priv_spec_class): New function. Get the corresponding | |
413 | privilege spec class by giving a spec string. | |
414 | (riscv_get_priv_spec_name): New function. Get the corresponding | |
415 | privilege spec string by giving a CSR version class. | |
416 | * riscv-dis.c: Updated since DECLARE_CSR is changed. | |
417 | * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR | |
418 | according to the chosen version. Build a hash table riscv_csr_hash to | |
419 | store the valid CSR for the chosen pirv verison. Dump the direct | |
420 | CSR address rather than it's name if it is invalid. | |
421 | (parse_riscv_dis_option_without_args): New function. Parse the options | |
422 | without arguments. | |
423 | (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to | |
424 | parse the options without arguments first, and then handle the options | |
425 | with arguments. Add the new option -Mpriv-spec, which has argument. | |
426 | * riscv-dis.c (print_riscv_disassembler_options): Add description | |
427 | about the new OBJDUMP option. | |
428 | ||
3d205eb4 PB |
429 | 2020-05-19 Peter Bergner <bergner@linux.ibm.com> |
430 | ||
431 | * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new | |
432 | WC values on POWER10 sync, dcbf and wait instructions. | |
433 | (insert_pl, extract_pl): New functions. | |
434 | (L2OPT, LS, WC): Use insert_ls and extract_ls. | |
435 | (LS3): New , 3-bit L for sync. | |
436 | (LS3, L3OPT): New, 3-bit L for sync and dcbf. | |
437 | (SC2, PL): New, 2-bit SC and PL for sync and wait. | |
438 | (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks. | |
439 | (XOPL3, XWCPL, XSYNCLS): New opcode macros. | |
440 | (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync, | |
441 | plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics. | |
442 | <wait>: Enable PL operand on POWER10. | |
443 | <dcbf>: Enable L3OPT operand on POWER10. | |
444 | <sync>: Enable SC2 operand on POWER10. | |
445 | ||
a501eb44 SH |
446 | 2020-05-19 Stafford Horne <shorne@gmail.com> |
447 | ||
448 | PR 25184 | |
449 | * or1k-asm.c: Regenerate. | |
450 | * or1k-desc.c: Regenerate. | |
451 | * or1k-desc.h: Regenerate. | |
452 | * or1k-dis.c: Regenerate. | |
453 | * or1k-ibld.c: Regenerate. | |
454 | * or1k-opc.c: Regenerate. | |
455 | * or1k-opc.h: Regenerate. | |
456 | * or1k-opinst.c: Regenerate. | |
457 | ||
3b646889 AM |
458 | 2020-05-11 Alan Modra <amodra@gmail.com> |
459 | ||
460 | * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp, | |
461 | xsmaxcqp, xsmincqp. | |
462 | ||
9cc4ce88 AM |
463 | 2020-05-11 Alan Modra <amodra@gmail.com> |
464 | ||
465 | * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx, | |
466 | stxvrbx, stxvrhx, stxvrwx, stxvrdx. | |
467 | ||
5d57bc3f AM |
468 | 2020-05-11 Alan Modra <amodra@gmail.com> |
469 | ||
470 | * ppc-opc.c (powerpc_opcodes): Add xvtlsbb. | |
471 | ||
66ef5847 AM |
472 | 2020-05-11 Alan Modra <amodra@gmail.com> |
473 | ||
474 | * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr, | |
475 | vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr.. | |
476 | ||
4f3e9537 PB |
477 | 2020-05-11 Peter Bergner <bergner@linux.ibm.com> |
478 | ||
479 | * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New | |
480 | mnemonics. | |
481 | ||
ec40e91c AM |
482 | 2020-05-11 Alan Modra <amodra@gmail.com> |
483 | ||
484 | * ppc-opc.c (UIM8, P_U8XX4_MASK): Define. | |
485 | (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm, | |
486 | vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm. | |
487 | (prefix_opcodes): Add xxeval. | |
488 | ||
d7e97a76 AM |
489 | 2020-05-11 Alan Modra <amodra@gmail.com> |
490 | ||
491 | * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm, | |
492 | xxgenpcvwm, xxgenpcvdm. | |
493 | ||
fdefed7c AM |
494 | 2020-05-11 Alan Modra <amodra@gmail.com> |
495 | ||
496 | * ppc-opc.c (MP, VXVAM_MASK): Define. | |
497 | (VXVAPS_MASK): Use VXVA_MASK. | |
498 | (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm, | |
499 | vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm, | |
500 | vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm, | |
501 | vcntmbb, vcntmbh, vcntmbw, vcntmbd. | |
502 | ||
aa3c112f AM |
503 | 2020-05-11 Alan Modra <amodra@gmail.com> |
504 | Peter Bergner <bergner@linux.ibm.com> | |
505 | ||
506 | * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a): | |
507 | New functions. | |
508 | (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK, | |
509 | YMSK2, XA6a, XA6ap, XB6a entries. | |
510 | (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define | |
511 | (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define. | |
512 | (PPCVSX4): Define. | |
513 | (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz, | |
514 | xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, | |
515 | xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, | |
516 | xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np, | |
517 | xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp, | |
518 | xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn, | |
519 | xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16. | |
520 | (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp, | |
521 | pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8, | |
522 | pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2, | |
523 | pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp, | |
524 | pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp, | |
525 | pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn, | |
526 | pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn. | |
527 | ||
6edbfd3b AM |
528 | 2020-05-11 Alan Modra <amodra@gmail.com> |
529 | ||
530 | * ppc-opc.c (insert_imm32, extract_imm32): New functions. | |
531 | (insert_xts, extract_xts): New functions. | |
532 | (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define. | |
533 | (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define. | |
534 | (VXRC_MASK, VXSH_MASK): Define. | |
535 | (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx, | |
536 | vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx, | |
537 | vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx, | |
538 | vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx, | |
539 | vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq. | |
540 | (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb, | |
541 | xxblendvh, xxblendvw, xxblendvd, xxpermx. | |
542 | ||
c7d7aea2 AM |
543 | 2020-05-11 Alan Modra <amodra@gmail.com> |
544 | ||
545 | * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi, | |
546 | vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd, | |
547 | vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd, | |
548 | vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz, | |
549 | xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq. | |
550 | ||
94ba9882 AM |
551 | 2020-05-11 Alan Modra <amodra@gmail.com> |
552 | ||
553 | * ppc-opc.c (insert_xtp, extract_xtp): New functions. | |
554 | (XTP, DQXP, DQXP_MASK): Define. | |
555 | (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx. | |
556 | (prefix_opcodes): Add plxvp and pstxvp. | |
557 | ||
f4791f1a AM |
558 | 2020-05-11 Alan Modra <amodra@gmail.com> |
559 | ||
560 | * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld, | |
561 | vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw, | |
562 | vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd. | |
563 | ||
3ff0a5ba PB |
564 | 2020-05-11 Peter Bergner <bergner@linux.ibm.com> |
565 | ||
566 | * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics. | |
567 | ||
afef4fe9 PB |
568 | 2020-05-11 Peter Bergner <bergner@linux.ibm.com> |
569 | ||
570 | * ppc-opc.c (insert_l1opt, extract_l1opt): New functions. | |
571 | (L1OPT): Define. | |
572 | (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10. | |
573 | ||
1224c05d PB |
574 | 2020-05-11 Peter Bergner <bergner@linux.ibm.com> |
575 | ||
576 | * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand. | |
577 | ||
6bbb0c05 AM |
578 | 2020-05-11 Alan Modra <amodra@gmail.com> |
579 | ||
580 | * ppc-dis.c (powerpc_init_dialect): Default to "power10". | |
581 | ||
7c1f4227 AM |
582 | 2020-05-11 Alan Modra <amodra@gmail.com> |
583 | ||
584 | * ppc-dis.c (ppc_opts): Add "power10" entry. | |
585 | (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming. | |
586 | * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses. | |
587 | ||
73199c2b NC |
588 | 2020-05-11 Nick Clifton <nickc@redhat.com> |
589 | ||
590 | * po/fr.po: Updated French translation. | |
591 | ||
09c1e68a AC |
592 | 2020-04-30 Alex Coplan <alex.coplan@arm.com> |
593 | ||
594 | * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2. | |
595 | * aarch64-opc.c (fields): Add entry for FLD_imm16_2. | |
596 | (operand_general_constraint_met_p): validate | |
597 | AARCH64_OPND_UNDEFINED. | |
598 | * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry | |
599 | for FLD_imm16_2. | |
600 | * aarch64-asm-2.c: Regenerated. | |
601 | * aarch64-dis-2.c: Regenerated. | |
602 | * aarch64-opc-2.c: Regenerated. | |
603 | ||
9654d51a NC |
604 | 2020-04-29 Nick Clifton <nickc@redhat.com> |
605 | ||
606 | PR 22699 | |
607 | * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC | |
608 | and SETRC insns. | |
609 | ||
c2e71e57 NC |
610 | 2020-04-29 Nick Clifton <nickc@redhat.com> |
611 | ||
612 | * po/sv.po: Updated Swedish translation. | |
613 | ||
5c936ef5 NC |
614 | 2020-04-29 Nick Clifton <nickc@redhat.com> |
615 | ||
616 | PR 22699 | |
617 | * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use | |
618 | IMM0_8S for arithmetic insns and IMM0_8U for logical insns. | |
619 | * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add | |
620 | IMM0_8U case. | |
621 | ||
bb2a1453 AS |
622 | 2020-04-21 Andreas Schwab <schwab@linux-m68k.org> |
623 | ||
624 | PR 25848 | |
625 | * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of | |
626 | cmpi only on m68020up and cpu32. | |
627 | ||
c2e5c986 SD |
628 | 2020-04-20 Sudakshina Das <sudi.das@arm.com> |
629 | ||
630 | * aarch64-asm.c (aarch64_ins_none): New. | |
631 | * aarch64-asm.h (ins_none): New declaration. | |
632 | * aarch64-dis.c (aarch64_ext_none): New. | |
633 | * aarch64-dis.h (ext_none): New declaration. | |
634 | * aarch64-opc.c (aarch64_print_operand): Update case for | |
635 | AARCH64_OPND_BARRIER_PSB. | |
636 | * aarch64-tbl.h (aarch64_opcode_table): Add tsb. | |
637 | (AARCH64_OPERANDS): Update inserter/extracter for | |
638 | AARCH64_OPND_BARRIER_PSB to use new dummy functions. | |
639 | * aarch64-asm-2.c: Regenerated. | |
640 | * aarch64-dis-2.c: Regenerated. | |
641 | * aarch64-opc-2.c: Regenerated. | |
642 | ||
8a6e1d1d SD |
643 | 2020-04-20 Sudakshina Das <sudi.das@arm.com> |
644 | ||
645 | * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove. | |
646 | (aarch64_feature_ras, RAS): Likewise. | |
647 | (aarch64_feature_stat_profile, STAT_PROFILE): Likewise. | |
648 | (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716, | |
649 | autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp, | |
650 | autiaz, autiasp, autibz, autibsp to be CORE_INSN. | |
651 | * aarch64-asm-2.c: Regenerated. | |
652 | * aarch64-dis-2.c: Regenerated. | |
653 | * aarch64-opc-2.c: Regenerated. | |
654 | ||
e409955d FS |
655 | 2020-04-17 Fredrik Strupe <fredrik@strupe.net> |
656 | ||
657 | * arm-dis.c (neon_opcodes): Fix VDUP instruction masks. | |
658 | (print_insn_neon): Support disassembly of conditional | |
659 | instructions. | |
660 | ||
c54a9b56 DF |
661 | 2020-02-16 David Faust <david.faust@oracle.com> |
662 | ||
663 | * bpf-desc.c: Regenerate. | |
664 | * bpf-desc.h: Likewise. | |
665 | * bpf-opc.c: Regenerate. | |
666 | * bpf-opc.h: Likewise. | |
667 | ||
bb651e8b CL |
668 | 2020-04-07 Lili Cui <lili.cui@intel.com> |
669 | ||
670 | * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1, | |
671 | (prefix_table): New instructions (see prefixes above). | |
672 | (rm_table): Likewise | |
673 | * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS, | |
674 | CPU_ANY_TSXLDTRK_FLAGS. | |
675 | (cpu_flags): Add CpuTSXLDTRK. | |
676 | * i386-opc.h (enum): Add CpuTSXLDTRK. | |
677 | (i386_cpu_flags): Add cputsxldtrk. | |
678 | * i386-opc.tbl: Add XSUSPLDTRK insns. | |
679 | * i386-init.h: Regenerate. | |
680 | * i386-tbl.h: Likewise. | |
681 | ||
4b27d27c L |
682 | 2020-04-02 Lili Cui <lili.cui@intel.com> |
683 | ||
684 | * i386-dis.c (prefix_table): New instructions serialize. | |
685 | * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS, | |
686 | CPU_ANY_SERIALIZE_FLAGS. | |
687 | (cpu_flags): Add CpuSERIALIZE. | |
688 | * i386-opc.h (enum): Add CpuSERIALIZE. | |
689 | (i386_cpu_flags): Add cpuserialize. | |
690 | * i386-opc.tbl: Add SERIALIZE insns. | |
691 | * i386-init.h: Regenerate. | |
692 | * i386-tbl.h: Likewise. | |
693 | ||
832a5807 AM |
694 | 2020-03-26 Alan Modra <amodra@gmail.com> |
695 | ||
696 | * disassemble.h (opcodes_assert): Declare. | |
697 | (OPCODES_ASSERT): Define. | |
698 | * disassemble.c: Don't include assert.h. Include opintl.h. | |
699 | (opcodes_assert): New function. | |
700 | * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT. | |
701 | (bfd_h8_disassemble): Reduce size of data array. Correctly | |
702 | calculate maxlen. Omit insn decoding when insn length exceeds | |
703 | maxlen. Exit from nibble loop when looking for E, before | |
704 | accessing next data byte. Move processing of E outside loop. | |
705 | Replace tests of maxlen in loop with assertions. | |
706 | ||
4c4addbe AM |
707 | 2020-03-26 Alan Modra <amodra@gmail.com> |
708 | ||
709 | * arc-dis.c (find_format): Init needs_limm. Simplify use of limm. | |
710 | ||
a18cd0ca AM |
711 | 2020-03-25 Alan Modra <amodra@gmail.com> |
712 | ||
713 | * z80-dis.c (suffix): Init mybuf. | |
714 | ||
57cb32b3 AM |
715 | 2020-03-22 Alan Modra <amodra@gmail.com> |
716 | ||
717 | * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that | |
718 | successflly read from section. | |
719 | ||
beea5cc1 AM |
720 | 2020-03-22 Alan Modra <amodra@gmail.com> |
721 | ||
722 | * arc-dis.c (find_format): Use ISO C string concatenation rather | |
723 | than line continuation within a string. Don't access needs_limm | |
724 | before testing opcode != NULL. | |
725 | ||
03704c77 AM |
726 | 2020-03-22 Alan Modra <amodra@gmail.com> |
727 | ||
728 | * ns32k-dis.c (print_insn_arg): Update comment. | |
729 | (print_insn_ns32k): Reduce size of index_offset array, and | |
730 | initialize, passing -1 to print_insn_arg for args that are not | |
731 | an index. Don't exit arg loop early. Abort on bad arg number. | |
732 | ||
d1023b5d AM |
733 | 2020-03-22 Alan Modra <amodra@gmail.com> |
734 | ||
735 | * s12z-dis.c (abstract_read_memory): Don't print error on EOI. | |
736 | * s12z-opc.c: Formatting. | |
737 | (operands_f): Return an int. | |
738 | (opr_n_bytes_p1): Return -1 on reaching buffer memory limit. | |
739 | (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes), | |
740 | (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes), | |
741 | (exg_sex_discrim): Likewise. | |
742 | (create_immediate_operand, create_bitfield_operand), | |
743 | (create_register_operand_with_size, create_register_all_operand), | |
744 | (create_register_all16_operand, create_simple_memory_operand), | |
745 | (create_memory_operand, create_memory_auto_operand): Don't | |
746 | segfault on malloc failure. | |
747 | (z_ext24_decode): Return an int status, negative on fail, zero | |
748 | on success. | |
749 | (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2), | |
750 | (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base), | |
751 | (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7), | |
752 | (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x), | |
753 | (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode), | |
754 | (mov_imm_opr, ld_18bit_decode, exg_sex_decode), | |
755 | (loop_primitive_decode, shift_decode, psh_pul_decode), | |
756 | (bit_field_decode): Similarly. | |
757 | (z_decode_signed_value, decode_signed_value): Similarly. Add arg | |
758 | to return value, update callers. | |
759 | (x_opr_decode_with_size): Check all reads, returning NULL on fail. | |
760 | Don't segfault on NULL operand. | |
761 | (decode_operation): Return OP_INVALID on first fail. | |
762 | (decode_s12z): Check all reads, returning -1 on fail. | |
763 | ||
340f3ac8 AM |
764 | 2020-03-20 Alan Modra <amodra@gmail.com> |
765 | ||
766 | * metag-dis.c (print_insn_metag): Don't ignore status from | |
767 | read_memory_func. | |
768 | ||
fe90ae8a AM |
769 | 2020-03-20 Alan Modra <amodra@gmail.com> |
770 | ||
771 | * nds32-dis.c (print_insn_nds32): Remove unnecessary casts. | |
772 | Initialize parts of buffer not written when handling a possible | |
773 | 2-byte insn at end of section. Don't attempt decoding of such | |
774 | an insn by the 4-byte machinery. | |
775 | ||
833d919c AM |
776 | 2020-03-20 Alan Modra <amodra@gmail.com> |
777 | ||
778 | * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of | |
779 | partially filled buffer. Prevent lookup of 4-byte insns when | |
780 | only VLE 2-byte insns are possible due to section size. Print | |
781 | ".word" rather than ".long" for 2-byte leftovers. | |
782 | ||
327ef784 NC |
783 | 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com> |
784 | ||
785 | PR 25641 | |
786 | * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes. | |
787 | ||
1673df32 JB |
788 | 2020-03-13 Jan Beulich <jbeulich@suse.com> |
789 | ||
790 | * i386-dis.c (X86_64_0D): Rename to ... | |
791 | (X86_64_0E): ... this. | |
792 | ||
384f3689 L |
793 | 2020-03-09 H.J. Lu <hongjiu.lu@intel.com> |
794 | ||
795 | * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP). | |
796 | * Makefile.in: Regenerated. | |
797 | ||
865e2027 JB |
798 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
799 | ||
800 | * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp* | |
801 | 3-operand pseudos. | |
802 | * i386-tbl.h: Re-generate. | |
803 | ||
2f13234b JB |
804 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
805 | ||
806 | * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*, | |
807 | vprot*, vpsha*, and vpshl*. | |
808 | * i386-tbl.h: Re-generate. | |
809 | ||
3fabc179 JB |
810 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
811 | ||
812 | * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps, | |
813 | vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops. | |
814 | * i386-tbl.h: Re-generate. | |
815 | ||
3677e4c1 JB |
816 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
817 | ||
818 | * i386-gen.c (set_bitfield): Ignore zero-length field names. | |
819 | * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps, | |
820 | cmpss, cmppd, and cmpsd 2-operand pseudo-ops. | |
821 | * i386-tbl.h: Re-generate. | |
822 | ||
4c4898e8 JB |
823 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
824 | ||
825 | * i386-gen.c (struct template_arg, struct template_instance, | |
826 | struct template_param, struct template, templates, | |
827 | parse_template, expand_templates): New. | |
828 | (process_i386_opcodes): Various local variables moved to | |
829 | expand_templates. Call parse_template and expand_templates. | |
830 | * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc. | |
831 | * i386-tbl.h: Re-generate. | |
832 | ||
bc49bfd8 JB |
833 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
834 | ||
835 | * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph, | |
836 | vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate | |
837 | register and memory source templates. Replace VexW= by VexW* | |
838 | where applicable. | |
839 | * i386-tbl.h: Re-generate. | |
840 | ||
4873e243 JB |
841 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
842 | ||
843 | * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace | |
844 | VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable. | |
845 | * i386-tbl.h: Re-generate. | |
846 | ||
672a349b JB |
847 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
848 | ||
849 | * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax. | |
850 | * i386-tbl.h: Re-generate. | |
851 | ||
4ed21b58 JB |
852 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
853 | ||
854 | * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants. | |
855 | (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps, | |
856 | pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use | |
857 | VexW0 on SSE2AVX variants. | |
858 | (vmovq): Drop NoRex64 from XMM/XMM variants. | |
859 | (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb, | |
860 | vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where | |
861 | applicable use VexW0. | |
862 | * i386-tbl.h: Re-generate. | |
863 | ||
643bb870 JB |
864 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
865 | ||
866 | * i386-gen.c (opcode_modifiers): Remove Rex64 field. | |
867 | * i386-opc.h (Rex64): Delete. | |
868 | (struct i386_opcode_modifier): Remove rex64 field. | |
869 | * i386-opc.tbl (crc32): Drop Rex64. | |
870 | Replace Rex64 with Size64 everywhere else. | |
871 | * i386-tbl.h: Re-generate. | |
872 | ||
a23b33b3 JB |
873 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
874 | ||
875 | * i386-dis.c (OP_E_memory): Exclude recording of used address | |
876 | prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit | |
877 | addressed memory operands for MPX insns. | |
878 | ||
a0497384 JB |
879 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
880 | ||
881 | * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept, | |
882 | invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx, | |
883 | adox, mwaitx, rdpid, movdiri): Add IgnoreSize. | |
884 | (ptwrite): Split into non-64-bit and 64-bit forms. | |
885 | * i386-tbl.h: Re-generate. | |
886 | ||
b630c145 JB |
887 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
888 | ||
889 | * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand | |
890 | template. | |
891 | * i386-tbl.h: Re-generate. | |
892 | ||
a847e322 JB |
893 | 2020-03-04 Jan Beulich <jbeulich@suse.com> |
894 | ||
895 | * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New. | |
896 | (prefix_table): Move vmmcall here. Add vmgexit. | |
897 | (rm_table): Replace vmmcall entry by prefix_table[] escape. | |
898 | * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry. | |
899 | (cpu_flags): Add CpuSEV_ES entry. | |
900 | * i386-opc.h (CpuSEV_ES): New. | |
901 | (union i386_cpu_flags): Add cpusev_es field. | |
902 | * i386-opc.tbl (vmgexit): New. | |
903 | * i386-init.h, i386-tbl.h: Re-generate. | |
904 | ||
3cd7f3e3 L |
905 | 2020-03-03 H.J. Lu <hongjiu.lu@intel.com> |
906 | ||
907 | * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize | |
908 | with MnemonicSize. | |
909 | * i386-opc.h (IGNORESIZE): New. | |
910 | (DEFAULTSIZE): Likewise. | |
911 | (IgnoreSize): Removed. | |
912 | (DefaultSize): Likewise. | |
913 | (MnemonicSize): New. | |
914 | (i386_opcode_modifier): Replace ignoresize/defaultsize with | |
915 | mnemonicsize. | |
916 | * i386-opc.tbl (IgnoreSize): New. | |
917 | (DefaultSize): Likewise. | |
918 | * i386-tbl.h: Regenerated. | |
919 | ||
b8ba1385 SB |
920 | 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com> |
921 | ||
922 | PR 25627 | |
923 | * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX | |
924 | instructions. | |
925 | ||
10d97a0f L |
926 | 2020-03-03 H.J. Lu <hongjiu.lu@intel.com> |
927 | ||
928 | PR gas/25622 | |
929 | * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd, | |
930 | vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax. | |
931 | * i386-tbl.h: Regenerated. | |
932 | ||
dc1e8a47 AM |
933 | 2020-02-26 Alan Modra <amodra@gmail.com> |
934 | ||
935 | * aarch64-asm.c: Indent labels correctly. | |
936 | * aarch64-dis.c: Likewise. | |
937 | * aarch64-gen.c: Likewise. | |
938 | * aarch64-opc.c: Likewise. | |
939 | * alpha-dis.c: Likewise. | |
940 | * i386-dis.c: Likewise. | |
941 | * nds32-asm.c: Likewise. | |
942 | * nfp-dis.c: Likewise. | |
943 | * visium-dis.c: Likewise. | |
944 | ||
265b4673 CZ |
945 | 2020-02-25 Claudiu Zissulescu <claziss@gmail.com> |
946 | ||
947 | * arc-regs.h (int_vector_base): Make it available for all ARC | |
948 | CPUs. | |
949 | ||
bd0cf5a6 NC |
950 | 2020-02-20 Nelson Chu <nelson.chu@sifive.com> |
951 | ||
952 | * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is | |
953 | changed. | |
954 | ||
fa164239 JW |
955 | 2020-02-19 Nelson Chu <nelson.chu@sifive.com> |
956 | ||
957 | * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed | |
958 | c.mv/c.li if rs1 is zero. | |
959 | ||
272a84b1 L |
960 | 2020-02-17 H.J. Lu <hongjiu.lu@intel.com> |
961 | ||
962 | * i386-gen.c (cpu_flag_init): Replace CpuABM with | |
963 | CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add | |
964 | CPU_POPCNT_FLAGS. | |
965 | (cpu_flags): Remove CpuABM. Add CpuPOPCNT. | |
966 | * i386-opc.h (CpuABM): Removed. | |
967 | (CpuPOPCNT): New. | |
968 | (i386_cpu_flags): Remove cpuabm. Add cpupopcnt. | |
969 | * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on | |
970 | popcnt. Remove CpuABM from lzcnt. | |
971 | * i386-init.h: Regenerated. | |
972 | * i386-tbl.h: Likewise. | |
973 | ||
1f730c46 JB |
974 | 2020-02-17 Jan Beulich <jbeulich@suse.com> |
975 | ||
976 | * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss): | |
977 | Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/ | |
978 | VexW1 instead of open-coding them. | |
979 | * i386-tbl.h: Re-generate. | |
980 | ||
c8f8eebc JB |
981 | 2020-02-17 Jan Beulich <jbeulich@suse.com> |
982 | ||
983 | * i386-opc.tbl (AddrPrefixOpReg): Define. | |
984 | (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx, | |
985 | umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64 | |
986 | templates. Drop NoRex64. | |
987 | * i386-tbl.h: Re-generate. | |
988 | ||
b9915cbc JB |
989 | 2020-02-17 Jan Beulich <jbeulich@suse.com> |
990 | ||
991 | PR gas/6518 | |
992 | * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq, | |
993 | vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms | |
994 | into Intel syntax instance (with Unpsecified) and AT&T one | |
995 | (without). | |
996 | (vcvtneps2bf16): Likewise, along with folding the two so far | |
997 | separate ones. | |
998 | * i386-tbl.h: Re-generate. | |
999 | ||
ce504911 L |
1000 | 2020-02-16 H.J. Lu <hongjiu.lu@intel.com> |
1001 | ||
1002 | * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from | |
1003 | CPU_ANY_SSE4A_FLAGS. | |
1004 | ||
dabec65d AM |
1005 | 2020-02-17 Alan Modra <amodra@gmail.com> |
1006 | ||
1007 | * i386-gen.c (cpu_flag_init): Correct last change. | |
1008 | ||
af5c13b0 L |
1009 | 2020-02-16 H.J. Lu <hongjiu.lu@intel.com> |
1010 | ||
1011 | * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove | |
1012 | CPU_ANY_SSE4_FLAGS. | |
1013 | ||
6867aac0 L |
1014 | 2020-02-14 H.J. Lu <hongjiu.lu@intel.com> |
1015 | ||
1016 | * i386-opc.tbl (movsx): Remove Intel syntax comments. | |
1017 | (movzx): Likewise. | |
1018 | ||
65fca059 JB |
1019 | 2020-02-14 Jan Beulich <jbeulich@suse.com> |
1020 | ||
1021 | PR gas/25438 | |
1022 | * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as | |
1023 | destination for Cpu64-only variant. | |
1024 | (movzx): Fold patterns. | |
1025 | * i386-tbl.h: Re-generate. | |
1026 | ||
7deea9aa JB |
1027 | 2020-02-13 Jan Beulich <jbeulich@suse.com> |
1028 | ||
1029 | * i386-gen.c (cpu_flag_init): Move CpuSSE4a from | |
1030 | CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add | |
1031 | CPU_ANY_SSE4_FLAGS entry. | |
1032 | * i386-init.h: Re-generate. | |
1033 | ||
6c0946d0 JB |
1034 | 2020-02-12 Jan Beulich <jbeulich@suse.com> |
1035 | ||
1036 | * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form | |
1037 | with Unspecified, making the present one AT&T syntax only. | |
1038 | * i386-tbl.h: Re-generate. | |
1039 | ||
ddb56fe6 JB |
1040 | 2020-02-12 Jan Beulich <jbeulich@suse.com> |
1041 | ||
1042 | * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants. | |
1043 | * i386-tbl.h: Re-generate. | |
1044 | ||
5990e377 JB |
1045 | 2020-02-12 Jan Beulich <jbeulich@suse.com> |
1046 | ||
1047 | PR gas/24546 | |
1048 | * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode. | |
1049 | * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into | |
1050 | Amd64 and Intel64 templates. | |
1051 | (call, jmp): Likewise for far indirect variants. Dro | |
1052 | Unspecified. | |
1053 | * i386-tbl.h: Re-generate. | |
1054 | ||
50128d0c JB |
1055 | 2020-02-11 Jan Beulich <jbeulich@suse.com> |
1056 | ||
1057 | * i386-gen.c (opcode_modifiers): Remove ShortForm entry. | |
1058 | * i386-opc.h (ShortForm): Delete. | |
1059 | (struct i386_opcode_modifier): Remove shortform field. | |
1060 | * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld, | |
1061 | fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub, | |
1062 | fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp, | |
1063 | ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq): | |
1064 | Drop ShortForm. | |
1065 | * i386-tbl.h: Re-generate. | |
1066 | ||
1e05b5c4 JB |
1067 | 2020-02-11 Jan Beulich <jbeulich@suse.com> |
1068 | ||
1069 | * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip, | |
1070 | fucompi): Drop ShortForm from operand-less templates. | |
1071 | * i386-tbl.h: Re-generate. | |
1072 | ||
2f5dd314 AM |
1073 | 2020-02-11 Alan Modra <amodra@gmail.com> |
1074 | ||
1075 | * cgen-ibld.in (extract_normal): Set *valuep on all return paths. | |
1076 | * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c, | |
1077 | * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c, | |
1078 | * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c, | |
1079 | * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate. | |
1080 | ||
5aae9ae9 MM |
1081 | 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com> |
1082 | ||
1083 | * arm-dis.c (print_insn_cde): Define 'V' parse character. | |
1084 | (cde_opcodes): Add VCX* instructions. | |
1085 | ||
4934a27c MM |
1086 | 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> |
1087 | Matthew Malcomson <matthew.malcomson@arm.com> | |
1088 | ||
1089 | * arm-dis.c (struct cdeopcode32): New. | |
1090 | (CDE_OPCODE): New macro. | |
1091 | (cde_opcodes): New disassembly table. | |
1092 | (regnames): New option to table. | |
1093 | (cde_coprocs): New global variable. | |
1094 | (print_insn_cde): New | |
1095 | (print_insn_thumb32): Use print_insn_cde. | |
1096 | (parse_arm_disassembler_options): Parse coprocN args. | |
1097 | ||
4b5aaf5f L |
1098 | 2020-02-10 H.J. Lu <hongjiu.lu@intel.com> |
1099 | ||
1100 | PR gas/25516 | |
1101 | * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64 | |
1102 | with ISA64. | |
1103 | * i386-opc.h (AMD64): Removed. | |
1104 | (Intel64): Likewose. | |
1105 | (AMD64): New. | |
1106 | (INTEL64): Likewise. | |
1107 | (INTEL64ONLY): Likewise. | |
1108 | (i386_opcode_modifier): Replace amd64 and intel64 with isa64. | |
1109 | * i386-opc.tbl (Amd64): New. | |
1110 | (Intel64): Likewise. | |
1111 | (Intel64Only): Likewise. | |
1112 | Replace AMD64 with Amd64. Update sysenter/sysenter with | |
1113 | Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter. | |
1114 | * i386-tbl.h: Regenerated. | |
1115 | ||
9fc0b501 SB |
1116 | 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com> |
1117 | ||
1118 | PR 25469 | |
1119 | * z80-dis.c: Add support for GBZ80 opcodes. | |
1120 | ||
c5d7be0c AM |
1121 | 2020-02-04 Alan Modra <amodra@gmail.com> |
1122 | ||
1123 | * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned. | |
1124 | ||
44e4546f AM |
1125 | 2020-02-03 Alan Modra <amodra@gmail.com> |
1126 | ||
1127 | * m32c-ibld.c: Regenerate. | |
1128 | ||
b2b1453a AM |
1129 | 2020-02-01 Alan Modra <amodra@gmail.com> |
1130 | ||
1131 | * frv-ibld.c: Regenerate. | |
1132 | ||
4102be5c JB |
1133 | 2020-01-31 Jan Beulich <jbeulich@suse.com> |
1134 | ||
1135 | * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete. | |
1136 | (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label. | |
1137 | (OP_E_memory): Replace xmm_mdq_mode case label by | |
1138 | vex_scalar_w_dq_mode one. | |
1139 | * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar. | |
1140 | ||
825bd36c JB |
1141 | 2020-01-31 Jan Beulich <jbeulich@suse.com> |
1142 | ||
1143 | * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete. | |
1144 | (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode, | |
1145 | vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments. | |
1146 | (intel_operand_size): Drop vex_w_dq_mode case label. | |
1147 | ||
c3036ed0 RS |
1148 | 2020-01-31 Richard Sandiford <richard.sandiford@arm.com> |
1149 | ||
1150 | * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt. | |
1151 | Remove C_SCAN_MOVPRFX for SVE bfcvtnt. | |
1152 | ||
0c115f84 AM |
1153 | 2020-01-30 Alan Modra <amodra@gmail.com> |
1154 | ||
1155 | * m32c-ibld.c: Regenerate. | |
1156 | ||
bd434cc4 JM |
1157 | 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> |
1158 | ||
1159 | * bpf-opc.c: Regenerate. | |
1160 | ||
aeab2b26 JB |
1161 | 2020-01-30 Jan Beulich <jbeulich@suse.com> |
1162 | ||
1163 | * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators. | |
1164 | (dis386): Use them to replace C2/C3 table entries. | |
1165 | (x86_64_table): Add X86_64_C2 and X86_64_C3 entries. | |
1166 | * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64 | |
1167 | ones. Use Size64 instead of DefaultSize on Intel64 ones. | |
1168 | * i386-tbl.h: Re-generate. | |
1169 | ||
62b3f548 JB |
1170 | 2020-01-30 Jan Beulich <jbeulich@suse.com> |
1171 | ||
1172 | * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword | |
1173 | forms. | |
1174 | (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop | |
1175 | DefaultSize. | |
1176 | * i386-tbl.h: Re-generate. | |
1177 | ||
1bd8ae10 AM |
1178 | 2020-01-30 Alan Modra <amodra@gmail.com> |
1179 | ||
1180 | * tic4x-dis.c (tic4x_dp): Make unsigned. | |
1181 | ||
bc31405e L |
1182 | 2020-01-27 H.J. Lu <hongjiu.lu@intel.com> |
1183 | Jan Beulich <jbeulich@suse.com> | |
1184 | ||
1185 | PR binutils/25445 | |
1186 | * i386-dis.c (MOVSXD_Fixup): New function. | |
1187 | (movsxd_mode): New enum. | |
1188 | (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd. | |
1189 | (intel_operand_size): Handle movsxd_mode. | |
1190 | (OP_E_register): Likewise. | |
1191 | (OP_G): Likewise. | |
1192 | * i386-opc.tbl: Remove Rex64 and allow 32-bit destination | |
1193 | register on movsxd. Add movsxd with 16-bit destination register | |
1194 | for AMD64 and Intel64 ISAs. | |
1195 | * i386-tbl.h: Regenerated. | |
1196 | ||
7568c93b TC |
1197 | 2020-01-27 Tamar Christina <tamar.christina@arm.com> |
1198 | ||
1199 | PR 25403 | |
1200 | * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv. | |
1201 | * aarch64-asm-2.c: Regenerate | |
1202 | * aarch64-dis-2.c: Likewise. | |
1203 | * aarch64-opc-2.c: Likewise. | |
1204 | ||
c006a730 JB |
1205 | 2020-01-21 Jan Beulich <jbeulich@suse.com> |
1206 | ||
1207 | * i386-opc.tbl (sysret): Drop DefaultSize. | |
1208 | * i386-tbl.h: Re-generate. | |
1209 | ||
c906a69a JB |
1210 | 2020-01-21 Jan Beulich <jbeulich@suse.com> |
1211 | ||
1212 | * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and | |
1213 | Dword. | |
1214 | (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword. | |
1215 | * i386-tbl.h: Re-generate. | |
1216 | ||
26916852 NC |
1217 | 2020-01-20 Nick Clifton <nickc@redhat.com> |
1218 | ||
1219 | * po/de.po: Updated German translation. | |
1220 | * po/pt_BR.po: Updated Brazilian Portuguese translation. | |
1221 | * po/uk.po: Updated Ukranian translation. | |
1222 | ||
4d6cbb64 AM |
1223 | 2020-01-20 Alan Modra <amodra@gmail.com> |
1224 | ||
1225 | * hppa-dis.c (fput_const): Remove useless cast. | |
1226 | ||
2bddb71a AM |
1227 | 2020-01-20 Alan Modra <amodra@gmail.com> |
1228 | ||
1229 | * arm-dis.c (print_insn_arm): Wrap 'T' value. | |
1230 | ||
1b1bb2c6 NC |
1231 | 2020-01-18 Nick Clifton <nickc@redhat.com> |
1232 | ||
1233 | * configure: Regenerate. | |
1234 | * po/opcodes.pot: Regenerate. | |
1235 | ||
ae774686 NC |
1236 | 2020-01-18 Nick Clifton <nickc@redhat.com> |
1237 | ||
1238 | Binutils 2.34 branch created. | |
1239 | ||
07f1f3aa CB |
1240 | 2020-01-17 Christian Biesinger <cbiesinger@google.com> |
1241 | ||
1242 | * opintl.h: Fix spelling error (seperate). | |
1243 | ||
42e04b36 L |
1244 | 2020-01-17 H.J. Lu <hongjiu.lu@intel.com> |
1245 | ||
1246 | * i386-opc.tbl: Add {vex} pseudo prefix. | |
1247 | * i386-tbl.h: Regenerated. | |
1248 | ||
2da2eaf4 AV |
1249 | 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
1250 | ||
1251 | PR 25376 | |
1252 | * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits. | |
1253 | (neon_opcodes): Likewise. | |
1254 | (select_arm_features): Make sure we enable MVE bits when selecting | |
1255 | armv8.1-m.main. Make sure we do not enable MVE bits when not selecting | |
1256 | any architecture. | |
1257 | ||
d0849eed JB |
1258 | 2020-01-16 Jan Beulich <jbeulich@suse.com> |
1259 | ||
1260 | * i386-opc.tbl: Drop stale comment from XOP section. | |
1261 | ||
9cf70a44 JB |
1262 | 2020-01-16 Jan Beulich <jbeulich@suse.com> |
1263 | ||
1264 | * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms. | |
1265 | (extractps): Add VexWIG to SSE2AVX forms. | |
1266 | * i386-tbl.h: Re-generate. | |
1267 | ||
4814632e JB |
1268 | 2020-01-16 Jan Beulich <jbeulich@suse.com> |
1269 | ||
1270 | * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop | |
1271 | Size64 from and use VexW1 on SSE2AVX forms. | |
1272 | (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from | |
1273 | VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1. | |
1274 | * i386-tbl.h: Re-generate. | |
1275 | ||
aad09917 AM |
1276 | 2020-01-15 Alan Modra <amodra@gmail.com> |
1277 | ||
1278 | * tic4x-dis.c (tic4x_version): Make unsigned long. | |
1279 | (optab, optab_special, registernames): New file scope vars. | |
1280 | (tic4x_print_register): Set up registernames rather than | |
1281 | malloc'd registertable. | |
1282 | (tic4x_disassemble): Delete optable and optable_special. Use | |
1283 | optab and optab_special instead. Throw away old optab, | |
1284 | optab_special and registernames when info->mach changes. | |
1285 | ||
7a6bf3be SB |
1286 | 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com> |
1287 | ||
1288 | PR 25377 | |
1289 | * z80-dis.c (suffix): Use .db instruction to generate double | |
1290 | prefix. | |
1291 | ||
ca1eaac0 AM |
1292 | 2020-01-14 Alan Modra <amodra@gmail.com> |
1293 | ||
1294 | * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short | |
1295 | values to unsigned before shifting. | |
1296 | ||
1d67fe3b TT |
1297 | 2020-01-13 Thomas Troeger <tstroege@gmx.de> |
1298 | ||
1299 | * arm-dis.c (print_insn_arm): Fill in insn info fields for control | |
1300 | flow instructions. | |
1301 | (print_insn_thumb16, print_insn_thumb32): Likewise. | |
1302 | (print_insn): Initialize the insn info. | |
1303 | * i386-dis.c (print_insn): Initialize the insn info fields, and | |
1304 | detect jumps. | |
1305 | ||
5e4f7e05 CZ |
1306 | 2012-01-13 Claudiu Zissulescu <claziss@gmail.com> |
1307 | ||
1308 | * arc-opc.c (C_NE): Make it required. | |
1309 | ||
b9fe6b8a CZ |
1310 | 2012-01-13 Claudiu Zissulescu <claziss@gmail.com> |
1311 | ||
1312 | * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo | |
1313 | reserved register name. | |
1314 | ||
90dee485 AM |
1315 | 2020-01-13 Alan Modra <amodra@gmail.com> |
1316 | ||
1317 | * ns32k-dis.c (Is_gen): Use strchr, add 'f'. | |
1318 | (print_insn_ns32k): Adjust ioffset for 'f' index_offset. | |
1319 | ||
febda64f AM |
1320 | 2020-01-13 Alan Modra <amodra@gmail.com> |
1321 | ||
1322 | * wasm32-dis.c (print_insn_wasm32): Localise variables. Store | |
1323 | result of wasm_read_leb128 in a uint64_t and check that bits | |
1324 | are not lost when copying to other locals. Use uint32_t for | |
1325 | most locals. Use PRId64 when printing int64_t. | |
1326 | ||
df08b588 AM |
1327 | 2020-01-13 Alan Modra <amodra@gmail.com> |
1328 | ||
1329 | * score-dis.c: Formatting. | |
1330 | * score7-dis.c: Formatting. | |
1331 | ||
b2c759ce AM |
1332 | 2020-01-13 Alan Modra <amodra@gmail.com> |
1333 | ||
1334 | * score-dis.c (print_insn_score48): Use unsigned variables for | |
1335 | unsigned values. Don't left shift negative values. | |
1336 | (print_insn_score32): Likewise. | |
1337 | * score7-dis.c (print_insn_score32, print_insn_score16): Likewise. | |
1338 | ||
5496abe1 AM |
1339 | 2020-01-13 Alan Modra <amodra@gmail.com> |
1340 | ||
1341 | * tic4x-dis.c (tic4x_print_register): Remove dead code. | |
1342 | ||
202e762b AM |
1343 | 2020-01-13 Alan Modra <amodra@gmail.com> |
1344 | ||
1345 | * fr30-ibld.c: Regenerate. | |
1346 | ||
7ef412cf AM |
1347 | 2020-01-13 Alan Modra <amodra@gmail.com> |
1348 | ||
1349 | * xgate-dis.c (print_insn): Don't left shift signed value. | |
1350 | (ripBits): Formatting, use 1u. | |
1351 | ||
7f578b95 AM |
1352 | 2020-01-10 Alan Modra <amodra@gmail.com> |
1353 | ||
1354 | * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned. | |
1355 | * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval. | |
1356 | ||
441af85b AM |
1357 | 2020-01-10 Alan Modra <amodra@gmail.com> |
1358 | ||
1359 | * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG, | |
1360 | and XRREG value earlier to avoid a shift with negative exponent. | |
1361 | * m10200-dis.c (disassemble): Similarly. | |
1362 | ||
bce58db4 NC |
1363 | 2020-01-09 Nick Clifton <nickc@redhat.com> |
1364 | ||
1365 | PR 25224 | |
1366 | * z80-dis.c (ld_ii_ii): Use correct cast. | |
1367 | ||
40c75bc8 SB |
1368 | 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com> |
1369 | ||
1370 | PR 25224 | |
1371 | * z80-dis.c (ld_ii_ii): Use character constant when checking | |
1372 | opcode byte value. | |
1373 | ||
d835a58b JB |
1374 | 2020-01-09 Jan Beulich <jbeulich@suse.com> |
1375 | ||
1376 | * i386-dis.c (SEP_Fixup): New. | |
1377 | (SEP): Define. | |
1378 | (dis386_twobyte): Use it for sysenter/sysexit. | |
1379 | (enum x86_64_isa): Change amd64 enumerator to value 1. | |
1380 | (OP_J): Compare isa64 against intel64 instead of amd64. | |
1381 | * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64 | |
1382 | forms. | |
1383 | * i386-tbl.h: Re-generate. | |
1384 | ||
030a2e78 AM |
1385 | 2020-01-08 Alan Modra <amodra@gmail.com> |
1386 | ||
1387 | * z8k-dis.c: Include libiberty.h | |
1388 | (instr_data_s): Make max_fetched unsigned. | |
1389 | (z8k_lookup_instr): Make nibl_index and tabl_index unsigned. | |
1390 | Don't exceed byte_info bounds. | |
1391 | (output_instr): Make num_bytes unsigned. | |
1392 | (unpack_instr): Likewise for nibl_count and loop. | |
1393 | * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and | |
1394 | idx unsigned. | |
1395 | * z8k-opc.h: Regenerate. | |
1396 | ||
bb82aefe SV |
1397 | 2020-01-07 Shahab Vahedi <shahab@synopsys.com> |
1398 | ||
1399 | * arc-tbl.h (llock): Use 'LLOCK' as class. | |
1400 | (llockd): Likewise. | |
1401 | (scond): Use 'SCOND' as class. | |
1402 | (scondd): Likewise. | |
1403 | (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit. | |
1404 | (scondd): Likewise. | |
1405 | ||
cc6aa1a6 AM |
1406 | 2020-01-06 Alan Modra <amodra@gmail.com> |
1407 | ||
1408 | * m32c-ibld.c: Regenerate. | |
1409 | ||
660e62b1 AM |
1410 | 2020-01-06 Alan Modra <amodra@gmail.com> |
1411 | ||
1412 | PR 25344 | |
1413 | * z80-dis.c (suffix): Don't use a local struct buffer copy. | |
1414 | Peek at next byte to prevent recursion on repeated prefix bytes. | |
1415 | Ensure uninitialised "mybuf" is not accessed. | |
1416 | (print_insn_z80): Don't zero n_fetch and n_used here,.. | |
1417 | (print_insn_z80_buf): ..do it here instead. | |
1418 | ||
c9ae58fe AM |
1419 | 2020-01-04 Alan Modra <amodra@gmail.com> |
1420 | ||
1421 | * m32r-ibld.c: Regenerate. | |
1422 | ||
5f57d4ec AM |
1423 | 2020-01-04 Alan Modra <amodra@gmail.com> |
1424 | ||
1425 | * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value. | |
1426 | ||
2c5c1196 AM |
1427 | 2020-01-04 Alan Modra <amodra@gmail.com> |
1428 | ||
1429 | * crx-dis.c (match_opcode): Avoid shift left of signed value. | |
1430 | ||
2e98c6c5 AM |
1431 | 2020-01-04 Alan Modra <amodra@gmail.com> |
1432 | ||
1433 | * d30v-dis.c (print_insn): Avoid signed overflow in left shift. | |
1434 | ||
567dfba2 JB |
1435 | 2020-01-03 Jan Beulich <jbeulich@suse.com> |
1436 | ||
5437a02a JB |
1437 | * aarch64-tbl.h (aarch64_opcode_table): Use |
1438 | SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}. | |
1439 | ||
1440 | 2020-01-03 Jan Beulich <jbeulich@suse.com> | |
1441 | ||
1442 | * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD | |
567dfba2 JB |
1443 | forms of SUDOT and USDOT. |
1444 | ||
8c45011a JB |
1445 | 2020-01-03 Jan Beulich <jbeulich@suse.com> |
1446 | ||
5437a02a | 1447 | * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from |
8c45011a JB |
1448 | uzip{1,2}. |
1449 | * opcodes/aarch64-dis-2.c: Re-generate. | |
1450 | ||
f4950f76 JB |
1451 | 2020-01-03 Jan Beulich <jbeulich@suse.com> |
1452 | ||
5437a02a | 1453 | * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit |
f4950f76 JB |
1454 | FMMLA encoding. |
1455 | * opcodes/aarch64-dis-2.c: Re-generate. | |
1456 | ||
6655dba2 SB |
1457 | 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com> |
1458 | ||
1459 | * z80-dis.c: Add support for eZ80 and Z80 instructions. | |
1460 | ||
b14ce8bf AM |
1461 | 2020-01-01 Alan Modra <amodra@gmail.com> |
1462 | ||
1463 | Update year range in copyright notice of all files. | |
1464 | ||
0b114740 | 1465 | For older changes see ChangeLog-2019 |
3499769a | 1466 | \f |
0b114740 | 1467 | Copyright (C) 2020 Free Software Foundation, Inc. |
3499769a AM |
1468 | |
1469 | Copying and distribution of this file, with or without modification, | |
1470 | are permitted in any medium without royalty provided the copyright | |
1471 | notice and this notice are preserved. | |
1472 | ||
1473 | Local Variables: | |
1474 | mode: change-log | |
1475 | left-margin: 8 | |
1476 | fill-column: 74 | |
1477 | version-control: never | |
1478 | End: |