Commit | Line | Data |
---|---|---|
46f900c0 MF |
1 | 2021-01-08 Mike Frysinger <vapier@gentoo.org> |
2 | ||
3 | * configure: Regenerate. | |
4 | ||
dfb856ba MF |
5 | 2021-01-04 Mike Frysinger <vapier@gentoo.org> |
6 | ||
7 | * configure: Regenerate. | |
8 | ||
69b1ffdb CB |
9 | 2020-02-06 Carlo Bramini <carlo_bramini@users.sourceforge.net> |
10 | ||
11 | PR sim/25318 | |
12 | * simulator.c (blr): Read destination register before calling | |
13 | aarch64_save_LR. | |
14 | ||
cd5b6074 AB |
15 | 2019-03-28 Andrew Burgess <andrew.burgess@embecosm.com> |
16 | ||
17 | * cpustate.c: Add 'libiberty.h' include. | |
18 | * interp.c: Add 'sim-assert.h' include. | |
19 | ||
5c887dd5 JB |
20 | 2017-09-06 John Baldwin <jhb@FreeBSD.org> |
21 | ||
22 | * configure: Regenerate. | |
23 | ||
bf155438 JW |
24 | 2017-04-22 Jim Wilson <jim.wilson@linaro.org> |
25 | ||
26 | * simulator.c (vec_load): Add M argument. Rewrite to iterate over | |
27 | registers based on structure size. | |
28 | (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load. | |
29 | (LD1_1): Replace with call to vec_load. | |
30 | (vec_store): Add new M argument. Rewrite to iterate over registers | |
31 | based on structure size. | |
32 | (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store. | |
33 | (ST1_1): Replace with call to vec_store. | |
34 | ||
ae27d3fe JW |
35 | 2017-04-08 Jim Wilson <jim.wilson@linaro.org> |
36 | ||
b630840c JW |
37 | * simulator.c (do_vec_FCVTL): New. |
38 | (do_vec_op1): Call do_vec_FCVTL. | |
39 | ||
ae27d3fe JW |
40 | * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero, |
41 | do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New. | |
42 | (do_scalar_vec): Add calls to new functions. | |
43 | ||
f1241682 JW |
44 | 2017-03-25 Jim Wilson <jim.wilson@linaro.org> |
45 | ||
46 | * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry | |
47 | flag check. | |
48 | ||
8ecbe595 JW |
49 | 2017-03-03 Jim Wilson <jim.wilson@linaro.org> |
50 | ||
51 | * simulator.c (mul64hi): Shift carry left by 32. | |
52 | (smulh): Change signum to negate. If negate, invert result, and add | |
53 | carry bit if low part of multiply result is zero. | |
54 | ||
ac189e7b JW |
55 | 2017-02-25 Jim Wilson <jim.wilson@linaro.org> |
56 | ||
152e1e1b JW |
57 | * simulator.c (do_vec_SMOV_into_scalar): New. |
58 | (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar. | |
59 | Rewritten. | |
60 | (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted. | |
61 | (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call. Add | |
62 | do_vec_SMOV_into_scalar call. Delete do_vec_MOV_into_scalar and | |
63 | do_vec_UMOV calls. Add do_vec_UMOV_into_scalar call. | |
64 | ||
ac189e7b JW |
65 | * simulator.c (popcount): New. |
66 | (do_vec_CNT): New. | |
67 | (do_vec_op1): Add do_vec_CNT call. | |
68 | ||
2e7e5e28 JW |
69 | 2017-02-19 Jim Wilson <jim.wilson@linaro.org> |
70 | ||
71 | * simulator.c (do_vec_ADDV): Mov val declaration inside each case, | |
72 | with type set to input type size. | |
73 | (do_vec_xtl): Change bias from 3 to 4 for byte case. | |
74 | ||
e8f42b5e JW |
75 | 2017-02-14 Jim Wilson <jim.wilson@linaro.org> |
76 | ||
742e3a77 JW |
77 | * simulator.c (do_vec_MLA): Rewrite switch body. |
78 | ||
bf25e9a0 JW |
79 | * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and |
80 | 2. Move test_false if inside loop. Fix logic for computing result | |
81 | stored to vd. | |
82 | ||
e8f42b5e JW |
83 | * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New. |
84 | (do_vec_LDn_single, do_vec_STn_single): New. | |
85 | (do_vec_LDnR): Add and set new nregs var. Replace switch on nregs with | |
86 | loop over nregs using new var n. Add n times size to address in loop. | |
87 | Add n to vd in loop. | |
88 | (do_vec_load_store): Add comment for instruction bit 24. New var | |
89 | single to hold instruction bit 24. Add new code to use single. Move | |
90 | ldnr support inside single if statements. Fix ldnr register counts | |
91 | inside post if statement. Change HALT_NYI calls to HALT_UNALLOC. | |
92 | ||
fbf32f63 JW |
93 | 2017-01-23 Jim Wilson <jim.wilson@linaro.org> |
94 | ||
95 | * simulator.c (do_vec_compare): Add case 0x23 for CMTST. | |
96 | ||
05b3d79d JW |
97 | 2017-01-17 Jim Wilson <jim.wilson@linaro.org> |
98 | ||
99 | * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of | |
100 | aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In | |
101 | case 3, call HALT_UNALLOC unconditionally. | |
102 | (do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to | |
103 | i + 2. Delete if on bias, change index to i + bias * X. | |
104 | ||
a4fb5981 JW |
105 | 2017-01-09 Jim Wilson <jim.wilson@linaro.org> |
106 | ||
107 | * simulator.c (do_vec_UZP): Rewrite. | |
108 | ||
c0386d4d JW |
109 | 2017-01-04 Jim Wilson <jim.wilson@linaro.org> |
110 | ||
111 | * cpustate.c: Include math.h. | |
112 | (aarch64_set_FP_float): Use signbit to check for signed zero. | |
113 | (aarch64_set_FP_double): Likewise. | |
114 | * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break. | |
115 | (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth | |
116 | args same size as third arg. | |
117 | (fmaxnm): Use isnan instead of fpclassify. | |
118 | (fminnm, dmaxnm, dminnm): Likewise. | |
119 | (do_vec_MLS): Reverse order of subtraction operands. | |
120 | (dexSimpleFPCondSelect): Call aarch64_get_FP_double or | |
121 | aarch64_get_FP_float to get source register contents. | |
122 | (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN, | |
123 | DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN, | |
124 | DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New. | |
125 | (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in | |
126 | raise_exception calls. | |
127 | ||
87903eaf JW |
128 | 2016-12-21 Jim Wilson <jim.wilson@linaro.org> |
129 | ||
130 | * simulator.c (set_flags_for_float_compare): Add code to handle Inf. | |
131 | Add comment to document NaN issue. | |
132 | (set_flags_for_double_compare): Likewise. | |
133 | ||
963201cf JW |
134 | 2016-12-13 Jim Wilson <jim.wilson@linaro.org> |
135 | ||
136 | * simulator.c (NEG, POS): Move before set_flags_for_add64. | |
137 | (set_flags_for_add64): Replace with a modified copy of | |
138 | set_flags_for_sub64. | |
139 | ||
668650d5 JW |
140 | 2016-12-03 Jim Wilson <jim.wilson@linaro.org> |
141 | ||
142 | * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting. | |
143 | (dexTestBranchImmediate): Shift high bit of pos by 5 not 4. | |
144 | ||
88ddd4a1 JW |
145 | 2016-12-01 Jim Wilson <jim.wilson@linaro.org> |
146 | ||
88256e71 | 147 | * simulator.c (fsturs): Switch use of rn and st variables. |
88ddd4a1 JW |
148 | (fsturd, fsturq): Likewise |
149 | ||
5357150c MF |
150 | 2016-08-15 Mike Frysinger <vapier@gentoo.org> |
151 | ||
152 | * interp.c: Include bfd.h. | |
153 | (symcount, symtab, aarch64_get_sym_value): Delete. | |
154 | (remove_useless_symbols): Change count type to long. | |
155 | (aarch64_get_func): Add SIM_DESC to arg list. Add symcount | |
156 | and symtab local variables. | |
157 | (sim_create_inferior): Delete storage. Replace symbol code | |
158 | with a call to trace_load_symbols. | |
159 | * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h | |
160 | includes. | |
161 | (aarch64_get_heap_start): Change aarch64_get_sym_value to | |
162 | trace_sym_value. | |
163 | * memory.h: Delete bfd.h include. | |
164 | (mem_add_blk): Delete unused prototype. | |
165 | * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func. | |
166 | * simulator.c (aarch64_get_func): Add SIM_DESC to arg list. | |
167 | (aarch64_get_sym_value): Delete. | |
168 | ||
b14bdb3b NC |
169 | 2016-08-12 Nick Clifton <nickc@redhat.com> |
170 | ||
171 | * simulator.c (aarch64_step): Revert pervious delta. | |
172 | (aarch64_run): Call sim_events_tick after each | |
173 | instruction is simulated, and if necessary call | |
174 | sim_events_process. | |
175 | * simulator.h: Revert previous delta. | |
176 | ||
6a277579 NC |
177 | 2016-08-11 Nick Clifton <nickc@redhat.com> |
178 | ||
179 | * interp.c (sim_create_inferior): Allow for being called with a | |
180 | NULL abfd parameter. If a bfd is provided, initialise the sim | |
181 | with that start address. | |
182 | * simulator.c (HALT_NYI): Just print out the numeric value of the | |
183 | instruction when not tracing. | |
b14bdb3b NC |
184 | (aarch64_step): Change from static to global. |
185 | * simulator.h: Add a prototype for aarch64_step(). | |
6a277579 | 186 | |
293acfae AM |
187 | 2016-07-27 Alan Modra <amodra@gmail.com> |
188 | ||
189 | * memory.c: Don't include libbfd.h. | |
190 | ||
0f118bc7 NC |
191 | 2016-07-21 Nick Clifton <nickc@redhat.com> |
192 | ||
0c66ea4c | 193 | * simulator.c (fsqrts): Use sqrtf rather than sqrt. |
0f118bc7 | 194 | |
c7be4414 JW |
195 | 2016-06-30 Jim Wilson <jim.wilson@linaro.org> |
196 | ||
197 | * cpustate.h: Include config.h. | |
198 | (union GRegisterValue): Add WORDS_BIGENDIAN check. For big endian code | |
199 | use anonymous structs to align members. | |
200 | * simulator.c (aarch64_step): Use sim_core_read_buffer and | |
201 | endian_le2h_4 to read instruction from pc. | |
202 | ||
fd7ed446 NC |
203 | 2016-05-06 Nick Clifton <nickc@redhat.com> |
204 | ||
205 | * simulator.c (do_FMLA_by_element): New function. | |
206 | (do_vec_op2): Call it. | |
207 | ||
2cdad34c NC |
208 | 2016-04-27 Nick Clifton <nickc@redhat.com> |
209 | ||
210 | * simulator.c: Add TRACE_DECODE statements to all emulation | |
211 | functions. | |
212 | ||
7517e550 NC |
213 | 2016-03-30 Nick Clifton <nickc@redhat.com> |
214 | ||
215 | * cpustate.c (aarch64_set_reg_s32): New function. | |
216 | (aarch64_set_reg_u32): New function. | |
217 | (aarch64_get_FP_half): Place half precision value into the correct | |
218 | slot of the union. | |
219 | (aarch64_set_FP_half): Likewise. | |
220 | * cpustate.h: Add prototypes for aarch64_set_reg_s32 and | |
221 | aarch64_set_reg_u32. | |
222 | * memory.c (FETCH_FUNC): Cast the read value to the access type | |
223 | before converting it to the return type. Rename to FETCH_FUNC64. | |
224 | (FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit | |
225 | accesses. Use for 32-bit memory access functions. | |
226 | * simulator.c (ldrsb_wb): Use sign extension not zero extension. | |
227 | (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise. | |
228 | (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise. | |
229 | (ldrsh_scale_ext, ldrsw_abs): Likewise. | |
230 | (ldrh32_abs): Store 32 bit value not 64-bits. | |
231 | (ldrh32_wb, ldrh32_scale_ext): Likewise. | |
232 | (do_vec_MOV_immediate): Fix computation of val. | |
233 | (do_vec_MVNI): Likewise. | |
234 | (DO_VEC_WIDENING_MUL): New macro. | |
235 | (do_vec_mull): Use new macro. | |
236 | (do_vec_mul): Use new macro. | |
237 | (do_vec_MLA): Read values before writing. | |
238 | (do_vec_xtl): Likewise. | |
239 | (do_vec_SSHL): Select correct shift value. | |
240 | (do_vec_USHL): Likewise. | |
241 | (do_scalar_UCVTF): New function. | |
242 | (do_scalar_vec): Call new function. | |
243 | (store_pair_u64): Treat reads of SP as reads of XZR. | |
244 | ||
ef0d8ffc NC |
245 | 2016-03-29 Nick Clifton <nickc@redhat.com> |
246 | ||
247 | * cpustate.c: Remove space after asterisk in function parameters. | |
248 | * decode.h (greg): Delete unused function. | |
249 | (vreg, shift, extension, scaling, writeback, condcode): Likewise. | |
250 | * simulator.c: Use INSTR macro in more places. | |
251 | (HALT_NYI): Use sim_io_eprintf in place of fprintf. | |
252 | Remove extraneous whitespace. | |
253 | ||
5ab6d79e NC |
254 | 2016-03-23 Nick Clifton <nickc@redhat.com> |
255 | ||
256 | * cpustate.c (aarch64_get_FP_half): New function. Read a vector | |
257 | register as a half precision floating point number. | |
258 | (aarch64_set_FP_half): New function. Similar, but for setting | |
259 | a half precision register. | |
260 | (aarch64_get_thread_id): New function. Returns the value of the | |
261 | CPU's TPIDR register. | |
262 | (aarch64_get_FPCR): New function. Returns the value of the CPU's | |
263 | floating point control register. | |
264 | (aarch64_set_FPCR): New function. Set the value of the CPU's FPCR | |
265 | register. | |
266 | * cpustate.h: Add prototypes for new functions. | |
267 | * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields. | |
268 | * memory.c: Use unaligned core access functions for all memory | |
269 | reads and writes. | |
270 | * simulator.c (HALT_NYI): Generate an error message if tracing | |
271 | will not tell the user why the simulator is halting. | |
272 | (HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro. | |
273 | (INSTR): New time-saver macro. | |
274 | (fldrb_abs): New function. Loads an 8-bit value using a scaled | |
275 | offset. | |
276 | (fldrh_abs): New function. Likewise for 16-bit values. | |
277 | (do_vec_SSHL): Allow for negative shift values. | |
278 | (do_vec_USHL): Likewise. | |
279 | (do_vec_SHL): Correct computation of shift amount. | |
280 | (do_vec_SSHR_USHR): Correct decision of signed vs unsigned | |
281 | shifts and computation of shift value. | |
282 | (clz): New function. Counts leading zero bits. | |
283 | (do_vec_CLZ): New function. Implements CLZ (vector). | |
284 | (do_vec_MOV_element): Call do_vec_CLZ. | |
285 | (dexSimpleFPCondCompare): Implement. | |
286 | (do_FCVT_half_to_single): New function. Implements one of the | |
287 | FCVT operations. | |
288 | (do_FCVT_half_to_double): New function. Likewise. | |
289 | (do_FCVT_single_to_half): New function. Likewise. | |
290 | (do_FCVT_double_to_half): New function. Likewise. | |
291 | (dexSimpleFPDataProc1Source): Call new FCVT functions. | |
292 | (do_scalar_SHL): Handle negative shifts. | |
293 | (do_scalar_shift): Handle SSHR. | |
294 | (do_scalar_USHL): New function. | |
295 | (do_double_add): Simplify to just performing a double precision | |
296 | add operation. Move remaining code into... | |
297 | (do_scalar_vec): ... New function. | |
298 | (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs | |
299 | functions. | |
300 | (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR | |
301 | registers. | |
302 | (system_set): New function. | |
303 | (do_MSR_immediate): New function. Stub for now. | |
304 | (do_MSR_reg): New function. Likewise. Partially implements MSR | |
305 | instruction. | |
306 | (do_SYS): New function. Stub for now, | |
307 | (dexSystem): Call new functions. | |
308 | ||
e101a78b NC |
309 | 2016-03-18 Nick Clifton <nickc@redhat.com> |
310 | ||
311 | * cpustate.c: Remove spurious spaces from TRACE strings. | |
312 | Print hex equivalents of floats and doubles. | |
313 | Check element number against array size when accessing vector | |
314 | registers. | |
4c0ca98e NC |
315 | (GET_VEC_ELEMENT): Fix off by one error checking for an invalid |
316 | element index. | |
317 | (SET_VEC_ELEMENT): Likewise. | |
87bba7a5 | 318 | (GET_VEC_ELEMENT): And fix thinko using macro arguments. |
4c0ca98e | 319 | |
e101a78b NC |
320 | * memory.c: Trace memory reads when --trace-memory is enabled. |
321 | Remove float and double load and store functions. | |
322 | * memory.h (aarch64_get_mem_float): Delete prototype. | |
323 | (aarch64_get_mem_double): Likewise. | |
324 | (aarch64_set_mem_float): Likewise. | |
325 | (aarch64_set_mem_double): Likewise. | |
326 | * simulator (IS_SET): Always return either 0 or 1. | |
327 | (IS_CLEAR): Likewise. | |
328 | (fldrs_pcrel): Load and store floats using 32-bit memory accesses | |
329 | and doubles using 64-bit memory accesses. | |
330 | (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise. | |
331 | (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise. | |
332 | (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise. | |
333 | (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise. | |
334 | (store_pair_double, load_pair_float, load_pair_double): Likewise. | |
335 | (do_vec_MUL_by_element): New function. | |
336 | (do_vec_op2): Call do_vec_MUL_by_element. | |
337 | (do_scalar_NEG): New function. | |
338 | (do_double_add): Call do_scalar_NEG. | |
339 | ||
57aa1742 NC |
340 | 2016-03-03 Nick Clifton <nickc@redhat.com> |
341 | ||
342 | * simulator.c (set_flags_for_sub32): Correct type of signbit. | |
343 | (CondCompare): Swap interpretation of bit 30. | |
344 | (DO_ADDP): Delete macro. | |
345 | (do_vec_ADDP): Copy source registers before starting to update | |
346 | destination register. | |
347 | (do_vec_FADDP): Likewise. | |
348 | (do_vec_load_store): Fix computation of sizeof_operation. | |
349 | (rbit64): Fix type of constant. | |
350 | (aarch64_step): When displaying insn value, display all 32 bits. | |
351 | ||
ce39bd38 MF |
352 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
353 | ||
354 | * config.in, configure: Regenerate. | |
355 | ||
e19418e0 MF |
356 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
357 | ||
358 | * configure: Regenerate. | |
359 | ||
16f7876d MF |
360 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
361 | ||
362 | * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call. | |
363 | * configure: Regenerate. | |
364 | ||
99d8e879 MF |
365 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
366 | ||
367 | * configure: Regenerate. | |
35656e95 MF |
368 | |
369 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> | |
370 | ||
371 | * configure: Regenerate. | |
99d8e879 | 372 | |
347fe5bb MF |
373 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
374 | ||
375 | * configure.ac (SIM_AC_OPTION_INLINE): Delete call. | |
376 | * configure: Regenerate. | |
377 | ||
22be3fbe MF |
378 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
379 | ||
380 | * configure: Regenerate. | |
381 | ||
0dc73ef7 MF |
382 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
383 | ||
384 | * configure: Regenerate. | |
385 | ||
936df756 MF |
386 | 2016-01-09 Mike Frysinger <vapier@gentoo.org> |
387 | ||
388 | * config.in, configure: Regenerate. | |
389 | ||
2e3d4f4d MF |
390 | 2016-01-06 Mike Frysinger <vapier@gentoo.org> |
391 | ||
392 | * interp.c (sim_create_inferior): Mark argv and env const. | |
393 | (sim_open): Mark argv const. | |
394 | ||
1a846c62 MF |
395 | 2016-01-05 Mike Frysinger <vapier@gentoo.org> |
396 | ||
397 | * interp.c: Delete dis-asm.h include. | |
398 | (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete. | |
399 | (sim_create_inferior): Delete disassemble init logic. | |
400 | (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete. | |
401 | (sim_open): Delete sim_add_option_table call. | |
402 | * memory.c (mem_error): Delete disas check. | |
403 | * simulator.c: Delete dis-asm.h include. | |
404 | (disas): Delete. | |
405 | (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM. | |
406 | (HALT_NYI): Likewise. | |
407 | (handle_halt): Delete disas call. | |
408 | (aarch64_step): Replace disas logic with TRACE_DISASM. | |
409 | * simulator.h: Delete dis-asm.h include. | |
410 | (aarch64_print_insn): Delete. | |
411 | ||
bc273e17 MF |
412 | 2016-01-04 Mike Frysinger <vapier@gentoo.org> |
413 | ||
414 | * simulator.c (MAX, MIN): Delete. | |
415 | (do_vec_maxv): Change MAX to max and MIN to min. | |
416 | (do_vec_fminmaxV): Likewise. | |
417 | ||
ac8eefeb TG |
418 | 2016-01-04 Tristan Gingold <gingold@adacore.com> |
419 | ||
420 | * simulator.c: Remove syscall.h include. | |
421 | ||
9bbf6f91 MF |
422 | 2016-01-04 Mike Frysinger <vapier@gentoo.org> |
423 | ||
424 | * configure: Regenerate. | |
425 | ||
0cb8d851 MF |
426 | 2016-01-03 Mike Frysinger <vapier@gentoo.org> |
427 | ||
428 | * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete. | |
429 | * configure: Regenerate. | |
430 | ||
1ac72f06 MF |
431 | 2016-01-02 Mike Frysinger <vapier@gentoo.org> |
432 | ||
433 | * configure: Regenerate. | |
434 | ||
5d015275 MF |
435 | 2015-12-27 Mike Frysinger <vapier@gentoo.org> |
436 | ||
437 | * interp.c (sim_dis_read): Change private_data to application_data. | |
438 | (sim_create_inferior): Likewise. | |
439 | ||
5e744ef8 MF |
440 | 2015-12-27 Mike Frysinger <vapier@gentoo.org> |
441 | ||
442 | * Makefile.in (SIM_OBJS): Delete sim-hload.o. | |
443 | ||
1b393626 MF |
444 | 2015-12-26 Mike Frysinger <vapier@gentoo.org> |
445 | ||
446 | * config.in, configure: Regenerate. | |
447 | ||
0e967299 MF |
448 | 2015-12-26 Mike Frysinger <vapier@gentoo.org> |
449 | ||
450 | * interp.c (sim_create_inferior): Update comment and argv check. | |
451 | ||
f66affe9 MF |
452 | 2015-12-14 Nick Clifton <nickc@redhat.com> |
453 | ||
454 | * simulator.c (system_get): New function. Provides read | |
455 | access to the dczid system register. | |
456 | (do_mrs): New function - implements the MRS instruction. | |
457 | (dexSystem): Call do_mrs for the MRS instruction. Halt on | |
458 | unimplemented system instructions. | |
459 | ||
460 | 2015-11-24 Nick Clifton <nickc@redhat.com> | |
461 | ||
462 | * configure.ac: New configure template. | |
463 | * aclocal.m4: Generate. | |
464 | * config.in: Generate. | |
465 | * configure: Generate. | |
466 | * cpustate.c: New file - functions for accessing AArch64 registers. | |
467 | * cpustate.h: New header. | |
468 | * decode.h: New header. | |
469 | * interp.c: New file - interface between GDB and simulator. | |
470 | * Makefile.in: New makefile template. | |
471 | * memory.c: New file - functions for simulating aarch64 memory | |
472 | accesses. | |
473 | * memory.h: New header. | |
474 | * sim-main.h: New header. | |
475 | * simulator.c: New file - aarch64 simulator functions. | |
476 | * simulator.h: New header. |