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b34f6357 | 1 | /* frv simulator support code |
88b9d363 | 2 | Copyright (C) 1999-2022 Free Software Foundation, Inc. |
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3 | Contributed by Red Hat. |
4 | ||
5 | This file is part of the GNU simulators. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
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9 | the Free Software Foundation; either version 3 of the License, or |
10 | (at your option) any later version. | |
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11 | |
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
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17 | You should have received a copy of the GNU General Public License |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
b34f6357 | 19 | |
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20 | /* This must come before any other includes. */ |
21 | #include "defs.h" | |
22 | ||
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23 | #define WANT_CPU |
24 | #define WANT_CPU_FRVBF | |
25 | ||
26 | #include "sim-main.h" | |
27 | #include "bfd.h" | |
a9d20039 | 28 | #include "cgen-mem.h" |
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29 | |
30 | /* Initialize the frv simulator. */ | |
31 | void | |
32 | frv_initialize (SIM_CPU *current_cpu, SIM_DESC sd) | |
33 | { | |
34 | FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu); | |
35 | PROFILE_DATA *p = CPU_PROFILE_DATA (current_cpu); | |
36 | FRV_CACHE *insn_cache = CPU_INSN_CACHE (current_cpu); | |
37 | FRV_CACHE *data_cache = CPU_DATA_CACHE (current_cpu); | |
38 | int insn_cache_enabled = CACHE_INITIALIZED (insn_cache); | |
39 | int data_cache_enabled = CACHE_INITIALIZED (data_cache); | |
40 | USI hsr0; | |
41 | ||
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42 | /* Initialize the register control information first since some of the |
43 | register values are used in further configuration. */ | |
44 | frv_register_control_init (current_cpu); | |
45 | ||
b34f6357 DB |
46 | /* We need to ensure that the caches are initialized even if they are not |
47 | initially enabled (via commandline) because they can be enabled by | |
48 | software. */ | |
49 | if (! insn_cache_enabled) | |
50 | frv_cache_init (current_cpu, CPU_INSN_CACHE (current_cpu)); | |
51 | if (! data_cache_enabled) | |
52 | frv_cache_init (current_cpu, CPU_DATA_CACHE (current_cpu)); | |
53 | ||
54 | /* Set the default cpu frequency if it has not been set on the command | |
55 | line. */ | |
56 | if (PROFILE_CPU_FREQ (p) == 0) | |
57 | PROFILE_CPU_FREQ (p) = 266000000; /* 266MHz */ | |
58 | ||
59 | /* Allocate one cache line of memory containing the address of the reset | |
60 | register Use the largest of the insn cache line size and the data cache | |
61 | line size. */ | |
62 | { | |
63 | int addr = RSTR_ADDRESS; | |
64 | void *aligned_buffer; | |
65 | int bytes; | |
66 | ||
67 | if (CPU_INSN_CACHE (current_cpu)->line_size | |
68 | > CPU_DATA_CACHE (current_cpu)->line_size) | |
69 | bytes = CPU_INSN_CACHE (current_cpu)->line_size; | |
70 | else | |
71 | bytes = CPU_DATA_CACHE (current_cpu)->line_size; | |
72 | ||
73 | /* 'bytes' is a power of 2. Calculate the starting address of the | |
74 | cache line. */ | |
75 | addr &= ~(bytes - 1); | |
76 | aligned_buffer = zalloc (bytes); /* clear */ | |
77 | sim_core_attach (sd, NULL, 0, access_read_write, 0, addr, bytes, | |
78 | 0, NULL, aligned_buffer); | |
79 | } | |
80 | ||
81 | PROFILE_INFO_CPU_CALLBACK(p) = frv_profile_info; | |
82 | ps->insn_fetch_address = -1; | |
83 | ps->branch_address = -1; | |
84 | ||
85 | cgen_init_accurate_fpu (current_cpu, CGEN_CPU_FPU (current_cpu), | |
86 | frvbf_fpu_error); | |
87 | ||
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88 | /* Now perform power-on reset. */ |
89 | frv_power_on_reset (current_cpu); | |
90 | ||
91 | /* Make sure that HSR0.ICE and HSR0.DCE are set properly. */ | |
92 | hsr0 = GET_HSR0 (); | |
93 | if (insn_cache_enabled) | |
94 | SET_HSR0_ICE (hsr0); | |
95 | else | |
96 | CLEAR_HSR0_ICE (hsr0); | |
97 | if (data_cache_enabled) | |
98 | SET_HSR0_DCE (hsr0); | |
99 | else | |
100 | CLEAR_HSR0_DCE (hsr0); | |
101 | SET_HSR0 (hsr0); | |
102 | } | |
103 | ||
104 | /* Initialize the frv simulator. */ | |
105 | void | |
106 | frv_term (SIM_DESC sd) | |
107 | { | |
108 | /* If the timer is enabled, and model profiling was not originally enabled, | |
109 | then turn it off again. This is the only place we can currently gain | |
110 | control to do this. */ | |
111 | if (frv_interrupt_state.timer.enabled && ! frv_save_profile_model_p) | |
d47f5b30 | 112 | sim_profile_set_option (sd, "-model", PROFILE_MODEL_IDX, "0"); |
b34f6357 DB |
113 | } |
114 | ||
115 | /* Perform a power on reset. */ | |
116 | void | |
117 | frv_power_on_reset (SIM_CPU *cpu) | |
118 | { | |
119 | /* GR, FR and CPR registers are undefined at initialization time. */ | |
120 | frv_initialize_spr (cpu); | |
121 | /* Initialize the RSTR register (in memory). */ | |
122 | if (frv_cache_enabled (CPU_DATA_CACHE (cpu))) | |
123 | frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_INITIAL_VALUE); | |
124 | else | |
125 | SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_INITIAL_VALUE); | |
126 | } | |
127 | ||
128 | /* Perform a hardware reset. */ | |
129 | void | |
130 | frv_hardware_reset (SIM_CPU *cpu) | |
131 | { | |
132 | /* GR, FR and CPR registers are undefined at hardware reset. */ | |
133 | frv_initialize_spr (cpu); | |
134 | /* Reset the RSTR register (in memory). */ | |
135 | if (frv_cache_enabled (CPU_DATA_CACHE (cpu))) | |
136 | frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_HARDWARE_RESET); | |
137 | else | |
138 | SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_HARDWARE_RESET); | |
139 | /* Reset the insn and data caches. */ | |
140 | frv_cache_invalidate_all (CPU_INSN_CACHE (cpu), 0/* no flush */); | |
141 | frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 0/* no flush */); | |
142 | } | |
143 | ||
144 | /* Perform a software reset. */ | |
145 | void | |
146 | frv_software_reset (SIM_CPU *cpu) | |
147 | { | |
148 | /* GR, FR and CPR registers are undefined at software reset. */ | |
149 | frv_reset_spr (cpu); | |
150 | /* Reset the RSTR register (in memory). */ | |
151 | if (frv_cache_enabled (CPU_DATA_CACHE (cpu))) | |
152 | frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_SOFTWARE_RESET); | |
153 | else | |
154 | SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_SOFTWARE_RESET); | |
155 | } |