[deliverable/binutils-gdb.git] / sim / riscv / configure.ac

dnl Process this file with autoconf to produce a configure script.
AC_INIT(Makefile.in)
AC_CONFIG_MACRO_DIRS([../m4 ../.. ../../config])

SIM_AC_COMMON

SIM_AC_OPTION_ENDIAN(LITTLE)
SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
SIM_AC_OPTION_WARNINGS

# Select the default model for the target.
riscv_model=
case "${target}" in
riscv32*) riscv_model="RV32G" ;;
riscv*) riscv_model="RV64G" ;;
esac
SIM_AC_OPTION_DEFAULT_MODEL(${riscv_model})

# Select the bitsize of the target.
riscv_addr_bitsize=
case "${target}" in
riscv32*) riscv_addr_bitsize=32 ;;
riscv*) riscv_addr_bitsize=64 ;;
esac
SIM_AC_OPTION_BITSIZE($riscv_addr_bitsize)

SIM_AC_OUTPUT
Commit	Line	Data
b9249c46 MF	1	dnl Process this file with autoconf to produce a configure script.
b9249c46 MF	2	AC_INIT(Makefile.in)
760b3e8b	3	AC_CONFIG_MACRO_DIRS([../m4 ../.. ../../config])
b9249c46 MF	4
	5	SIM_AC_COMMON
	6
	7	SIM_AC_OPTION_ENDIAN(LITTLE)
	8	SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
b9249c46 MF	9	SIM_AC_OPTION_WARNINGS
	10
	11	# Select the default model for the target.
	12	riscv_model=
	13	case "${target}" in
	14	riscv32*) riscv_model="RV32G" ;;
	15	riscv*) riscv_model="RV64G" ;;
	16	esac
	17	SIM_AC_OPTION_DEFAULT_MODEL(${riscv_model})
	18
	19	# Select the bitsize of the target.
	20	riscv_addr_bitsize=
	21	case "${target}" in
	22	riscv32*) riscv_addr_bitsize=32 ;;
	23	riscv*) riscv_addr_bitsize=64 ;;
	24	esac
	25	SIM_AC_OPTION_BITSIZE($riscv_addr_bitsize)
	26
	27	SIM_AC_OUTPUT