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9a76f1ff MB |
1 | /* |
2 | * wm8962.c -- WM8962 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2010 Wolfson Microelectronics plc | |
5 | * | |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/moduleparam.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/pm.h> | |
19 | #include <linux/gcd.h> | |
3367b8d4 | 20 | #include <linux/gpio.h> |
9a76f1ff MB |
21 | #include <linux/i2c.h> |
22 | #include <linux/input.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/regulator/consumer.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/workqueue.h> | |
27 | #include <sound/core.h> | |
7711308a | 28 | #include <sound/jack.h> |
9a76f1ff MB |
29 | #include <sound/pcm.h> |
30 | #include <sound/pcm_params.h> | |
31 | #include <sound/soc.h> | |
9a76f1ff MB |
32 | #include <sound/initval.h> |
33 | #include <sound/tlv.h> | |
34 | #include <sound/wm8962.h> | |
2bbb5d66 | 35 | #include <trace/events/asoc.h> |
9a76f1ff MB |
36 | |
37 | #include "wm8962.h" | |
38 | ||
9a76f1ff MB |
39 | #define WM8962_NUM_SUPPLIES 8 |
40 | static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = { | |
41 | "DCVDD", | |
42 | "DBVDD", | |
43 | "AVDD", | |
44 | "CPVDD", | |
45 | "MICVDD", | |
46 | "PLLVDD", | |
47 | "SPKVDD1", | |
48 | "SPKVDD2", | |
49 | }; | |
50 | ||
51 | /* codec private data */ | |
52 | struct wm8962_priv { | |
54d8d0ae MB |
53 | struct snd_soc_codec *codec; |
54 | ||
9a76f1ff MB |
55 | int sysclk; |
56 | int sysclk_rate; | |
57 | ||
58 | int bclk; /* Desired BCLK */ | |
59 | int lrclk; | |
60 | ||
3b8a6d80 | 61 | struct completion fll_lock; |
9a76f1ff MB |
62 | int fll_src; |
63 | int fll_fref; | |
64 | int fll_fout; | |
65 | ||
6f88a4e5 MB |
66 | u16 dsp2_ena; |
67 | ||
7711308a MB |
68 | struct delayed_work mic_work; |
69 | struct snd_soc_jack *jack; | |
70 | ||
9a76f1ff MB |
71 | struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES]; |
72 | struct notifier_block disable_nb[WM8962_NUM_SUPPLIES]; | |
73 | ||
74 | #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE) | |
75 | struct input_dev *beep; | |
76 | struct work_struct beep_work; | |
77 | int beep_rate; | |
78 | #endif | |
3367b8d4 MB |
79 | |
80 | #ifdef CONFIG_GPIOLIB | |
81 | struct gpio_chip gpio_chip; | |
82 | #endif | |
c7356da9 MB |
83 | |
84 | int irq; | |
9a76f1ff MB |
85 | }; |
86 | ||
87 | /* We can't use the same notifier block for more than one supply and | |
88 | * there's no way I can see to get from a callback to the caller | |
89 | * except container_of(). | |
90 | */ | |
91 | #define WM8962_REGULATOR_EVENT(n) \ | |
92 | static int wm8962_regulator_event_##n(struct notifier_block *nb, \ | |
93 | unsigned long event, void *data) \ | |
94 | { \ | |
95 | struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \ | |
96 | disable_nb[n]); \ | |
97 | if (event & REGULATOR_EVENT_DISABLE) { \ | |
54d8d0ae | 98 | wm8962->codec->cache_sync = 1; \ |
9a76f1ff MB |
99 | } \ |
100 | return 0; \ | |
101 | } | |
102 | ||
103 | WM8962_REGULATOR_EVENT(0) | |
104 | WM8962_REGULATOR_EVENT(1) | |
105 | WM8962_REGULATOR_EVENT(2) | |
106 | WM8962_REGULATOR_EVENT(3) | |
107 | WM8962_REGULATOR_EVENT(4) | |
108 | WM8962_REGULATOR_EVENT(5) | |
109 | WM8962_REGULATOR_EVENT(6) | |
110 | WM8962_REGULATOR_EVENT(7) | |
111 | ||
f57f6c04 MB |
112 | static const u16 wm8962_reg[WM8962_MAX_REGISTER + 1] = { |
113 | [0] = 0x009F, /* R0 - Left Input volume */ | |
114 | [1] = 0x049F, /* R1 - Right Input volume */ | |
115 | [2] = 0x0000, /* R2 - HPOUTL volume */ | |
116 | [3] = 0x0000, /* R3 - HPOUTR volume */ | |
117 | [4] = 0x0020, /* R4 - Clocking1 */ | |
118 | [5] = 0x0018, /* R5 - ADC & DAC Control 1 */ | |
119 | [6] = 0x2008, /* R6 - ADC & DAC Control 2 */ | |
120 | [7] = 0x000A, /* R7 - Audio Interface 0 */ | |
121 | [8] = 0x01E4, /* R8 - Clocking2 */ | |
122 | [9] = 0x0300, /* R9 - Audio Interface 1 */ | |
123 | [10] = 0x00C0, /* R10 - Left DAC volume */ | |
124 | [11] = 0x00C0, /* R11 - Right DAC volume */ | |
125 | ||
126 | [14] = 0x0040, /* R14 - Audio Interface 2 */ | |
127 | [15] = 0x6243, /* R15 - Software Reset */ | |
128 | ||
129 | [17] = 0x007B, /* R17 - ALC1 */ | |
130 | [18] = 0x0000, /* R18 - ALC2 */ | |
131 | [19] = 0x1C32, /* R19 - ALC3 */ | |
132 | [20] = 0x3200, /* R20 - Noise Gate */ | |
133 | [21] = 0x00C0, /* R21 - Left ADC volume */ | |
134 | [22] = 0x00C0, /* R22 - Right ADC volume */ | |
135 | [23] = 0x0160, /* R23 - Additional control(1) */ | |
136 | [24] = 0x0000, /* R24 - Additional control(2) */ | |
137 | [25] = 0x0000, /* R25 - Pwr Mgmt (1) */ | |
138 | [26] = 0x0000, /* R26 - Pwr Mgmt (2) */ | |
139 | [27] = 0x0010, /* R27 - Additional Control (3) */ | |
140 | [28] = 0x0000, /* R28 - Anti-pop */ | |
141 | ||
142 | [30] = 0x005E, /* R30 - Clocking 3 */ | |
143 | [31] = 0x0000, /* R31 - Input mixer control (1) */ | |
144 | [32] = 0x0145, /* R32 - Left input mixer volume */ | |
145 | [33] = 0x0145, /* R33 - Right input mixer volume */ | |
146 | [34] = 0x0009, /* R34 - Input mixer control (2) */ | |
147 | [35] = 0x0003, /* R35 - Input bias control */ | |
148 | [37] = 0x0008, /* R37 - Left input PGA control */ | |
149 | [38] = 0x0008, /* R38 - Right input PGA control */ | |
150 | ||
151 | [40] = 0x0000, /* R40 - SPKOUTL volume */ | |
152 | [41] = 0x0000, /* R41 - SPKOUTR volume */ | |
153 | ||
154 | [47] = 0x0000, /* R47 - Thermal Shutdown Status */ | |
155 | [48] = 0x8027, /* R48 - Additional Control (4) */ | |
156 | [49] = 0x0010, /* R49 - Class D Control 1 */ | |
157 | ||
158 | [51] = 0x0003, /* R51 - Class D Control 2 */ | |
159 | ||
160 | [56] = 0x0506, /* R56 - Clocking 4 */ | |
161 | [57] = 0x0000, /* R57 - DAC DSP Mixing (1) */ | |
162 | [58] = 0x0000, /* R58 - DAC DSP Mixing (2) */ | |
163 | ||
164 | [60] = 0x0300, /* R60 - DC Servo 0 */ | |
165 | [61] = 0x0300, /* R61 - DC Servo 1 */ | |
166 | ||
167 | [64] = 0x0810, /* R64 - DC Servo 4 */ | |
168 | ||
169 | [66] = 0x0000, /* R66 - DC Servo 6 */ | |
170 | ||
171 | [68] = 0x001B, /* R68 - Analogue PGA Bias */ | |
172 | [69] = 0x0000, /* R69 - Analogue HP 0 */ | |
173 | ||
174 | [71] = 0x01FB, /* R71 - Analogue HP 2 */ | |
175 | [72] = 0x0000, /* R72 - Charge Pump 1 */ | |
176 | ||
177 | [82] = 0x0004, /* R82 - Charge Pump B */ | |
178 | ||
179 | [87] = 0x0000, /* R87 - Write Sequencer Control 1 */ | |
180 | ||
181 | [90] = 0x0000, /* R90 - Write Sequencer Control 2 */ | |
182 | ||
183 | [93] = 0x0000, /* R93 - Write Sequencer Control 3 */ | |
184 | [94] = 0x0000, /* R94 - Control Interface */ | |
185 | ||
186 | [99] = 0x0000, /* R99 - Mixer Enables */ | |
187 | [100] = 0x0000, /* R100 - Headphone Mixer (1) */ | |
188 | [101] = 0x0000, /* R101 - Headphone Mixer (2) */ | |
189 | [102] = 0x013F, /* R102 - Headphone Mixer (3) */ | |
190 | [103] = 0x013F, /* R103 - Headphone Mixer (4) */ | |
191 | ||
192 | [105] = 0x0000, /* R105 - Speaker Mixer (1) */ | |
193 | [106] = 0x0000, /* R106 - Speaker Mixer (2) */ | |
194 | [107] = 0x013F, /* R107 - Speaker Mixer (3) */ | |
195 | [108] = 0x013F, /* R108 - Speaker Mixer (4) */ | |
196 | [109] = 0x0003, /* R109 - Speaker Mixer (5) */ | |
197 | [110] = 0x0002, /* R110 - Beep Generator (1) */ | |
198 | ||
199 | [115] = 0x0006, /* R115 - Oscillator Trim (3) */ | |
200 | [116] = 0x0026, /* R116 - Oscillator Trim (4) */ | |
201 | ||
202 | [119] = 0x0000, /* R119 - Oscillator Trim (7) */ | |
203 | ||
204 | [124] = 0x0011, /* R124 - Analogue Clocking1 */ | |
205 | [125] = 0x004B, /* R125 - Analogue Clocking2 */ | |
206 | [126] = 0x000D, /* R126 - Analogue Clocking3 */ | |
207 | [127] = 0x0000, /* R127 - PLL Software Reset */ | |
208 | ||
209 | [129] = 0x0000, /* R129 - PLL2 */ | |
210 | ||
211 | [131] = 0x0000, /* R131 - PLL 4 */ | |
212 | ||
213 | [136] = 0x0067, /* R136 - PLL 9 */ | |
214 | [137] = 0x001C, /* R137 - PLL 10 */ | |
215 | [138] = 0x0071, /* R138 - PLL 11 */ | |
216 | [139] = 0x00C7, /* R139 - PLL 12 */ | |
217 | [140] = 0x0067, /* R140 - PLL 13 */ | |
218 | [141] = 0x0048, /* R141 - PLL 14 */ | |
219 | [142] = 0x0022, /* R142 - PLL 15 */ | |
220 | [143] = 0x0097, /* R143 - PLL 16 */ | |
221 | ||
222 | [155] = 0x000C, /* R155 - FLL Control (1) */ | |
223 | [156] = 0x0039, /* R156 - FLL Control (2) */ | |
224 | [157] = 0x0180, /* R157 - FLL Control (3) */ | |
225 | ||
226 | [159] = 0x0032, /* R159 - FLL Control (5) */ | |
227 | [160] = 0x0018, /* R160 - FLL Control (6) */ | |
228 | [161] = 0x007D, /* R161 - FLL Control (7) */ | |
229 | [162] = 0x0008, /* R162 - FLL Control (8) */ | |
230 | ||
231 | [252] = 0x0005, /* R252 - General test 1 */ | |
232 | ||
233 | [256] = 0x0000, /* R256 - DF1 */ | |
234 | [257] = 0x0000, /* R257 - DF2 */ | |
235 | [258] = 0x0000, /* R258 - DF3 */ | |
236 | [259] = 0x0000, /* R259 - DF4 */ | |
237 | [260] = 0x0000, /* R260 - DF5 */ | |
238 | [261] = 0x0000, /* R261 - DF6 */ | |
239 | [262] = 0x0000, /* R262 - DF7 */ | |
240 | ||
241 | [264] = 0x0000, /* R264 - LHPF1 */ | |
242 | [265] = 0x0000, /* R265 - LHPF2 */ | |
243 | ||
244 | [268] = 0x0000, /* R268 - THREED1 */ | |
245 | [269] = 0x0000, /* R269 - THREED2 */ | |
246 | [270] = 0x0000, /* R270 - THREED3 */ | |
247 | [271] = 0x0000, /* R271 - THREED4 */ | |
248 | ||
249 | [276] = 0x000C, /* R276 - DRC 1 */ | |
250 | [277] = 0x0925, /* R277 - DRC 2 */ | |
251 | [278] = 0x0000, /* R278 - DRC 3 */ | |
252 | [279] = 0x0000, /* R279 - DRC 4 */ | |
253 | [280] = 0x0000, /* R280 - DRC 5 */ | |
254 | ||
255 | [285] = 0x0000, /* R285 - Tloopback */ | |
256 | ||
257 | [335] = 0x0004, /* R335 - EQ1 */ | |
258 | [336] = 0x6318, /* R336 - EQ2 */ | |
259 | [337] = 0x6300, /* R337 - EQ3 */ | |
260 | [338] = 0x0FCA, /* R338 - EQ4 */ | |
261 | [339] = 0x0400, /* R339 - EQ5 */ | |
262 | [340] = 0x00D8, /* R340 - EQ6 */ | |
263 | [341] = 0x1EB5, /* R341 - EQ7 */ | |
264 | [342] = 0xF145, /* R342 - EQ8 */ | |
265 | [343] = 0x0B75, /* R343 - EQ9 */ | |
266 | [344] = 0x01C5, /* R344 - EQ10 */ | |
267 | [345] = 0x1C58, /* R345 - EQ11 */ | |
268 | [346] = 0xF373, /* R346 - EQ12 */ | |
269 | [347] = 0x0A54, /* R347 - EQ13 */ | |
270 | [348] = 0x0558, /* R348 - EQ14 */ | |
271 | [349] = 0x168E, /* R349 - EQ15 */ | |
272 | [350] = 0xF829, /* R350 - EQ16 */ | |
273 | [351] = 0x07AD, /* R351 - EQ17 */ | |
274 | [352] = 0x1103, /* R352 - EQ18 */ | |
275 | [353] = 0x0564, /* R353 - EQ19 */ | |
276 | [354] = 0x0559, /* R354 - EQ20 */ | |
277 | [355] = 0x4000, /* R355 - EQ21 */ | |
278 | [356] = 0x6318, /* R356 - EQ22 */ | |
279 | [357] = 0x6300, /* R357 - EQ23 */ | |
280 | [358] = 0x0FCA, /* R358 - EQ24 */ | |
281 | [359] = 0x0400, /* R359 - EQ25 */ | |
282 | [360] = 0x00D8, /* R360 - EQ26 */ | |
283 | [361] = 0x1EB5, /* R361 - EQ27 */ | |
284 | [362] = 0xF145, /* R362 - EQ28 */ | |
285 | [363] = 0x0B75, /* R363 - EQ29 */ | |
286 | [364] = 0x01C5, /* R364 - EQ30 */ | |
287 | [365] = 0x1C58, /* R365 - EQ31 */ | |
288 | [366] = 0xF373, /* R366 - EQ32 */ | |
289 | [367] = 0x0A54, /* R367 - EQ33 */ | |
290 | [368] = 0x0558, /* R368 - EQ34 */ | |
291 | [369] = 0x168E, /* R369 - EQ35 */ | |
292 | [370] = 0xF829, /* R370 - EQ36 */ | |
293 | [371] = 0x07AD, /* R371 - EQ37 */ | |
294 | [372] = 0x1103, /* R372 - EQ38 */ | |
295 | [373] = 0x0564, /* R373 - EQ39 */ | |
296 | [374] = 0x0559, /* R374 - EQ40 */ | |
297 | [375] = 0x4000, /* R375 - EQ41 */ | |
298 | ||
299 | [513] = 0x0000, /* R513 - GPIO 2 */ | |
300 | [514] = 0x0000, /* R514 - GPIO 3 */ | |
301 | ||
302 | [516] = 0x8100, /* R516 - GPIO 5 */ | |
303 | [517] = 0x8100, /* R517 - GPIO 6 */ | |
304 | ||
305 | [560] = 0x0000, /* R560 - Interrupt Status 1 */ | |
306 | [561] = 0x0000, /* R561 - Interrupt Status 2 */ | |
307 | ||
308 | [568] = 0x0030, /* R568 - Interrupt Status 1 Mask */ | |
309 | [569] = 0xFFED, /* R569 - Interrupt Status 2 Mask */ | |
310 | ||
311 | [576] = 0x0000, /* R576 - Interrupt Control */ | |
312 | ||
313 | [584] = 0x002D, /* R584 - IRQ Debounce */ | |
314 | ||
315 | [586] = 0x0000, /* R586 - MICINT Source Pol */ | |
316 | ||
317 | [768] = 0x1C00, /* R768 - DSP2 Power Management */ | |
318 | ||
319 | [1037] = 0x0000, /* R1037 - DSP2_ExecControl */ | |
320 | ||
321 | [8192] = 0x0000, /* R8192 - DSP2 Instruction RAM 0 */ | |
322 | ||
323 | [9216] = 0x0030, /* R9216 - DSP2 Address RAM 2 */ | |
324 | [9217] = 0x0000, /* R9217 - DSP2 Address RAM 1 */ | |
325 | [9218] = 0x0000, /* R9218 - DSP2 Address RAM 0 */ | |
326 | ||
327 | [12288] = 0x0000, /* R12288 - DSP2 Data1 RAM 1 */ | |
328 | [12289] = 0x0000, /* R12289 - DSP2 Data1 RAM 0 */ | |
329 | ||
330 | [13312] = 0x0000, /* R13312 - DSP2 Data2 RAM 1 */ | |
331 | [13313] = 0x0000, /* R13313 - DSP2 Data2 RAM 0 */ | |
332 | ||
333 | [14336] = 0x0000, /* R14336 - DSP2 Data3 RAM 1 */ | |
334 | [14337] = 0x0000, /* R14337 - DSP2 Data3 RAM 0 */ | |
335 | ||
336 | [15360] = 0x000A, /* R15360 - DSP2 Coeff RAM 0 */ | |
337 | ||
338 | [16384] = 0x0000, /* R16384 - RETUNEADC_SHARED_COEFF_1 */ | |
339 | [16385] = 0x0000, /* R16385 - RETUNEADC_SHARED_COEFF_0 */ | |
340 | [16386] = 0x0000, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */ | |
341 | [16387] = 0x0000, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */ | |
342 | [16388] = 0x0000, /* R16388 - SOUNDSTAGE_ENABLES_1 */ | |
343 | [16389] = 0x0000, /* R16389 - SOUNDSTAGE_ENABLES_0 */ | |
344 | ||
345 | [16896] = 0x0002, /* R16896 - HDBASS_AI_1 */ | |
346 | [16897] = 0xBD12, /* R16897 - HDBASS_AI_0 */ | |
347 | [16898] = 0x007C, /* R16898 - HDBASS_AR_1 */ | |
348 | [16899] = 0x586C, /* R16899 - HDBASS_AR_0 */ | |
349 | [16900] = 0x0053, /* R16900 - HDBASS_B_1 */ | |
350 | [16901] = 0x8121, /* R16901 - HDBASS_B_0 */ | |
351 | [16902] = 0x003F, /* R16902 - HDBASS_K_1 */ | |
352 | [16903] = 0x8BD8, /* R16903 - HDBASS_K_0 */ | |
353 | [16904] = 0x0032, /* R16904 - HDBASS_N1_1 */ | |
354 | [16905] = 0xF52D, /* R16905 - HDBASS_N1_0 */ | |
355 | [16906] = 0x0065, /* R16906 - HDBASS_N2_1 */ | |
356 | [16907] = 0xAC8C, /* R16907 - HDBASS_N2_0 */ | |
357 | [16908] = 0x006B, /* R16908 - HDBASS_N3_1 */ | |
358 | [16909] = 0xE087, /* R16909 - HDBASS_N3_0 */ | |
359 | [16910] = 0x0072, /* R16910 - HDBASS_N4_1 */ | |
360 | [16911] = 0x1483, /* R16911 - HDBASS_N4_0 */ | |
361 | [16912] = 0x0072, /* R16912 - HDBASS_N5_1 */ | |
362 | [16913] = 0x1483, /* R16913 - HDBASS_N5_0 */ | |
363 | [16914] = 0x0043, /* R16914 - HDBASS_X1_1 */ | |
364 | [16915] = 0x3525, /* R16915 - HDBASS_X1_0 */ | |
365 | [16916] = 0x0006, /* R16916 - HDBASS_X2_1 */ | |
366 | [16917] = 0x6A4A, /* R16917 - HDBASS_X2_0 */ | |
367 | [16918] = 0x0043, /* R16918 - HDBASS_X3_1 */ | |
368 | [16919] = 0x6079, /* R16919 - HDBASS_X3_0 */ | |
369 | [16920] = 0x0008, /* R16920 - HDBASS_ATK_1 */ | |
370 | [16921] = 0x0000, /* R16921 - HDBASS_ATK_0 */ | |
371 | [16922] = 0x0001, /* R16922 - HDBASS_DCY_1 */ | |
372 | [16923] = 0x0000, /* R16923 - HDBASS_DCY_0 */ | |
373 | [16924] = 0x0059, /* R16924 - HDBASS_PG_1 */ | |
374 | [16925] = 0x999A, /* R16925 - HDBASS_PG_0 */ | |
375 | ||
376 | [17048] = 0x0083, /* R17408 - HPF_C_1 */ | |
377 | [17049] = 0x98AD, /* R17409 - HPF_C_0 */ | |
378 | ||
379 | [17920] = 0x007F, /* R17920 - ADCL_RETUNE_C1_1 */ | |
380 | [17921] = 0xFFFF, /* R17921 - ADCL_RETUNE_C1_0 */ | |
381 | [17922] = 0x0000, /* R17922 - ADCL_RETUNE_C2_1 */ | |
382 | [17923] = 0x0000, /* R17923 - ADCL_RETUNE_C2_0 */ | |
383 | [17924] = 0x0000, /* R17924 - ADCL_RETUNE_C3_1 */ | |
384 | [17925] = 0x0000, /* R17925 - ADCL_RETUNE_C3_0 */ | |
385 | [17926] = 0x0000, /* R17926 - ADCL_RETUNE_C4_1 */ | |
386 | [17927] = 0x0000, /* R17927 - ADCL_RETUNE_C4_0 */ | |
387 | [17928] = 0x0000, /* R17928 - ADCL_RETUNE_C5_1 */ | |
388 | [17929] = 0x0000, /* R17929 - ADCL_RETUNE_C5_0 */ | |
389 | [17930] = 0x0000, /* R17930 - ADCL_RETUNE_C6_1 */ | |
390 | [17931] = 0x0000, /* R17931 - ADCL_RETUNE_C6_0 */ | |
391 | [17932] = 0x0000, /* R17932 - ADCL_RETUNE_C7_1 */ | |
392 | [17933] = 0x0000, /* R17933 - ADCL_RETUNE_C7_0 */ | |
393 | [17934] = 0x0000, /* R17934 - ADCL_RETUNE_C8_1 */ | |
394 | [17935] = 0x0000, /* R17935 - ADCL_RETUNE_C8_0 */ | |
395 | [17936] = 0x0000, /* R17936 - ADCL_RETUNE_C9_1 */ | |
396 | [17937] = 0x0000, /* R17937 - ADCL_RETUNE_C9_0 */ | |
397 | [17938] = 0x0000, /* R17938 - ADCL_RETUNE_C10_1 */ | |
398 | [17939] = 0x0000, /* R17939 - ADCL_RETUNE_C10_0 */ | |
399 | [17940] = 0x0000, /* R17940 - ADCL_RETUNE_C11_1 */ | |
400 | [17941] = 0x0000, /* R17941 - ADCL_RETUNE_C11_0 */ | |
401 | [17942] = 0x0000, /* R17942 - ADCL_RETUNE_C12_1 */ | |
402 | [17943] = 0x0000, /* R17943 - ADCL_RETUNE_C12_0 */ | |
403 | [17944] = 0x0000, /* R17944 - ADCL_RETUNE_C13_1 */ | |
404 | [17945] = 0x0000, /* R17945 - ADCL_RETUNE_C13_0 */ | |
405 | [17946] = 0x0000, /* R17946 - ADCL_RETUNE_C14_1 */ | |
406 | [17947] = 0x0000, /* R17947 - ADCL_RETUNE_C14_0 */ | |
407 | [17948] = 0x0000, /* R17948 - ADCL_RETUNE_C15_1 */ | |
408 | [17949] = 0x0000, /* R17949 - ADCL_RETUNE_C15_0 */ | |
409 | [17950] = 0x0000, /* R17950 - ADCL_RETUNE_C16_1 */ | |
410 | [17951] = 0x0000, /* R17951 - ADCL_RETUNE_C16_0 */ | |
411 | [17952] = 0x0000, /* R17952 - ADCL_RETUNE_C17_1 */ | |
412 | [17953] = 0x0000, /* R17953 - ADCL_RETUNE_C17_0 */ | |
413 | [17954] = 0x0000, /* R17954 - ADCL_RETUNE_C18_1 */ | |
414 | [17955] = 0x0000, /* R17955 - ADCL_RETUNE_C18_0 */ | |
415 | [17956] = 0x0000, /* R17956 - ADCL_RETUNE_C19_1 */ | |
416 | [17957] = 0x0000, /* R17957 - ADCL_RETUNE_C19_0 */ | |
417 | [17958] = 0x0000, /* R17958 - ADCL_RETUNE_C20_1 */ | |
418 | [17959] = 0x0000, /* R17959 - ADCL_RETUNE_C20_0 */ | |
419 | [17960] = 0x0000, /* R17960 - ADCL_RETUNE_C21_1 */ | |
420 | [17961] = 0x0000, /* R17961 - ADCL_RETUNE_C21_0 */ | |
421 | [17962] = 0x0000, /* R17962 - ADCL_RETUNE_C22_1 */ | |
422 | [17963] = 0x0000, /* R17963 - ADCL_RETUNE_C22_0 */ | |
423 | [17964] = 0x0000, /* R17964 - ADCL_RETUNE_C23_1 */ | |
424 | [17965] = 0x0000, /* R17965 - ADCL_RETUNE_C23_0 */ | |
425 | [17966] = 0x0000, /* R17966 - ADCL_RETUNE_C24_1 */ | |
426 | [17967] = 0x0000, /* R17967 - ADCL_RETUNE_C24_0 */ | |
427 | [17968] = 0x0000, /* R17968 - ADCL_RETUNE_C25_1 */ | |
428 | [17969] = 0x0000, /* R17969 - ADCL_RETUNE_C25_0 */ | |
429 | [17970] = 0x0000, /* R17970 - ADCL_RETUNE_C26_1 */ | |
430 | [17971] = 0x0000, /* R17971 - ADCL_RETUNE_C26_0 */ | |
431 | [17972] = 0x0000, /* R17972 - ADCL_RETUNE_C27_1 */ | |
432 | [17973] = 0x0000, /* R17973 - ADCL_RETUNE_C27_0 */ | |
433 | [17974] = 0x0000, /* R17974 - ADCL_RETUNE_C28_1 */ | |
434 | [17975] = 0x0000, /* R17975 - ADCL_RETUNE_C28_0 */ | |
435 | [17976] = 0x0000, /* R17976 - ADCL_RETUNE_C29_1 */ | |
436 | [17977] = 0x0000, /* R17977 - ADCL_RETUNE_C29_0 */ | |
437 | [17978] = 0x0000, /* R17978 - ADCL_RETUNE_C30_1 */ | |
438 | [17979] = 0x0000, /* R17979 - ADCL_RETUNE_C30_0 */ | |
439 | [17980] = 0x0000, /* R17980 - ADCL_RETUNE_C31_1 */ | |
440 | [17981] = 0x0000, /* R17981 - ADCL_RETUNE_C31_0 */ | |
441 | [17982] = 0x0000, /* R17982 - ADCL_RETUNE_C32_1 */ | |
442 | [17983] = 0x0000, /* R17983 - ADCL_RETUNE_C32_0 */ | |
443 | ||
444 | [18432] = 0x0020, /* R18432 - RETUNEADC_PG2_1 */ | |
445 | [18433] = 0x0000, /* R18433 - RETUNEADC_PG2_0 */ | |
446 | [18434] = 0x0040, /* R18434 - RETUNEADC_PG_1 */ | |
447 | [18435] = 0x0000, /* R18435 - RETUNEADC_PG_0 */ | |
448 | ||
449 | [18944] = 0x007F, /* R18944 - ADCR_RETUNE_C1_1 */ | |
450 | [18945] = 0xFFFF, /* R18945 - ADCR_RETUNE_C1_0 */ | |
451 | [18946] = 0x0000, /* R18946 - ADCR_RETUNE_C2_1 */ | |
452 | [18947] = 0x0000, /* R18947 - ADCR_RETUNE_C2_0 */ | |
453 | [18948] = 0x0000, /* R18948 - ADCR_RETUNE_C3_1 */ | |
454 | [18949] = 0x0000, /* R18949 - ADCR_RETUNE_C3_0 */ | |
455 | [18950] = 0x0000, /* R18950 - ADCR_RETUNE_C4_1 */ | |
456 | [18951] = 0x0000, /* R18951 - ADCR_RETUNE_C4_0 */ | |
457 | [18952] = 0x0000, /* R18952 - ADCR_RETUNE_C5_1 */ | |
458 | [18953] = 0x0000, /* R18953 - ADCR_RETUNE_C5_0 */ | |
459 | [18954] = 0x0000, /* R18954 - ADCR_RETUNE_C6_1 */ | |
460 | [18955] = 0x0000, /* R18955 - ADCR_RETUNE_C6_0 */ | |
461 | [18956] = 0x0000, /* R18956 - ADCR_RETUNE_C7_1 */ | |
462 | [18957] = 0x0000, /* R18957 - ADCR_RETUNE_C7_0 */ | |
463 | [18958] = 0x0000, /* R18958 - ADCR_RETUNE_C8_1 */ | |
464 | [18959] = 0x0000, /* R18959 - ADCR_RETUNE_C8_0 */ | |
465 | [18960] = 0x0000, /* R18960 - ADCR_RETUNE_C9_1 */ | |
466 | [18961] = 0x0000, /* R18961 - ADCR_RETUNE_C9_0 */ | |
467 | [18962] = 0x0000, /* R18962 - ADCR_RETUNE_C10_1 */ | |
468 | [18963] = 0x0000, /* R18963 - ADCR_RETUNE_C10_0 */ | |
469 | [18964] = 0x0000, /* R18964 - ADCR_RETUNE_C11_1 */ | |
470 | [18965] = 0x0000, /* R18965 - ADCR_RETUNE_C11_0 */ | |
471 | [18966] = 0x0000, /* R18966 - ADCR_RETUNE_C12_1 */ | |
472 | [18967] = 0x0000, /* R18967 - ADCR_RETUNE_C12_0 */ | |
473 | [18968] = 0x0000, /* R18968 - ADCR_RETUNE_C13_1 */ | |
474 | [18969] = 0x0000, /* R18969 - ADCR_RETUNE_C13_0 */ | |
475 | [18970] = 0x0000, /* R18970 - ADCR_RETUNE_C14_1 */ | |
476 | [18971] = 0x0000, /* R18971 - ADCR_RETUNE_C14_0 */ | |
477 | [18972] = 0x0000, /* R18972 - ADCR_RETUNE_C15_1 */ | |
478 | [18973] = 0x0000, /* R18973 - ADCR_RETUNE_C15_0 */ | |
479 | [18974] = 0x0000, /* R18974 - ADCR_RETUNE_C16_1 */ | |
480 | [18975] = 0x0000, /* R18975 - ADCR_RETUNE_C16_0 */ | |
481 | [18976] = 0x0000, /* R18976 - ADCR_RETUNE_C17_1 */ | |
482 | [18977] = 0x0000, /* R18977 - ADCR_RETUNE_C17_0 */ | |
483 | [18978] = 0x0000, /* R18978 - ADCR_RETUNE_C18_1 */ | |
484 | [18979] = 0x0000, /* R18979 - ADCR_RETUNE_C18_0 */ | |
485 | [18980] = 0x0000, /* R18980 - ADCR_RETUNE_C19_1 */ | |
486 | [18981] = 0x0000, /* R18981 - ADCR_RETUNE_C19_0 */ | |
487 | [18982] = 0x0000, /* R18982 - ADCR_RETUNE_C20_1 */ | |
488 | [18983] = 0x0000, /* R18983 - ADCR_RETUNE_C20_0 */ | |
489 | [18984] = 0x0000, /* R18984 - ADCR_RETUNE_C21_1 */ | |
490 | [18985] = 0x0000, /* R18985 - ADCR_RETUNE_C21_0 */ | |
491 | [18986] = 0x0000, /* R18986 - ADCR_RETUNE_C22_1 */ | |
492 | [18987] = 0x0000, /* R18987 - ADCR_RETUNE_C22_0 */ | |
493 | [18988] = 0x0000, /* R18988 - ADCR_RETUNE_C23_1 */ | |
494 | [18989] = 0x0000, /* R18989 - ADCR_RETUNE_C23_0 */ | |
495 | [18990] = 0x0000, /* R18990 - ADCR_RETUNE_C24_1 */ | |
496 | [18991] = 0x0000, /* R18991 - ADCR_RETUNE_C24_0 */ | |
497 | [18992] = 0x0000, /* R18992 - ADCR_RETUNE_C25_1 */ | |
498 | [18993] = 0x0000, /* R18993 - ADCR_RETUNE_C25_0 */ | |
499 | [18994] = 0x0000, /* R18994 - ADCR_RETUNE_C26_1 */ | |
500 | [18995] = 0x0000, /* R18995 - ADCR_RETUNE_C26_0 */ | |
501 | [18996] = 0x0000, /* R18996 - ADCR_RETUNE_C27_1 */ | |
502 | [18997] = 0x0000, /* R18997 - ADCR_RETUNE_C27_0 */ | |
503 | [18998] = 0x0000, /* R18998 - ADCR_RETUNE_C28_1 */ | |
504 | [18999] = 0x0000, /* R18999 - ADCR_RETUNE_C28_0 */ | |
505 | [19000] = 0x0000, /* R19000 - ADCR_RETUNE_C29_1 */ | |
506 | [19001] = 0x0000, /* R19001 - ADCR_RETUNE_C29_0 */ | |
507 | [19002] = 0x0000, /* R19002 - ADCR_RETUNE_C30_1 */ | |
508 | [19003] = 0x0000, /* R19003 - ADCR_RETUNE_C30_0 */ | |
509 | [19004] = 0x0000, /* R19004 - ADCR_RETUNE_C31_1 */ | |
510 | [19005] = 0x0000, /* R19005 - ADCR_RETUNE_C31_0 */ | |
511 | [19006] = 0x0000, /* R19006 - ADCR_RETUNE_C32_1 */ | |
512 | [19007] = 0x0000, /* R19007 - ADCR_RETUNE_C32_0 */ | |
513 | ||
514 | [19456] = 0x007F, /* R19456 - DACL_RETUNE_C1_1 */ | |
515 | [19457] = 0xFFFF, /* R19457 - DACL_RETUNE_C1_0 */ | |
516 | [19458] = 0x0000, /* R19458 - DACL_RETUNE_C2_1 */ | |
517 | [19459] = 0x0000, /* R19459 - DACL_RETUNE_C2_0 */ | |
518 | [19460] = 0x0000, /* R19460 - DACL_RETUNE_C3_1 */ | |
519 | [19461] = 0x0000, /* R19461 - DACL_RETUNE_C3_0 */ | |
520 | [19462] = 0x0000, /* R19462 - DACL_RETUNE_C4_1 */ | |
521 | [19463] = 0x0000, /* R19463 - DACL_RETUNE_C4_0 */ | |
522 | [19464] = 0x0000, /* R19464 - DACL_RETUNE_C5_1 */ | |
523 | [19465] = 0x0000, /* R19465 - DACL_RETUNE_C5_0 */ | |
524 | [19466] = 0x0000, /* R19466 - DACL_RETUNE_C6_1 */ | |
525 | [19467] = 0x0000, /* R19467 - DACL_RETUNE_C6_0 */ | |
526 | [19468] = 0x0000, /* R19468 - DACL_RETUNE_C7_1 */ | |
527 | [19469] = 0x0000, /* R19469 - DACL_RETUNE_C7_0 */ | |
528 | [19470] = 0x0000, /* R19470 - DACL_RETUNE_C8_1 */ | |
529 | [19471] = 0x0000, /* R19471 - DACL_RETUNE_C8_0 */ | |
530 | [19472] = 0x0000, /* R19472 - DACL_RETUNE_C9_1 */ | |
531 | [19473] = 0x0000, /* R19473 - DACL_RETUNE_C9_0 */ | |
532 | [19474] = 0x0000, /* R19474 - DACL_RETUNE_C10_1 */ | |
533 | [19475] = 0x0000, /* R19475 - DACL_RETUNE_C10_0 */ | |
534 | [19476] = 0x0000, /* R19476 - DACL_RETUNE_C11_1 */ | |
535 | [19477] = 0x0000, /* R19477 - DACL_RETUNE_C11_0 */ | |
536 | [19478] = 0x0000, /* R19478 - DACL_RETUNE_C12_1 */ | |
537 | [19479] = 0x0000, /* R19479 - DACL_RETUNE_C12_0 */ | |
538 | [19480] = 0x0000, /* R19480 - DACL_RETUNE_C13_1 */ | |
539 | [19481] = 0x0000, /* R19481 - DACL_RETUNE_C13_0 */ | |
540 | [19482] = 0x0000, /* R19482 - DACL_RETUNE_C14_1 */ | |
541 | [19483] = 0x0000, /* R19483 - DACL_RETUNE_C14_0 */ | |
542 | [19484] = 0x0000, /* R19484 - DACL_RETUNE_C15_1 */ | |
543 | [19485] = 0x0000, /* R19485 - DACL_RETUNE_C15_0 */ | |
544 | [19486] = 0x0000, /* R19486 - DACL_RETUNE_C16_1 */ | |
545 | [19487] = 0x0000, /* R19487 - DACL_RETUNE_C16_0 */ | |
546 | [19488] = 0x0000, /* R19488 - DACL_RETUNE_C17_1 */ | |
547 | [19489] = 0x0000, /* R19489 - DACL_RETUNE_C17_0 */ | |
548 | [19490] = 0x0000, /* R19490 - DACL_RETUNE_C18_1 */ | |
549 | [19491] = 0x0000, /* R19491 - DACL_RETUNE_C18_0 */ | |
550 | [19492] = 0x0000, /* R19492 - DACL_RETUNE_C19_1 */ | |
551 | [19493] = 0x0000, /* R19493 - DACL_RETUNE_C19_0 */ | |
552 | [19494] = 0x0000, /* R19494 - DACL_RETUNE_C20_1 */ | |
553 | [19495] = 0x0000, /* R19495 - DACL_RETUNE_C20_0 */ | |
554 | [19496] = 0x0000, /* R19496 - DACL_RETUNE_C21_1 */ | |
555 | [19497] = 0x0000, /* R19497 - DACL_RETUNE_C21_0 */ | |
556 | [19498] = 0x0000, /* R19498 - DACL_RETUNE_C22_1 */ | |
557 | [19499] = 0x0000, /* R19499 - DACL_RETUNE_C22_0 */ | |
558 | [19500] = 0x0000, /* R19500 - DACL_RETUNE_C23_1 */ | |
559 | [19501] = 0x0000, /* R19501 - DACL_RETUNE_C23_0 */ | |
560 | [19502] = 0x0000, /* R19502 - DACL_RETUNE_C24_1 */ | |
561 | [19503] = 0x0000, /* R19503 - DACL_RETUNE_C24_0 */ | |
562 | [19504] = 0x0000, /* R19504 - DACL_RETUNE_C25_1 */ | |
563 | [19505] = 0x0000, /* R19505 - DACL_RETUNE_C25_0 */ | |
564 | [19506] = 0x0000, /* R19506 - DACL_RETUNE_C26_1 */ | |
565 | [19507] = 0x0000, /* R19507 - DACL_RETUNE_C26_0 */ | |
566 | [19508] = 0x0000, /* R19508 - DACL_RETUNE_C27_1 */ | |
567 | [19509] = 0x0000, /* R19509 - DACL_RETUNE_C27_0 */ | |
568 | [19510] = 0x0000, /* R19510 - DACL_RETUNE_C28_1 */ | |
569 | [19511] = 0x0000, /* R19511 - DACL_RETUNE_C28_0 */ | |
570 | [19512] = 0x0000, /* R19512 - DACL_RETUNE_C29_1 */ | |
571 | [19513] = 0x0000, /* R19513 - DACL_RETUNE_C29_0 */ | |
572 | [19514] = 0x0000, /* R19514 - DACL_RETUNE_C30_1 */ | |
573 | [19515] = 0x0000, /* R19515 - DACL_RETUNE_C30_0 */ | |
574 | [19516] = 0x0000, /* R19516 - DACL_RETUNE_C31_1 */ | |
575 | [19517] = 0x0000, /* R19517 - DACL_RETUNE_C31_0 */ | |
576 | [19518] = 0x0000, /* R19518 - DACL_RETUNE_C32_1 */ | |
577 | [19519] = 0x0000, /* R19519 - DACL_RETUNE_C32_0 */ | |
578 | ||
579 | [19968] = 0x0020, /* R19968 - RETUNEDAC_PG2_1 */ | |
580 | [19969] = 0x0000, /* R19969 - RETUNEDAC_PG2_0 */ | |
581 | [19970] = 0x0040, /* R19970 - RETUNEDAC_PG_1 */ | |
582 | [19971] = 0x0000, /* R19971 - RETUNEDAC_PG_0 */ | |
583 | ||
584 | [20480] = 0x007F, /* R20480 - DACR_RETUNE_C1_1 */ | |
585 | [20481] = 0xFFFF, /* R20481 - DACR_RETUNE_C1_0 */ | |
586 | [20482] = 0x0000, /* R20482 - DACR_RETUNE_C2_1 */ | |
587 | [20483] = 0x0000, /* R20483 - DACR_RETUNE_C2_0 */ | |
588 | [20484] = 0x0000, /* R20484 - DACR_RETUNE_C3_1 */ | |
589 | [20485] = 0x0000, /* R20485 - DACR_RETUNE_C3_0 */ | |
590 | [20486] = 0x0000, /* R20486 - DACR_RETUNE_C4_1 */ | |
591 | [20487] = 0x0000, /* R20487 - DACR_RETUNE_C4_0 */ | |
592 | [20488] = 0x0000, /* R20488 - DACR_RETUNE_C5_1 */ | |
593 | [20489] = 0x0000, /* R20489 - DACR_RETUNE_C5_0 */ | |
594 | [20490] = 0x0000, /* R20490 - DACR_RETUNE_C6_1 */ | |
595 | [20491] = 0x0000, /* R20491 - DACR_RETUNE_C6_0 */ | |
596 | [20492] = 0x0000, /* R20492 - DACR_RETUNE_C7_1 */ | |
597 | [20493] = 0x0000, /* R20493 - DACR_RETUNE_C7_0 */ | |
598 | [20494] = 0x0000, /* R20494 - DACR_RETUNE_C8_1 */ | |
599 | [20495] = 0x0000, /* R20495 - DACR_RETUNE_C8_0 */ | |
600 | [20496] = 0x0000, /* R20496 - DACR_RETUNE_C9_1 */ | |
601 | [20497] = 0x0000, /* R20497 - DACR_RETUNE_C9_0 */ | |
602 | [20498] = 0x0000, /* R20498 - DACR_RETUNE_C10_1 */ | |
603 | [20499] = 0x0000, /* R20499 - DACR_RETUNE_C10_0 */ | |
604 | [20500] = 0x0000, /* R20500 - DACR_RETUNE_C11_1 */ | |
605 | [20501] = 0x0000, /* R20501 - DACR_RETUNE_C11_0 */ | |
606 | [20502] = 0x0000, /* R20502 - DACR_RETUNE_C12_1 */ | |
607 | [20503] = 0x0000, /* R20503 - DACR_RETUNE_C12_0 */ | |
608 | [20504] = 0x0000, /* R20504 - DACR_RETUNE_C13_1 */ | |
609 | [20505] = 0x0000, /* R20505 - DACR_RETUNE_C13_0 */ | |
610 | [20506] = 0x0000, /* R20506 - DACR_RETUNE_C14_1 */ | |
611 | [20507] = 0x0000, /* R20507 - DACR_RETUNE_C14_0 */ | |
612 | [20508] = 0x0000, /* R20508 - DACR_RETUNE_C15_1 */ | |
613 | [20509] = 0x0000, /* R20509 - DACR_RETUNE_C15_0 */ | |
614 | [20510] = 0x0000, /* R20510 - DACR_RETUNE_C16_1 */ | |
615 | [20511] = 0x0000, /* R20511 - DACR_RETUNE_C16_0 */ | |
616 | [20512] = 0x0000, /* R20512 - DACR_RETUNE_C17_1 */ | |
617 | [20513] = 0x0000, /* R20513 - DACR_RETUNE_C17_0 */ | |
618 | [20514] = 0x0000, /* R20514 - DACR_RETUNE_C18_1 */ | |
619 | [20515] = 0x0000, /* R20515 - DACR_RETUNE_C18_0 */ | |
620 | [20516] = 0x0000, /* R20516 - DACR_RETUNE_C19_1 */ | |
621 | [20517] = 0x0000, /* R20517 - DACR_RETUNE_C19_0 */ | |
622 | [20518] = 0x0000, /* R20518 - DACR_RETUNE_C20_1 */ | |
623 | [20519] = 0x0000, /* R20519 - DACR_RETUNE_C20_0 */ | |
624 | [20520] = 0x0000, /* R20520 - DACR_RETUNE_C21_1 */ | |
625 | [20521] = 0x0000, /* R20521 - DACR_RETUNE_C21_0 */ | |
626 | [20522] = 0x0000, /* R20522 - DACR_RETUNE_C22_1 */ | |
627 | [20523] = 0x0000, /* R20523 - DACR_RETUNE_C22_0 */ | |
628 | [20524] = 0x0000, /* R20524 - DACR_RETUNE_C23_1 */ | |
629 | [20525] = 0x0000, /* R20525 - DACR_RETUNE_C23_0 */ | |
630 | [20526] = 0x0000, /* R20526 - DACR_RETUNE_C24_1 */ | |
631 | [20527] = 0x0000, /* R20527 - DACR_RETUNE_C24_0 */ | |
632 | [20528] = 0x0000, /* R20528 - DACR_RETUNE_C25_1 */ | |
633 | [20529] = 0x0000, /* R20529 - DACR_RETUNE_C25_0 */ | |
634 | [20530] = 0x0000, /* R20530 - DACR_RETUNE_C26_1 */ | |
635 | [20531] = 0x0000, /* R20531 - DACR_RETUNE_C26_0 */ | |
636 | [20532] = 0x0000, /* R20532 - DACR_RETUNE_C27_1 */ | |
637 | [20533] = 0x0000, /* R20533 - DACR_RETUNE_C27_0 */ | |
638 | [20534] = 0x0000, /* R20534 - DACR_RETUNE_C28_1 */ | |
639 | [20535] = 0x0000, /* R20535 - DACR_RETUNE_C28_0 */ | |
640 | [20536] = 0x0000, /* R20536 - DACR_RETUNE_C29_1 */ | |
641 | [20537] = 0x0000, /* R20537 - DACR_RETUNE_C29_0 */ | |
642 | [20538] = 0x0000, /* R20538 - DACR_RETUNE_C30_1 */ | |
643 | [20539] = 0x0000, /* R20539 - DACR_RETUNE_C30_0 */ | |
644 | [20540] = 0x0000, /* R20540 - DACR_RETUNE_C31_1 */ | |
645 | [20541] = 0x0000, /* R20541 - DACR_RETUNE_C31_0 */ | |
646 | [20542] = 0x0000, /* R20542 - DACR_RETUNE_C32_1 */ | |
647 | [20543] = 0x0000, /* R20543 - DACR_RETUNE_C32_0 */ | |
648 | ||
649 | [20992] = 0x008C, /* R20992 - VSS_XHD2_1 */ | |
650 | [20993] = 0x0200, /* R20993 - VSS_XHD2_0 */ | |
651 | [20994] = 0x0035, /* R20994 - VSS_XHD3_1 */ | |
652 | [20995] = 0x0700, /* R20995 - VSS_XHD3_0 */ | |
653 | [20996] = 0x003A, /* R20996 - VSS_XHN1_1 */ | |
654 | [20997] = 0x4100, /* R20997 - VSS_XHN1_0 */ | |
655 | [20998] = 0x008B, /* R20998 - VSS_XHN2_1 */ | |
656 | [20999] = 0x7D00, /* R20999 - VSS_XHN2_0 */ | |
657 | [21000] = 0x003A, /* R21000 - VSS_XHN3_1 */ | |
658 | [21001] = 0x4100, /* R21001 - VSS_XHN3_0 */ | |
659 | [21002] = 0x008C, /* R21002 - VSS_XLA_1 */ | |
660 | [21003] = 0xFEE8, /* R21003 - VSS_XLA_0 */ | |
661 | [21004] = 0x0078, /* R21004 - VSS_XLB_1 */ | |
662 | [21005] = 0x0000, /* R21005 - VSS_XLB_0 */ | |
663 | [21006] = 0x003F, /* R21006 - VSS_XLG_1 */ | |
664 | [21007] = 0xB260, /* R21007 - VSS_XLG_0 */ | |
665 | [21008] = 0x002D, /* R21008 - VSS_PG2_1 */ | |
666 | [21009] = 0x1818, /* R21009 - VSS_PG2_0 */ | |
667 | [21010] = 0x0020, /* R21010 - VSS_PG_1 */ | |
668 | [21011] = 0x0000, /* R21011 - VSS_PG_0 */ | |
669 | [21012] = 0x00F1, /* R21012 - VSS_XTD1_1 */ | |
670 | [21013] = 0x8340, /* R21013 - VSS_XTD1_0 */ | |
671 | [21014] = 0x00FB, /* R21014 - VSS_XTD2_1 */ | |
672 | [21015] = 0x8300, /* R21015 - VSS_XTD2_0 */ | |
673 | [21016] = 0x00EE, /* R21016 - VSS_XTD3_1 */ | |
674 | [21017] = 0xAEC0, /* R21017 - VSS_XTD3_0 */ | |
675 | [21018] = 0x00FB, /* R21018 - VSS_XTD4_1 */ | |
676 | [21019] = 0xAC40, /* R21019 - VSS_XTD4_0 */ | |
677 | [21020] = 0x00F1, /* R21020 - VSS_XTD5_1 */ | |
678 | [21021] = 0x7F80, /* R21021 - VSS_XTD5_0 */ | |
679 | [21022] = 0x00F4, /* R21022 - VSS_XTD6_1 */ | |
680 | [21023] = 0x3B40, /* R21023 - VSS_XTD6_0 */ | |
681 | [21024] = 0x00F5, /* R21024 - VSS_XTD7_1 */ | |
682 | [21025] = 0xFB00, /* R21025 - VSS_XTD7_0 */ | |
683 | [21026] = 0x00EA, /* R21026 - VSS_XTD8_1 */ | |
684 | [21027] = 0x10C0, /* R21027 - VSS_XTD8_0 */ | |
685 | [21028] = 0x00FC, /* R21028 - VSS_XTD9_1 */ | |
686 | [21029] = 0xC580, /* R21029 - VSS_XTD9_0 */ | |
687 | [21030] = 0x00E2, /* R21030 - VSS_XTD10_1 */ | |
688 | [21031] = 0x75C0, /* R21031 - VSS_XTD10_0 */ | |
689 | [21032] = 0x0004, /* R21032 - VSS_XTD11_1 */ | |
690 | [21033] = 0xB480, /* R21033 - VSS_XTD11_0 */ | |
691 | [21034] = 0x00D4, /* R21034 - VSS_XTD12_1 */ | |
692 | [21035] = 0xF980, /* R21035 - VSS_XTD12_0 */ | |
693 | [21036] = 0x0004, /* R21036 - VSS_XTD13_1 */ | |
694 | [21037] = 0x9140, /* R21037 - VSS_XTD13_0 */ | |
695 | [21038] = 0x00D8, /* R21038 - VSS_XTD14_1 */ | |
696 | [21039] = 0xA480, /* R21039 - VSS_XTD14_0 */ | |
697 | [21040] = 0x0002, /* R21040 - VSS_XTD15_1 */ | |
698 | [21041] = 0x3DC0, /* R21041 - VSS_XTD15_0 */ | |
699 | [21042] = 0x00CF, /* R21042 - VSS_XTD16_1 */ | |
700 | [21043] = 0x7A80, /* R21043 - VSS_XTD16_0 */ | |
701 | [21044] = 0x00DC, /* R21044 - VSS_XTD17_1 */ | |
702 | [21045] = 0x0600, /* R21045 - VSS_XTD17_0 */ | |
703 | [21046] = 0x00F2, /* R21046 - VSS_XTD18_1 */ | |
704 | [21047] = 0xDAC0, /* R21047 - VSS_XTD18_0 */ | |
705 | [21048] = 0x00BA, /* R21048 - VSS_XTD19_1 */ | |
706 | [21049] = 0xF340, /* R21049 - VSS_XTD19_0 */ | |
707 | [21050] = 0x000A, /* R21050 - VSS_XTD20_1 */ | |
708 | [21051] = 0x7940, /* R21051 - VSS_XTD20_0 */ | |
709 | [21052] = 0x001C, /* R21052 - VSS_XTD21_1 */ | |
710 | [21053] = 0x0680, /* R21053 - VSS_XTD21_0 */ | |
711 | [21054] = 0x00FD, /* R21054 - VSS_XTD22_1 */ | |
712 | [21055] = 0x2D00, /* R21055 - VSS_XTD22_0 */ | |
713 | [21056] = 0x001C, /* R21056 - VSS_XTD23_1 */ | |
714 | [21057] = 0xE840, /* R21057 - VSS_XTD23_0 */ | |
715 | [21058] = 0x000D, /* R21058 - VSS_XTD24_1 */ | |
716 | [21059] = 0xDC40, /* R21059 - VSS_XTD24_0 */ | |
717 | [21060] = 0x00FC, /* R21060 - VSS_XTD25_1 */ | |
718 | [21061] = 0x9D00, /* R21061 - VSS_XTD25_0 */ | |
719 | [21062] = 0x0009, /* R21062 - VSS_XTD26_1 */ | |
720 | [21063] = 0x5580, /* R21063 - VSS_XTD26_0 */ | |
721 | [21064] = 0x00FE, /* R21064 - VSS_XTD27_1 */ | |
722 | [21065] = 0x7E80, /* R21065 - VSS_XTD27_0 */ | |
723 | [21066] = 0x000E, /* R21066 - VSS_XTD28_1 */ | |
724 | [21067] = 0xAB40, /* R21067 - VSS_XTD28_0 */ | |
725 | [21068] = 0x00F9, /* R21068 - VSS_XTD29_1 */ | |
726 | [21069] = 0x9880, /* R21069 - VSS_XTD29_0 */ | |
727 | [21070] = 0x0009, /* R21070 - VSS_XTD30_1 */ | |
728 | [21071] = 0x87C0, /* R21071 - VSS_XTD30_0 */ | |
729 | [21072] = 0x00FD, /* R21072 - VSS_XTD31_1 */ | |
730 | [21073] = 0x2C40, /* R21073 - VSS_XTD31_0 */ | |
731 | [21074] = 0x0009, /* R21074 - VSS_XTD32_1 */ | |
732 | [21075] = 0x4800, /* R21075 - VSS_XTD32_0 */ | |
733 | [21076] = 0x0003, /* R21076 - VSS_XTS1_1 */ | |
734 | [21077] = 0x5F40, /* R21077 - VSS_XTS1_0 */ | |
735 | [21078] = 0x0000, /* R21078 - VSS_XTS2_1 */ | |
736 | [21079] = 0x8700, /* R21079 - VSS_XTS2_0 */ | |
737 | [21080] = 0x00FA, /* R21080 - VSS_XTS3_1 */ | |
738 | [21081] = 0xE4C0, /* R21081 - VSS_XTS3_0 */ | |
739 | [21082] = 0x0000, /* R21082 - VSS_XTS4_1 */ | |
740 | [21083] = 0x0B40, /* R21083 - VSS_XTS4_0 */ | |
741 | [21084] = 0x0004, /* R21084 - VSS_XTS5_1 */ | |
742 | [21085] = 0xE180, /* R21085 - VSS_XTS5_0 */ | |
743 | [21086] = 0x0001, /* R21086 - VSS_XTS6_1 */ | |
744 | [21087] = 0x1F40, /* R21087 - VSS_XTS6_0 */ | |
745 | [21088] = 0x00F8, /* R21088 - VSS_XTS7_1 */ | |
746 | [21089] = 0xB000, /* R21089 - VSS_XTS7_0 */ | |
747 | [21090] = 0x00FB, /* R21090 - VSS_XTS8_1 */ | |
748 | [21091] = 0xCBC0, /* R21091 - VSS_XTS8_0 */ | |
749 | [21092] = 0x0004, /* R21092 - VSS_XTS9_1 */ | |
750 | [21093] = 0xF380, /* R21093 - VSS_XTS9_0 */ | |
751 | [21094] = 0x0007, /* R21094 - VSS_XTS10_1 */ | |
752 | [21095] = 0xDF40, /* R21095 - VSS_XTS10_0 */ | |
753 | [21096] = 0x00FF, /* R21096 - VSS_XTS11_1 */ | |
754 | [21097] = 0x0700, /* R21097 - VSS_XTS11_0 */ | |
755 | [21098] = 0x00EF, /* R21098 - VSS_XTS12_1 */ | |
756 | [21099] = 0xD700, /* R21099 - VSS_XTS12_0 */ | |
757 | [21100] = 0x00FB, /* R21100 - VSS_XTS13_1 */ | |
758 | [21101] = 0xAF40, /* R21101 - VSS_XTS13_0 */ | |
759 | [21102] = 0x0010, /* R21102 - VSS_XTS14_1 */ | |
760 | [21103] = 0x8A80, /* R21103 - VSS_XTS14_0 */ | |
761 | [21104] = 0x0011, /* R21104 - VSS_XTS15_1 */ | |
762 | [21105] = 0x07C0, /* R21105 - VSS_XTS15_0 */ | |
763 | [21106] = 0x00E0, /* R21106 - VSS_XTS16_1 */ | |
764 | [21107] = 0x0800, /* R21107 - VSS_XTS16_0 */ | |
765 | [21108] = 0x00D2, /* R21108 - VSS_XTS17_1 */ | |
766 | [21109] = 0x7600, /* R21109 - VSS_XTS17_0 */ | |
767 | [21110] = 0x0020, /* R21110 - VSS_XTS18_1 */ | |
768 | [21111] = 0xCF40, /* R21111 - VSS_XTS18_0 */ | |
769 | [21112] = 0x0030, /* R21112 - VSS_XTS19_1 */ | |
770 | [21113] = 0x2340, /* R21113 - VSS_XTS19_0 */ | |
771 | [21114] = 0x00FD, /* R21114 - VSS_XTS20_1 */ | |
772 | [21115] = 0x69C0, /* R21115 - VSS_XTS20_0 */ | |
773 | [21116] = 0x0028, /* R21116 - VSS_XTS21_1 */ | |
774 | [21117] = 0x3500, /* R21117 - VSS_XTS21_0 */ | |
775 | [21118] = 0x0006, /* R21118 - VSS_XTS22_1 */ | |
776 | [21119] = 0x3300, /* R21119 - VSS_XTS22_0 */ | |
777 | [21120] = 0x00D9, /* R21120 - VSS_XTS23_1 */ | |
778 | [21121] = 0xF6C0, /* R21121 - VSS_XTS23_0 */ | |
779 | [21122] = 0x00F3, /* R21122 - VSS_XTS24_1 */ | |
780 | [21123] = 0x3340, /* R21123 - VSS_XTS24_0 */ | |
781 | [21124] = 0x000F, /* R21124 - VSS_XTS25_1 */ | |
782 | [21125] = 0x4200, /* R21125 - VSS_XTS25_0 */ | |
783 | [21126] = 0x0004, /* R21126 - VSS_XTS26_1 */ | |
784 | [21127] = 0x0C80, /* R21127 - VSS_XTS26_0 */ | |
785 | [21128] = 0x00FB, /* R21128 - VSS_XTS27_1 */ | |
786 | [21129] = 0x3F80, /* R21129 - VSS_XTS27_0 */ | |
787 | [21130] = 0x00F7, /* R21130 - VSS_XTS28_1 */ | |
788 | [21131] = 0x57C0, /* R21131 - VSS_XTS28_0 */ | |
789 | [21132] = 0x0003, /* R21132 - VSS_XTS29_1 */ | |
790 | [21133] = 0x5400, /* R21133 - VSS_XTS29_0 */ | |
791 | [21134] = 0x0000, /* R21134 - VSS_XTS30_1 */ | |
792 | [21135] = 0xC6C0, /* R21135 - VSS_XTS30_0 */ | |
793 | [21136] = 0x0003, /* R21136 - VSS_XTS31_1 */ | |
794 | [21137] = 0x12C0, /* R21137 - VSS_XTS31_0 */ | |
795 | [21138] = 0x00FD, /* R21138 - VSS_XTS32_1 */ | |
796 | [21139] = 0x8580, /* R21139 - VSS_XTS32_0 */ | |
797 | }; | |
798 | ||
c969f19f MB |
799 | static const struct wm8962_reg_access { |
800 | u16 read; | |
801 | u16 write; | |
802 | u16 vol; | |
803 | } wm8962_reg_access[WM8962_MAX_REGISTER + 1] = { | |
804 | [0] = { 0x00FF, 0x01FF, 0x0000 }, /* R0 - Left Input volume */ | |
805 | [1] = { 0xFEFF, 0x01FF, 0xFFFF }, /* R1 - Right Input volume */ | |
806 | [2] = { 0x00FF, 0x01FF, 0x0000 }, /* R2 - HPOUTL volume */ | |
807 | [3] = { 0x00FF, 0x01FF, 0x0000 }, /* R3 - HPOUTR volume */ | |
808 | [4] = { 0x07FE, 0x07FE, 0xFFFF }, /* R4 - Clocking1 */ | |
809 | [5] = { 0x007F, 0x007F, 0x0000 }, /* R5 - ADC & DAC Control 1 */ | |
810 | [6] = { 0x37ED, 0x37ED, 0x0000 }, /* R6 - ADC & DAC Control 2 */ | |
811 | [7] = { 0x1FFF, 0x1FFF, 0x0000 }, /* R7 - Audio Interface 0 */ | |
812 | [8] = { 0x0FEF, 0x0FEF, 0xFFFF }, /* R8 - Clocking2 */ | |
813 | [9] = { 0x0B9F, 0x039F, 0x0000 }, /* R9 - Audio Interface 1 */ | |
814 | [10] = { 0x00FF, 0x01FF, 0x0000 }, /* R10 - Left DAC volume */ | |
815 | [11] = { 0x00FF, 0x01FF, 0x0000 }, /* R11 - Right DAC volume */ | |
816 | [14] = { 0x07FF, 0x07FF, 0x0000 }, /* R14 - Audio Interface 2 */ | |
817 | [15] = { 0xFFFF, 0xFFFF, 0xFFFF }, /* R15 - Software Reset */ | |
818 | [17] = { 0x07FF, 0x07FF, 0x0000 }, /* R17 - ALC1 */ | |
819 | [18] = { 0xF8FF, 0x00FF, 0xFFFF }, /* R18 - ALC2 */ | |
820 | [19] = { 0x1DFF, 0x1DFF, 0x0000 }, /* R19 - ALC3 */ | |
821 | [20] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20 - Noise Gate */ | |
822 | [21] = { 0x00FF, 0x01FF, 0x0000 }, /* R21 - Left ADC volume */ | |
823 | [22] = { 0x00FF, 0x01FF, 0x0000 }, /* R22 - Right ADC volume */ | |
824 | [23] = { 0x0161, 0x0161, 0x0000 }, /* R23 - Additional control(1) */ | |
825 | [24] = { 0x0008, 0x0008, 0x0000 }, /* R24 - Additional control(2) */ | |
826 | [25] = { 0x07FE, 0x07FE, 0x0000 }, /* R25 - Pwr Mgmt (1) */ | |
827 | [26] = { 0x01FB, 0x01FB, 0x0000 }, /* R26 - Pwr Mgmt (2) */ | |
828 | [27] = { 0x0017, 0x0017, 0x0000 }, /* R27 - Additional Control (3) */ | |
829 | [28] = { 0x001C, 0x001C, 0x0000 }, /* R28 - Anti-pop */ | |
830 | ||
831 | [30] = { 0xFFFE, 0xFFFE, 0x0000 }, /* R30 - Clocking 3 */ | |
832 | [31] = { 0x000F, 0x000F, 0x0000 }, /* R31 - Input mixer control (1) */ | |
833 | [32] = { 0x01FF, 0x01FF, 0x0000 }, /* R32 - Left input mixer volume */ | |
834 | [33] = { 0x01FF, 0x01FF, 0x0000 }, /* R33 - Right input mixer volume */ | |
835 | [34] = { 0x003F, 0x003F, 0x0000 }, /* R34 - Input mixer control (2) */ | |
836 | [35] = { 0x003F, 0x003F, 0x0000 }, /* R35 - Input bias control */ | |
837 | [37] = { 0x001F, 0x001F, 0x0000 }, /* R37 - Left input PGA control */ | |
838 | [38] = { 0x001F, 0x001F, 0x0000 }, /* R38 - Right input PGA control */ | |
839 | [40] = { 0x00FF, 0x01FF, 0x0000 }, /* R40 - SPKOUTL volume */ | |
840 | [41] = { 0x00FF, 0x01FF, 0x0000 }, /* R41 - SPKOUTR volume */ | |
841 | ||
fbf04076 | 842 | [47] = { 0x000F, 0x0000, 0xFFFF }, /* R47 - Thermal Shutdown Status */ |
c969f19f MB |
843 | [48] = { 0x7EC7, 0x7E07, 0xFFFF }, /* R48 - Additional Control (4) */ |
844 | [49] = { 0x00D3, 0x00D7, 0xFFFF }, /* R49 - Class D Control 1 */ | |
845 | [51] = { 0x0047, 0x0047, 0x0000 }, /* R51 - Class D Control 2 */ | |
846 | [56] = { 0x001E, 0x001E, 0x0000 }, /* R56 - Clocking 4 */ | |
847 | [57] = { 0x02FC, 0x02FC, 0x0000 }, /* R57 - DAC DSP Mixing (1) */ | |
848 | [58] = { 0x00FC, 0x00FC, 0x0000 }, /* R58 - DAC DSP Mixing (2) */ | |
849 | [60] = { 0x00CC, 0x00CC, 0x0000 }, /* R60 - DC Servo 0 */ | |
850 | [61] = { 0x00DD, 0x00DD, 0x0000 }, /* R61 - DC Servo 1 */ | |
851 | [64] = { 0x3F80, 0x3F80, 0x0000 }, /* R64 - DC Servo 4 */ | |
852 | [66] = { 0x0780, 0x0000, 0xFFFF }, /* R66 - DC Servo 6 */ | |
853 | [68] = { 0x0007, 0x0007, 0x0000 }, /* R68 - Analogue PGA Bias */ | |
854 | [69] = { 0x00FF, 0x00FF, 0x0000 }, /* R69 - Analogue HP 0 */ | |
855 | [71] = { 0x01FF, 0x01FF, 0x0000 }, /* R71 - Analogue HP 2 */ | |
856 | [72] = { 0x0001, 0x0001, 0x0000 }, /* R72 - Charge Pump 1 */ | |
857 | [82] = { 0x0001, 0x0001, 0x0000 }, /* R82 - Charge Pump B */ | |
858 | [87] = { 0x00A0, 0x00A0, 0x0000 }, /* R87 - Write Sequencer Control 1 */ | |
859 | [90] = { 0x007F, 0x01FF, 0x0000 }, /* R90 - Write Sequencer Control 2 */ | |
860 | [93] = { 0x03F9, 0x0000, 0x0000 }, /* R93 - Write Sequencer Control 3 */ | |
861 | [94] = { 0x0070, 0x0070, 0x0000 }, /* R94 - Control Interface */ | |
862 | [99] = { 0x000F, 0x000F, 0x0000 }, /* R99 - Mixer Enables */ | |
863 | [100] = { 0x00BF, 0x00BF, 0x0000 }, /* R100 - Headphone Mixer (1) */ | |
864 | [101] = { 0x00BF, 0x00BF, 0x0000 }, /* R101 - Headphone Mixer (2) */ | |
865 | [102] = { 0x01FF, 0x01FF, 0x0000 }, /* R102 - Headphone Mixer (3) */ | |
866 | [103] = { 0x01FF, 0x01FF, 0x0000 }, /* R103 - Headphone Mixer (4) */ | |
867 | [105] = { 0x00BF, 0x00BF, 0x0000 }, /* R105 - Speaker Mixer (1) */ | |
868 | [106] = { 0x00BF, 0x00BF, 0x0000 }, /* R106 - Speaker Mixer (2) */ | |
869 | [107] = { 0x01FF, 0x01FF, 0x0000 }, /* R107 - Speaker Mixer (3) */ | |
870 | [108] = { 0x01FF, 0x01FF, 0x0000 }, /* R108 - Speaker Mixer (4) */ | |
871 | [109] = { 0x00F0, 0x00F0, 0x0000 }, /* R109 - Speaker Mixer (5) */ | |
872 | [110] = { 0x00F7, 0x00F7, 0x0000 }, /* R110 - Beep Generator (1) */ | |
873 | [115] = { 0x001F, 0x001F, 0x0000 }, /* R115 - Oscillator Trim (3) */ | |
874 | [116] = { 0x001F, 0x001F, 0x0000 }, /* R116 - Oscillator Trim (4) */ | |
875 | [119] = { 0x00FF, 0x00FF, 0x0000 }, /* R119 - Oscillator Trim (7) */ | |
876 | [124] = { 0x0079, 0x0079, 0x0000 }, /* R124 - Analogue Clocking1 */ | |
877 | [125] = { 0x00DF, 0x00DF, 0x0000 }, /* R125 - Analogue Clocking2 */ | |
878 | [126] = { 0x000D, 0x000D, 0x0000 }, /* R126 - Analogue Clocking3 */ | |
879 | [127] = { 0x0000, 0xFFFF, 0x0000 }, /* R127 - PLL Software Reset */ | |
880 | [129] = { 0x00B0, 0x00B0, 0x0000 }, /* R129 - PLL2 */ | |
881 | [131] = { 0x0003, 0x0003, 0x0000 }, /* R131 - PLL 4 */ | |
882 | [136] = { 0x005F, 0x005F, 0x0000 }, /* R136 - PLL 9 */ | |
883 | [137] = { 0x00FF, 0x00FF, 0x0000 }, /* R137 - PLL 10 */ | |
884 | [138] = { 0x00FF, 0x00FF, 0x0000 }, /* R138 - PLL 11 */ | |
885 | [139] = { 0x00FF, 0x00FF, 0x0000 }, /* R139 - PLL 12 */ | |
886 | [140] = { 0x005F, 0x005F, 0x0000 }, /* R140 - PLL 13 */ | |
887 | [141] = { 0x00FF, 0x00FF, 0x0000 }, /* R141 - PLL 14 */ | |
888 | [142] = { 0x00FF, 0x00FF, 0x0000 }, /* R142 - PLL 15 */ | |
889 | [143] = { 0x00FF, 0x00FF, 0x0000 }, /* R143 - PLL 16 */ | |
890 | [155] = { 0x0067, 0x0067, 0x0000 }, /* R155 - FLL Control (1) */ | |
891 | [156] = { 0x01FB, 0x01FB, 0x0000 }, /* R156 - FLL Control (2) */ | |
892 | [157] = { 0x0007, 0x0007, 0x0000 }, /* R157 - FLL Control (3) */ | |
893 | [159] = { 0x007F, 0x007F, 0x0000 }, /* R159 - FLL Control (5) */ | |
894 | [160] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R160 - FLL Control (6) */ | |
895 | [161] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R161 - FLL Control (7) */ | |
896 | [162] = { 0x03FF, 0x03FF, 0x0000 }, /* R162 - FLL Control (8) */ | |
897 | [252] = { 0x0005, 0x0005, 0x0000 }, /* R252 - General test 1 */ | |
898 | [256] = { 0x000F, 0x000F, 0x0000 }, /* R256 - DF1 */ | |
899 | [257] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R257 - DF2 */ | |
900 | [258] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R258 - DF3 */ | |
901 | [259] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R259 - DF4 */ | |
902 | [260] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R260 - DF5 */ | |
903 | [261] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R261 - DF6 */ | |
904 | [262] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R262 - DF7 */ | |
905 | [264] = { 0x0003, 0x0003, 0x0000 }, /* R264 - LHPF1 */ | |
906 | [265] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R265 - LHPF2 */ | |
907 | [268] = { 0x0077, 0x0077, 0x0000 }, /* R268 - THREED1 */ | |
908 | [269] = { 0xFFFC, 0xFFFC, 0x0000 }, /* R269 - THREED2 */ | |
909 | [270] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R270 - THREED3 */ | |
910 | [271] = { 0xFFFC, 0xFFFC, 0x0000 }, /* R271 - THREED4 */ | |
911 | [276] = { 0x7FFF, 0x7FFF, 0x0000 }, /* R276 - DRC 1 */ | |
912 | [277] = { 0x1FFF, 0x1FFF, 0x0000 }, /* R277 - DRC 2 */ | |
913 | [278] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R278 - DRC 3 */ | |
914 | [279] = { 0x07FF, 0x07FF, 0x0000 }, /* R279 - DRC 4 */ | |
915 | [280] = { 0x03FF, 0x03FF, 0x0000 }, /* R280 - DRC 5 */ | |
916 | [285] = { 0x0003, 0x0003, 0x0000 }, /* R285 - Tloopback */ | |
917 | [335] = { 0x0007, 0x0007, 0x0000 }, /* R335 - EQ1 */ | |
918 | [336] = { 0xFFFE, 0xFFFE, 0x0000 }, /* R336 - EQ2 */ | |
919 | [337] = { 0xFFC0, 0xFFC0, 0x0000 }, /* R337 - EQ3 */ | |
920 | [338] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R338 - EQ4 */ | |
921 | [339] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R339 - EQ5 */ | |
922 | [340] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R340 - EQ6 */ | |
923 | [341] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R341 - EQ7 */ | |
924 | [342] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R342 - EQ8 */ | |
925 | [343] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R343 - EQ9 */ | |
926 | [344] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R344 - EQ10 */ | |
927 | [345] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R345 - EQ11 */ | |
928 | [346] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R346 - EQ12 */ | |
929 | [347] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R347 - EQ13 */ | |
930 | [348] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R348 - EQ14 */ | |
931 | [349] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R349 - EQ15 */ | |
932 | [350] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R350 - EQ16 */ | |
933 | [351] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R351 - EQ17 */ | |
934 | [352] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R352 - EQ18 */ | |
935 | [353] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R353 - EQ19 */ | |
936 | [354] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R354 - EQ20 */ | |
937 | [355] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R355 - EQ21 */ | |
938 | [356] = { 0xFFFE, 0xFFFE, 0x0000 }, /* R356 - EQ22 */ | |
939 | [357] = { 0xFFC0, 0xFFC0, 0x0000 }, /* R357 - EQ23 */ | |
940 | [358] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R358 - EQ24 */ | |
941 | [359] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R359 - EQ25 */ | |
942 | [360] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R360 - EQ26 */ | |
943 | [361] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R361 - EQ27 */ | |
944 | [362] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R362 - EQ28 */ | |
945 | [363] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R363 - EQ29 */ | |
946 | [364] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R364 - EQ30 */ | |
947 | [365] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R365 - EQ31 */ | |
948 | [366] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R366 - EQ32 */ | |
949 | [367] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R367 - EQ33 */ | |
950 | [368] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R368 - EQ34 */ | |
951 | [369] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R369 - EQ35 */ | |
952 | [370] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R370 - EQ36 */ | |
953 | [371] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R371 - EQ37 */ | |
954 | [372] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R372 - EQ38 */ | |
955 | [373] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R373 - EQ39 */ | |
956 | [374] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R374 - EQ40 */ | |
957 | [375] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R375 - EQ41 */ | |
958 | [513] = { 0x045F, 0x045F, 0x0000 }, /* R513 - GPIO 2 */ | |
959 | [514] = { 0x045F, 0x045F, 0x0000 }, /* R514 - GPIO 3 */ | |
960 | [516] = { 0xE75F, 0xE75F, 0x0000 }, /* R516 - GPIO 5 */ | |
961 | [517] = { 0xE75F, 0xE75F, 0x0000 }, /* R517 - GPIO 6 */ | |
962 | [560] = { 0x0030, 0x0030, 0xFFFF }, /* R560 - Interrupt Status 1 */ | |
963 | [561] = { 0xFFED, 0xFFED, 0xFFFF }, /* R561 - Interrupt Status 2 */ | |
964 | [568] = { 0x0030, 0x0030, 0x0000 }, /* R568 - Interrupt Status 1 Mask */ | |
965 | [569] = { 0xFFED, 0xFFED, 0x0000 }, /* R569 - Interrupt Status 2 Mask */ | |
966 | [576] = { 0x0001, 0x0001, 0x0000 }, /* R576 - Interrupt Control */ | |
967 | [584] = { 0x002D, 0x002D, 0x0000 }, /* R584 - IRQ Debounce */ | |
968 | [586] = { 0xC000, 0xC000, 0x0000 }, /* R586 - MICINT Source Pol */ | |
969 | [768] = { 0x0001, 0x0001, 0x0000 }, /* R768 - DSP2 Power Management */ | |
6f88a4e5 | 970 | [1037] = { 0x0000, 0x003F, 0xFFFF }, /* R1037 - DSP2_ExecControl */ |
c969f19f MB |
971 | [4096] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4096 - Write Sequencer 0 */ |
972 | [4097] = { 0x00FF, 0x00FF, 0x0000 }, /* R4097 - Write Sequencer 1 */ | |
973 | [4098] = { 0x070F, 0x070F, 0x0000 }, /* R4098 - Write Sequencer 2 */ | |
974 | [4099] = { 0x010F, 0x010F, 0x0000 }, /* R4099 - Write Sequencer 3 */ | |
975 | [4100] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4100 - Write Sequencer 4 */ | |
976 | [4101] = { 0x00FF, 0x00FF, 0x0000 }, /* R4101 - Write Sequencer 5 */ | |
977 | [4102] = { 0x070F, 0x070F, 0x0000 }, /* R4102 - Write Sequencer 6 */ | |
978 | [4103] = { 0x010F, 0x010F, 0x0000 }, /* R4103 - Write Sequencer 7 */ | |
979 | [4104] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4104 - Write Sequencer 8 */ | |
980 | [4105] = { 0x00FF, 0x00FF, 0x0000 }, /* R4105 - Write Sequencer 9 */ | |
981 | [4106] = { 0x070F, 0x070F, 0x0000 }, /* R4106 - Write Sequencer 10 */ | |
982 | [4107] = { 0x010F, 0x010F, 0x0000 }, /* R4107 - Write Sequencer 11 */ | |
983 | [4108] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4108 - Write Sequencer 12 */ | |
984 | [4109] = { 0x00FF, 0x00FF, 0x0000 }, /* R4109 - Write Sequencer 13 */ | |
985 | [4110] = { 0x070F, 0x070F, 0x0000 }, /* R4110 - Write Sequencer 14 */ | |
986 | [4111] = { 0x010F, 0x010F, 0x0000 }, /* R4111 - Write Sequencer 15 */ | |
987 | [4112] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4112 - Write Sequencer 16 */ | |
988 | [4113] = { 0x00FF, 0x00FF, 0x0000 }, /* R4113 - Write Sequencer 17 */ | |
989 | [4114] = { 0x070F, 0x070F, 0x0000 }, /* R4114 - Write Sequencer 18 */ | |
990 | [4115] = { 0x010F, 0x010F, 0x0000 }, /* R4115 - Write Sequencer 19 */ | |
991 | [4116] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4116 - Write Sequencer 20 */ | |
992 | [4117] = { 0x00FF, 0x00FF, 0x0000 }, /* R4117 - Write Sequencer 21 */ | |
993 | [4118] = { 0x070F, 0x070F, 0x0000 }, /* R4118 - Write Sequencer 22 */ | |
994 | [4119] = { 0x010F, 0x010F, 0x0000 }, /* R4119 - Write Sequencer 23 */ | |
995 | [4120] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4120 - Write Sequencer 24 */ | |
996 | [4121] = { 0x00FF, 0x00FF, 0x0000 }, /* R4121 - Write Sequencer 25 */ | |
997 | [4122] = { 0x070F, 0x070F, 0x0000 }, /* R4122 - Write Sequencer 26 */ | |
998 | [4123] = { 0x010F, 0x010F, 0x0000 }, /* R4123 - Write Sequencer 27 */ | |
999 | [4124] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4124 - Write Sequencer 28 */ | |
1000 | [4125] = { 0x00FF, 0x00FF, 0x0000 }, /* R4125 - Write Sequencer 29 */ | |
1001 | [4126] = { 0x070F, 0x070F, 0x0000 }, /* R4126 - Write Sequencer 30 */ | |
1002 | [4127] = { 0x010F, 0x010F, 0x0000 }, /* R4127 - Write Sequencer 31 */ | |
1003 | [4128] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4128 - Write Sequencer 32 */ | |
1004 | [4129] = { 0x00FF, 0x00FF, 0x0000 }, /* R4129 - Write Sequencer 33 */ | |
1005 | [4130] = { 0x070F, 0x070F, 0x0000 }, /* R4130 - Write Sequencer 34 */ | |
1006 | [4131] = { 0x010F, 0x010F, 0x0000 }, /* R4131 - Write Sequencer 35 */ | |
1007 | [4132] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4132 - Write Sequencer 36 */ | |
1008 | [4133] = { 0x00FF, 0x00FF, 0x0000 }, /* R4133 - Write Sequencer 37 */ | |
1009 | [4134] = { 0x070F, 0x070F, 0x0000 }, /* R4134 - Write Sequencer 38 */ | |
1010 | [4135] = { 0x010F, 0x010F, 0x0000 }, /* R4135 - Write Sequencer 39 */ | |
1011 | [4136] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4136 - Write Sequencer 40 */ | |
1012 | [4137] = { 0x00FF, 0x00FF, 0x0000 }, /* R4137 - Write Sequencer 41 */ | |
1013 | [4138] = { 0x070F, 0x070F, 0x0000 }, /* R4138 - Write Sequencer 42 */ | |
1014 | [4139] = { 0x010F, 0x010F, 0x0000 }, /* R4139 - Write Sequencer 43 */ | |
1015 | [4140] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4140 - Write Sequencer 44 */ | |
1016 | [4141] = { 0x00FF, 0x00FF, 0x0000 }, /* R4141 - Write Sequencer 45 */ | |
1017 | [4142] = { 0x070F, 0x070F, 0x0000 }, /* R4142 - Write Sequencer 46 */ | |
1018 | [4143] = { 0x010F, 0x010F, 0x0000 }, /* R4143 - Write Sequencer 47 */ | |
1019 | [4144] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4144 - Write Sequencer 48 */ | |
1020 | [4145] = { 0x00FF, 0x00FF, 0x0000 }, /* R4145 - Write Sequencer 49 */ | |
1021 | [4146] = { 0x070F, 0x070F, 0x0000 }, /* R4146 - Write Sequencer 50 */ | |
1022 | [4147] = { 0x010F, 0x010F, 0x0000 }, /* R4147 - Write Sequencer 51 */ | |
1023 | [4148] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4148 - Write Sequencer 52 */ | |
1024 | [4149] = { 0x00FF, 0x00FF, 0x0000 }, /* R4149 - Write Sequencer 53 */ | |
1025 | [4150] = { 0x070F, 0x070F, 0x0000 }, /* R4150 - Write Sequencer 54 */ | |
1026 | [4151] = { 0x010F, 0x010F, 0x0000 }, /* R4151 - Write Sequencer 55 */ | |
1027 | [4152] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4152 - Write Sequencer 56 */ | |
1028 | [4153] = { 0x00FF, 0x00FF, 0x0000 }, /* R4153 - Write Sequencer 57 */ | |
1029 | [4154] = { 0x070F, 0x070F, 0x0000 }, /* R4154 - Write Sequencer 58 */ | |
1030 | [4155] = { 0x010F, 0x010F, 0x0000 }, /* R4155 - Write Sequencer 59 */ | |
1031 | [4156] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4156 - Write Sequencer 60 */ | |
1032 | [4157] = { 0x00FF, 0x00FF, 0x0000 }, /* R4157 - Write Sequencer 61 */ | |
1033 | [4158] = { 0x070F, 0x070F, 0x0000 }, /* R4158 - Write Sequencer 62 */ | |
1034 | [4159] = { 0x010F, 0x010F, 0x0000 }, /* R4159 - Write Sequencer 63 */ | |
1035 | [4160] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4160 - Write Sequencer 64 */ | |
1036 | [4161] = { 0x00FF, 0x00FF, 0x0000 }, /* R4161 - Write Sequencer 65 */ | |
1037 | [4162] = { 0x070F, 0x070F, 0x0000 }, /* R4162 - Write Sequencer 66 */ | |
1038 | [4163] = { 0x010F, 0x010F, 0x0000 }, /* R4163 - Write Sequencer 67 */ | |
1039 | [4164] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4164 - Write Sequencer 68 */ | |
1040 | [4165] = { 0x00FF, 0x00FF, 0x0000 }, /* R4165 - Write Sequencer 69 */ | |
1041 | [4166] = { 0x070F, 0x070F, 0x0000 }, /* R4166 - Write Sequencer 70 */ | |
1042 | [4167] = { 0x010F, 0x010F, 0x0000 }, /* R4167 - Write Sequencer 71 */ | |
1043 | [4168] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4168 - Write Sequencer 72 */ | |
1044 | [4169] = { 0x00FF, 0x00FF, 0x0000 }, /* R4169 - Write Sequencer 73 */ | |
1045 | [4170] = { 0x070F, 0x070F, 0x0000 }, /* R4170 - Write Sequencer 74 */ | |
1046 | [4171] = { 0x010F, 0x010F, 0x0000 }, /* R4171 - Write Sequencer 75 */ | |
1047 | [4172] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4172 - Write Sequencer 76 */ | |
1048 | [4173] = { 0x00FF, 0x00FF, 0x0000 }, /* R4173 - Write Sequencer 77 */ | |
1049 | [4174] = { 0x070F, 0x070F, 0x0000 }, /* R4174 - Write Sequencer 78 */ | |
1050 | [4175] = { 0x010F, 0x010F, 0x0000 }, /* R4175 - Write Sequencer 79 */ | |
1051 | [4176] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4176 - Write Sequencer 80 */ | |
1052 | [4177] = { 0x00FF, 0x00FF, 0x0000 }, /* R4177 - Write Sequencer 81 */ | |
1053 | [4178] = { 0x070F, 0x070F, 0x0000 }, /* R4178 - Write Sequencer 82 */ | |
1054 | [4179] = { 0x010F, 0x010F, 0x0000 }, /* R4179 - Write Sequencer 83 */ | |
1055 | [4180] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4180 - Write Sequencer 84 */ | |
1056 | [4181] = { 0x00FF, 0x00FF, 0x0000 }, /* R4181 - Write Sequencer 85 */ | |
1057 | [4182] = { 0x070F, 0x070F, 0x0000 }, /* R4182 - Write Sequencer 86 */ | |
1058 | [4183] = { 0x010F, 0x010F, 0x0000 }, /* R4183 - Write Sequencer 87 */ | |
1059 | [4184] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4184 - Write Sequencer 88 */ | |
1060 | [4185] = { 0x00FF, 0x00FF, 0x0000 }, /* R4185 - Write Sequencer 89 */ | |
1061 | [4186] = { 0x070F, 0x070F, 0x0000 }, /* R4186 - Write Sequencer 90 */ | |
1062 | [4187] = { 0x010F, 0x010F, 0x0000 }, /* R4187 - Write Sequencer 91 */ | |
1063 | [4188] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4188 - Write Sequencer 92 */ | |
1064 | [4189] = { 0x00FF, 0x00FF, 0x0000 }, /* R4189 - Write Sequencer 93 */ | |
1065 | [4190] = { 0x070F, 0x070F, 0x0000 }, /* R4190 - Write Sequencer 94 */ | |
1066 | [4191] = { 0x010F, 0x010F, 0x0000 }, /* R4191 - Write Sequencer 95 */ | |
1067 | [4192] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4192 - Write Sequencer 96 */ | |
1068 | [4193] = { 0x00FF, 0x00FF, 0x0000 }, /* R4193 - Write Sequencer 97 */ | |
1069 | [4194] = { 0x070F, 0x070F, 0x0000 }, /* R4194 - Write Sequencer 98 */ | |
1070 | [4195] = { 0x010F, 0x010F, 0x0000 }, /* R4195 - Write Sequencer 99 */ | |
1071 | [4196] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4196 - Write Sequencer 100 */ | |
1072 | [4197] = { 0x00FF, 0x00FF, 0x0000 }, /* R4197 - Write Sequencer 101 */ | |
1073 | [4198] = { 0x070F, 0x070F, 0x0000 }, /* R4198 - Write Sequencer 102 */ | |
1074 | [4199] = { 0x010F, 0x010F, 0x0000 }, /* R4199 - Write Sequencer 103 */ | |
1075 | [4200] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4200 - Write Sequencer 104 */ | |
1076 | [4201] = { 0x00FF, 0x00FF, 0x0000 }, /* R4201 - Write Sequencer 105 */ | |
1077 | [4202] = { 0x070F, 0x070F, 0x0000 }, /* R4202 - Write Sequencer 106 */ | |
1078 | [4203] = { 0x010F, 0x010F, 0x0000 }, /* R4203 - Write Sequencer 107 */ | |
1079 | [4204] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4204 - Write Sequencer 108 */ | |
1080 | [4205] = { 0x00FF, 0x00FF, 0x0000 }, /* R4205 - Write Sequencer 109 */ | |
1081 | [4206] = { 0x070F, 0x070F, 0x0000 }, /* R4206 - Write Sequencer 110 */ | |
1082 | [4207] = { 0x010F, 0x010F, 0x0000 }, /* R4207 - Write Sequencer 111 */ | |
1083 | [4208] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4208 - Write Sequencer 112 */ | |
1084 | [4209] = { 0x00FF, 0x00FF, 0x0000 }, /* R4209 - Write Sequencer 113 */ | |
1085 | [4210] = { 0x070F, 0x070F, 0x0000 }, /* R4210 - Write Sequencer 114 */ | |
1086 | [4211] = { 0x010F, 0x010F, 0x0000 }, /* R4211 - Write Sequencer 115 */ | |
1087 | [4212] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4212 - Write Sequencer 116 */ | |
1088 | [4213] = { 0x00FF, 0x00FF, 0x0000 }, /* R4213 - Write Sequencer 117 */ | |
1089 | [4214] = { 0x070F, 0x070F, 0x0000 }, /* R4214 - Write Sequencer 118 */ | |
1090 | [4215] = { 0x010F, 0x010F, 0x0000 }, /* R4215 - Write Sequencer 119 */ | |
1091 | [4216] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4216 - Write Sequencer 120 */ | |
1092 | [4217] = { 0x00FF, 0x00FF, 0x0000 }, /* R4217 - Write Sequencer 121 */ | |
1093 | [4218] = { 0x070F, 0x070F, 0x0000 }, /* R4218 - Write Sequencer 122 */ | |
1094 | [4219] = { 0x010F, 0x010F, 0x0000 }, /* R4219 - Write Sequencer 123 */ | |
1095 | [4220] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4220 - Write Sequencer 124 */ | |
1096 | [4221] = { 0x00FF, 0x00FF, 0x0000 }, /* R4221 - Write Sequencer 125 */ | |
1097 | [4222] = { 0x070F, 0x070F, 0x0000 }, /* R4222 - Write Sequencer 126 */ | |
1098 | [4223] = { 0x010F, 0x010F, 0x0000 }, /* R4223 - Write Sequencer 127 */ | |
1099 | [4224] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4224 - Write Sequencer 128 */ | |
1100 | [4225] = { 0x00FF, 0x00FF, 0x0000 }, /* R4225 - Write Sequencer 129 */ | |
1101 | [4226] = { 0x070F, 0x070F, 0x0000 }, /* R4226 - Write Sequencer 130 */ | |
1102 | [4227] = { 0x010F, 0x010F, 0x0000 }, /* R4227 - Write Sequencer 131 */ | |
1103 | [4228] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4228 - Write Sequencer 132 */ | |
1104 | [4229] = { 0x00FF, 0x00FF, 0x0000 }, /* R4229 - Write Sequencer 133 */ | |
1105 | [4230] = { 0x070F, 0x070F, 0x0000 }, /* R4230 - Write Sequencer 134 */ | |
1106 | [4231] = { 0x010F, 0x010F, 0x0000 }, /* R4231 - Write Sequencer 135 */ | |
1107 | [4232] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4232 - Write Sequencer 136 */ | |
1108 | [4233] = { 0x00FF, 0x00FF, 0x0000 }, /* R4233 - Write Sequencer 137 */ | |
1109 | [4234] = { 0x070F, 0x070F, 0x0000 }, /* R4234 - Write Sequencer 138 */ | |
1110 | [4235] = { 0x010F, 0x010F, 0x0000 }, /* R4235 - Write Sequencer 139 */ | |
1111 | [4236] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4236 - Write Sequencer 140 */ | |
1112 | [4237] = { 0x00FF, 0x00FF, 0x0000 }, /* R4237 - Write Sequencer 141 */ | |
1113 | [4238] = { 0x070F, 0x070F, 0x0000 }, /* R4238 - Write Sequencer 142 */ | |
1114 | [4239] = { 0x010F, 0x010F, 0x0000 }, /* R4239 - Write Sequencer 143 */ | |
1115 | [4240] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4240 - Write Sequencer 144 */ | |
1116 | [4241] = { 0x00FF, 0x00FF, 0x0000 }, /* R4241 - Write Sequencer 145 */ | |
1117 | [4242] = { 0x070F, 0x070F, 0x0000 }, /* R4242 - Write Sequencer 146 */ | |
1118 | [4243] = { 0x010F, 0x010F, 0x0000 }, /* R4243 - Write Sequencer 147 */ | |
1119 | [4244] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4244 - Write Sequencer 148 */ | |
1120 | [4245] = { 0x00FF, 0x00FF, 0x0000 }, /* R4245 - Write Sequencer 149 */ | |
1121 | [4246] = { 0x070F, 0x070F, 0x0000 }, /* R4246 - Write Sequencer 150 */ | |
1122 | [4247] = { 0x010F, 0x010F, 0x0000 }, /* R4247 - Write Sequencer 151 */ | |
1123 | [4248] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4248 - Write Sequencer 152 */ | |
1124 | [4249] = { 0x00FF, 0x00FF, 0x0000 }, /* R4249 - Write Sequencer 153 */ | |
1125 | [4250] = { 0x070F, 0x070F, 0x0000 }, /* R4250 - Write Sequencer 154 */ | |
1126 | [4251] = { 0x010F, 0x010F, 0x0000 }, /* R4251 - Write Sequencer 155 */ | |
1127 | [4252] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4252 - Write Sequencer 156 */ | |
1128 | [4253] = { 0x00FF, 0x00FF, 0x0000 }, /* R4253 - Write Sequencer 157 */ | |
1129 | [4254] = { 0x070F, 0x070F, 0x0000 }, /* R4254 - Write Sequencer 158 */ | |
1130 | [4255] = { 0x010F, 0x010F, 0x0000 }, /* R4255 - Write Sequencer 159 */ | |
1131 | [4256] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4256 - Write Sequencer 160 */ | |
1132 | [4257] = { 0x00FF, 0x00FF, 0x0000 }, /* R4257 - Write Sequencer 161 */ | |
1133 | [4258] = { 0x070F, 0x070F, 0x0000 }, /* R4258 - Write Sequencer 162 */ | |
1134 | [4259] = { 0x010F, 0x010F, 0x0000 }, /* R4259 - Write Sequencer 163 */ | |
1135 | [4260] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4260 - Write Sequencer 164 */ | |
1136 | [4261] = { 0x00FF, 0x00FF, 0x0000 }, /* R4261 - Write Sequencer 165 */ | |
1137 | [4262] = { 0x070F, 0x070F, 0x0000 }, /* R4262 - Write Sequencer 166 */ | |
1138 | [4263] = { 0x010F, 0x010F, 0x0000 }, /* R4263 - Write Sequencer 167 */ | |
1139 | [4264] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4264 - Write Sequencer 168 */ | |
1140 | [4265] = { 0x00FF, 0x00FF, 0x0000 }, /* R4265 - Write Sequencer 169 */ | |
1141 | [4266] = { 0x070F, 0x070F, 0x0000 }, /* R4266 - Write Sequencer 170 */ | |
1142 | [4267] = { 0x010F, 0x010F, 0x0000 }, /* R4267 - Write Sequencer 171 */ | |
1143 | [4268] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4268 - Write Sequencer 172 */ | |
1144 | [4269] = { 0x00FF, 0x00FF, 0x0000 }, /* R4269 - Write Sequencer 173 */ | |
1145 | [4270] = { 0x070F, 0x070F, 0x0000 }, /* R4270 - Write Sequencer 174 */ | |
1146 | [4271] = { 0x010F, 0x010F, 0x0000 }, /* R4271 - Write Sequencer 175 */ | |
1147 | [4272] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4272 - Write Sequencer 176 */ | |
1148 | [4273] = { 0x00FF, 0x00FF, 0x0000 }, /* R4273 - Write Sequencer 177 */ | |
1149 | [4274] = { 0x070F, 0x070F, 0x0000 }, /* R4274 - Write Sequencer 178 */ | |
1150 | [4275] = { 0x010F, 0x010F, 0x0000 }, /* R4275 - Write Sequencer 179 */ | |
1151 | [4276] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4276 - Write Sequencer 180 */ | |
1152 | [4277] = { 0x00FF, 0x00FF, 0x0000 }, /* R4277 - Write Sequencer 181 */ | |
1153 | [4278] = { 0x070F, 0x070F, 0x0000 }, /* R4278 - Write Sequencer 182 */ | |
1154 | [4279] = { 0x010F, 0x010F, 0x0000 }, /* R4279 - Write Sequencer 183 */ | |
1155 | [4280] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4280 - Write Sequencer 184 */ | |
1156 | [4281] = { 0x00FF, 0x00FF, 0x0000 }, /* R4281 - Write Sequencer 185 */ | |
1157 | [4282] = { 0x070F, 0x070F, 0x0000 }, /* R4282 - Write Sequencer 186 */ | |
1158 | [4283] = { 0x010F, 0x010F, 0x0000 }, /* R4283 - Write Sequencer 187 */ | |
1159 | [4284] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4284 - Write Sequencer 188 */ | |
1160 | [4285] = { 0x00FF, 0x00FF, 0x0000 }, /* R4285 - Write Sequencer 189 */ | |
1161 | [4286] = { 0x070F, 0x070F, 0x0000 }, /* R4286 - Write Sequencer 190 */ | |
1162 | [4287] = { 0x010F, 0x010F, 0x0000 }, /* R4287 - Write Sequencer 191 */ | |
1163 | [4288] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4288 - Write Sequencer 192 */ | |
1164 | [4289] = { 0x00FF, 0x00FF, 0x0000 }, /* R4289 - Write Sequencer 193 */ | |
1165 | [4290] = { 0x070F, 0x070F, 0x0000 }, /* R4290 - Write Sequencer 194 */ | |
1166 | [4291] = { 0x010F, 0x010F, 0x0000 }, /* R4291 - Write Sequencer 195 */ | |
1167 | [4292] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4292 - Write Sequencer 196 */ | |
1168 | [4293] = { 0x00FF, 0x00FF, 0x0000 }, /* R4293 - Write Sequencer 197 */ | |
1169 | [4294] = { 0x070F, 0x070F, 0x0000 }, /* R4294 - Write Sequencer 198 */ | |
1170 | [4295] = { 0x010F, 0x010F, 0x0000 }, /* R4295 - Write Sequencer 199 */ | |
1171 | [4296] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4296 - Write Sequencer 200 */ | |
1172 | [4297] = { 0x00FF, 0x00FF, 0x0000 }, /* R4297 - Write Sequencer 201 */ | |
1173 | [4298] = { 0x070F, 0x070F, 0x0000 }, /* R4298 - Write Sequencer 202 */ | |
1174 | [4299] = { 0x010F, 0x010F, 0x0000 }, /* R4299 - Write Sequencer 203 */ | |
1175 | [4300] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4300 - Write Sequencer 204 */ | |
1176 | [4301] = { 0x00FF, 0x00FF, 0x0000 }, /* R4301 - Write Sequencer 205 */ | |
1177 | [4302] = { 0x070F, 0x070F, 0x0000 }, /* R4302 - Write Sequencer 206 */ | |
1178 | [4303] = { 0x010F, 0x010F, 0x0000 }, /* R4303 - Write Sequencer 207 */ | |
1179 | [4304] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4304 - Write Sequencer 208 */ | |
1180 | [4305] = { 0x00FF, 0x00FF, 0x0000 }, /* R4305 - Write Sequencer 209 */ | |
1181 | [4306] = { 0x070F, 0x070F, 0x0000 }, /* R4306 - Write Sequencer 210 */ | |
1182 | [4307] = { 0x010F, 0x010F, 0x0000 }, /* R4307 - Write Sequencer 211 */ | |
1183 | [4308] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4308 - Write Sequencer 212 */ | |
1184 | [4309] = { 0x00FF, 0x00FF, 0x0000 }, /* R4309 - Write Sequencer 213 */ | |
1185 | [4310] = { 0x070F, 0x070F, 0x0000 }, /* R4310 - Write Sequencer 214 */ | |
1186 | [4311] = { 0x010F, 0x010F, 0x0000 }, /* R4311 - Write Sequencer 215 */ | |
1187 | [4312] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4312 - Write Sequencer 216 */ | |
1188 | [4313] = { 0x00FF, 0x00FF, 0x0000 }, /* R4313 - Write Sequencer 217 */ | |
1189 | [4314] = { 0x070F, 0x070F, 0x0000 }, /* R4314 - Write Sequencer 218 */ | |
1190 | [4315] = { 0x010F, 0x010F, 0x0000 }, /* R4315 - Write Sequencer 219 */ | |
1191 | [4316] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4316 - Write Sequencer 220 */ | |
1192 | [4317] = { 0x00FF, 0x00FF, 0x0000 }, /* R4317 - Write Sequencer 221 */ | |
1193 | [4318] = { 0x070F, 0x070F, 0x0000 }, /* R4318 - Write Sequencer 222 */ | |
1194 | [4319] = { 0x010F, 0x010F, 0x0000 }, /* R4319 - Write Sequencer 223 */ | |
1195 | [4320] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4320 - Write Sequencer 224 */ | |
1196 | [4321] = { 0x00FF, 0x00FF, 0x0000 }, /* R4321 - Write Sequencer 225 */ | |
1197 | [4322] = { 0x070F, 0x070F, 0x0000 }, /* R4322 - Write Sequencer 226 */ | |
1198 | [4323] = { 0x010F, 0x010F, 0x0000 }, /* R4323 - Write Sequencer 227 */ | |
1199 | [4324] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4324 - Write Sequencer 228 */ | |
1200 | [4325] = { 0x00FF, 0x00FF, 0x0000 }, /* R4325 - Write Sequencer 229 */ | |
1201 | [4326] = { 0x070F, 0x070F, 0x0000 }, /* R4326 - Write Sequencer 230 */ | |
1202 | [4327] = { 0x010F, 0x010F, 0x0000 }, /* R4327 - Write Sequencer 231 */ | |
1203 | [4328] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4328 - Write Sequencer 232 */ | |
1204 | [4329] = { 0x00FF, 0x00FF, 0x0000 }, /* R4329 - Write Sequencer 233 */ | |
1205 | [4330] = { 0x070F, 0x070F, 0x0000 }, /* R4330 - Write Sequencer 234 */ | |
1206 | [4331] = { 0x010F, 0x010F, 0x0000 }, /* R4331 - Write Sequencer 235 */ | |
1207 | [4332] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4332 - Write Sequencer 236 */ | |
1208 | [4333] = { 0x00FF, 0x00FF, 0x0000 }, /* R4333 - Write Sequencer 237 */ | |
1209 | [4334] = { 0x070F, 0x070F, 0x0000 }, /* R4334 - Write Sequencer 238 */ | |
1210 | [4335] = { 0x010F, 0x010F, 0x0000 }, /* R4335 - Write Sequencer 239 */ | |
1211 | [4336] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4336 - Write Sequencer 240 */ | |
1212 | [4337] = { 0x00FF, 0x00FF, 0x0000 }, /* R4337 - Write Sequencer 241 */ | |
1213 | [4338] = { 0x070F, 0x070F, 0x0000 }, /* R4338 - Write Sequencer 242 */ | |
1214 | [4339] = { 0x010F, 0x010F, 0x0000 }, /* R4339 - Write Sequencer 243 */ | |
1215 | [4340] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4340 - Write Sequencer 244 */ | |
1216 | [4341] = { 0x00FF, 0x00FF, 0x0000 }, /* R4341 - Write Sequencer 245 */ | |
1217 | [4342] = { 0x070F, 0x070F, 0x0000 }, /* R4342 - Write Sequencer 246 */ | |
1218 | [4343] = { 0x010F, 0x010F, 0x0000 }, /* R4343 - Write Sequencer 247 */ | |
1219 | [4344] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4344 - Write Sequencer 248 */ | |
1220 | [4345] = { 0x00FF, 0x00FF, 0x0000 }, /* R4345 - Write Sequencer 249 */ | |
1221 | [4346] = { 0x070F, 0x070F, 0x0000 }, /* R4346 - Write Sequencer 250 */ | |
1222 | [4347] = { 0x010F, 0x010F, 0x0000 }, /* R4347 - Write Sequencer 251 */ | |
1223 | [4348] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4348 - Write Sequencer 252 */ | |
1224 | [4349] = { 0x00FF, 0x00FF, 0x0000 }, /* R4349 - Write Sequencer 253 */ | |
1225 | [4350] = { 0x070F, 0x070F, 0x0000 }, /* R4350 - Write Sequencer 254 */ | |
1226 | [4351] = { 0x010F, 0x010F, 0x0000 }, /* R4351 - Write Sequencer 255 */ | |
1227 | [4352] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4352 - Write Sequencer 256 */ | |
1228 | [4353] = { 0x00FF, 0x00FF, 0x0000 }, /* R4353 - Write Sequencer 257 */ | |
1229 | [4354] = { 0x070F, 0x070F, 0x0000 }, /* R4354 - Write Sequencer 258 */ | |
1230 | [4355] = { 0x010F, 0x010F, 0x0000 }, /* R4355 - Write Sequencer 259 */ | |
1231 | [4356] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4356 - Write Sequencer 260 */ | |
1232 | [4357] = { 0x00FF, 0x00FF, 0x0000 }, /* R4357 - Write Sequencer 261 */ | |
1233 | [4358] = { 0x070F, 0x070F, 0x0000 }, /* R4358 - Write Sequencer 262 */ | |
1234 | [4359] = { 0x010F, 0x010F, 0x0000 }, /* R4359 - Write Sequencer 263 */ | |
1235 | [4360] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4360 - Write Sequencer 264 */ | |
1236 | [4361] = { 0x00FF, 0x00FF, 0x0000 }, /* R4361 - Write Sequencer 265 */ | |
1237 | [4362] = { 0x070F, 0x070F, 0x0000 }, /* R4362 - Write Sequencer 266 */ | |
1238 | [4363] = { 0x010F, 0x010F, 0x0000 }, /* R4363 - Write Sequencer 267 */ | |
1239 | [4364] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4364 - Write Sequencer 268 */ | |
1240 | [4365] = { 0x00FF, 0x00FF, 0x0000 }, /* R4365 - Write Sequencer 269 */ | |
1241 | [4366] = { 0x070F, 0x070F, 0x0000 }, /* R4366 - Write Sequencer 270 */ | |
1242 | [4367] = { 0x010F, 0x010F, 0x0000 }, /* R4367 - Write Sequencer 271 */ | |
1243 | [4368] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4368 - Write Sequencer 272 */ | |
1244 | [4369] = { 0x00FF, 0x00FF, 0x0000 }, /* R4369 - Write Sequencer 273 */ | |
1245 | [4370] = { 0x070F, 0x070F, 0x0000 }, /* R4370 - Write Sequencer 274 */ | |
1246 | [4371] = { 0x010F, 0x010F, 0x0000 }, /* R4371 - Write Sequencer 275 */ | |
1247 | [4372] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4372 - Write Sequencer 276 */ | |
1248 | [4373] = { 0x00FF, 0x00FF, 0x0000 }, /* R4373 - Write Sequencer 277 */ | |
1249 | [4374] = { 0x070F, 0x070F, 0x0000 }, /* R4374 - Write Sequencer 278 */ | |
1250 | [4375] = { 0x010F, 0x010F, 0x0000 }, /* R4375 - Write Sequencer 279 */ | |
1251 | [4376] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4376 - Write Sequencer 280 */ | |
1252 | [4377] = { 0x00FF, 0x00FF, 0x0000 }, /* R4377 - Write Sequencer 281 */ | |
1253 | [4378] = { 0x070F, 0x070F, 0x0000 }, /* R4378 - Write Sequencer 282 */ | |
1254 | [4379] = { 0x010F, 0x010F, 0x0000 }, /* R4379 - Write Sequencer 283 */ | |
1255 | [4380] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4380 - Write Sequencer 284 */ | |
1256 | [4381] = { 0x00FF, 0x00FF, 0x0000 }, /* R4381 - Write Sequencer 285 */ | |
1257 | [4382] = { 0x070F, 0x070F, 0x0000 }, /* R4382 - Write Sequencer 286 */ | |
1258 | [4383] = { 0x010F, 0x010F, 0x0000 }, /* R4383 - Write Sequencer 287 */ | |
1259 | [4384] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4384 - Write Sequencer 288 */ | |
1260 | [4385] = { 0x00FF, 0x00FF, 0x0000 }, /* R4385 - Write Sequencer 289 */ | |
1261 | [4386] = { 0x070F, 0x070F, 0x0000 }, /* R4386 - Write Sequencer 290 */ | |
1262 | [4387] = { 0x010F, 0x010F, 0x0000 }, /* R4387 - Write Sequencer 291 */ | |
1263 | [4388] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4388 - Write Sequencer 292 */ | |
1264 | [4389] = { 0x00FF, 0x00FF, 0x0000 }, /* R4389 - Write Sequencer 293 */ | |
1265 | [4390] = { 0x070F, 0x070F, 0x0000 }, /* R4390 - Write Sequencer 294 */ | |
1266 | [4391] = { 0x010F, 0x010F, 0x0000 }, /* R4391 - Write Sequencer 295 */ | |
1267 | [4392] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4392 - Write Sequencer 296 */ | |
1268 | [4393] = { 0x00FF, 0x00FF, 0x0000 }, /* R4393 - Write Sequencer 297 */ | |
1269 | [4394] = { 0x070F, 0x070F, 0x0000 }, /* R4394 - Write Sequencer 298 */ | |
1270 | [4395] = { 0x010F, 0x010F, 0x0000 }, /* R4395 - Write Sequencer 299 */ | |
1271 | [4396] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4396 - Write Sequencer 300 */ | |
1272 | [4397] = { 0x00FF, 0x00FF, 0x0000 }, /* R4397 - Write Sequencer 301 */ | |
1273 | [4398] = { 0x070F, 0x070F, 0x0000 }, /* R4398 - Write Sequencer 302 */ | |
1274 | [4399] = { 0x010F, 0x010F, 0x0000 }, /* R4399 - Write Sequencer 303 */ | |
1275 | [4400] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4400 - Write Sequencer 304 */ | |
1276 | [4401] = { 0x00FF, 0x00FF, 0x0000 }, /* R4401 - Write Sequencer 305 */ | |
1277 | [4402] = { 0x070F, 0x070F, 0x0000 }, /* R4402 - Write Sequencer 306 */ | |
1278 | [4403] = { 0x010F, 0x010F, 0x0000 }, /* R4403 - Write Sequencer 307 */ | |
1279 | [4404] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4404 - Write Sequencer 308 */ | |
1280 | [4405] = { 0x00FF, 0x00FF, 0x0000 }, /* R4405 - Write Sequencer 309 */ | |
1281 | [4406] = { 0x070F, 0x070F, 0x0000 }, /* R4406 - Write Sequencer 310 */ | |
1282 | [4407] = { 0x010F, 0x010F, 0x0000 }, /* R4407 - Write Sequencer 311 */ | |
1283 | [4408] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4408 - Write Sequencer 312 */ | |
1284 | [4409] = { 0x00FF, 0x00FF, 0x0000 }, /* R4409 - Write Sequencer 313 */ | |
1285 | [4410] = { 0x070F, 0x070F, 0x0000 }, /* R4410 - Write Sequencer 314 */ | |
1286 | [4411] = { 0x010F, 0x010F, 0x0000 }, /* R4411 - Write Sequencer 315 */ | |
1287 | [4412] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4412 - Write Sequencer 316 */ | |
1288 | [4413] = { 0x00FF, 0x00FF, 0x0000 }, /* R4413 - Write Sequencer 317 */ | |
1289 | [4414] = { 0x070F, 0x070F, 0x0000 }, /* R4414 - Write Sequencer 318 */ | |
1290 | [4415] = { 0x010F, 0x010F, 0x0000 }, /* R4415 - Write Sequencer 319 */ | |
1291 | [4416] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4416 - Write Sequencer 320 */ | |
1292 | [4417] = { 0x00FF, 0x00FF, 0x0000 }, /* R4417 - Write Sequencer 321 */ | |
1293 | [4418] = { 0x070F, 0x070F, 0x0000 }, /* R4418 - Write Sequencer 322 */ | |
1294 | [4419] = { 0x010F, 0x010F, 0x0000 }, /* R4419 - Write Sequencer 323 */ | |
1295 | [4420] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4420 - Write Sequencer 324 */ | |
1296 | [4421] = { 0x00FF, 0x00FF, 0x0000 }, /* R4421 - Write Sequencer 325 */ | |
1297 | [4422] = { 0x070F, 0x070F, 0x0000 }, /* R4422 - Write Sequencer 326 */ | |
1298 | [4423] = { 0x010F, 0x010F, 0x0000 }, /* R4423 - Write Sequencer 327 */ | |
1299 | [4424] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4424 - Write Sequencer 328 */ | |
1300 | [4425] = { 0x00FF, 0x00FF, 0x0000 }, /* R4425 - Write Sequencer 329 */ | |
1301 | [4426] = { 0x070F, 0x070F, 0x0000 }, /* R4426 - Write Sequencer 330 */ | |
1302 | [4427] = { 0x010F, 0x010F, 0x0000 }, /* R4427 - Write Sequencer 331 */ | |
1303 | [4428] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4428 - Write Sequencer 332 */ | |
1304 | [4429] = { 0x00FF, 0x00FF, 0x0000 }, /* R4429 - Write Sequencer 333 */ | |
1305 | [4430] = { 0x070F, 0x070F, 0x0000 }, /* R4430 - Write Sequencer 334 */ | |
1306 | [4431] = { 0x010F, 0x010F, 0x0000 }, /* R4431 - Write Sequencer 335 */ | |
1307 | [4432] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4432 - Write Sequencer 336 */ | |
1308 | [4433] = { 0x00FF, 0x00FF, 0x0000 }, /* R4433 - Write Sequencer 337 */ | |
1309 | [4434] = { 0x070F, 0x070F, 0x0000 }, /* R4434 - Write Sequencer 338 */ | |
1310 | [4435] = { 0x010F, 0x010F, 0x0000 }, /* R4435 - Write Sequencer 339 */ | |
1311 | [4436] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4436 - Write Sequencer 340 */ | |
1312 | [4437] = { 0x00FF, 0x00FF, 0x0000 }, /* R4437 - Write Sequencer 341 */ | |
1313 | [4438] = { 0x070F, 0x070F, 0x0000 }, /* R4438 - Write Sequencer 342 */ | |
1314 | [4439] = { 0x010F, 0x010F, 0x0000 }, /* R4439 - Write Sequencer 343 */ | |
1315 | [4440] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4440 - Write Sequencer 344 */ | |
1316 | [4441] = { 0x00FF, 0x00FF, 0x0000 }, /* R4441 - Write Sequencer 345 */ | |
1317 | [4442] = { 0x070F, 0x070F, 0x0000 }, /* R4442 - Write Sequencer 346 */ | |
1318 | [4443] = { 0x010F, 0x010F, 0x0000 }, /* R4443 - Write Sequencer 347 */ | |
1319 | [4444] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4444 - Write Sequencer 348 */ | |
1320 | [4445] = { 0x00FF, 0x00FF, 0x0000 }, /* R4445 - Write Sequencer 349 */ | |
1321 | [4446] = { 0x070F, 0x070F, 0x0000 }, /* R4446 - Write Sequencer 350 */ | |
1322 | [4447] = { 0x010F, 0x010F, 0x0000 }, /* R4447 - Write Sequencer 351 */ | |
1323 | [4448] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4448 - Write Sequencer 352 */ | |
1324 | [4449] = { 0x00FF, 0x00FF, 0x0000 }, /* R4449 - Write Sequencer 353 */ | |
1325 | [4450] = { 0x070F, 0x070F, 0x0000 }, /* R4450 - Write Sequencer 354 */ | |
1326 | [4451] = { 0x010F, 0x010F, 0x0000 }, /* R4451 - Write Sequencer 355 */ | |
1327 | [4452] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4452 - Write Sequencer 356 */ | |
1328 | [4453] = { 0x00FF, 0x00FF, 0x0000 }, /* R4453 - Write Sequencer 357 */ | |
1329 | [4454] = { 0x070F, 0x070F, 0x0000 }, /* R4454 - Write Sequencer 358 */ | |
1330 | [4455] = { 0x010F, 0x010F, 0x0000 }, /* R4455 - Write Sequencer 359 */ | |
1331 | [4456] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4456 - Write Sequencer 360 */ | |
1332 | [4457] = { 0x00FF, 0x00FF, 0x0000 }, /* R4457 - Write Sequencer 361 */ | |
1333 | [4458] = { 0x070F, 0x070F, 0x0000 }, /* R4458 - Write Sequencer 362 */ | |
1334 | [4459] = { 0x010F, 0x010F, 0x0000 }, /* R4459 - Write Sequencer 363 */ | |
1335 | [4460] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4460 - Write Sequencer 364 */ | |
1336 | [4461] = { 0x00FF, 0x00FF, 0x0000 }, /* R4461 - Write Sequencer 365 */ | |
1337 | [4462] = { 0x070F, 0x070F, 0x0000 }, /* R4462 - Write Sequencer 366 */ | |
1338 | [4463] = { 0x010F, 0x010F, 0x0000 }, /* R4463 - Write Sequencer 367 */ | |
1339 | [4464] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4464 - Write Sequencer 368 */ | |
1340 | [4465] = { 0x00FF, 0x00FF, 0x0000 }, /* R4465 - Write Sequencer 369 */ | |
1341 | [4466] = { 0x070F, 0x070F, 0x0000 }, /* R4466 - Write Sequencer 370 */ | |
1342 | [4467] = { 0x010F, 0x010F, 0x0000 }, /* R4467 - Write Sequencer 371 */ | |
1343 | [4468] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4468 - Write Sequencer 372 */ | |
1344 | [4469] = { 0x00FF, 0x00FF, 0x0000 }, /* R4469 - Write Sequencer 373 */ | |
1345 | [4470] = { 0x070F, 0x070F, 0x0000 }, /* R4470 - Write Sequencer 374 */ | |
1346 | [4471] = { 0x010F, 0x010F, 0x0000 }, /* R4471 - Write Sequencer 375 */ | |
1347 | [4472] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4472 - Write Sequencer 376 */ | |
1348 | [4473] = { 0x00FF, 0x00FF, 0x0000 }, /* R4473 - Write Sequencer 377 */ | |
1349 | [4474] = { 0x070F, 0x070F, 0x0000 }, /* R4474 - Write Sequencer 378 */ | |
1350 | [4475] = { 0x010F, 0x010F, 0x0000 }, /* R4475 - Write Sequencer 379 */ | |
1351 | [4476] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4476 - Write Sequencer 380 */ | |
1352 | [4477] = { 0x00FF, 0x00FF, 0x0000 }, /* R4477 - Write Sequencer 381 */ | |
1353 | [4478] = { 0x070F, 0x070F, 0x0000 }, /* R4478 - Write Sequencer 382 */ | |
1354 | [4479] = { 0x010F, 0x010F, 0x0000 }, /* R4479 - Write Sequencer 383 */ | |
1355 | [4480] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4480 - Write Sequencer 384 */ | |
1356 | [4481] = { 0x00FF, 0x00FF, 0x0000 }, /* R4481 - Write Sequencer 385 */ | |
1357 | [4482] = { 0x070F, 0x070F, 0x0000 }, /* R4482 - Write Sequencer 386 */ | |
1358 | [4483] = { 0x010F, 0x010F, 0x0000 }, /* R4483 - Write Sequencer 387 */ | |
1359 | [4484] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4484 - Write Sequencer 388 */ | |
1360 | [4485] = { 0x00FF, 0x00FF, 0x0000 }, /* R4485 - Write Sequencer 389 */ | |
1361 | [4486] = { 0x070F, 0x070F, 0x0000 }, /* R4486 - Write Sequencer 390 */ | |
1362 | [4487] = { 0x010F, 0x010F, 0x0000 }, /* R4487 - Write Sequencer 391 */ | |
1363 | [4488] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4488 - Write Sequencer 392 */ | |
1364 | [4489] = { 0x00FF, 0x00FF, 0x0000 }, /* R4489 - Write Sequencer 393 */ | |
1365 | [4490] = { 0x070F, 0x070F, 0x0000 }, /* R4490 - Write Sequencer 394 */ | |
1366 | [4491] = { 0x010F, 0x010F, 0x0000 }, /* R4491 - Write Sequencer 395 */ | |
1367 | [4492] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4492 - Write Sequencer 396 */ | |
1368 | [4493] = { 0x00FF, 0x00FF, 0x0000 }, /* R4493 - Write Sequencer 397 */ | |
1369 | [4494] = { 0x070F, 0x070F, 0x0000 }, /* R4494 - Write Sequencer 398 */ | |
1370 | [4495] = { 0x010F, 0x010F, 0x0000 }, /* R4495 - Write Sequencer 399 */ | |
1371 | [4496] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4496 - Write Sequencer 400 */ | |
1372 | [4497] = { 0x00FF, 0x00FF, 0x0000 }, /* R4497 - Write Sequencer 401 */ | |
1373 | [4498] = { 0x070F, 0x070F, 0x0000 }, /* R4498 - Write Sequencer 402 */ | |
1374 | [4499] = { 0x010F, 0x010F, 0x0000 }, /* R4499 - Write Sequencer 403 */ | |
1375 | [4500] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4500 - Write Sequencer 404 */ | |
1376 | [4501] = { 0x00FF, 0x00FF, 0x0000 }, /* R4501 - Write Sequencer 405 */ | |
1377 | [4502] = { 0x070F, 0x070F, 0x0000 }, /* R4502 - Write Sequencer 406 */ | |
1378 | [4503] = { 0x010F, 0x010F, 0x0000 }, /* R4503 - Write Sequencer 407 */ | |
1379 | [4504] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4504 - Write Sequencer 408 */ | |
1380 | [4505] = { 0x00FF, 0x00FF, 0x0000 }, /* R4505 - Write Sequencer 409 */ | |
1381 | [4506] = { 0x070F, 0x070F, 0x0000 }, /* R4506 - Write Sequencer 410 */ | |
1382 | [4507] = { 0x010F, 0x010F, 0x0000 }, /* R4507 - Write Sequencer 411 */ | |
1383 | [4508] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4508 - Write Sequencer 412 */ | |
1384 | [4509] = { 0x00FF, 0x00FF, 0x0000 }, /* R4509 - Write Sequencer 413 */ | |
1385 | [4510] = { 0x070F, 0x070F, 0x0000 }, /* R4510 - Write Sequencer 414 */ | |
1386 | [4511] = { 0x010F, 0x010F, 0x0000 }, /* R4511 - Write Sequencer 415 */ | |
1387 | [4512] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4512 - Write Sequencer 416 */ | |
1388 | [4513] = { 0x00FF, 0x00FF, 0x0000 }, /* R4513 - Write Sequencer 417 */ | |
1389 | [4514] = { 0x070F, 0x070F, 0x0000 }, /* R4514 - Write Sequencer 418 */ | |
1390 | [4515] = { 0x010F, 0x010F, 0x0000 }, /* R4515 - Write Sequencer 419 */ | |
1391 | [4516] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4516 - Write Sequencer 420 */ | |
1392 | [4517] = { 0x00FF, 0x00FF, 0x0000 }, /* R4517 - Write Sequencer 421 */ | |
1393 | [4518] = { 0x070F, 0x070F, 0x0000 }, /* R4518 - Write Sequencer 422 */ | |
1394 | [4519] = { 0x010F, 0x010F, 0x0000 }, /* R4519 - Write Sequencer 423 */ | |
1395 | [4520] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4520 - Write Sequencer 424 */ | |
1396 | [4521] = { 0x00FF, 0x00FF, 0x0000 }, /* R4521 - Write Sequencer 425 */ | |
1397 | [4522] = { 0x070F, 0x070F, 0x0000 }, /* R4522 - Write Sequencer 426 */ | |
1398 | [4523] = { 0x010F, 0x010F, 0x0000 }, /* R4523 - Write Sequencer 427 */ | |
1399 | [4524] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4524 - Write Sequencer 428 */ | |
1400 | [4525] = { 0x00FF, 0x00FF, 0x0000 }, /* R4525 - Write Sequencer 429 */ | |
1401 | [4526] = { 0x070F, 0x070F, 0x0000 }, /* R4526 - Write Sequencer 430 */ | |
1402 | [4527] = { 0x010F, 0x010F, 0x0000 }, /* R4527 - Write Sequencer 431 */ | |
1403 | [4528] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4528 - Write Sequencer 432 */ | |
1404 | [4529] = { 0x00FF, 0x00FF, 0x0000 }, /* R4529 - Write Sequencer 433 */ | |
1405 | [4530] = { 0x070F, 0x070F, 0x0000 }, /* R4530 - Write Sequencer 434 */ | |
1406 | [4531] = { 0x010F, 0x010F, 0x0000 }, /* R4531 - Write Sequencer 435 */ | |
1407 | [4532] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4532 - Write Sequencer 436 */ | |
1408 | [4533] = { 0x00FF, 0x00FF, 0x0000 }, /* R4533 - Write Sequencer 437 */ | |
1409 | [4534] = { 0x070F, 0x070F, 0x0000 }, /* R4534 - Write Sequencer 438 */ | |
1410 | [4535] = { 0x010F, 0x010F, 0x0000 }, /* R4535 - Write Sequencer 439 */ | |
1411 | [4536] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4536 - Write Sequencer 440 */ | |
1412 | [4537] = { 0x00FF, 0x00FF, 0x0000 }, /* R4537 - Write Sequencer 441 */ | |
1413 | [4538] = { 0x070F, 0x070F, 0x0000 }, /* R4538 - Write Sequencer 442 */ | |
1414 | [4539] = { 0x010F, 0x010F, 0x0000 }, /* R4539 - Write Sequencer 443 */ | |
1415 | [4540] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4540 - Write Sequencer 444 */ | |
1416 | [4541] = { 0x00FF, 0x00FF, 0x0000 }, /* R4541 - Write Sequencer 445 */ | |
1417 | [4542] = { 0x070F, 0x070F, 0x0000 }, /* R4542 - Write Sequencer 446 */ | |
1418 | [4543] = { 0x010F, 0x010F, 0x0000 }, /* R4543 - Write Sequencer 447 */ | |
1419 | [4544] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4544 - Write Sequencer 448 */ | |
1420 | [4545] = { 0x00FF, 0x00FF, 0x0000 }, /* R4545 - Write Sequencer 449 */ | |
1421 | [4546] = { 0x070F, 0x070F, 0x0000 }, /* R4546 - Write Sequencer 450 */ | |
1422 | [4547] = { 0x010F, 0x010F, 0x0000 }, /* R4547 - Write Sequencer 451 */ | |
1423 | [4548] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4548 - Write Sequencer 452 */ | |
1424 | [4549] = { 0x00FF, 0x00FF, 0x0000 }, /* R4549 - Write Sequencer 453 */ | |
1425 | [4550] = { 0x070F, 0x070F, 0x0000 }, /* R4550 - Write Sequencer 454 */ | |
1426 | [4551] = { 0x010F, 0x010F, 0x0000 }, /* R4551 - Write Sequencer 455 */ | |
1427 | [4552] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4552 - Write Sequencer 456 */ | |
1428 | [4553] = { 0x00FF, 0x00FF, 0x0000 }, /* R4553 - Write Sequencer 457 */ | |
1429 | [4554] = { 0x070F, 0x070F, 0x0000 }, /* R4554 - Write Sequencer 458 */ | |
1430 | [4555] = { 0x010F, 0x010F, 0x0000 }, /* R4555 - Write Sequencer 459 */ | |
1431 | [4556] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4556 - Write Sequencer 460 */ | |
1432 | [4557] = { 0x00FF, 0x00FF, 0x0000 }, /* R4557 - Write Sequencer 461 */ | |
1433 | [4558] = { 0x070F, 0x070F, 0x0000 }, /* R4558 - Write Sequencer 462 */ | |
1434 | [4559] = { 0x010F, 0x010F, 0x0000 }, /* R4559 - Write Sequencer 463 */ | |
1435 | [4560] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4560 - Write Sequencer 464 */ | |
1436 | [4561] = { 0x00FF, 0x00FF, 0x0000 }, /* R4561 - Write Sequencer 465 */ | |
1437 | [4562] = { 0x070F, 0x070F, 0x0000 }, /* R4562 - Write Sequencer 466 */ | |
1438 | [4563] = { 0x010F, 0x010F, 0x0000 }, /* R4563 - Write Sequencer 467 */ | |
1439 | [4564] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4564 - Write Sequencer 468 */ | |
1440 | [4565] = { 0x00FF, 0x00FF, 0x0000 }, /* R4565 - Write Sequencer 469 */ | |
1441 | [4566] = { 0x070F, 0x070F, 0x0000 }, /* R4566 - Write Sequencer 470 */ | |
1442 | [4567] = { 0x010F, 0x010F, 0x0000 }, /* R4567 - Write Sequencer 471 */ | |
1443 | [4568] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4568 - Write Sequencer 472 */ | |
1444 | [4569] = { 0x00FF, 0x00FF, 0x0000 }, /* R4569 - Write Sequencer 473 */ | |
1445 | [4570] = { 0x070F, 0x070F, 0x0000 }, /* R4570 - Write Sequencer 474 */ | |
1446 | [4571] = { 0x010F, 0x010F, 0x0000 }, /* R4571 - Write Sequencer 475 */ | |
1447 | [4572] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4572 - Write Sequencer 476 */ | |
1448 | [4573] = { 0x00FF, 0x00FF, 0x0000 }, /* R4573 - Write Sequencer 477 */ | |
1449 | [4574] = { 0x070F, 0x070F, 0x0000 }, /* R4574 - Write Sequencer 478 */ | |
1450 | [4575] = { 0x010F, 0x010F, 0x0000 }, /* R4575 - Write Sequencer 479 */ | |
1451 | [4576] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4576 - Write Sequencer 480 */ | |
1452 | [4577] = { 0x00FF, 0x00FF, 0x0000 }, /* R4577 - Write Sequencer 481 */ | |
1453 | [4578] = { 0x070F, 0x070F, 0x0000 }, /* R4578 - Write Sequencer 482 */ | |
1454 | [4579] = { 0x010F, 0x010F, 0x0000 }, /* R4579 - Write Sequencer 483 */ | |
1455 | [4580] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4580 - Write Sequencer 484 */ | |
1456 | [4581] = { 0x00FF, 0x00FF, 0x0000 }, /* R4581 - Write Sequencer 485 */ | |
1457 | [4582] = { 0x070F, 0x070F, 0x0000 }, /* R4582 - Write Sequencer 486 */ | |
1458 | [4583] = { 0x010F, 0x010F, 0x0000 }, /* R4583 - Write Sequencer 487 */ | |
1459 | [4584] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4584 - Write Sequencer 488 */ | |
1460 | [4585] = { 0x00FF, 0x00FF, 0x0000 }, /* R4585 - Write Sequencer 489 */ | |
1461 | [4586] = { 0x070F, 0x070F, 0x0000 }, /* R4586 - Write Sequencer 490 */ | |
1462 | [4587] = { 0x010F, 0x010F, 0x0000 }, /* R4587 - Write Sequencer 491 */ | |
1463 | [4588] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4588 - Write Sequencer 492 */ | |
1464 | [4589] = { 0x00FF, 0x00FF, 0x0000 }, /* R4589 - Write Sequencer 493 */ | |
1465 | [4590] = { 0x070F, 0x070F, 0x0000 }, /* R4590 - Write Sequencer 494 */ | |
1466 | [4591] = { 0x010F, 0x010F, 0x0000 }, /* R4591 - Write Sequencer 495 */ | |
1467 | [4592] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4592 - Write Sequencer 496 */ | |
1468 | [4593] = { 0x00FF, 0x00FF, 0x0000 }, /* R4593 - Write Sequencer 497 */ | |
1469 | [4594] = { 0x070F, 0x070F, 0x0000 }, /* R4594 - Write Sequencer 498 */ | |
1470 | [4595] = { 0x010F, 0x010F, 0x0000 }, /* R4595 - Write Sequencer 499 */ | |
1471 | [4596] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4596 - Write Sequencer 500 */ | |
1472 | [4597] = { 0x00FF, 0x00FF, 0x0000 }, /* R4597 - Write Sequencer 501 */ | |
1473 | [4598] = { 0x070F, 0x070F, 0x0000 }, /* R4598 - Write Sequencer 502 */ | |
1474 | [4599] = { 0x010F, 0x010F, 0x0000 }, /* R4599 - Write Sequencer 503 */ | |
1475 | [4600] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4600 - Write Sequencer 504 */ | |
1476 | [4601] = { 0x00FF, 0x00FF, 0x0000 }, /* R4601 - Write Sequencer 505 */ | |
1477 | [4602] = { 0x070F, 0x070F, 0x0000 }, /* R4602 - Write Sequencer 506 */ | |
1478 | [4603] = { 0x010F, 0x010F, 0x0000 }, /* R4603 - Write Sequencer 507 */ | |
1479 | [4604] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4604 - Write Sequencer 508 */ | |
1480 | [4605] = { 0x00FF, 0x00FF, 0x0000 }, /* R4605 - Write Sequencer 509 */ | |
1481 | [4606] = { 0x070F, 0x070F, 0x0000 }, /* R4606 - Write Sequencer 510 */ | |
1482 | [4607] = { 0x010F, 0x010F, 0x0000 }, /* R4607 - Write Sequencer 511 */ | |
1483 | [8192] = { 0x03FF, 0x03FF, 0x0000 }, /* R8192 - DSP2 Instruction RAM 0 */ | |
1484 | [9216] = { 0x003F, 0x003F, 0x0000 }, /* R9216 - DSP2 Address RAM 2 */ | |
1485 | [9217] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R9217 - DSP2 Address RAM 1 */ | |
1486 | [9218] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R9218 - DSP2 Address RAM 0 */ | |
1487 | [12288] = { 0x00FF, 0x00FF, 0x0000 }, /* R12288 - DSP2 Data1 RAM 1 */ | |
1488 | [12289] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R12289 - DSP2 Data1 RAM 0 */ | |
1489 | [13312] = { 0x00FF, 0x00FF, 0x0000 }, /* R13312 - DSP2 Data2 RAM 1 */ | |
1490 | [13313] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R13313 - DSP2 Data2 RAM 0 */ | |
1491 | [14336] = { 0x00FF, 0x00FF, 0x0000 }, /* R14336 - DSP2 Data3 RAM 1 */ | |
1492 | [14337] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R14337 - DSP2 Data3 RAM 0 */ | |
1493 | [15360] = { 0x07FF, 0x07FF, 0x0000 }, /* R15360 - DSP2 Coeff RAM 0 */ | |
1494 | [16384] = { 0x00FF, 0x00FF, 0x0000 }, /* R16384 - RETUNEADC_SHARED_COEFF_1 */ | |
1495 | [16385] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16385 - RETUNEADC_SHARED_COEFF_0 */ | |
1496 | [16386] = { 0x00FF, 0x00FF, 0x0000 }, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */ | |
1497 | [16387] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */ | |
1498 | [16388] = { 0x00FF, 0x00FF, 0x0000 }, /* R16388 - SOUNDSTAGE_ENABLES_1 */ | |
1499 | [16389] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16389 - SOUNDSTAGE_ENABLES_0 */ | |
1500 | [16896] = { 0x00FF, 0x00FF, 0x0000 }, /* R16896 - HDBASS_AI_1 */ | |
1501 | [16897] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16897 - HDBASS_AI_0 */ | |
1502 | [16898] = { 0x00FF, 0x00FF, 0x0000 }, /* R16898 - HDBASS_AR_1 */ | |
1503 | [16899] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16899 - HDBASS_AR_0 */ | |
1504 | [16900] = { 0x00FF, 0x00FF, 0x0000 }, /* R16900 - HDBASS_B_1 */ | |
1505 | [16901] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16901 - HDBASS_B_0 */ | |
1506 | [16902] = { 0x00FF, 0x00FF, 0x0000 }, /* R16902 - HDBASS_K_1 */ | |
1507 | [16903] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16903 - HDBASS_K_0 */ | |
1508 | [16904] = { 0x00FF, 0x00FF, 0x0000 }, /* R16904 - HDBASS_N1_1 */ | |
1509 | [16905] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16905 - HDBASS_N1_0 */ | |
1510 | [16906] = { 0x00FF, 0x00FF, 0x0000 }, /* R16906 - HDBASS_N2_1 */ | |
1511 | [16907] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16907 - HDBASS_N2_0 */ | |
1512 | [16908] = { 0x00FF, 0x00FF, 0x0000 }, /* R16908 - HDBASS_N3_1 */ | |
1513 | [16909] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16909 - HDBASS_N3_0 */ | |
1514 | [16910] = { 0x00FF, 0x00FF, 0x0000 }, /* R16910 - HDBASS_N4_1 */ | |
1515 | [16911] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16911 - HDBASS_N4_0 */ | |
1516 | [16912] = { 0x00FF, 0x00FF, 0x0000 }, /* R16912 - HDBASS_N5_1 */ | |
1517 | [16913] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16913 - HDBASS_N5_0 */ | |
1518 | [16914] = { 0x00FF, 0x00FF, 0x0000 }, /* R16914 - HDBASS_X1_1 */ | |
1519 | [16915] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16915 - HDBASS_X1_0 */ | |
1520 | [16916] = { 0x00FF, 0x00FF, 0x0000 }, /* R16916 - HDBASS_X2_1 */ | |
1521 | [16917] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16917 - HDBASS_X2_0 */ | |
1522 | [16918] = { 0x00FF, 0x00FF, 0x0000 }, /* R16918 - HDBASS_X3_1 */ | |
1523 | [16919] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16919 - HDBASS_X3_0 */ | |
1524 | [16920] = { 0x00FF, 0x00FF, 0x0000 }, /* R16920 - HDBASS_ATK_1 */ | |
1525 | [16921] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16921 - HDBASS_ATK_0 */ | |
1526 | [16922] = { 0x00FF, 0x00FF, 0x0000 }, /* R16922 - HDBASS_DCY_1 */ | |
1527 | [16923] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16923 - HDBASS_DCY_0 */ | |
1528 | [16924] = { 0x00FF, 0x00FF, 0x0000 }, /* R16924 - HDBASS_PG_1 */ | |
1529 | [16925] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16925 - HDBASS_PG_0 */ | |
1530 | [17408] = { 0x00FF, 0x00FF, 0x0000 }, /* R17408 - HPF_C_1 */ | |
1531 | [17409] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17409 - HPF_C_0 */ | |
1532 | [17920] = { 0x00FF, 0x00FF, 0x0000 }, /* R17920 - ADCL_RETUNE_C1_1 */ | |
1533 | [17921] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17921 - ADCL_RETUNE_C1_0 */ | |
1534 | [17922] = { 0x00FF, 0x00FF, 0x0000 }, /* R17922 - ADCL_RETUNE_C2_1 */ | |
1535 | [17923] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17923 - ADCL_RETUNE_C2_0 */ | |
1536 | [17924] = { 0x00FF, 0x00FF, 0x0000 }, /* R17924 - ADCL_RETUNE_C3_1 */ | |
1537 | [17925] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17925 - ADCL_RETUNE_C3_0 */ | |
1538 | [17926] = { 0x00FF, 0x00FF, 0x0000 }, /* R17926 - ADCL_RETUNE_C4_1 */ | |
1539 | [17927] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17927 - ADCL_RETUNE_C4_0 */ | |
1540 | [17928] = { 0x00FF, 0x00FF, 0x0000 }, /* R17928 - ADCL_RETUNE_C5_1 */ | |
1541 | [17929] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17929 - ADCL_RETUNE_C5_0 */ | |
1542 | [17930] = { 0x00FF, 0x00FF, 0x0000 }, /* R17930 - ADCL_RETUNE_C6_1 */ | |
1543 | [17931] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17931 - ADCL_RETUNE_C6_0 */ | |
1544 | [17932] = { 0x00FF, 0x00FF, 0x0000 }, /* R17932 - ADCL_RETUNE_C7_1 */ | |
1545 | [17933] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17933 - ADCL_RETUNE_C7_0 */ | |
1546 | [17934] = { 0x00FF, 0x00FF, 0x0000 }, /* R17934 - ADCL_RETUNE_C8_1 */ | |
1547 | [17935] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17935 - ADCL_RETUNE_C8_0 */ | |
1548 | [17936] = { 0x00FF, 0x00FF, 0x0000 }, /* R17936 - ADCL_RETUNE_C9_1 */ | |
1549 | [17937] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17937 - ADCL_RETUNE_C9_0 */ | |
1550 | [17938] = { 0x00FF, 0x00FF, 0x0000 }, /* R17938 - ADCL_RETUNE_C10_1 */ | |
1551 | [17939] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17939 - ADCL_RETUNE_C10_0 */ | |
1552 | [17940] = { 0x00FF, 0x00FF, 0x0000 }, /* R17940 - ADCL_RETUNE_C11_1 */ | |
1553 | [17941] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17941 - ADCL_RETUNE_C11_0 */ | |
1554 | [17942] = { 0x00FF, 0x00FF, 0x0000 }, /* R17942 - ADCL_RETUNE_C12_1 */ | |
1555 | [17943] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17943 - ADCL_RETUNE_C12_0 */ | |
1556 | [17944] = { 0x00FF, 0x00FF, 0x0000 }, /* R17944 - ADCL_RETUNE_C13_1 */ | |
1557 | [17945] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17945 - ADCL_RETUNE_C13_0 */ | |
1558 | [17946] = { 0x00FF, 0x00FF, 0x0000 }, /* R17946 - ADCL_RETUNE_C14_1 */ | |
1559 | [17947] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17947 - ADCL_RETUNE_C14_0 */ | |
1560 | [17948] = { 0x00FF, 0x00FF, 0x0000 }, /* R17948 - ADCL_RETUNE_C15_1 */ | |
1561 | [17949] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17949 - ADCL_RETUNE_C15_0 */ | |
1562 | [17950] = { 0x00FF, 0x00FF, 0x0000 }, /* R17950 - ADCL_RETUNE_C16_1 */ | |
1563 | [17951] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17951 - ADCL_RETUNE_C16_0 */ | |
1564 | [17952] = { 0x00FF, 0x00FF, 0x0000 }, /* R17952 - ADCL_RETUNE_C17_1 */ | |
1565 | [17953] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17953 - ADCL_RETUNE_C17_0 */ | |
1566 | [17954] = { 0x00FF, 0x00FF, 0x0000 }, /* R17954 - ADCL_RETUNE_C18_1 */ | |
1567 | [17955] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17955 - ADCL_RETUNE_C18_0 */ | |
1568 | [17956] = { 0x00FF, 0x00FF, 0x0000 }, /* R17956 - ADCL_RETUNE_C19_1 */ | |
1569 | [17957] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17957 - ADCL_RETUNE_C19_0 */ | |
1570 | [17958] = { 0x00FF, 0x00FF, 0x0000 }, /* R17958 - ADCL_RETUNE_C20_1 */ | |
1571 | [17959] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17959 - ADCL_RETUNE_C20_0 */ | |
1572 | [17960] = { 0x00FF, 0x00FF, 0x0000 }, /* R17960 - ADCL_RETUNE_C21_1 */ | |
1573 | [17961] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17961 - ADCL_RETUNE_C21_0 */ | |
1574 | [17962] = { 0x00FF, 0x00FF, 0x0000 }, /* R17962 - ADCL_RETUNE_C22_1 */ | |
1575 | [17963] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17963 - ADCL_RETUNE_C22_0 */ | |
1576 | [17964] = { 0x00FF, 0x00FF, 0x0000 }, /* R17964 - ADCL_RETUNE_C23_1 */ | |
1577 | [17965] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17965 - ADCL_RETUNE_C23_0 */ | |
1578 | [17966] = { 0x00FF, 0x00FF, 0x0000 }, /* R17966 - ADCL_RETUNE_C24_1 */ | |
1579 | [17967] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17967 - ADCL_RETUNE_C24_0 */ | |
1580 | [17968] = { 0x00FF, 0x00FF, 0x0000 }, /* R17968 - ADCL_RETUNE_C25_1 */ | |
1581 | [17969] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17969 - ADCL_RETUNE_C25_0 */ | |
1582 | [17970] = { 0x00FF, 0x00FF, 0x0000 }, /* R17970 - ADCL_RETUNE_C26_1 */ | |
1583 | [17971] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17971 - ADCL_RETUNE_C26_0 */ | |
1584 | [17972] = { 0x00FF, 0x00FF, 0x0000 }, /* R17972 - ADCL_RETUNE_C27_1 */ | |
1585 | [17973] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17973 - ADCL_RETUNE_C27_0 */ | |
1586 | [17974] = { 0x00FF, 0x00FF, 0x0000 }, /* R17974 - ADCL_RETUNE_C28_1 */ | |
1587 | [17975] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17975 - ADCL_RETUNE_C28_0 */ | |
1588 | [17976] = { 0x00FF, 0x00FF, 0x0000 }, /* R17976 - ADCL_RETUNE_C29_1 */ | |
1589 | [17977] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17977 - ADCL_RETUNE_C29_0 */ | |
1590 | [17978] = { 0x00FF, 0x00FF, 0x0000 }, /* R17978 - ADCL_RETUNE_C30_1 */ | |
1591 | [17979] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17979 - ADCL_RETUNE_C30_0 */ | |
1592 | [17980] = { 0x00FF, 0x00FF, 0x0000 }, /* R17980 - ADCL_RETUNE_C31_1 */ | |
1593 | [17981] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17981 - ADCL_RETUNE_C31_0 */ | |
1594 | [17982] = { 0x00FF, 0x00FF, 0x0000 }, /* R17982 - ADCL_RETUNE_C32_1 */ | |
1595 | [17983] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17983 - ADCL_RETUNE_C32_0 */ | |
1596 | [18432] = { 0x00FF, 0x00FF, 0x0000 }, /* R18432 - RETUNEADC_PG2_1 */ | |
1597 | [18433] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18433 - RETUNEADC_PG2_0 */ | |
1598 | [18434] = { 0x00FF, 0x00FF, 0x0000 }, /* R18434 - RETUNEADC_PG_1 */ | |
1599 | [18435] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18435 - RETUNEADC_PG_0 */ | |
1600 | [18944] = { 0x00FF, 0x00FF, 0x0000 }, /* R18944 - ADCR_RETUNE_C1_1 */ | |
1601 | [18945] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18945 - ADCR_RETUNE_C1_0 */ | |
1602 | [18946] = { 0x00FF, 0x00FF, 0x0000 }, /* R18946 - ADCR_RETUNE_C2_1 */ | |
1603 | [18947] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18947 - ADCR_RETUNE_C2_0 */ | |
1604 | [18948] = { 0x00FF, 0x00FF, 0x0000 }, /* R18948 - ADCR_RETUNE_C3_1 */ | |
1605 | [18949] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18949 - ADCR_RETUNE_C3_0 */ | |
1606 | [18950] = { 0x00FF, 0x00FF, 0x0000 }, /* R18950 - ADCR_RETUNE_C4_1 */ | |
1607 | [18951] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18951 - ADCR_RETUNE_C4_0 */ | |
1608 | [18952] = { 0x00FF, 0x00FF, 0x0000 }, /* R18952 - ADCR_RETUNE_C5_1 */ | |
1609 | [18953] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18953 - ADCR_RETUNE_C5_0 */ | |
1610 | [18954] = { 0x00FF, 0x00FF, 0x0000 }, /* R18954 - ADCR_RETUNE_C6_1 */ | |
1611 | [18955] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18955 - ADCR_RETUNE_C6_0 */ | |
1612 | [18956] = { 0x00FF, 0x00FF, 0x0000 }, /* R18956 - ADCR_RETUNE_C7_1 */ | |
1613 | [18957] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18957 - ADCR_RETUNE_C7_0 */ | |
1614 | [18958] = { 0x00FF, 0x00FF, 0x0000 }, /* R18958 - ADCR_RETUNE_C8_1 */ | |
1615 | [18959] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18959 - ADCR_RETUNE_C8_0 */ | |
1616 | [18960] = { 0x00FF, 0x00FF, 0x0000 }, /* R18960 - ADCR_RETUNE_C9_1 */ | |
1617 | [18961] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18961 - ADCR_RETUNE_C9_0 */ | |
1618 | [18962] = { 0x00FF, 0x00FF, 0x0000 }, /* R18962 - ADCR_RETUNE_C10_1 */ | |
1619 | [18963] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18963 - ADCR_RETUNE_C10_0 */ | |
1620 | [18964] = { 0x00FF, 0x00FF, 0x0000 }, /* R18964 - ADCR_RETUNE_C11_1 */ | |
1621 | [18965] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18965 - ADCR_RETUNE_C11_0 */ | |
1622 | [18966] = { 0x00FF, 0x00FF, 0x0000 }, /* R18966 - ADCR_RETUNE_C12_1 */ | |
1623 | [18967] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18967 - ADCR_RETUNE_C12_0 */ | |
1624 | [18968] = { 0x00FF, 0x00FF, 0x0000 }, /* R18968 - ADCR_RETUNE_C13_1 */ | |
1625 | [18969] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18969 - ADCR_RETUNE_C13_0 */ | |
1626 | [18970] = { 0x00FF, 0x00FF, 0x0000 }, /* R18970 - ADCR_RETUNE_C14_1 */ | |
1627 | [18971] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18971 - ADCR_RETUNE_C14_0 */ | |
1628 | [18972] = { 0x00FF, 0x00FF, 0x0000 }, /* R18972 - ADCR_RETUNE_C15_1 */ | |
1629 | [18973] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18973 - ADCR_RETUNE_C15_0 */ | |
1630 | [18974] = { 0x00FF, 0x00FF, 0x0000 }, /* R18974 - ADCR_RETUNE_C16_1 */ | |
1631 | [18975] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18975 - ADCR_RETUNE_C16_0 */ | |
1632 | [18976] = { 0x00FF, 0x00FF, 0x0000 }, /* R18976 - ADCR_RETUNE_C17_1 */ | |
1633 | [18977] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18977 - ADCR_RETUNE_C17_0 */ | |
1634 | [18978] = { 0x00FF, 0x00FF, 0x0000 }, /* R18978 - ADCR_RETUNE_C18_1 */ | |
1635 | [18979] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18979 - ADCR_RETUNE_C18_0 */ | |
1636 | [18980] = { 0x00FF, 0x00FF, 0x0000 }, /* R18980 - ADCR_RETUNE_C19_1 */ | |
1637 | [18981] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18981 - ADCR_RETUNE_C19_0 */ | |
1638 | [18982] = { 0x00FF, 0x00FF, 0x0000 }, /* R18982 - ADCR_RETUNE_C20_1 */ | |
1639 | [18983] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18983 - ADCR_RETUNE_C20_0 */ | |
1640 | [18984] = { 0x00FF, 0x00FF, 0x0000 }, /* R18984 - ADCR_RETUNE_C21_1 */ | |
1641 | [18985] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18985 - ADCR_RETUNE_C21_0 */ | |
1642 | [18986] = { 0x00FF, 0x00FF, 0x0000 }, /* R18986 - ADCR_RETUNE_C22_1 */ | |
1643 | [18987] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18987 - ADCR_RETUNE_C22_0 */ | |
1644 | [18988] = { 0x00FF, 0x00FF, 0x0000 }, /* R18988 - ADCR_RETUNE_C23_1 */ | |
1645 | [18989] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18989 - ADCR_RETUNE_C23_0 */ | |
1646 | [18990] = { 0x00FF, 0x00FF, 0x0000 }, /* R18990 - ADCR_RETUNE_C24_1 */ | |
1647 | [18991] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18991 - ADCR_RETUNE_C24_0 */ | |
1648 | [18992] = { 0x00FF, 0x00FF, 0x0000 }, /* R18992 - ADCR_RETUNE_C25_1 */ | |
1649 | [18993] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18993 - ADCR_RETUNE_C25_0 */ | |
1650 | [18994] = { 0x00FF, 0x00FF, 0x0000 }, /* R18994 - ADCR_RETUNE_C26_1 */ | |
1651 | [18995] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18995 - ADCR_RETUNE_C26_0 */ | |
1652 | [18996] = { 0x00FF, 0x00FF, 0x0000 }, /* R18996 - ADCR_RETUNE_C27_1 */ | |
1653 | [18997] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18997 - ADCR_RETUNE_C27_0 */ | |
1654 | [18998] = { 0x00FF, 0x00FF, 0x0000 }, /* R18998 - ADCR_RETUNE_C28_1 */ | |
1655 | [18999] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18999 - ADCR_RETUNE_C28_0 */ | |
1656 | [19000] = { 0x00FF, 0x00FF, 0x0000 }, /* R19000 - ADCR_RETUNE_C29_1 */ | |
1657 | [19001] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19001 - ADCR_RETUNE_C29_0 */ | |
1658 | [19002] = { 0x00FF, 0x00FF, 0x0000 }, /* R19002 - ADCR_RETUNE_C30_1 */ | |
1659 | [19003] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19003 - ADCR_RETUNE_C30_0 */ | |
1660 | [19004] = { 0x00FF, 0x00FF, 0x0000 }, /* R19004 - ADCR_RETUNE_C31_1 */ | |
1661 | [19005] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19005 - ADCR_RETUNE_C31_0 */ | |
1662 | [19006] = { 0x00FF, 0x00FF, 0x0000 }, /* R19006 - ADCR_RETUNE_C32_1 */ | |
1663 | [19007] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19007 - ADCR_RETUNE_C32_0 */ | |
1664 | [19456] = { 0x00FF, 0x00FF, 0x0000 }, /* R19456 - DACL_RETUNE_C1_1 */ | |
1665 | [19457] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19457 - DACL_RETUNE_C1_0 */ | |
1666 | [19458] = { 0x00FF, 0x00FF, 0x0000 }, /* R19458 - DACL_RETUNE_C2_1 */ | |
1667 | [19459] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19459 - DACL_RETUNE_C2_0 */ | |
1668 | [19460] = { 0x00FF, 0x00FF, 0x0000 }, /* R19460 - DACL_RETUNE_C3_1 */ | |
1669 | [19461] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19461 - DACL_RETUNE_C3_0 */ | |
1670 | [19462] = { 0x00FF, 0x00FF, 0x0000 }, /* R19462 - DACL_RETUNE_C4_1 */ | |
1671 | [19463] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19463 - DACL_RETUNE_C4_0 */ | |
1672 | [19464] = { 0x00FF, 0x00FF, 0x0000 }, /* R19464 - DACL_RETUNE_C5_1 */ | |
1673 | [19465] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19465 - DACL_RETUNE_C5_0 */ | |
1674 | [19466] = { 0x00FF, 0x00FF, 0x0000 }, /* R19466 - DACL_RETUNE_C6_1 */ | |
1675 | [19467] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19467 - DACL_RETUNE_C6_0 */ | |
1676 | [19468] = { 0x00FF, 0x00FF, 0x0000 }, /* R19468 - DACL_RETUNE_C7_1 */ | |
1677 | [19469] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19469 - DACL_RETUNE_C7_0 */ | |
1678 | [19470] = { 0x00FF, 0x00FF, 0x0000 }, /* R19470 - DACL_RETUNE_C8_1 */ | |
1679 | [19471] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19471 - DACL_RETUNE_C8_0 */ | |
1680 | [19472] = { 0x00FF, 0x00FF, 0x0000 }, /* R19472 - DACL_RETUNE_C9_1 */ | |
1681 | [19473] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19473 - DACL_RETUNE_C9_0 */ | |
1682 | [19474] = { 0x00FF, 0x00FF, 0x0000 }, /* R19474 - DACL_RETUNE_C10_1 */ | |
1683 | [19475] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19475 - DACL_RETUNE_C10_0 */ | |
1684 | [19476] = { 0x00FF, 0x00FF, 0x0000 }, /* R19476 - DACL_RETUNE_C11_1 */ | |
1685 | [19477] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19477 - DACL_RETUNE_C11_0 */ | |
1686 | [19478] = { 0x00FF, 0x00FF, 0x0000 }, /* R19478 - DACL_RETUNE_C12_1 */ | |
1687 | [19479] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19479 - DACL_RETUNE_C12_0 */ | |
1688 | [19480] = { 0x00FF, 0x00FF, 0x0000 }, /* R19480 - DACL_RETUNE_C13_1 */ | |
1689 | [19481] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19481 - DACL_RETUNE_C13_0 */ | |
1690 | [19482] = { 0x00FF, 0x00FF, 0x0000 }, /* R19482 - DACL_RETUNE_C14_1 */ | |
1691 | [19483] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19483 - DACL_RETUNE_C14_0 */ | |
1692 | [19484] = { 0x00FF, 0x00FF, 0x0000 }, /* R19484 - DACL_RETUNE_C15_1 */ | |
1693 | [19485] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19485 - DACL_RETUNE_C15_0 */ | |
1694 | [19486] = { 0x00FF, 0x00FF, 0x0000 }, /* R19486 - DACL_RETUNE_C16_1 */ | |
1695 | [19487] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19487 - DACL_RETUNE_C16_0 */ | |
1696 | [19488] = { 0x00FF, 0x00FF, 0x0000 }, /* R19488 - DACL_RETUNE_C17_1 */ | |
1697 | [19489] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19489 - DACL_RETUNE_C17_0 */ | |
1698 | [19490] = { 0x00FF, 0x00FF, 0x0000 }, /* R19490 - DACL_RETUNE_C18_1 */ | |
1699 | [19491] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19491 - DACL_RETUNE_C18_0 */ | |
1700 | [19492] = { 0x00FF, 0x00FF, 0x0000 }, /* R19492 - DACL_RETUNE_C19_1 */ | |
1701 | [19493] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19493 - DACL_RETUNE_C19_0 */ | |
1702 | [19494] = { 0x00FF, 0x00FF, 0x0000 }, /* R19494 - DACL_RETUNE_C20_1 */ | |
1703 | [19495] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19495 - DACL_RETUNE_C20_0 */ | |
1704 | [19496] = { 0x00FF, 0x00FF, 0x0000 }, /* R19496 - DACL_RETUNE_C21_1 */ | |
1705 | [19497] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19497 - DACL_RETUNE_C21_0 */ | |
1706 | [19498] = { 0x00FF, 0x00FF, 0x0000 }, /* R19498 - DACL_RETUNE_C22_1 */ | |
1707 | [19499] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19499 - DACL_RETUNE_C22_0 */ | |
1708 | [19500] = { 0x00FF, 0x00FF, 0x0000 }, /* R19500 - DACL_RETUNE_C23_1 */ | |
1709 | [19501] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19501 - DACL_RETUNE_C23_0 */ | |
1710 | [19502] = { 0x00FF, 0x00FF, 0x0000 }, /* R19502 - DACL_RETUNE_C24_1 */ | |
1711 | [19503] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19503 - DACL_RETUNE_C24_0 */ | |
1712 | [19504] = { 0x00FF, 0x00FF, 0x0000 }, /* R19504 - DACL_RETUNE_C25_1 */ | |
1713 | [19505] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19505 - DACL_RETUNE_C25_0 */ | |
1714 | [19506] = { 0x00FF, 0x00FF, 0x0000 }, /* R19506 - DACL_RETUNE_C26_1 */ | |
1715 | [19507] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19507 - DACL_RETUNE_C26_0 */ | |
1716 | [19508] = { 0x00FF, 0x00FF, 0x0000 }, /* R19508 - DACL_RETUNE_C27_1 */ | |
1717 | [19509] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19509 - DACL_RETUNE_C27_0 */ | |
1718 | [19510] = { 0x00FF, 0x00FF, 0x0000 }, /* R19510 - DACL_RETUNE_C28_1 */ | |
1719 | [19511] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19511 - DACL_RETUNE_C28_0 */ | |
1720 | [19512] = { 0x00FF, 0x00FF, 0x0000 }, /* R19512 - DACL_RETUNE_C29_1 */ | |
1721 | [19513] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19513 - DACL_RETUNE_C29_0 */ | |
1722 | [19514] = { 0x00FF, 0x00FF, 0x0000 }, /* R19514 - DACL_RETUNE_C30_1 */ | |
1723 | [19515] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19515 - DACL_RETUNE_C30_0 */ | |
1724 | [19516] = { 0x00FF, 0x00FF, 0x0000 }, /* R19516 - DACL_RETUNE_C31_1 */ | |
1725 | [19517] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19517 - DACL_RETUNE_C31_0 */ | |
1726 | [19518] = { 0x00FF, 0x00FF, 0x0000 }, /* R19518 - DACL_RETUNE_C32_1 */ | |
1727 | [19519] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19519 - DACL_RETUNE_C32_0 */ | |
1728 | [19968] = { 0x00FF, 0x00FF, 0x0000 }, /* R19968 - RETUNEDAC_PG2_1 */ | |
1729 | [19969] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19969 - RETUNEDAC_PG2_0 */ | |
1730 | [19970] = { 0x00FF, 0x00FF, 0x0000 }, /* R19970 - RETUNEDAC_PG_1 */ | |
1731 | [19971] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19971 - RETUNEDAC_PG_0 */ | |
1732 | [20480] = { 0x00FF, 0x00FF, 0x0000 }, /* R20480 - DACR_RETUNE_C1_1 */ | |
1733 | [20481] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20481 - DACR_RETUNE_C1_0 */ | |
1734 | [20482] = { 0x00FF, 0x00FF, 0x0000 }, /* R20482 - DACR_RETUNE_C2_1 */ | |
1735 | [20483] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20483 - DACR_RETUNE_C2_0 */ | |
1736 | [20484] = { 0x00FF, 0x00FF, 0x0000 }, /* R20484 - DACR_RETUNE_C3_1 */ | |
1737 | [20485] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20485 - DACR_RETUNE_C3_0 */ | |
1738 | [20486] = { 0x00FF, 0x00FF, 0x0000 }, /* R20486 - DACR_RETUNE_C4_1 */ | |
1739 | [20487] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20487 - DACR_RETUNE_C4_0 */ | |
1740 | [20488] = { 0x00FF, 0x00FF, 0x0000 }, /* R20488 - DACR_RETUNE_C5_1 */ | |
1741 | [20489] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20489 - DACR_RETUNE_C5_0 */ | |
1742 | [20490] = { 0x00FF, 0x00FF, 0x0000 }, /* R20490 - DACR_RETUNE_C6_1 */ | |
1743 | [20491] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20491 - DACR_RETUNE_C6_0 */ | |
1744 | [20492] = { 0x00FF, 0x00FF, 0x0000 }, /* R20492 - DACR_RETUNE_C7_1 */ | |
1745 | [20493] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20493 - DACR_RETUNE_C7_0 */ | |
1746 | [20494] = { 0x00FF, 0x00FF, 0x0000 }, /* R20494 - DACR_RETUNE_C8_1 */ | |
1747 | [20495] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20495 - DACR_RETUNE_C8_0 */ | |
1748 | [20496] = { 0x00FF, 0x00FF, 0x0000 }, /* R20496 - DACR_RETUNE_C9_1 */ | |
1749 | [20497] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20497 - DACR_RETUNE_C9_0 */ | |
1750 | [20498] = { 0x00FF, 0x00FF, 0x0000 }, /* R20498 - DACR_RETUNE_C10_1 */ | |
1751 | [20499] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20499 - DACR_RETUNE_C10_0 */ | |
1752 | [20500] = { 0x00FF, 0x00FF, 0x0000 }, /* R20500 - DACR_RETUNE_C11_1 */ | |
1753 | [20501] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20501 - DACR_RETUNE_C11_0 */ | |
1754 | [20502] = { 0x00FF, 0x00FF, 0x0000 }, /* R20502 - DACR_RETUNE_C12_1 */ | |
1755 | [20503] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20503 - DACR_RETUNE_C12_0 */ | |
1756 | [20504] = { 0x00FF, 0x00FF, 0x0000 }, /* R20504 - DACR_RETUNE_C13_1 */ | |
1757 | [20505] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20505 - DACR_RETUNE_C13_0 */ | |
1758 | [20506] = { 0x00FF, 0x00FF, 0x0000 }, /* R20506 - DACR_RETUNE_C14_1 */ | |
1759 | [20507] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20507 - DACR_RETUNE_C14_0 */ | |
1760 | [20508] = { 0x00FF, 0x00FF, 0x0000 }, /* R20508 - DACR_RETUNE_C15_1 */ | |
1761 | [20509] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20509 - DACR_RETUNE_C15_0 */ | |
1762 | [20510] = { 0x00FF, 0x00FF, 0x0000 }, /* R20510 - DACR_RETUNE_C16_1 */ | |
1763 | [20511] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20511 - DACR_RETUNE_C16_0 */ | |
1764 | [20512] = { 0x00FF, 0x00FF, 0x0000 }, /* R20512 - DACR_RETUNE_C17_1 */ | |
1765 | [20513] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20513 - DACR_RETUNE_C17_0 */ | |
1766 | [20514] = { 0x00FF, 0x00FF, 0x0000 }, /* R20514 - DACR_RETUNE_C18_1 */ | |
1767 | [20515] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20515 - DACR_RETUNE_C18_0 */ | |
1768 | [20516] = { 0x00FF, 0x00FF, 0x0000 }, /* R20516 - DACR_RETUNE_C19_1 */ | |
1769 | [20517] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20517 - DACR_RETUNE_C19_0 */ | |
1770 | [20518] = { 0x00FF, 0x00FF, 0x0000 }, /* R20518 - DACR_RETUNE_C20_1 */ | |
1771 | [20519] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20519 - DACR_RETUNE_C20_0 */ | |
1772 | [20520] = { 0x00FF, 0x00FF, 0x0000 }, /* R20520 - DACR_RETUNE_C21_1 */ | |
1773 | [20521] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20521 - DACR_RETUNE_C21_0 */ | |
1774 | [20522] = { 0x00FF, 0x00FF, 0x0000 }, /* R20522 - DACR_RETUNE_C22_1 */ | |
1775 | [20523] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20523 - DACR_RETUNE_C22_0 */ | |
1776 | [20524] = { 0x00FF, 0x00FF, 0x0000 }, /* R20524 - DACR_RETUNE_C23_1 */ | |
1777 | [20525] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20525 - DACR_RETUNE_C23_0 */ | |
1778 | [20526] = { 0x00FF, 0x00FF, 0x0000 }, /* R20526 - DACR_RETUNE_C24_1 */ | |
1779 | [20527] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20527 - DACR_RETUNE_C24_0 */ | |
1780 | [20528] = { 0x00FF, 0x00FF, 0x0000 }, /* R20528 - DACR_RETUNE_C25_1 */ | |
1781 | [20529] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20529 - DACR_RETUNE_C25_0 */ | |
1782 | [20530] = { 0x00FF, 0x00FF, 0x0000 }, /* R20530 - DACR_RETUNE_C26_1 */ | |
1783 | [20531] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20531 - DACR_RETUNE_C26_0 */ | |
1784 | [20532] = { 0x00FF, 0x00FF, 0x0000 }, /* R20532 - DACR_RETUNE_C27_1 */ | |
1785 | [20533] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20533 - DACR_RETUNE_C27_0 */ | |
1786 | [20534] = { 0x00FF, 0x00FF, 0x0000 }, /* R20534 - DACR_RETUNE_C28_1 */ | |
1787 | [20535] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20535 - DACR_RETUNE_C28_0 */ | |
1788 | [20536] = { 0x00FF, 0x00FF, 0x0000 }, /* R20536 - DACR_RETUNE_C29_1 */ | |
1789 | [20537] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20537 - DACR_RETUNE_C29_0 */ | |
1790 | [20538] = { 0x00FF, 0x00FF, 0x0000 }, /* R20538 - DACR_RETUNE_C30_1 */ | |
1791 | [20539] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20539 - DACR_RETUNE_C30_0 */ | |
1792 | [20540] = { 0x00FF, 0x00FF, 0x0000 }, /* R20540 - DACR_RETUNE_C31_1 */ | |
1793 | [20541] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20541 - DACR_RETUNE_C31_0 */ | |
1794 | [20542] = { 0x00FF, 0x00FF, 0x0000 }, /* R20542 - DACR_RETUNE_C32_1 */ | |
1795 | [20543] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20543 - DACR_RETUNE_C32_0 */ | |
1796 | [20992] = { 0x00FF, 0x00FF, 0x0000 }, /* R20992 - VSS_XHD2_1 */ | |
1797 | [20993] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20993 - VSS_XHD2_0 */ | |
1798 | [20994] = { 0x00FF, 0x00FF, 0x0000 }, /* R20994 - VSS_XHD3_1 */ | |
1799 | [20995] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20995 - VSS_XHD3_0 */ | |
1800 | [20996] = { 0x00FF, 0x00FF, 0x0000 }, /* R20996 - VSS_XHN1_1 */ | |
1801 | [20997] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20997 - VSS_XHN1_0 */ | |
1802 | [20998] = { 0x00FF, 0x00FF, 0x0000 }, /* R20998 - VSS_XHN2_1 */ | |
1803 | [20999] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20999 - VSS_XHN2_0 */ | |
1804 | [21000] = { 0x00FF, 0x00FF, 0x0000 }, /* R21000 - VSS_XHN3_1 */ | |
1805 | [21001] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21001 - VSS_XHN3_0 */ | |
1806 | [21002] = { 0x00FF, 0x00FF, 0x0000 }, /* R21002 - VSS_XLA_1 */ | |
1807 | [21003] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21003 - VSS_XLA_0 */ | |
1808 | [21004] = { 0x00FF, 0x00FF, 0x0000 }, /* R21004 - VSS_XLB_1 */ | |
1809 | [21005] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21005 - VSS_XLB_0 */ | |
1810 | [21006] = { 0x00FF, 0x00FF, 0x0000 }, /* R21006 - VSS_XLG_1 */ | |
1811 | [21007] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21007 - VSS_XLG_0 */ | |
1812 | [21008] = { 0x00FF, 0x00FF, 0x0000 }, /* R21008 - VSS_PG2_1 */ | |
1813 | [21009] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21009 - VSS_PG2_0 */ | |
1814 | [21010] = { 0x00FF, 0x00FF, 0x0000 }, /* R21010 - VSS_PG_1 */ | |
1815 | [21011] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21011 - VSS_PG_0 */ | |
1816 | [21012] = { 0x00FF, 0x00FF, 0x0000 }, /* R21012 - VSS_XTD1_1 */ | |
1817 | [21013] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21013 - VSS_XTD1_0 */ | |
1818 | [21014] = { 0x00FF, 0x00FF, 0x0000 }, /* R21014 - VSS_XTD2_1 */ | |
1819 | [21015] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21015 - VSS_XTD2_0 */ | |
1820 | [21016] = { 0x00FF, 0x00FF, 0x0000 }, /* R21016 - VSS_XTD3_1 */ | |
1821 | [21017] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21017 - VSS_XTD3_0 */ | |
1822 | [21018] = { 0x00FF, 0x00FF, 0x0000 }, /* R21018 - VSS_XTD4_1 */ | |
1823 | [21019] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21019 - VSS_XTD4_0 */ | |
1824 | [21020] = { 0x00FF, 0x00FF, 0x0000 }, /* R21020 - VSS_XTD5_1 */ | |
1825 | [21021] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21021 - VSS_XTD5_0 */ | |
1826 | [21022] = { 0x00FF, 0x00FF, 0x0000 }, /* R21022 - VSS_XTD6_1 */ | |
1827 | [21023] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21023 - VSS_XTD6_0 */ | |
1828 | [21024] = { 0x00FF, 0x00FF, 0x0000 }, /* R21024 - VSS_XTD7_1 */ | |
1829 | [21025] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21025 - VSS_XTD7_0 */ | |
1830 | [21026] = { 0x00FF, 0x00FF, 0x0000 }, /* R21026 - VSS_XTD8_1 */ | |
1831 | [21027] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21027 - VSS_XTD8_0 */ | |
1832 | [21028] = { 0x00FF, 0x00FF, 0x0000 }, /* R21028 - VSS_XTD9_1 */ | |
1833 | [21029] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21029 - VSS_XTD9_0 */ | |
1834 | [21030] = { 0x00FF, 0x00FF, 0x0000 }, /* R21030 - VSS_XTD10_1 */ | |
1835 | [21031] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21031 - VSS_XTD10_0 */ | |
1836 | [21032] = { 0x00FF, 0x00FF, 0x0000 }, /* R21032 - VSS_XTD11_1 */ | |
1837 | [21033] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21033 - VSS_XTD11_0 */ | |
1838 | [21034] = { 0x00FF, 0x00FF, 0x0000 }, /* R21034 - VSS_XTD12_1 */ | |
1839 | [21035] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21035 - VSS_XTD12_0 */ | |
1840 | [21036] = { 0x00FF, 0x00FF, 0x0000 }, /* R21036 - VSS_XTD13_1 */ | |
1841 | [21037] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21037 - VSS_XTD13_0 */ | |
1842 | [21038] = { 0x00FF, 0x00FF, 0x0000 }, /* R21038 - VSS_XTD14_1 */ | |
1843 | [21039] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21039 - VSS_XTD14_0 */ | |
1844 | [21040] = { 0x00FF, 0x00FF, 0x0000 }, /* R21040 - VSS_XTD15_1 */ | |
1845 | [21041] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21041 - VSS_XTD15_0 */ | |
1846 | [21042] = { 0x00FF, 0x00FF, 0x0000 }, /* R21042 - VSS_XTD16_1 */ | |
1847 | [21043] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21043 - VSS_XTD16_0 */ | |
1848 | [21044] = { 0x00FF, 0x00FF, 0x0000 }, /* R21044 - VSS_XTD17_1 */ | |
1849 | [21045] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21045 - VSS_XTD17_0 */ | |
1850 | [21046] = { 0x00FF, 0x00FF, 0x0000 }, /* R21046 - VSS_XTD18_1 */ | |
1851 | [21047] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21047 - VSS_XTD18_0 */ | |
1852 | [21048] = { 0x00FF, 0x00FF, 0x0000 }, /* R21048 - VSS_XTD19_1 */ | |
1853 | [21049] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21049 - VSS_XTD19_0 */ | |
1854 | [21050] = { 0x00FF, 0x00FF, 0x0000 }, /* R21050 - VSS_XTD20_1 */ | |
1855 | [21051] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21051 - VSS_XTD20_0 */ | |
1856 | [21052] = { 0x00FF, 0x00FF, 0x0000 }, /* R21052 - VSS_XTD21_1 */ | |
1857 | [21053] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21053 - VSS_XTD21_0 */ | |
1858 | [21054] = { 0x00FF, 0x00FF, 0x0000 }, /* R21054 - VSS_XTD22_1 */ | |
1859 | [21055] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21055 - VSS_XTD22_0 */ | |
1860 | [21056] = { 0x00FF, 0x00FF, 0x0000 }, /* R21056 - VSS_XTD23_1 */ | |
1861 | [21057] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21057 - VSS_XTD23_0 */ | |
1862 | [21058] = { 0x00FF, 0x00FF, 0x0000 }, /* R21058 - VSS_XTD24_1 */ | |
1863 | [21059] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21059 - VSS_XTD24_0 */ | |
1864 | [21060] = { 0x00FF, 0x00FF, 0x0000 }, /* R21060 - VSS_XTD25_1 */ | |
1865 | [21061] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21061 - VSS_XTD25_0 */ | |
1866 | [21062] = { 0x00FF, 0x00FF, 0x0000 }, /* R21062 - VSS_XTD26_1 */ | |
1867 | [21063] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21063 - VSS_XTD26_0 */ | |
1868 | [21064] = { 0x00FF, 0x00FF, 0x0000 }, /* R21064 - VSS_XTD27_1 */ | |
1869 | [21065] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21065 - VSS_XTD27_0 */ | |
1870 | [21066] = { 0x00FF, 0x00FF, 0x0000 }, /* R21066 - VSS_XTD28_1 */ | |
1871 | [21067] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21067 - VSS_XTD28_0 */ | |
1872 | [21068] = { 0x00FF, 0x00FF, 0x0000 }, /* R21068 - VSS_XTD29_1 */ | |
1873 | [21069] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21069 - VSS_XTD29_0 */ | |
1874 | [21070] = { 0x00FF, 0x00FF, 0x0000 }, /* R21070 - VSS_XTD30_1 */ | |
1875 | [21071] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21071 - VSS_XTD30_0 */ | |
1876 | [21072] = { 0x00FF, 0x00FF, 0x0000 }, /* R21072 - VSS_XTD31_1 */ | |
1877 | [21073] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21073 - VSS_XTD31_0 */ | |
1878 | [21074] = { 0x00FF, 0x00FF, 0x0000 }, /* R21074 - VSS_XTD32_1 */ | |
1879 | [21075] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21075 - VSS_XTD32_0 */ | |
1880 | [21076] = { 0x00FF, 0x00FF, 0x0000 }, /* R21076 - VSS_XTS1_1 */ | |
1881 | [21077] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21077 - VSS_XTS1_0 */ | |
1882 | [21078] = { 0x00FF, 0x00FF, 0x0000 }, /* R21078 - VSS_XTS2_1 */ | |
1883 | [21079] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21079 - VSS_XTS2_0 */ | |
1884 | [21080] = { 0x00FF, 0x00FF, 0x0000 }, /* R21080 - VSS_XTS3_1 */ | |
1885 | [21081] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21081 - VSS_XTS3_0 */ | |
1886 | [21082] = { 0x00FF, 0x00FF, 0x0000 }, /* R21082 - VSS_XTS4_1 */ | |
1887 | [21083] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21083 - VSS_XTS4_0 */ | |
1888 | [21084] = { 0x00FF, 0x00FF, 0x0000 }, /* R21084 - VSS_XTS5_1 */ | |
1889 | [21085] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21085 - VSS_XTS5_0 */ | |
1890 | [21086] = { 0x00FF, 0x00FF, 0x0000 }, /* R21086 - VSS_XTS6_1 */ | |
1891 | [21087] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21087 - VSS_XTS6_0 */ | |
1892 | [21088] = { 0x00FF, 0x00FF, 0x0000 }, /* R21088 - VSS_XTS7_1 */ | |
1893 | [21089] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21089 - VSS_XTS7_0 */ | |
1894 | [21090] = { 0x00FF, 0x00FF, 0x0000 }, /* R21090 - VSS_XTS8_1 */ | |
1895 | [21091] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21091 - VSS_XTS8_0 */ | |
1896 | [21092] = { 0x00FF, 0x00FF, 0x0000 }, /* R21092 - VSS_XTS9_1 */ | |
1897 | [21093] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21093 - VSS_XTS9_0 */ | |
1898 | [21094] = { 0x00FF, 0x00FF, 0x0000 }, /* R21094 - VSS_XTS10_1 */ | |
1899 | [21095] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21095 - VSS_XTS10_0 */ | |
1900 | [21096] = { 0x00FF, 0x00FF, 0x0000 }, /* R21096 - VSS_XTS11_1 */ | |
1901 | [21097] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21097 - VSS_XTS11_0 */ | |
1902 | [21098] = { 0x00FF, 0x00FF, 0x0000 }, /* R21098 - VSS_XTS12_1 */ | |
1903 | [21099] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21099 - VSS_XTS12_0 */ | |
1904 | [21100] = { 0x00FF, 0x00FF, 0x0000 }, /* R21100 - VSS_XTS13_1 */ | |
1905 | [21101] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21101 - VSS_XTS13_0 */ | |
1906 | [21102] = { 0x00FF, 0x00FF, 0x0000 }, /* R21102 - VSS_XTS14_1 */ | |
1907 | [21103] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21103 - VSS_XTS14_0 */ | |
1908 | [21104] = { 0x00FF, 0x00FF, 0x0000 }, /* R21104 - VSS_XTS15_1 */ | |
1909 | [21105] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21105 - VSS_XTS15_0 */ | |
1910 | [21106] = { 0x00FF, 0x00FF, 0x0000 }, /* R21106 - VSS_XTS16_1 */ | |
1911 | [21107] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21107 - VSS_XTS16_0 */ | |
1912 | [21108] = { 0x00FF, 0x00FF, 0x0000 }, /* R21108 - VSS_XTS17_1 */ | |
1913 | [21109] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21109 - VSS_XTS17_0 */ | |
1914 | [21110] = { 0x00FF, 0x00FF, 0x0000 }, /* R21110 - VSS_XTS18_1 */ | |
1915 | [21111] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21111 - VSS_XTS18_0 */ | |
1916 | [21112] = { 0x00FF, 0x00FF, 0x0000 }, /* R21112 - VSS_XTS19_1 */ | |
1917 | [21113] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21113 - VSS_XTS19_0 */ | |
1918 | [21114] = { 0x00FF, 0x00FF, 0x0000 }, /* R21114 - VSS_XTS20_1 */ | |
1919 | [21115] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21115 - VSS_XTS20_0 */ | |
1920 | [21116] = { 0x00FF, 0x00FF, 0x0000 }, /* R21116 - VSS_XTS21_1 */ | |
1921 | [21117] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21117 - VSS_XTS21_0 */ | |
1922 | [21118] = { 0x00FF, 0x00FF, 0x0000 }, /* R21118 - VSS_XTS22_1 */ | |
1923 | [21119] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21119 - VSS_XTS22_0 */ | |
1924 | [21120] = { 0x00FF, 0x00FF, 0x0000 }, /* R21120 - VSS_XTS23_1 */ | |
1925 | [21121] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21121 - VSS_XTS23_0 */ | |
1926 | [21122] = { 0x00FF, 0x00FF, 0x0000 }, /* R21122 - VSS_XTS24_1 */ | |
1927 | [21123] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21123 - VSS_XTS24_0 */ | |
1928 | [21124] = { 0x00FF, 0x00FF, 0x0000 }, /* R21124 - VSS_XTS25_1 */ | |
1929 | [21125] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21125 - VSS_XTS25_0 */ | |
1930 | [21126] = { 0x00FF, 0x00FF, 0x0000 }, /* R21126 - VSS_XTS26_1 */ | |
1931 | [21127] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21127 - VSS_XTS26_0 */ | |
1932 | [21128] = { 0x00FF, 0x00FF, 0x0000 }, /* R21128 - VSS_XTS27_1 */ | |
1933 | [21129] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21129 - VSS_XTS27_0 */ | |
1934 | [21130] = { 0x00FF, 0x00FF, 0x0000 }, /* R21130 - VSS_XTS28_1 */ | |
1935 | [21131] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21131 - VSS_XTS28_0 */ | |
1936 | [21132] = { 0x00FF, 0x00FF, 0x0000 }, /* R21132 - VSS_XTS29_1 */ | |
1937 | [21133] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21133 - VSS_XTS29_0 */ | |
1938 | [21134] = { 0x00FF, 0x00FF, 0x0000 }, /* R21134 - VSS_XTS30_1 */ | |
1939 | [21135] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21135 - VSS_XTS30_0 */ | |
1940 | [21136] = { 0x00FF, 0x00FF, 0x0000 }, /* R21136 - VSS_XTS31_1 */ | |
1941 | [21137] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21137 - VSS_XTS31_0 */ | |
1942 | [21138] = { 0x00FF, 0x00FF, 0x0000 }, /* R21138 - VSS_XTS32_1 */ | |
1943 | [21139] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21139 - VSS_XTS32_0 */ | |
1944 | }; | |
1945 | ||
d4754ec9 | 1946 | static int wm8962_volatile_register(struct snd_soc_codec *codec, unsigned int reg) |
9a76f1ff MB |
1947 | { |
1948 | if (wm8962_reg_access[reg].vol) | |
1949 | return 1; | |
1950 | else | |
1951 | return 0; | |
1952 | } | |
1953 | ||
d4754ec9 | 1954 | static int wm8962_readable_register(struct snd_soc_codec *codec, unsigned int reg) |
9a76f1ff MB |
1955 | { |
1956 | if (wm8962_reg_access[reg].read) | |
1957 | return 1; | |
1958 | else | |
1959 | return 0; | |
1960 | } | |
1961 | ||
1962 | static int wm8962_reset(struct snd_soc_codec *codec) | |
1963 | { | |
cb2b3cf1 | 1964 | return snd_soc_write(codec, WM8962_SOFTWARE_RESET, 0x6243); |
9a76f1ff MB |
1965 | } |
1966 | ||
1967 | static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0); | |
1968 | static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0); | |
1969 | static const unsigned int mixinpga_tlv[] = { | |
1970 | TLV_DB_RANGE_HEAD(7), | |
1971 | 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0), | |
1972 | 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0), | |
1973 | 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0), | |
1974 | 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0), | |
1975 | 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0), | |
1976 | }; | |
1977 | static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1); | |
1978 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); | |
1979 | static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); | |
1980 | static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0); | |
1981 | static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); | |
1982 | static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1); | |
1983 | static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0); | |
1984 | static const unsigned int classd_tlv[] = { | |
1985 | TLV_DB_RANGE_HEAD(7), | |
1986 | 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0), | |
1987 | 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0), | |
1988 | }; | |
8f63aaa8 | 1989 | static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); |
9a76f1ff | 1990 | |
6f88a4e5 MB |
1991 | static int wm8962_dsp2_write_config(struct snd_soc_codec *codec) |
1992 | { | |
1993 | return 0; | |
1994 | } | |
1995 | ||
1996 | static int wm8962_dsp2_set_enable(struct snd_soc_codec *codec, u16 val) | |
1997 | { | |
1998 | u16 adcl = snd_soc_read(codec, WM8962_LEFT_ADC_VOLUME); | |
1999 | u16 adcr = snd_soc_read(codec, WM8962_RIGHT_ADC_VOLUME); | |
2000 | u16 dac = snd_soc_read(codec, WM8962_ADC_DAC_CONTROL_1); | |
2001 | ||
2002 | /* Mute the ADCs and DACs */ | |
2003 | snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, 0); | |
2004 | snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU); | |
2005 | snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1, | |
2006 | WM8962_DAC_MUTE, WM8962_DAC_MUTE); | |
2007 | ||
2008 | snd_soc_write(codec, WM8962_SOUNDSTAGE_ENABLES_0, val); | |
2009 | ||
2010 | /* Restore the ADCs and DACs */ | |
2011 | snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, adcl); | |
2012 | snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, adcr); | |
2013 | snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1, | |
2014 | WM8962_DAC_MUTE, dac); | |
2015 | ||
2016 | return 0; | |
2017 | } | |
2018 | ||
2019 | static int wm8962_dsp2_start(struct snd_soc_codec *codec) | |
2020 | { | |
2021 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
2022 | ||
2023 | wm8962_dsp2_write_config(codec); | |
2024 | ||
2025 | snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR); | |
2026 | ||
2027 | wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena); | |
2028 | ||
2029 | return 0; | |
2030 | } | |
2031 | ||
2032 | static int wm8962_dsp2_stop(struct snd_soc_codec *codec) | |
2033 | { | |
2034 | wm8962_dsp2_set_enable(codec, 0); | |
2035 | ||
2036 | snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP); | |
2037 | ||
2038 | return 0; | |
2039 | } | |
2040 | ||
2041 | #define WM8962_DSP2_ENABLE(xname, xshift) \ | |
2042 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
2043 | .info = wm8962_dsp2_ena_info, \ | |
2044 | .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \ | |
2045 | .private_value = xshift } | |
2046 | ||
2047 | static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol, | |
2048 | struct snd_ctl_elem_info *uinfo) | |
2049 | { | |
2050 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; | |
2051 | ||
2052 | uinfo->count = 1; | |
2053 | uinfo->value.integer.min = 0; | |
2054 | uinfo->value.integer.max = 1; | |
2055 | ||
2056 | return 0; | |
2057 | } | |
2058 | ||
2059 | static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol, | |
2060 | struct snd_ctl_elem_value *ucontrol) | |
2061 | { | |
2062 | int shift = kcontrol->private_value; | |
2063 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
2064 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
2065 | ||
2066 | ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift); | |
2067 | ||
2068 | return 0; | |
2069 | } | |
2070 | ||
2071 | static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol, | |
2072 | struct snd_ctl_elem_value *ucontrol) | |
2073 | { | |
2074 | int shift = kcontrol->private_value; | |
2075 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
2076 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
2077 | int old = wm8962->dsp2_ena; | |
2078 | int ret = 0; | |
2079 | int dsp2_running = snd_soc_read(codec, WM8962_DSP2_POWER_MANAGEMENT) & | |
2080 | WM8962_DSP2_ENA; | |
2081 | ||
2082 | mutex_lock(&codec->mutex); | |
2083 | ||
2084 | if (ucontrol->value.integer.value[0]) | |
2085 | wm8962->dsp2_ena |= 1 << shift; | |
2086 | else | |
2087 | wm8962->dsp2_ena &= ~(1 << shift); | |
2088 | ||
2089 | if (wm8962->dsp2_ena == old) | |
2090 | goto out; | |
2091 | ||
2092 | ret = 1; | |
2093 | ||
2094 | if (dsp2_running) { | |
2095 | if (wm8962->dsp2_ena) | |
2096 | wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena); | |
2097 | else | |
2098 | wm8962_dsp2_stop(codec); | |
2099 | } | |
2100 | ||
2101 | out: | |
2102 | mutex_unlock(&codec->mutex); | |
2103 | ||
2104 | return ret; | |
2105 | } | |
2106 | ||
9a76f1ff MB |
2107 | /* The VU bits for the headphones are in a different register to the mute |
2108 | * bits and only take effect on the PGA if it is actually powered. | |
2109 | */ | |
2110 | static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol, | |
2111 | struct snd_ctl_elem_value *ucontrol) | |
2112 | { | |
2113 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
7f87e30e | 2114 | u16 *reg_cache = codec->reg_cache; |
9a76f1ff MB |
2115 | int ret; |
2116 | ||
2117 | /* Apply the update (if any) */ | |
2118 | ret = snd_soc_put_volsw(kcontrol, ucontrol); | |
2119 | if (ret == 0) | |
2120 | return 0; | |
2121 | ||
2122 | /* If the left PGA is enabled hit that VU bit... */ | |
0f82bdf5 | 2123 | if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTL_PGA_ENA) |
9a76f1ff MB |
2124 | return snd_soc_write(codec, WM8962_HPOUTL_VOLUME, |
2125 | reg_cache[WM8962_HPOUTL_VOLUME]); | |
2126 | ||
2127 | /* ...otherwise the right. The VU is stereo. */ | |
0f82bdf5 | 2128 | if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTR_PGA_ENA) |
9a76f1ff MB |
2129 | return snd_soc_write(codec, WM8962_HPOUTR_VOLUME, |
2130 | reg_cache[WM8962_HPOUTR_VOLUME]); | |
2131 | ||
2132 | return 0; | |
2133 | } | |
2134 | ||
2135 | /* The VU bits for the speakers are in a different register to the mute | |
2136 | * bits and only take effect on the PGA if it is actually powered. | |
2137 | */ | |
2138 | static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol, | |
2139 | struct snd_ctl_elem_value *ucontrol) | |
2140 | { | |
2141 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
9a76f1ff MB |
2142 | int ret; |
2143 | ||
2144 | /* Apply the update (if any) */ | |
2145 | ret = snd_soc_put_volsw(kcontrol, ucontrol); | |
2146 | if (ret == 0) | |
2147 | return 0; | |
2148 | ||
2149 | /* If the left PGA is enabled hit that VU bit... */ | |
38f3f31a MB |
2150 | ret = snd_soc_read(codec, WM8962_PWR_MGMT_2); |
2151 | if (ret & WM8962_SPKOUTL_PGA_ENA) { | |
2152 | snd_soc_write(codec, WM8962_SPKOUTL_VOLUME, | |
2153 | snd_soc_read(codec, WM8962_SPKOUTL_VOLUME)); | |
2154 | return 1; | |
2155 | } | |
9a76f1ff MB |
2156 | |
2157 | /* ...otherwise the right. The VU is stereo. */ | |
38f3f31a MB |
2158 | if (ret & WM8962_SPKOUTR_PGA_ENA) |
2159 | snd_soc_write(codec, WM8962_SPKOUTR_VOLUME, | |
2160 | snd_soc_read(codec, WM8962_SPKOUTR_VOLUME)); | |
9a76f1ff | 2161 | |
38f3f31a | 2162 | return 1; |
9a76f1ff MB |
2163 | } |
2164 | ||
6be449e5 MB |
2165 | static const char *cap_hpf_mode_text[] = { |
2166 | "Hi-fi", "Application" | |
2167 | }; | |
2168 | ||
2169 | static const struct soc_enum cap_hpf_mode = | |
2170 | SOC_ENUM_SINGLE(WM8962_ADC_DAC_CONTROL_2, 10, 2, cap_hpf_mode_text); | |
2171 | ||
1ab63da7 MB |
2172 | |
2173 | static const char *cap_lhpf_mode_text[] = { | |
2174 | "LPF", "HPF" | |
2175 | }; | |
2176 | ||
2177 | static const struct soc_enum cap_lhpf_mode = | |
2178 | SOC_ENUM_SINGLE(WM8962_LHPF1, 1, 2, cap_lhpf_mode_text); | |
2179 | ||
9a76f1ff MB |
2180 | static const struct snd_kcontrol_new wm8962_snd_controls[] = { |
2181 | SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1), | |
2182 | ||
2183 | SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0, | |
2184 | mixin_tlv), | |
2185 | SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0, | |
2186 | mixinpga_tlv), | |
2187 | SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0, | |
2188 | mixin_tlv), | |
2189 | ||
2190 | SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0, | |
2191 | mixin_tlv), | |
2192 | SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0, | |
2193 | mixinpga_tlv), | |
2194 | SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0, | |
2195 | mixin_tlv), | |
2196 | ||
2197 | SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME, | |
2198 | WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv), | |
2199 | SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME, | |
2200 | WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv), | |
2201 | SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME, | |
2202 | WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1), | |
2203 | SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME, | |
2204 | WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1), | |
6be449e5 MB |
2205 | SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1), |
2206 | SOC_ENUM("Capture HPF Mode", cap_hpf_mode), | |
2207 | SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0), | |
1ab63da7 MB |
2208 | SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0), |
2209 | SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode), | |
9a76f1ff MB |
2210 | |
2211 | SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1, | |
2212 | WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv), | |
2213 | ||
2214 | SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME, | |
2215 | WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv), | |
2216 | SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0), | |
2217 | ||
2218 | SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1, | |
2219 | 5, 1, 0), | |
2220 | ||
2221 | SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv), | |
2222 | ||
2223 | SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME, | |
2224 | WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv), | |
2225 | SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1, | |
2226 | snd_soc_get_volsw, wm8962_put_hp_sw), | |
2227 | SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME, | |
2228 | 7, 1, 0), | |
2229 | SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0, | |
2230 | hp_tlv), | |
2231 | ||
2232 | SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3, | |
2233 | WM8962_HEADPHONE_MIXER_4, 8, 1, 1), | |
2234 | ||
2235 | SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3, | |
2236 | 3, 7, 0, bypass_tlv), | |
2237 | SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3, | |
2238 | 0, 7, 0, bypass_tlv), | |
2239 | SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3, | |
2240 | 7, 1, 1, inmix_tlv), | |
2241 | SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3, | |
2242 | 6, 1, 1, inmix_tlv), | |
2243 | ||
2244 | SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4, | |
2245 | 3, 7, 0, bypass_tlv), | |
2246 | SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4, | |
2247 | 0, 7, 0, bypass_tlv), | |
2248 | SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4, | |
2249 | 7, 1, 1, inmix_tlv), | |
2250 | SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4, | |
2251 | 6, 1, 1, inmix_tlv), | |
2252 | ||
2253 | SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0, | |
2254 | classd_tlv), | |
8f63aaa8 MB |
2255 | |
2256 | SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0), | |
2257 | SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22, | |
2258 | WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv), | |
2259 | SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22, | |
2260 | WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv), | |
2261 | SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22, | |
2262 | WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv), | |
2263 | SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23, | |
2264 | WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv), | |
2265 | SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23, | |
2266 | WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv), | |
6f88a4e5 MB |
2267 | |
2268 | WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT), | |
2269 | WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT), | |
2270 | WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT), | |
2271 | WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT), | |
9a76f1ff MB |
2272 | }; |
2273 | ||
2274 | static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = { | |
2275 | SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv), | |
2276 | SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1, | |
2277 | snd_soc_get_volsw, wm8962_put_spk_sw), | |
2278 | SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0), | |
2279 | ||
2280 | SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1), | |
2281 | SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3, | |
2282 | 3, 7, 0, bypass_tlv), | |
2283 | SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3, | |
2284 | 0, 7, 0, bypass_tlv), | |
2285 | SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3, | |
2286 | 7, 1, 1, inmix_tlv), | |
2287 | SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3, | |
2288 | 6, 1, 1, inmix_tlv), | |
2289 | SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5, | |
2290 | 7, 1, 0, inmix_tlv), | |
2291 | SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5, | |
2292 | 6, 1, 0, inmix_tlv), | |
2293 | }; | |
2294 | ||
2295 | static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = { | |
2296 | SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, | |
2297 | WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv), | |
2298 | SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1, | |
2299 | snd_soc_get_volsw, wm8962_put_spk_sw), | |
2300 | SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME, | |
2301 | 7, 1, 0), | |
2302 | ||
2303 | SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, | |
2304 | WM8962_SPEAKER_MIXER_4, 8, 1, 1), | |
2305 | ||
2306 | SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3, | |
2307 | 3, 7, 0, bypass_tlv), | |
2308 | SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3, | |
2309 | 0, 7, 0, bypass_tlv), | |
2310 | SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3, | |
2311 | 7, 1, 1, inmix_tlv), | |
2312 | SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3, | |
2313 | 6, 1, 1, inmix_tlv), | |
2314 | SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5, | |
2315 | 7, 1, 0, inmix_tlv), | |
2316 | SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5, | |
2317 | 6, 1, 0, inmix_tlv), | |
2318 | ||
2319 | SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4, | |
2320 | 3, 7, 0, bypass_tlv), | |
2321 | SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4, | |
2322 | 0, 7, 0, bypass_tlv), | |
2323 | SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4, | |
2324 | 7, 1, 1, inmix_tlv), | |
2325 | SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4, | |
2326 | 6, 1, 1, inmix_tlv), | |
2327 | SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5, | |
2328 | 5, 1, 0, inmix_tlv), | |
2329 | SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5, | |
2330 | 4, 1, 0, inmix_tlv), | |
2331 | }; | |
2332 | ||
2333 | static int sysclk_event(struct snd_soc_dapm_widget *w, | |
2334 | struct snd_kcontrol *kcontrol, int event) | |
2335 | { | |
2336 | struct snd_soc_codec *codec = w->codec; | |
649a1a0e MB |
2337 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
2338 | unsigned long timeout; | |
9a76f1ff MB |
2339 | int src; |
2340 | int fll; | |
2341 | ||
2342 | src = snd_soc_read(codec, WM8962_CLOCKING2) & WM8962_SYSCLK_SRC_MASK; | |
2343 | ||
2344 | switch (src) { | |
2345 | case 0: /* MCLK */ | |
2346 | fll = 0; | |
2347 | break; | |
2348 | case 0x200: /* FLL */ | |
2349 | fll = 1; | |
2350 | break; | |
2351 | default: | |
2352 | dev_err(codec->dev, "Unknown SYSCLK source %x\n", src); | |
2353 | return -EINVAL; | |
2354 | } | |
2355 | ||
2356 | switch (event) { | |
2357 | case SND_SOC_DAPM_PRE_PMU: | |
649a1a0e | 2358 | if (fll) { |
4df0cb2f MB |
2359 | try_wait_for_completion(&wm8962->fll_lock); |
2360 | ||
9a76f1ff MB |
2361 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, |
2362 | WM8962_FLL_ENA, WM8962_FLL_ENA); | |
649a1a0e MB |
2363 | if (wm8962->irq) { |
2364 | timeout = msecs_to_jiffies(5); | |
2365 | timeout = wait_for_completion_timeout(&wm8962->fll_lock, | |
2366 | timeout); | |
2367 | ||
2368 | if (timeout == 0) | |
2369 | dev_err(codec->dev, | |
2370 | "Timed out starting FLL\n"); | |
2371 | } | |
2372 | } | |
9a76f1ff MB |
2373 | break; |
2374 | ||
2375 | case SND_SOC_DAPM_POST_PMD: | |
2376 | if (fll) | |
2377 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, | |
2378 | WM8962_FLL_ENA, 0); | |
2379 | break; | |
2380 | ||
2381 | default: | |
2382 | BUG(); | |
2383 | return -EINVAL; | |
2384 | } | |
2385 | ||
2386 | return 0; | |
2387 | } | |
2388 | ||
2389 | static int cp_event(struct snd_soc_dapm_widget *w, | |
2390 | struct snd_kcontrol *kcontrol, int event) | |
2391 | { | |
2392 | switch (event) { | |
2393 | case SND_SOC_DAPM_POST_PMU: | |
2394 | msleep(5); | |
2395 | break; | |
2396 | ||
2397 | default: | |
2398 | BUG(); | |
2399 | return -EINVAL; | |
2400 | } | |
2401 | ||
2402 | return 0; | |
2403 | } | |
2404 | ||
2405 | static int hp_event(struct snd_soc_dapm_widget *w, | |
2406 | struct snd_kcontrol *kcontrol, int event) | |
2407 | { | |
2408 | struct snd_soc_codec *codec = w->codec; | |
2409 | int timeout; | |
2410 | int reg; | |
2411 | int expected = (WM8962_DCS_STARTUP_DONE_HP1L | | |
2412 | WM8962_DCS_STARTUP_DONE_HP1R); | |
2413 | ||
2414 | switch (event) { | |
2415 | case SND_SOC_DAPM_POST_PMU: | |
2416 | snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, | |
2417 | WM8962_HP1L_ENA | WM8962_HP1R_ENA, | |
2418 | WM8962_HP1L_ENA | WM8962_HP1R_ENA); | |
2419 | udelay(20); | |
2420 | ||
2421 | snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, | |
2422 | WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY, | |
2423 | WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY); | |
2424 | ||
2425 | /* Start the DC servo */ | |
2426 | snd_soc_update_bits(codec, WM8962_DC_SERVO_1, | |
2427 | WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | | |
2428 | WM8962_HP1L_DCS_STARTUP | | |
2429 | WM8962_HP1R_DCS_STARTUP, | |
2430 | WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | | |
2431 | WM8962_HP1L_DCS_STARTUP | | |
2432 | WM8962_HP1R_DCS_STARTUP); | |
2433 | ||
2434 | /* Wait for it to complete, should be well under 100ms */ | |
2435 | timeout = 0; | |
2436 | do { | |
2437 | msleep(1); | |
2438 | reg = snd_soc_read(codec, WM8962_DC_SERVO_6); | |
2439 | if (reg < 0) { | |
2440 | dev_err(codec->dev, | |
2441 | "Failed to read DCS status: %d\n", | |
2442 | reg); | |
2443 | continue; | |
2444 | } | |
2445 | dev_dbg(codec->dev, "DCS status: %x\n", reg); | |
2446 | } while (++timeout < 200 && (reg & expected) != expected); | |
2447 | ||
2448 | if ((reg & expected) != expected) | |
2449 | dev_err(codec->dev, "DC servo timed out\n"); | |
2450 | else | |
2451 | dev_dbg(codec->dev, "DC servo complete after %dms\n", | |
2452 | timeout); | |
2453 | ||
2454 | snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, | |
2455 | WM8962_HP1L_ENA_OUTP | | |
2456 | WM8962_HP1R_ENA_OUTP, | |
2457 | WM8962_HP1L_ENA_OUTP | | |
2458 | WM8962_HP1R_ENA_OUTP); | |
2459 | udelay(20); | |
2460 | ||
2461 | snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, | |
2462 | WM8962_HP1L_RMV_SHORT | | |
2463 | WM8962_HP1R_RMV_SHORT, | |
2464 | WM8962_HP1L_RMV_SHORT | | |
2465 | WM8962_HP1R_RMV_SHORT); | |
2466 | break; | |
2467 | ||
2468 | case SND_SOC_DAPM_PRE_PMD: | |
2469 | snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, | |
2470 | WM8962_HP1L_RMV_SHORT | | |
2471 | WM8962_HP1R_RMV_SHORT, 0); | |
2472 | ||
2473 | udelay(20); | |
2474 | ||
2475 | snd_soc_update_bits(codec, WM8962_DC_SERVO_1, | |
2476 | WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | | |
2477 | WM8962_HP1L_DCS_STARTUP | | |
2478 | WM8962_HP1R_DCS_STARTUP, | |
2479 | 0); | |
2480 | ||
2481 | snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, | |
2482 | WM8962_HP1L_ENA | WM8962_HP1R_ENA | | |
2483 | WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY | | |
2484 | WM8962_HP1L_ENA_OUTP | | |
2485 | WM8962_HP1R_ENA_OUTP, 0); | |
2486 | ||
2487 | break; | |
2488 | ||
2489 | default: | |
2490 | BUG(); | |
2491 | return -EINVAL; | |
2492 | ||
2493 | } | |
2494 | ||
2495 | return 0; | |
2496 | } | |
2497 | ||
2498 | /* VU bits for the output PGAs only take effect while the PGA is powered */ | |
2499 | static int out_pga_event(struct snd_soc_dapm_widget *w, | |
2500 | struct snd_kcontrol *kcontrol, int event) | |
2501 | { | |
2502 | struct snd_soc_codec *codec = w->codec; | |
9a76f1ff MB |
2503 | int reg; |
2504 | ||
2505 | switch (w->shift) { | |
2506 | case WM8962_HPOUTR_PGA_ENA_SHIFT: | |
2507 | reg = WM8962_HPOUTR_VOLUME; | |
2508 | break; | |
2509 | case WM8962_HPOUTL_PGA_ENA_SHIFT: | |
2510 | reg = WM8962_HPOUTL_VOLUME; | |
2511 | break; | |
2512 | case WM8962_SPKOUTR_PGA_ENA_SHIFT: | |
2513 | reg = WM8962_SPKOUTR_VOLUME; | |
2514 | break; | |
2515 | case WM8962_SPKOUTL_PGA_ENA_SHIFT: | |
2516 | reg = WM8962_SPKOUTL_VOLUME; | |
2517 | break; | |
2518 | default: | |
2519 | BUG(); | |
2520 | return -EINVAL; | |
2521 | } | |
2522 | ||
2523 | switch (event) { | |
2524 | case SND_SOC_DAPM_POST_PMU: | |
38f3f31a | 2525 | return snd_soc_write(codec, reg, snd_soc_read(codec, reg)); |
9a76f1ff MB |
2526 | default: |
2527 | BUG(); | |
2528 | return -EINVAL; | |
2529 | } | |
2530 | } | |
2531 | ||
6f88a4e5 MB |
2532 | static int dsp2_event(struct snd_soc_dapm_widget *w, |
2533 | struct snd_kcontrol *kcontrol, int event) | |
2534 | { | |
2535 | struct snd_soc_codec *codec = w->codec; | |
2536 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
2537 | ||
2538 | switch (event) { | |
2539 | case SND_SOC_DAPM_POST_PMU: | |
2540 | if (wm8962->dsp2_ena) | |
2541 | wm8962_dsp2_start(codec); | |
2542 | break; | |
2543 | ||
2544 | case SND_SOC_DAPM_PRE_PMD: | |
2545 | if (wm8962->dsp2_ena) | |
2546 | wm8962_dsp2_stop(codec); | |
2547 | break; | |
2548 | ||
2549 | default: | |
2550 | BUG(); | |
2551 | return -EINVAL; | |
2552 | } | |
2553 | ||
2554 | return 0; | |
2555 | } | |
2556 | ||
9a76f1ff MB |
2557 | static const char *st_text[] = { "None", "Right", "Left" }; |
2558 | ||
2559 | static const struct soc_enum str_enum = | |
2560 | SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text); | |
2561 | ||
2562 | static const struct snd_kcontrol_new str_mux = | |
2563 | SOC_DAPM_ENUM("Right Sidetone", str_enum); | |
2564 | ||
2565 | static const struct soc_enum stl_enum = | |
2566 | SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text); | |
2567 | ||
2568 | static const struct snd_kcontrol_new stl_mux = | |
2569 | SOC_DAPM_ENUM("Left Sidetone", stl_enum); | |
2570 | ||
2571 | static const char *outmux_text[] = { "DAC", "Mixer" }; | |
2572 | ||
2573 | static const struct soc_enum spkoutr_enum = | |
2574 | SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text); | |
2575 | ||
2576 | static const struct snd_kcontrol_new spkoutr_mux = | |
2577 | SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum); | |
2578 | ||
2579 | static const struct soc_enum spkoutl_enum = | |
2580 | SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text); | |
2581 | ||
2582 | static const struct snd_kcontrol_new spkoutl_mux = | |
2583 | SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum); | |
2584 | ||
2585 | static const struct soc_enum hpoutr_enum = | |
2586 | SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text); | |
2587 | ||
2588 | static const struct snd_kcontrol_new hpoutr_mux = | |
2589 | SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum); | |
2590 | ||
2591 | static const struct soc_enum hpoutl_enum = | |
2592 | SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text); | |
2593 | ||
2594 | static const struct snd_kcontrol_new hpoutl_mux = | |
2595 | SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum); | |
2596 | ||
2597 | static const struct snd_kcontrol_new inpgal[] = { | |
2598 | SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0), | |
2599 | SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0), | |
2600 | SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0), | |
2601 | SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0), | |
2602 | }; | |
2603 | ||
2604 | static const struct snd_kcontrol_new inpgar[] = { | |
2605 | SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0), | |
2606 | SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0), | |
2607 | SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0), | |
2608 | SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0), | |
2609 | }; | |
2610 | ||
2611 | static const struct snd_kcontrol_new mixinl[] = { | |
2612 | SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0), | |
2613 | SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0), | |
2614 | SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0), | |
2615 | }; | |
2616 | ||
2617 | static const struct snd_kcontrol_new mixinr[] = { | |
2618 | SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0), | |
2619 | SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0), | |
2620 | SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0), | |
2621 | }; | |
2622 | ||
2623 | static const struct snd_kcontrol_new hpmixl[] = { | |
2624 | SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0), | |
2625 | SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0), | |
2626 | SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0), | |
2627 | SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0), | |
2628 | SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0), | |
2629 | SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0), | |
2630 | }; | |
2631 | ||
2632 | static const struct snd_kcontrol_new hpmixr[] = { | |
2633 | SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0), | |
2634 | SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0), | |
2635 | SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0), | |
2636 | SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0), | |
2637 | SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0), | |
2638 | SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0), | |
2639 | }; | |
2640 | ||
2641 | static const struct snd_kcontrol_new spkmixl[] = { | |
2642 | SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0), | |
2643 | SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0), | |
2644 | SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0), | |
2645 | SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0), | |
2646 | SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0), | |
2647 | SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0), | |
2648 | }; | |
2649 | ||
2650 | static const struct snd_kcontrol_new spkmixr[] = { | |
2651 | SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0), | |
2652 | SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0), | |
2653 | SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0), | |
2654 | SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0), | |
2655 | SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0), | |
2656 | SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0), | |
2657 | }; | |
2658 | ||
2659 | static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = { | |
2660 | SND_SOC_DAPM_INPUT("IN1L"), | |
2661 | SND_SOC_DAPM_INPUT("IN1R"), | |
2662 | SND_SOC_DAPM_INPUT("IN2L"), | |
2663 | SND_SOC_DAPM_INPUT("IN2R"), | |
2664 | SND_SOC_DAPM_INPUT("IN3L"), | |
2665 | SND_SOC_DAPM_INPUT("IN3R"), | |
2666 | SND_SOC_DAPM_INPUT("IN4L"), | |
2667 | SND_SOC_DAPM_INPUT("IN4R"), | |
2668 | SND_SOC_DAPM_INPUT("Beep"), | |
e47ac37c | 2669 | SND_SOC_DAPM_INPUT("DMICDAT"), |
9a76f1ff | 2670 | |
086d7f80 | 2671 | SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0), |
a4f28c00 | 2672 | |
9a76f1ff MB |
2673 | SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0), |
2674 | SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, sysclk_event, | |
2675 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
2676 | SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event, | |
2677 | SND_SOC_DAPM_POST_PMU), | |
2678 | SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0), | |
6f88a4e5 MB |
2679 | SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT, |
2680 | WM8962_DSP2_ENA_SHIFT, 0, dsp2_event, | |
2681 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
9a76f1ff MB |
2682 | |
2683 | SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0, | |
2684 | inpgal, ARRAY_SIZE(inpgal)), | |
2685 | SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0, | |
2686 | inpgar, ARRAY_SIZE(inpgar)), | |
2687 | SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0, | |
2688 | mixinl, ARRAY_SIZE(mixinl)), | |
2689 | SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0, | |
2690 | mixinr, ARRAY_SIZE(mixinr)), | |
2691 | ||
3f7d55a1 | 2692 | SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0), |
e47ac37c | 2693 | |
9a76f1ff MB |
2694 | SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0), |
2695 | SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0), | |
2696 | ||
2697 | SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux), | |
2698 | SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux), | |
2699 | ||
2700 | SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0), | |
2701 | SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0), | |
2702 | ||
2703 | SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2704 | SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2705 | ||
2706 | SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0, | |
2707 | hpmixl, ARRAY_SIZE(hpmixl)), | |
2708 | SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0, | |
2709 | hpmixr, ARRAY_SIZE(hpmixr)), | |
2710 | ||
2711 | SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux, | |
2712 | out_pga_event, SND_SOC_DAPM_POST_PMU), | |
2713 | SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux, | |
2714 | out_pga_event, SND_SOC_DAPM_POST_PMU), | |
2715 | ||
2716 | SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event, | |
2717 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
2718 | ||
2719 | SND_SOC_DAPM_OUTPUT("HPOUTL"), | |
2720 | SND_SOC_DAPM_OUTPUT("HPOUTR"), | |
2721 | }; | |
2722 | ||
2723 | static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = { | |
2724 | SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0, | |
2725 | spkmixl, ARRAY_SIZE(spkmixl)), | |
2726 | SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux, | |
2727 | out_pga_event, SND_SOC_DAPM_POST_PMU), | |
2728 | SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0), | |
2729 | SND_SOC_DAPM_OUTPUT("SPKOUT"), | |
2730 | }; | |
2731 | ||
2732 | static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = { | |
2733 | SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0, | |
2734 | spkmixl, ARRAY_SIZE(spkmixl)), | |
2735 | SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0, | |
2736 | spkmixr, ARRAY_SIZE(spkmixr)), | |
2737 | ||
2738 | SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux, | |
2739 | out_pga_event, SND_SOC_DAPM_POST_PMU), | |
2740 | SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux, | |
2741 | out_pga_event, SND_SOC_DAPM_POST_PMU), | |
2742 | ||
2743 | SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0), | |
2744 | SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0), | |
2745 | ||
2746 | SND_SOC_DAPM_OUTPUT("SPKOUTL"), | |
2747 | SND_SOC_DAPM_OUTPUT("SPKOUTR"), | |
2748 | }; | |
2749 | ||
2750 | static const struct snd_soc_dapm_route wm8962_intercon[] = { | |
2751 | { "INPGAL", "IN1L Switch", "IN1L" }, | |
2752 | { "INPGAL", "IN2L Switch", "IN2L" }, | |
2753 | { "INPGAL", "IN3L Switch", "IN3L" }, | |
2754 | { "INPGAL", "IN4L Switch", "IN4L" }, | |
2755 | ||
2756 | { "INPGAR", "IN1R Switch", "IN1R" }, | |
2757 | { "INPGAR", "IN2R Switch", "IN2R" }, | |
2758 | { "INPGAR", "IN3R Switch", "IN3R" }, | |
2759 | { "INPGAR", "IN4R Switch", "IN4R" }, | |
2760 | ||
2761 | { "MIXINL", "IN2L Switch", "IN2L" }, | |
2762 | { "MIXINL", "IN3L Switch", "IN3L" }, | |
2763 | { "MIXINL", "PGA Switch", "INPGAL" }, | |
2764 | ||
2765 | { "MIXINR", "IN2R Switch", "IN2R" }, | |
2766 | { "MIXINR", "IN3R Switch", "IN3R" }, | |
2767 | { "MIXINR", "PGA Switch", "INPGAR" }, | |
2768 | ||
821f4206 MB |
2769 | { "MICBIAS", NULL, "SYSCLK" }, |
2770 | ||
3f7d55a1 | 2771 | { "DMIC_ENA", NULL, "DMICDAT" }, |
e47ac37c | 2772 | |
9a76f1ff MB |
2773 | { "ADCL", NULL, "SYSCLK" }, |
2774 | { "ADCL", NULL, "TOCLK" }, | |
2775 | { "ADCL", NULL, "MIXINL" }, | |
3f7d55a1 | 2776 | { "ADCL", NULL, "DMIC_ENA" }, |
6f88a4e5 | 2777 | { "ADCL", NULL, "DSP2" }, |
9a76f1ff MB |
2778 | |
2779 | { "ADCR", NULL, "SYSCLK" }, | |
2780 | { "ADCR", NULL, "TOCLK" }, | |
2781 | { "ADCR", NULL, "MIXINR" }, | |
3f7d55a1 | 2782 | { "ADCR", NULL, "DMIC_ENA" }, |
6f88a4e5 | 2783 | { "ADCR", NULL, "DSP2" }, |
9a76f1ff MB |
2784 | |
2785 | { "STL", "Left", "ADCL" }, | |
2786 | { "STL", "Right", "ADCR" }, | |
2787 | ||
2788 | { "STR", "Left", "ADCL" }, | |
2789 | { "STR", "Right", "ADCR" }, | |
2790 | ||
2791 | { "DACL", NULL, "SYSCLK" }, | |
2792 | { "DACL", NULL, "TOCLK" }, | |
2793 | { "DACL", NULL, "Beep" }, | |
2794 | { "DACL", NULL, "STL" }, | |
6f88a4e5 | 2795 | { "DACL", NULL, "DSP2" }, |
9a76f1ff MB |
2796 | |
2797 | { "DACR", NULL, "SYSCLK" }, | |
2798 | { "DACR", NULL, "TOCLK" }, | |
2799 | { "DACR", NULL, "Beep" }, | |
2800 | { "DACR", NULL, "STR" }, | |
6f88a4e5 | 2801 | { "DACR", NULL, "DSP2" }, |
9a76f1ff MB |
2802 | |
2803 | { "HPMIXL", "IN4L Switch", "IN4L" }, | |
2804 | { "HPMIXL", "IN4R Switch", "IN4R" }, | |
2805 | { "HPMIXL", "DACL Switch", "DACL" }, | |
2806 | { "HPMIXL", "DACR Switch", "DACR" }, | |
2807 | { "HPMIXL", "MIXINL Switch", "MIXINL" }, | |
2808 | { "HPMIXL", "MIXINR Switch", "MIXINR" }, | |
2809 | ||
2810 | { "HPMIXR", "IN4L Switch", "IN4L" }, | |
2811 | { "HPMIXR", "IN4R Switch", "IN4R" }, | |
2812 | { "HPMIXR", "DACL Switch", "DACL" }, | |
2813 | { "HPMIXR", "DACR Switch", "DACR" }, | |
2814 | { "HPMIXR", "MIXINL Switch", "MIXINL" }, | |
2815 | { "HPMIXR", "MIXINR Switch", "MIXINR" }, | |
2816 | ||
2817 | { "Left Bypass", NULL, "HPMIXL" }, | |
2818 | { "Left Bypass", NULL, "Class G" }, | |
2819 | ||
2820 | { "Right Bypass", NULL, "HPMIXR" }, | |
2821 | { "Right Bypass", NULL, "Class G" }, | |
2822 | ||
2823 | { "HPOUTL PGA", "Mixer", "Left Bypass" }, | |
2824 | { "HPOUTL PGA", "DAC", "DACL" }, | |
2825 | ||
2826 | { "HPOUTR PGA", "Mixer", "Right Bypass" }, | |
2827 | { "HPOUTR PGA", "DAC", "DACR" }, | |
2828 | ||
2829 | { "HPOUT", NULL, "HPOUTL PGA" }, | |
2830 | { "HPOUT", NULL, "HPOUTR PGA" }, | |
2831 | { "HPOUT", NULL, "Charge Pump" }, | |
2832 | { "HPOUT", NULL, "SYSCLK" }, | |
2833 | { "HPOUT", NULL, "TOCLK" }, | |
2834 | ||
2835 | { "HPOUTL", NULL, "HPOUT" }, | |
2836 | { "HPOUTR", NULL, "HPOUT" }, | |
2837 | }; | |
2838 | ||
2839 | static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = { | |
2840 | { "Speaker Mixer", "IN4L Switch", "IN4L" }, | |
2841 | { "Speaker Mixer", "IN4R Switch", "IN4R" }, | |
2842 | { "Speaker Mixer", "DACL Switch", "DACL" }, | |
2843 | { "Speaker Mixer", "DACR Switch", "DACR" }, | |
2844 | { "Speaker Mixer", "MIXINL Switch", "MIXINL" }, | |
2845 | { "Speaker Mixer", "MIXINR Switch", "MIXINR" }, | |
2846 | ||
2847 | { "Speaker PGA", "Mixer", "Speaker Mixer" }, | |
2848 | { "Speaker PGA", "DAC", "DACL" }, | |
2849 | ||
2850 | { "Speaker Output", NULL, "Speaker PGA" }, | |
2851 | { "Speaker Output", NULL, "SYSCLK" }, | |
2852 | { "Speaker Output", NULL, "TOCLK" }, | |
2853 | ||
2854 | { "SPKOUT", NULL, "Speaker Output" }, | |
2855 | }; | |
2856 | ||
2857 | static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = { | |
2858 | { "SPKOUTL Mixer", "IN4L Switch", "IN4L" }, | |
2859 | { "SPKOUTL Mixer", "IN4R Switch", "IN4R" }, | |
2860 | { "SPKOUTL Mixer", "DACL Switch", "DACL" }, | |
2861 | { "SPKOUTL Mixer", "DACR Switch", "DACR" }, | |
2862 | { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" }, | |
2863 | { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" }, | |
2864 | ||
2865 | { "SPKOUTR Mixer", "IN4L Switch", "IN4L" }, | |
2866 | { "SPKOUTR Mixer", "IN4R Switch", "IN4R" }, | |
2867 | { "SPKOUTR Mixer", "DACL Switch", "DACL" }, | |
2868 | { "SPKOUTR Mixer", "DACR Switch", "DACR" }, | |
2869 | { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" }, | |
2870 | { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" }, | |
2871 | ||
2872 | { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" }, | |
2873 | { "SPKOUTL PGA", "DAC", "DACL" }, | |
2874 | ||
2875 | { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" }, | |
2876 | { "SPKOUTR PGA", "DAC", "DACR" }, | |
2877 | ||
2878 | { "SPKOUTL Output", NULL, "SPKOUTL PGA" }, | |
2879 | { "SPKOUTL Output", NULL, "SYSCLK" }, | |
2880 | { "SPKOUTL Output", NULL, "TOCLK" }, | |
2881 | ||
2882 | { "SPKOUTR Output", NULL, "SPKOUTR PGA" }, | |
2883 | { "SPKOUTR Output", NULL, "SYSCLK" }, | |
2884 | { "SPKOUTR Output", NULL, "TOCLK" }, | |
2885 | ||
2886 | { "SPKOUTL", NULL, "SPKOUTL Output" }, | |
2887 | { "SPKOUTR", NULL, "SPKOUTR Output" }, | |
2888 | }; | |
2889 | ||
2890 | static int wm8962_add_widgets(struct snd_soc_codec *codec) | |
2891 | { | |
2892 | struct wm8962_pdata *pdata = dev_get_platdata(codec->dev); | |
ce6120cc | 2893 | struct snd_soc_dapm_context *dapm = &codec->dapm; |
9a76f1ff MB |
2894 | |
2895 | snd_soc_add_controls(codec, wm8962_snd_controls, | |
2896 | ARRAY_SIZE(wm8962_snd_controls)); | |
2897 | if (pdata && pdata->spk_mono) | |
2898 | snd_soc_add_controls(codec, wm8962_spk_mono_controls, | |
2899 | ARRAY_SIZE(wm8962_spk_mono_controls)); | |
2900 | else | |
2901 | snd_soc_add_controls(codec, wm8962_spk_stereo_controls, | |
2902 | ARRAY_SIZE(wm8962_spk_stereo_controls)); | |
2903 | ||
2904 | ||
ce6120cc | 2905 | snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets, |
9a76f1ff MB |
2906 | ARRAY_SIZE(wm8962_dapm_widgets)); |
2907 | if (pdata && pdata->spk_mono) | |
ce6120cc | 2908 | snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets, |
9a76f1ff MB |
2909 | ARRAY_SIZE(wm8962_dapm_spk_mono_widgets)); |
2910 | else | |
ce6120cc | 2911 | snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets, |
9a76f1ff MB |
2912 | ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets)); |
2913 | ||
ce6120cc | 2914 | snd_soc_dapm_add_routes(dapm, wm8962_intercon, |
9a76f1ff MB |
2915 | ARRAY_SIZE(wm8962_intercon)); |
2916 | if (pdata && pdata->spk_mono) | |
ce6120cc | 2917 | snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon, |
9a76f1ff MB |
2918 | ARRAY_SIZE(wm8962_spk_mono_intercon)); |
2919 | else | |
ce6120cc | 2920 | snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon, |
9a76f1ff MB |
2921 | ARRAY_SIZE(wm8962_spk_stereo_intercon)); |
2922 | ||
2923 | ||
ce6120cc | 2924 | snd_soc_dapm_disable_pin(dapm, "Beep"); |
9a76f1ff MB |
2925 | |
2926 | return 0; | |
2927 | } | |
2928 | ||
2929 | static void wm8962_sync_cache(struct snd_soc_codec *codec) | |
2930 | { | |
7f87e30e | 2931 | u16 *reg_cache = codec->reg_cache; |
9a76f1ff MB |
2932 | int i; |
2933 | ||
2934 | if (!codec->cache_sync) | |
2935 | return; | |
2936 | ||
2937 | dev_dbg(codec->dev, "Syncing cache\n"); | |
2938 | ||
2939 | codec->cache_only = 0; | |
2940 | ||
2941 | /* Sync back cached values if they're different from the | |
2942 | * hardware default. | |
2943 | */ | |
7f87e30e | 2944 | for (i = 1; i < codec->driver->reg_cache_size; i++) { |
9a76f1ff MB |
2945 | if (i == WM8962_SOFTWARE_RESET) |
2946 | continue; | |
7f87e30e | 2947 | if (reg_cache[i] == wm8962_reg[i]) |
9a76f1ff MB |
2948 | continue; |
2949 | ||
7f87e30e | 2950 | snd_soc_write(codec, i, reg_cache[i]); |
9a76f1ff MB |
2951 | } |
2952 | ||
2953 | codec->cache_sync = 0; | |
2954 | } | |
2955 | ||
2956 | /* -1 for reserved values */ | |
2957 | static const int bclk_divs[] = { | |
2958 | 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32 | |
2959 | }; | |
2960 | ||
417ceff9 MB |
2961 | static const int sysclk_rates[] = { |
2962 | 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, | |
2963 | }; | |
2964 | ||
9a76f1ff MB |
2965 | static void wm8962_configure_bclk(struct snd_soc_codec *codec) |
2966 | { | |
2967 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
2968 | int dspclk, i; | |
2969 | int clocking2 = 0; | |
417ceff9 | 2970 | int clocking4 = 0; |
9a76f1ff MB |
2971 | int aif2 = 0; |
2972 | ||
417ceff9 MB |
2973 | if (!wm8962->sysclk_rate) { |
2974 | dev_dbg(codec->dev, "No SYSCLK configured\n"); | |
9a76f1ff MB |
2975 | return; |
2976 | } | |
2977 | ||
417ceff9 MB |
2978 | if (!wm8962->bclk || !wm8962->lrclk) { |
2979 | dev_dbg(codec->dev, "No audio clocks configured\n"); | |
2980 | return; | |
2981 | } | |
2982 | ||
2983 | for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) { | |
2984 | if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) { | |
2985 | clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT; | |
2986 | break; | |
2987 | } | |
2988 | } | |
2989 | ||
2990 | if (i == ARRAY_SIZE(sysclk_rates)) { | |
2991 | dev_err(codec->dev, "Unsupported sysclk ratio %d\n", | |
2992 | wm8962->sysclk_rate / wm8962->lrclk); | |
2993 | return; | |
2994 | } | |
2995 | ||
2996 | snd_soc_update_bits(codec, WM8962_CLOCKING_4, | |
2997 | WM8962_SYSCLK_RATE_MASK, clocking4); | |
2998 | ||
9a76f1ff MB |
2999 | dspclk = snd_soc_read(codec, WM8962_CLOCKING1); |
3000 | if (dspclk < 0) { | |
3001 | dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk); | |
3002 | return; | |
3003 | } | |
3004 | ||
3005 | dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT; | |
3006 | switch (dspclk) { | |
3007 | case 0: | |
3008 | dspclk = wm8962->sysclk_rate; | |
3009 | break; | |
3010 | case 1: | |
3011 | dspclk = wm8962->sysclk_rate / 2; | |
3012 | break; | |
3013 | case 2: | |
3014 | dspclk = wm8962->sysclk_rate / 4; | |
3015 | break; | |
3016 | default: | |
3017 | dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n"); | |
3018 | dspclk = wm8962->sysclk; | |
3019 | } | |
3020 | ||
3021 | dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk); | |
3022 | ||
3023 | /* We're expecting an exact match */ | |
3024 | for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { | |
3025 | if (bclk_divs[i] < 0) | |
3026 | continue; | |
3027 | ||
3028 | if (dspclk / bclk_divs[i] == wm8962->bclk) { | |
3029 | dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n", | |
3030 | bclk_divs[i], wm8962->bclk); | |
3031 | clocking2 |= i; | |
3032 | break; | |
3033 | } | |
3034 | } | |
3035 | if (i == ARRAY_SIZE(bclk_divs)) { | |
3036 | dev_err(codec->dev, "Unsupported BCLK ratio %d\n", | |
3037 | dspclk / wm8962->bclk); | |
3038 | return; | |
3039 | } | |
3040 | ||
3041 | aif2 |= wm8962->bclk / wm8962->lrclk; | |
3042 | dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n", | |
3043 | wm8962->bclk / wm8962->lrclk, wm8962->lrclk); | |
3044 | ||
3045 | snd_soc_update_bits(codec, WM8962_CLOCKING2, | |
3046 | WM8962_BCLK_DIV_MASK, clocking2); | |
3047 | snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2, | |
3048 | WM8962_AIF_RATE_MASK, aif2); | |
3049 | } | |
3050 | ||
3051 | static int wm8962_set_bias_level(struct snd_soc_codec *codec, | |
3052 | enum snd_soc_bias_level level) | |
3053 | { | |
3054 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
3055 | int ret; | |
3056 | ||
ce6120cc | 3057 | if (level == codec->dapm.bias_level) |
9a76f1ff MB |
3058 | return 0; |
3059 | ||
3060 | switch (level) { | |
3061 | case SND_SOC_BIAS_ON: | |
3062 | break; | |
3063 | ||
3064 | case SND_SOC_BIAS_PREPARE: | |
3065 | /* VMID 2*50k */ | |
3066 | snd_soc_update_bits(codec, WM8962_PWR_MGMT_1, | |
3067 | WM8962_VMID_SEL_MASK, 0x80); | |
417ceff9 MB |
3068 | |
3069 | wm8962_configure_bclk(codec); | |
9a76f1ff MB |
3070 | break; |
3071 | ||
3072 | case SND_SOC_BIAS_STANDBY: | |
ce6120cc | 3073 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
9a76f1ff MB |
3074 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies), |
3075 | wm8962->supplies); | |
3076 | if (ret != 0) { | |
3077 | dev_err(codec->dev, | |
3078 | "Failed to enable supplies: %d\n", | |
3079 | ret); | |
3080 | return ret; | |
3081 | } | |
3082 | ||
3083 | wm8962_sync_cache(codec); | |
3084 | ||
3085 | snd_soc_update_bits(codec, WM8962_ANTI_POP, | |
3086 | WM8962_STARTUP_BIAS_ENA | | |
3087 | WM8962_VMID_BUF_ENA, | |
3088 | WM8962_STARTUP_BIAS_ENA | | |
3089 | WM8962_VMID_BUF_ENA); | |
3090 | ||
3091 | /* Bias enable at 2*50k for ramp */ | |
3092 | snd_soc_update_bits(codec, WM8962_PWR_MGMT_1, | |
3093 | WM8962_VMID_SEL_MASK | | |
3094 | WM8962_BIAS_ENA, | |
3095 | WM8962_BIAS_ENA | 0x180); | |
3096 | ||
3097 | msleep(5); | |
9a76f1ff MB |
3098 | } |
3099 | ||
3100 | /* VMID 2*250k */ | |
3101 | snd_soc_update_bits(codec, WM8962_PWR_MGMT_1, | |
3102 | WM8962_VMID_SEL_MASK, 0x100); | |
3103 | break; | |
3104 | ||
3105 | case SND_SOC_BIAS_OFF: | |
3106 | snd_soc_update_bits(codec, WM8962_PWR_MGMT_1, | |
3107 | WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0); | |
3108 | ||
3109 | snd_soc_update_bits(codec, WM8962_ANTI_POP, | |
3110 | WM8962_STARTUP_BIAS_ENA | | |
3111 | WM8962_VMID_BUF_ENA, 0); | |
3112 | ||
3113 | regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), | |
3114 | wm8962->supplies); | |
3115 | break; | |
3116 | } | |
ce6120cc | 3117 | codec->dapm.bias_level = level; |
9a76f1ff MB |
3118 | return 0; |
3119 | } | |
3120 | ||
3121 | static const struct { | |
3122 | int rate; | |
3123 | int reg; | |
3124 | } sr_vals[] = { | |
3125 | { 48000, 0 }, | |
3126 | { 44100, 0 }, | |
3127 | { 32000, 1 }, | |
3128 | { 22050, 2 }, | |
3129 | { 24000, 2 }, | |
3130 | { 16000, 3 }, | |
3131 | { 11025, 4 }, | |
3132 | { 12000, 4 }, | |
3133 | { 8000, 5 }, | |
3134 | { 88200, 6 }, | |
3135 | { 96000, 6 }, | |
3136 | }; | |
3137 | ||
9a76f1ff MB |
3138 | static int wm8962_hw_params(struct snd_pcm_substream *substream, |
3139 | struct snd_pcm_hw_params *params, | |
3140 | struct snd_soc_dai *dai) | |
3141 | { | |
3142 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
54d8d0ae | 3143 | struct snd_soc_codec *codec = rtd->codec; |
9a76f1ff | 3144 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
9a76f1ff MB |
3145 | int i; |
3146 | int aif0 = 0; | |
3147 | int adctl3 = 0; | |
9a76f1ff MB |
3148 | |
3149 | wm8962->bclk = snd_soc_params_to_bclk(params); | |
3150 | wm8962->lrclk = params_rate(params); | |
3151 | ||
3152 | for (i = 0; i < ARRAY_SIZE(sr_vals); i++) { | |
417ceff9 | 3153 | if (sr_vals[i].rate == wm8962->lrclk) { |
9a76f1ff MB |
3154 | adctl3 |= sr_vals[i].reg; |
3155 | break; | |
3156 | } | |
3157 | } | |
3158 | if (i == ARRAY_SIZE(sr_vals)) { | |
417ceff9 | 3159 | dev_err(codec->dev, "Unsupported rate %dHz\n", wm8962->lrclk); |
9a76f1ff MB |
3160 | return -EINVAL; |
3161 | } | |
3162 | ||
417ceff9 | 3163 | if (wm8962->lrclk % 8000 == 0) |
9a76f1ff MB |
3164 | adctl3 |= WM8962_SAMPLE_RATE_INT_MODE; |
3165 | ||
9a76f1ff MB |
3166 | switch (params_format(params)) { |
3167 | case SNDRV_PCM_FORMAT_S16_LE: | |
3168 | break; | |
3169 | case SNDRV_PCM_FORMAT_S20_3LE: | |
3170 | aif0 |= 0x40; | |
3171 | break; | |
3172 | case SNDRV_PCM_FORMAT_S24_LE: | |
3173 | aif0 |= 0x80; | |
3174 | break; | |
3175 | case SNDRV_PCM_FORMAT_S32_LE: | |
3176 | aif0 |= 0xc0; | |
3177 | break; | |
3178 | default: | |
3179 | return -EINVAL; | |
3180 | } | |
3181 | ||
3182 | snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0, | |
3183 | WM8962_WL_MASK, aif0); | |
3184 | snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3, | |
3185 | WM8962_SAMPLE_RATE_INT_MODE | | |
3186 | WM8962_SAMPLE_RATE_MASK, adctl3); | |
9a76f1ff MB |
3187 | |
3188 | wm8962_configure_bclk(codec); | |
3189 | ||
3190 | return 0; | |
3191 | } | |
3192 | ||
3193 | static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, | |
3194 | unsigned int freq, int dir) | |
3195 | { | |
3196 | struct snd_soc_codec *codec = dai->codec; | |
3197 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
3198 | int src; | |
3199 | ||
3200 | switch (clk_id) { | |
3201 | case WM8962_SYSCLK_MCLK: | |
3202 | wm8962->sysclk = WM8962_SYSCLK_MCLK; | |
3203 | src = 0; | |
3204 | break; | |
3205 | case WM8962_SYSCLK_FLL: | |
3206 | wm8962->sysclk = WM8962_SYSCLK_FLL; | |
3207 | src = 1 << WM8962_SYSCLK_SRC_SHIFT; | |
9a76f1ff MB |
3208 | break; |
3209 | default: | |
3210 | return -EINVAL; | |
3211 | } | |
3212 | ||
3213 | snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK, | |
3214 | src); | |
3215 | ||
3216 | wm8962->sysclk_rate = freq; | |
3217 | ||
3218 | return 0; | |
3219 | } | |
3220 | ||
3221 | static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
3222 | { | |
3223 | struct snd_soc_codec *codec = dai->codec; | |
3224 | int aif0 = 0; | |
3225 | ||
3226 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
9a76f1ff | 3227 | case SND_SOC_DAIFMT_DSP_B: |
fbc7c62a SG |
3228 | aif0 |= WM8962_LRCLK_INV | 3; |
3229 | case SND_SOC_DAIFMT_DSP_A: | |
9a76f1ff MB |
3230 | aif0 |= 3; |
3231 | ||
3232 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
3233 | case SND_SOC_DAIFMT_NB_NF: | |
3234 | case SND_SOC_DAIFMT_IB_NF: | |
3235 | break; | |
3236 | default: | |
3237 | return -EINVAL; | |
3238 | } | |
3239 | break; | |
3240 | ||
3241 | case SND_SOC_DAIFMT_RIGHT_J: | |
3242 | break; | |
3243 | case SND_SOC_DAIFMT_LEFT_J: | |
3244 | aif0 |= 1; | |
3245 | break; | |
3246 | case SND_SOC_DAIFMT_I2S: | |
3247 | aif0 |= 2; | |
3248 | break; | |
3249 | default: | |
3250 | return -EINVAL; | |
3251 | } | |
3252 | ||
3253 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
3254 | case SND_SOC_DAIFMT_NB_NF: | |
3255 | break; | |
3256 | case SND_SOC_DAIFMT_IB_NF: | |
3257 | aif0 |= WM8962_BCLK_INV; | |
3258 | break; | |
3259 | case SND_SOC_DAIFMT_NB_IF: | |
3260 | aif0 |= WM8962_LRCLK_INV; | |
3261 | break; | |
3262 | case SND_SOC_DAIFMT_IB_IF: | |
3263 | aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV; | |
3264 | break; | |
3265 | default: | |
3266 | return -EINVAL; | |
3267 | } | |
3268 | ||
3269 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
3270 | case SND_SOC_DAIFMT_CBM_CFM: | |
3271 | aif0 |= WM8962_MSTR; | |
3272 | break; | |
3273 | case SND_SOC_DAIFMT_CBS_CFS: | |
3274 | break; | |
3275 | default: | |
3276 | return -EINVAL; | |
3277 | } | |
3278 | ||
3279 | snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0, | |
3280 | WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR | | |
3281 | WM8962_LRCLK_INV, aif0); | |
3282 | ||
3283 | return 0; | |
3284 | } | |
3285 | ||
3286 | struct _fll_div { | |
3287 | u16 fll_fratio; | |
3288 | u16 fll_outdiv; | |
3289 | u16 fll_refclk_div; | |
3290 | u16 n; | |
3291 | u16 theta; | |
3292 | u16 lambda; | |
3293 | }; | |
3294 | ||
3295 | /* The size in bits of the FLL divide multiplied by 10 | |
3296 | * to allow rounding later */ | |
3297 | #define FIXED_FLL_SIZE ((1 << 16) * 10) | |
3298 | ||
3299 | static struct { | |
3300 | unsigned int min; | |
3301 | unsigned int max; | |
3302 | u16 fll_fratio; | |
3303 | int ratio; | |
3304 | } fll_fratios[] = { | |
3305 | { 0, 64000, 4, 16 }, | |
3306 | { 64000, 128000, 3, 8 }, | |
3307 | { 128000, 256000, 2, 4 }, | |
3308 | { 256000, 1000000, 1, 2 }, | |
3309 | { 1000000, 13500000, 0, 1 }, | |
3310 | }; | |
3311 | ||
3312 | static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, | |
3313 | unsigned int Fout) | |
3314 | { | |
3315 | unsigned int target; | |
3316 | unsigned int div; | |
3317 | unsigned int fratio, gcd_fll; | |
3318 | int i; | |
3319 | ||
3320 | /* Fref must be <=13.5MHz */ | |
3321 | div = 1; | |
3322 | fll_div->fll_refclk_div = 0; | |
3323 | while ((Fref / div) > 13500000) { | |
3324 | div *= 2; | |
3325 | fll_div->fll_refclk_div++; | |
3326 | ||
3327 | if (div > 4) { | |
3328 | pr_err("Can't scale %dMHz input down to <=13.5MHz\n", | |
3329 | Fref); | |
3330 | return -EINVAL; | |
3331 | } | |
3332 | } | |
3333 | ||
3334 | pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout); | |
3335 | ||
3336 | /* Apply the division for our remaining calculations */ | |
3337 | Fref /= div; | |
3338 | ||
3339 | /* Fvco should be 90-100MHz; don't check the upper bound */ | |
3340 | div = 2; | |
3341 | while (Fout * div < 90000000) { | |
3342 | div++; | |
3343 | if (div > 64) { | |
3344 | pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", | |
3345 | Fout); | |
3346 | return -EINVAL; | |
3347 | } | |
3348 | } | |
3349 | target = Fout * div; | |
3350 | fll_div->fll_outdiv = div - 1; | |
3351 | ||
3352 | pr_debug("FLL Fvco=%dHz\n", target); | |
3353 | ||
25985edc | 3354 | /* Find an appropriate FLL_FRATIO and factor it out of the target */ |
9a76f1ff MB |
3355 | for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { |
3356 | if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { | |
3357 | fll_div->fll_fratio = fll_fratios[i].fll_fratio; | |
3358 | fratio = fll_fratios[i].ratio; | |
3359 | break; | |
3360 | } | |
3361 | } | |
3362 | if (i == ARRAY_SIZE(fll_fratios)) { | |
3363 | pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); | |
3364 | return -EINVAL; | |
3365 | } | |
3366 | ||
3367 | fll_div->n = target / (fratio * Fref); | |
3368 | ||
3369 | if (target % Fref == 0) { | |
3370 | fll_div->theta = 0; | |
3371 | fll_div->lambda = 0; | |
3372 | } else { | |
3373 | gcd_fll = gcd(target, fratio * Fref); | |
3374 | ||
3375 | fll_div->theta = (target - (fll_div->n * fratio * Fref)) | |
3376 | / gcd_fll; | |
3377 | fll_div->lambda = (fratio * Fref) / gcd_fll; | |
3378 | } | |
3379 | ||
3380 | pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n", | |
3381 | fll_div->n, fll_div->theta, fll_div->lambda); | |
3382 | pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n", | |
3383 | fll_div->fll_fratio, fll_div->fll_outdiv, | |
3384 | fll_div->fll_refclk_div); | |
3385 | ||
3386 | return 0; | |
3387 | } | |
3388 | ||
92a4352c | 3389 | static int wm8962_set_fll(struct snd_soc_codec *codec, int fll_id, int source, |
9a76f1ff MB |
3390 | unsigned int Fref, unsigned int Fout) |
3391 | { | |
9a76f1ff MB |
3392 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
3393 | struct _fll_div fll_div; | |
3b8a6d80 | 3394 | unsigned long timeout; |
9a76f1ff | 3395 | int ret; |
61371126 | 3396 | int fll1 = snd_soc_read(codec, WM8962_FLL_CONTROL_1) & WM8962_FLL_ENA; |
2a761cde | 3397 | int sysclk = snd_soc_read(codec, WM8962_CLOCKING2) & WM8962_SYSCLK_ENA; |
9a76f1ff MB |
3398 | |
3399 | /* Any change? */ | |
3400 | if (source == wm8962->fll_src && Fref == wm8962->fll_fref && | |
3401 | Fout == wm8962->fll_fout) | |
3402 | return 0; | |
3403 | ||
3404 | if (Fout == 0) { | |
3405 | dev_dbg(codec->dev, "FLL disabled\n"); | |
3406 | ||
3407 | wm8962->fll_fref = 0; | |
3408 | wm8962->fll_fout = 0; | |
3409 | ||
3410 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, | |
3411 | WM8962_FLL_ENA, 0); | |
3412 | ||
3413 | return 0; | |
3414 | } | |
3415 | ||
3416 | ret = fll_factors(&fll_div, Fref, Fout); | |
3417 | if (ret != 0) | |
3418 | return ret; | |
3419 | ||
3420 | switch (fll_id) { | |
3421 | case WM8962_FLL_MCLK: | |
3422 | case WM8962_FLL_BCLK: | |
3423 | case WM8962_FLL_OSC: | |
3424 | fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT; | |
3425 | break; | |
3426 | case WM8962_FLL_INT: | |
3427 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, | |
3428 | WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA); | |
3429 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5, | |
3430 | WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO); | |
3431 | break; | |
3432 | default: | |
3433 | dev_err(codec->dev, "Unknown FLL source %d\n", ret); | |
3434 | return -EINVAL; | |
3435 | } | |
3436 | ||
3437 | if (fll_div.theta || fll_div.lambda) | |
3438 | fll1 |= WM8962_FLL_FRAC; | |
3439 | ||
3440 | /* Stop the FLL while we reconfigure */ | |
3441 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0); | |
3442 | ||
3443 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2, | |
3444 | WM8962_FLL_OUTDIV_MASK | | |
3445 | WM8962_FLL_REFCLK_DIV_MASK, | |
3446 | (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) | | |
3447 | (fll_div.fll_refclk_div)); | |
3448 | ||
3449 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3, | |
3450 | WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio); | |
3451 | ||
3452 | snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta); | |
3453 | snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda); | |
3454 | snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n); | |
3455 | ||
4df0cb2f MB |
3456 | try_wait_for_completion(&wm8962->fll_lock); |
3457 | ||
2a761cde MB |
3458 | if (sysclk) |
3459 | fll1 |= WM8962_FLL_ENA; | |
3460 | ||
9a76f1ff MB |
3461 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, |
3462 | WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK | | |
3463 | WM8962_FLL_ENA, fll1); | |
3464 | ||
3465 | dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); | |
3466 | ||
649a1a0e | 3467 | ret = 0; |
3b8a6d80 | 3468 | |
649a1a0e MB |
3469 | if (fll1 & WM8962_FLL_ENA) { |
3470 | /* This should be a massive overestimate but go even | |
3471 | * higher if we'll error out | |
3472 | */ | |
3473 | if (wm8962->irq) | |
3474 | timeout = msecs_to_jiffies(5); | |
3475 | else | |
3476 | timeout = msecs_to_jiffies(1); | |
3477 | ||
3478 | timeout = wait_for_completion_timeout(&wm8962->fll_lock, | |
3479 | timeout); | |
3480 | ||
3481 | if (timeout == 0 && wm8962->irq) { | |
3482 | dev_err(codec->dev, "FLL lock timed out"); | |
3483 | ret = -ETIMEDOUT; | |
3484 | } | |
3485 | } | |
3b8a6d80 | 3486 | |
9a76f1ff MB |
3487 | wm8962->fll_fref = Fref; |
3488 | wm8962->fll_fout = Fout; | |
3489 | wm8962->fll_src = source; | |
3490 | ||
649a1a0e | 3491 | return ret; |
9a76f1ff MB |
3492 | } |
3493 | ||
3494 | static int wm8962_mute(struct snd_soc_dai *dai, int mute) | |
3495 | { | |
3496 | struct snd_soc_codec *codec = dai->codec; | |
3497 | int val; | |
3498 | ||
3499 | if (mute) | |
3500 | val = WM8962_DAC_MUTE; | |
3501 | else | |
3502 | val = 0; | |
3503 | ||
3504 | return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1, | |
3505 | WM8962_DAC_MUTE, val); | |
3506 | } | |
3507 | ||
3508 | #define WM8962_RATES SNDRV_PCM_RATE_8000_96000 | |
3509 | ||
3510 | #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
3511 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
3512 | ||
3513 | static struct snd_soc_dai_ops wm8962_dai_ops = { | |
3514 | .hw_params = wm8962_hw_params, | |
3515 | .set_sysclk = wm8962_set_dai_sysclk, | |
3516 | .set_fmt = wm8962_set_dai_fmt, | |
9a76f1ff MB |
3517 | .digital_mute = wm8962_mute, |
3518 | }; | |
3519 | ||
54d8d0ae MB |
3520 | static struct snd_soc_dai_driver wm8962_dai = { |
3521 | .name = "wm8962", | |
9a76f1ff MB |
3522 | .playback = { |
3523 | .stream_name = "Playback", | |
3524 | .channels_min = 2, | |
3525 | .channels_max = 2, | |
3526 | .rates = WM8962_RATES, | |
3527 | .formats = WM8962_FORMATS, | |
3528 | }, | |
3529 | .capture = { | |
3530 | .stream_name = "Capture", | |
3531 | .channels_min = 2, | |
3532 | .channels_max = 2, | |
3533 | .rates = WM8962_RATES, | |
3534 | .formats = WM8962_FORMATS, | |
3535 | }, | |
3536 | .ops = &wm8962_dai_ops, | |
3537 | .symmetric_rates = 1, | |
3538 | }; | |
9a76f1ff | 3539 | |
7711308a MB |
3540 | static void wm8962_mic_work(struct work_struct *work) |
3541 | { | |
3542 | struct wm8962_priv *wm8962 = container_of(work, | |
3543 | struct wm8962_priv, | |
3544 | mic_work.work); | |
3545 | struct snd_soc_codec *codec = wm8962->codec; | |
3546 | int status = 0; | |
3547 | int irq_pol = 0; | |
3548 | int reg; | |
3549 | ||
3550 | reg = snd_soc_read(codec, WM8962_ADDITIONAL_CONTROL_4); | |
3551 | ||
3552 | if (reg & WM8962_MICDET_STS) { | |
3553 | status |= SND_JACK_MICROPHONE; | |
3554 | irq_pol |= WM8962_MICD_IRQ_POL; | |
3555 | } | |
3556 | ||
3557 | if (reg & WM8962_MICSHORT_STS) { | |
3558 | status |= SND_JACK_BTN_0; | |
3559 | irq_pol |= WM8962_MICSCD_IRQ_POL; | |
3560 | } | |
3561 | ||
3562 | snd_soc_jack_report(wm8962->jack, status, | |
3563 | SND_JACK_MICROPHONE | SND_JACK_BTN_0); | |
3564 | ||
3565 | snd_soc_update_bits(codec, WM8962_MICINT_SOURCE_POL, | |
3566 | WM8962_MICSCD_IRQ_POL | | |
3567 | WM8962_MICD_IRQ_POL, irq_pol); | |
3568 | } | |
3569 | ||
45e65504 MB |
3570 | static irqreturn_t wm8962_irq(int irq, void *data) |
3571 | { | |
3572 | struct snd_soc_codec *codec = data; | |
7711308a | 3573 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
45e65504 MB |
3574 | int mask; |
3575 | int active; | |
fbf04076 | 3576 | int reg; |
45e65504 | 3577 | |
2a7b1a00 | 3578 | mask = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2_MASK); |
45e65504 MB |
3579 | |
3580 | active = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2); | |
3581 | active &= ~mask; | |
3582 | ||
e6ef5870 MB |
3583 | if (!active) |
3584 | return IRQ_NONE; | |
3585 | ||
3198b9eb MB |
3586 | /* Acknowledge the interrupts */ |
3587 | snd_soc_write(codec, WM8962_INTERRUPT_STATUS_2, active); | |
3588 | ||
3b8a6d80 MB |
3589 | if (active & WM8962_FLL_LOCK_EINT) { |
3590 | dev_dbg(codec->dev, "FLL locked\n"); | |
3591 | complete(&wm8962->fll_lock); | |
3592 | } | |
3593 | ||
45e65504 MB |
3594 | if (active & WM8962_FIFOS_ERR_EINT) |
3595 | dev_err(codec->dev, "FIFO error\n"); | |
3596 | ||
fbf04076 | 3597 | if (active & WM8962_TEMP_SHUT_EINT) { |
45e65504 MB |
3598 | dev_crit(codec->dev, "Thermal shutdown\n"); |
3599 | ||
fbf04076 MB |
3600 | reg = snd_soc_read(codec, WM8962_THERMAL_SHUTDOWN_STATUS); |
3601 | ||
3602 | if (reg & WM8962_TEMP_ERR_HP) | |
3603 | dev_crit(codec->dev, "Headphone thermal error\n"); | |
3604 | if (reg & WM8962_TEMP_WARN_HP) | |
3605 | dev_crit(codec->dev, "Headphone thermal warning\n"); | |
3606 | if (reg & WM8962_TEMP_ERR_SPK) | |
3607 | dev_crit(codec->dev, "Speaker thermal error\n"); | |
3608 | if (reg & WM8962_TEMP_WARN_SPK) | |
3609 | dev_crit(codec->dev, "Speaker thermal warning\n"); | |
3610 | } | |
3611 | ||
7711308a MB |
3612 | if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) { |
3613 | dev_dbg(codec->dev, "Microphone event detected\n"); | |
3614 | ||
6dc47e97 | 3615 | #ifndef CONFIG_SND_SOC_WM8962_MODULE |
2bbb5d66 | 3616 | trace_snd_soc_jack_irq(dev_name(codec->dev)); |
1435b940 | 3617 | #endif |
2bbb5d66 | 3618 | |
11e16eb3 MB |
3619 | pm_wakeup_event(codec->dev, 300); |
3620 | ||
7711308a MB |
3621 | schedule_delayed_work(&wm8962->mic_work, |
3622 | msecs_to_jiffies(250)); | |
3623 | } | |
3624 | ||
45e65504 MB |
3625 | return IRQ_HANDLED; |
3626 | } | |
3627 | ||
7711308a MB |
3628 | /** |
3629 | * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ | |
3630 | * | |
3631 | * @codec: WM8962 codec | |
3632 | * @jack: jack to report detection events on | |
3633 | * | |
3634 | * Enable microphone detection via IRQ on the WM8962. If GPIOs are | |
3635 | * being used to bring out signals to the processor then only platform | |
3636 | * data configuration is needed for WM8962 and processor GPIOs should | |
3637 | * be configured using snd_soc_jack_add_gpios() instead. | |
3638 | * | |
3639 | * If no jack is supplied detection will be disabled. | |
3640 | */ | |
3641 | int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack) | |
3642 | { | |
3643 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
3644 | int irq_mask, enable; | |
3645 | ||
3646 | wm8962->jack = jack; | |
3647 | if (jack) { | |
3648 | irq_mask = 0; | |
3649 | enable = WM8962_MICDET_ENA; | |
3650 | } else { | |
3651 | irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT; | |
3652 | enable = 0; | |
3653 | } | |
3654 | ||
3655 | snd_soc_update_bits(codec, WM8962_INTERRUPT_STATUS_2_MASK, | |
3656 | WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask); | |
3657 | snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4, | |
3658 | WM8962_MICDET_ENA, enable); | |
3659 | ||
3660 | /* Send an initial empty report */ | |
3661 | snd_soc_jack_report(wm8962->jack, 0, | |
3662 | SND_JACK_MICROPHONE | SND_JACK_BTN_0); | |
3663 | ||
a5ef9884 | 3664 | if (jack) { |
db0e5543 | 3665 | snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK"); |
a5ef9884 MB |
3666 | snd_soc_dapm_force_enable_pin(&codec->dapm, "MICBIAS"); |
3667 | } | |
db0e5543 | 3668 | |
7711308a MB |
3669 | return 0; |
3670 | } | |
3671 | EXPORT_SYMBOL_GPL(wm8962_mic_detect); | |
3672 | ||
9a76f1ff MB |
3673 | #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE) |
3674 | static int beep_rates[] = { | |
3675 | 500, 1000, 2000, 4000, | |
3676 | }; | |
3677 | ||
3678 | static void wm8962_beep_work(struct work_struct *work) | |
3679 | { | |
3680 | struct wm8962_priv *wm8962 = | |
3681 | container_of(work, struct wm8962_priv, beep_work); | |
54d8d0ae | 3682 | struct snd_soc_codec *codec = wm8962->codec; |
ce6120cc | 3683 | struct snd_soc_dapm_context *dapm = &codec->dapm; |
9a76f1ff MB |
3684 | int i; |
3685 | int reg = 0; | |
3686 | int best = 0; | |
3687 | ||
3688 | if (wm8962->beep_rate) { | |
3689 | for (i = 0; i < ARRAY_SIZE(beep_rates); i++) { | |
3690 | if (abs(wm8962->beep_rate - beep_rates[i]) < | |
3691 | abs(wm8962->beep_rate - beep_rates[best])) | |
3692 | best = i; | |
3693 | } | |
3694 | ||
3695 | dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n", | |
3696 | beep_rates[best], wm8962->beep_rate); | |
3697 | ||
3698 | reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT); | |
3699 | ||
ce6120cc | 3700 | snd_soc_dapm_enable_pin(dapm, "Beep"); |
9a76f1ff MB |
3701 | } else { |
3702 | dev_dbg(codec->dev, "Disabling beep\n"); | |
ce6120cc | 3703 | snd_soc_dapm_disable_pin(dapm, "Beep"); |
9a76f1ff MB |
3704 | } |
3705 | ||
3706 | snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, | |
3707 | WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg); | |
3708 | ||
ce6120cc | 3709 | snd_soc_dapm_sync(dapm); |
9a76f1ff MB |
3710 | } |
3711 | ||
3712 | /* For usability define a way of injecting beep events for the device - | |
3713 | * many systems will not have a keyboard. | |
3714 | */ | |
3715 | static int wm8962_beep_event(struct input_dev *dev, unsigned int type, | |
3716 | unsigned int code, int hz) | |
3717 | { | |
3718 | struct snd_soc_codec *codec = input_get_drvdata(dev); | |
3719 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
3720 | ||
3721 | dev_dbg(codec->dev, "Beep event %x %x\n", code, hz); | |
3722 | ||
3723 | switch (code) { | |
3724 | case SND_BELL: | |
3725 | if (hz) | |
3726 | hz = 1000; | |
3727 | case SND_TONE: | |
3728 | break; | |
3729 | default: | |
3730 | return -1; | |
3731 | } | |
3732 | ||
3733 | /* Kick the beep from a workqueue */ | |
3734 | wm8962->beep_rate = hz; | |
3735 | schedule_work(&wm8962->beep_work); | |
3736 | return 0; | |
3737 | } | |
3738 | ||
3739 | static ssize_t wm8962_beep_set(struct device *dev, | |
3740 | struct device_attribute *attr, | |
3741 | const char *buf, size_t count) | |
3742 | { | |
3743 | struct wm8962_priv *wm8962 = dev_get_drvdata(dev); | |
3744 | long int time; | |
74a557e2 | 3745 | int ret; |
9a76f1ff | 3746 | |
74a557e2 MB |
3747 | ret = strict_strtol(buf, 10, &time); |
3748 | if (ret != 0) | |
3749 | return ret; | |
9a76f1ff MB |
3750 | |
3751 | input_event(wm8962->beep, EV_SND, SND_TONE, time); | |
3752 | ||
3753 | return count; | |
3754 | } | |
3755 | ||
3756 | static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set); | |
3757 | ||
3758 | static void wm8962_init_beep(struct snd_soc_codec *codec) | |
3759 | { | |
3760 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
3761 | int ret; | |
3762 | ||
3763 | wm8962->beep = input_allocate_device(); | |
3764 | if (!wm8962->beep) { | |
3765 | dev_err(codec->dev, "Failed to allocate beep device\n"); | |
3766 | return; | |
3767 | } | |
3768 | ||
3769 | INIT_WORK(&wm8962->beep_work, wm8962_beep_work); | |
3770 | wm8962->beep_rate = 0; | |
3771 | ||
3772 | wm8962->beep->name = "WM8962 Beep Generator"; | |
3773 | wm8962->beep->phys = dev_name(codec->dev); | |
3774 | wm8962->beep->id.bustype = BUS_I2C; | |
3775 | ||
3776 | wm8962->beep->evbit[0] = BIT_MASK(EV_SND); | |
3777 | wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE); | |
3778 | wm8962->beep->event = wm8962_beep_event; | |
3779 | wm8962->beep->dev.parent = codec->dev; | |
3780 | input_set_drvdata(wm8962->beep, codec); | |
3781 | ||
3782 | ret = input_register_device(wm8962->beep); | |
3783 | if (ret != 0) { | |
3784 | input_free_device(wm8962->beep); | |
3785 | wm8962->beep = NULL; | |
3786 | dev_err(codec->dev, "Failed to register beep device\n"); | |
3787 | } | |
3788 | ||
3789 | ret = device_create_file(codec->dev, &dev_attr_beep); | |
3790 | if (ret != 0) { | |
3791 | dev_err(codec->dev, "Failed to create keyclick file: %d\n", | |
3792 | ret); | |
3793 | } | |
3794 | } | |
3795 | ||
3796 | static void wm8962_free_beep(struct snd_soc_codec *codec) | |
3797 | { | |
3798 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
3799 | ||
3800 | device_remove_file(codec->dev, &dev_attr_beep); | |
3801 | input_unregister_device(wm8962->beep); | |
3802 | cancel_work_sync(&wm8962->beep_work); | |
3803 | wm8962->beep = NULL; | |
3804 | ||
3805 | snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0); | |
3806 | } | |
3807 | #else | |
3808 | static void wm8962_init_beep(struct snd_soc_codec *codec) | |
3809 | { | |
3810 | } | |
3811 | ||
3812 | static void wm8962_free_beep(struct snd_soc_codec *codec) | |
3813 | { | |
3814 | } | |
3815 | #endif | |
3816 | ||
8ca2aa9c MB |
3817 | static void wm8962_set_gpio_mode(struct snd_soc_codec *codec, int gpio) |
3818 | { | |
3819 | int mask = 0; | |
3820 | int val = 0; | |
3821 | ||
3822 | /* Some of the GPIOs are behind MFP configuration and need to | |
3823 | * be put into GPIO mode. */ | |
3824 | switch (gpio) { | |
3825 | case 2: | |
3826 | mask = WM8962_CLKOUT2_SEL_MASK; | |
3827 | val = 1 << WM8962_CLKOUT2_SEL_SHIFT; | |
3828 | break; | |
3829 | case 3: | |
3830 | mask = WM8962_CLKOUT3_SEL_MASK; | |
3831 | val = 1 << WM8962_CLKOUT3_SEL_SHIFT; | |
3832 | break; | |
3833 | default: | |
3834 | break; | |
3835 | } | |
3836 | ||
3837 | if (mask) | |
3838 | snd_soc_update_bits(codec, WM8962_ANALOGUE_CLOCKING1, | |
3839 | mask, val); | |
3840 | } | |
3841 | ||
3367b8d4 MB |
3842 | #ifdef CONFIG_GPIOLIB |
3843 | static inline struct wm8962_priv *gpio_to_wm8962(struct gpio_chip *chip) | |
3844 | { | |
3845 | return container_of(chip, struct wm8962_priv, gpio_chip); | |
3846 | } | |
3847 | ||
3848 | static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset) | |
3849 | { | |
3850 | struct wm8962_priv *wm8962 = gpio_to_wm8962(chip); | |
3851 | struct snd_soc_codec *codec = wm8962->codec; | |
3367b8d4 MB |
3852 | |
3853 | /* The WM8962 GPIOs aren't linearly numbered. For simplicity | |
3854 | * we export linear numbers and error out if the unsupported | |
3855 | * ones are requsted. | |
3856 | */ | |
3857 | switch (offset + 1) { | |
3858 | case 2: | |
3367b8d4 | 3859 | case 3: |
3367b8d4 MB |
3860 | case 5: |
3861 | case 6: | |
3862 | break; | |
3863 | default: | |
3864 | return -EINVAL; | |
3865 | } | |
3866 | ||
8ca2aa9c | 3867 | wm8962_set_gpio_mode(codec, offset + 1); |
3367b8d4 MB |
3868 | |
3869 | return 0; | |
3870 | } | |
3871 | ||
3872 | static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
3873 | { | |
3874 | struct wm8962_priv *wm8962 = gpio_to_wm8962(chip); | |
3875 | struct snd_soc_codec *codec = wm8962->codec; | |
3876 | ||
3877 | snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset, | |
d71bb810 | 3878 | WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT); |
3367b8d4 MB |
3879 | } |
3880 | ||
3881 | static int wm8962_gpio_direction_out(struct gpio_chip *chip, | |
3882 | unsigned offset, int value) | |
3883 | { | |
3884 | struct wm8962_priv *wm8962 = gpio_to_wm8962(chip); | |
3885 | struct snd_soc_codec *codec = wm8962->codec; | |
3886 | int val; | |
3887 | ||
3888 | /* Force function 1 (logic output) */ | |
3889 | val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT); | |
3890 | ||
3891 | return snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset, | |
3892 | WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val); | |
3893 | } | |
3894 | ||
3895 | static struct gpio_chip wm8962_template_chip = { | |
3896 | .label = "wm8962", | |
3897 | .owner = THIS_MODULE, | |
3898 | .request = wm8962_gpio_request, | |
3899 | .direction_output = wm8962_gpio_direction_out, | |
3900 | .set = wm8962_gpio_set, | |
3901 | .can_sleep = 1, | |
3902 | }; | |
3903 | ||
3904 | static void wm8962_init_gpio(struct snd_soc_codec *codec) | |
3905 | { | |
3906 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
3907 | struct wm8962_pdata *pdata = dev_get_platdata(codec->dev); | |
3908 | int ret; | |
3909 | ||
3910 | wm8962->gpio_chip = wm8962_template_chip; | |
3911 | wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO; | |
3912 | wm8962->gpio_chip.dev = codec->dev; | |
3913 | ||
3914 | if (pdata && pdata->gpio_base) | |
3915 | wm8962->gpio_chip.base = pdata->gpio_base; | |
3916 | else | |
3917 | wm8962->gpio_chip.base = -1; | |
3918 | ||
3919 | ret = gpiochip_add(&wm8962->gpio_chip); | |
3920 | if (ret != 0) | |
3921 | dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret); | |
3922 | } | |
3923 | ||
3924 | static void wm8962_free_gpio(struct snd_soc_codec *codec) | |
3925 | { | |
3926 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
3927 | int ret; | |
3928 | ||
3929 | ret = gpiochip_remove(&wm8962->gpio_chip); | |
3930 | if (ret != 0) | |
3931 | dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret); | |
3932 | } | |
3933 | #else | |
3934 | static void wm8962_init_gpio(struct snd_soc_codec *codec) | |
3935 | { | |
3936 | } | |
3937 | ||
3938 | static void wm8962_free_gpio(struct snd_soc_codec *codec) | |
3939 | { | |
3940 | } | |
3941 | #endif | |
3942 | ||
54d8d0ae | 3943 | static int wm8962_probe(struct snd_soc_codec *codec) |
9a76f1ff MB |
3944 | { |
3945 | int ret; | |
54d8d0ae | 3946 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
9a76f1ff | 3947 | struct wm8962_pdata *pdata = dev_get_platdata(codec->dev); |
7f87e30e | 3948 | u16 *reg_cache = codec->reg_cache; |
45e65504 | 3949 | int i, trigger, irq_pol; |
e47ac37c | 3950 | bool dmicclk, dmicdat; |
9a76f1ff | 3951 | |
54d8d0ae | 3952 | wm8962->codec = codec; |
7711308a | 3953 | INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work); |
3b8a6d80 | 3954 | init_completion(&wm8962->fll_lock); |
9a76f1ff | 3955 | |
9a76f1ff | 3956 | codec->cache_sync = 1; |
ce6120cc | 3957 | codec->dapm.idle_bias_off = 1; |
9a76f1ff | 3958 | |
54d8d0ae | 3959 | ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C); |
9a76f1ff MB |
3960 | if (ret != 0) { |
3961 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); | |
3962 | goto err; | |
3963 | } | |
3964 | ||
3965 | for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) | |
3966 | wm8962->supplies[i].supply = wm8962_supply_names[i]; | |
3967 | ||
3968 | ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8962->supplies), | |
3969 | wm8962->supplies); | |
3970 | if (ret != 0) { | |
3971 | dev_err(codec->dev, "Failed to request supplies: %d\n", ret); | |
3972 | goto err; | |
3973 | } | |
3974 | ||
3975 | wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0; | |
3976 | wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1; | |
3977 | wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2; | |
3978 | wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3; | |
3979 | wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4; | |
3980 | wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5; | |
3981 | wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6; | |
3982 | wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7; | |
3983 | ||
3984 | /* This should really be moved into the regulator core */ | |
3985 | for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) { | |
3986 | ret = regulator_register_notifier(wm8962->supplies[i].consumer, | |
3987 | &wm8962->disable_nb[i]); | |
3988 | if (ret != 0) { | |
3989 | dev_err(codec->dev, | |
3990 | "Failed to register regulator notifier: %d\n", | |
3991 | ret); | |
3992 | } | |
3993 | } | |
3994 | ||
3995 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies), | |
3996 | wm8962->supplies); | |
3997 | if (ret != 0) { | |
3998 | dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); | |
3999 | goto err_get; | |
4000 | } | |
4001 | ||
4002 | ret = snd_soc_read(codec, WM8962_SOFTWARE_RESET); | |
4003 | if (ret < 0) { | |
4004 | dev_err(codec->dev, "Failed to read ID register\n"); | |
4005 | goto err_enable; | |
4006 | } | |
4007 | if (ret != wm8962_reg[WM8962_SOFTWARE_RESET]) { | |
4008 | dev_err(codec->dev, "Device is not a WM8962, ID %x != %x\n", | |
4009 | ret, wm8962_reg[WM8962_SOFTWARE_RESET]); | |
4010 | ret = -EINVAL; | |
4011 | goto err_enable; | |
4012 | } | |
4013 | ||
4014 | ret = snd_soc_read(codec, WM8962_RIGHT_INPUT_VOLUME); | |
4015 | if (ret < 0) { | |
4016 | dev_err(codec->dev, "Failed to read device revision: %d\n", | |
4017 | ret); | |
4018 | goto err_enable; | |
4019 | } | |
4020 | ||
4021 | dev_info(codec->dev, "customer id %x revision %c\n", | |
4022 | (ret & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT, | |
4023 | ((ret & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT) | |
4024 | + 'A'); | |
4025 | ||
4026 | ret = wm8962_reset(codec); | |
4027 | if (ret < 0) { | |
4028 | dev_err(codec->dev, "Failed to issue reset\n"); | |
4029 | goto err_enable; | |
4030 | } | |
4031 | ||
4032 | /* SYSCLK defaults to on; make sure it is off so we can safely | |
4033 | * write to registers if the device is declocked. | |
4034 | */ | |
4035 | snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0); | |
4036 | ||
a115c728 MB |
4037 | /* Ensure we have soft control over all registers */ |
4038 | snd_soc_update_bits(codec, WM8962_CLOCKING2, | |
4039 | WM8962_CLKREG_OVD, WM8962_CLKREG_OVD); | |
4040 | ||
9a76f1ff MB |
4041 | regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); |
4042 | ||
4043 | if (pdata) { | |
4044 | /* Apply static configuration for GPIOs */ | |
4045 | for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++) | |
8ca2aa9c MB |
4046 | if (pdata->gpio_init[i]) { |
4047 | wm8962_set_gpio_mode(codec, i + 1); | |
9a76f1ff MB |
4048 | snd_soc_write(codec, 0x200 + i, |
4049 | pdata->gpio_init[i] & 0xffff); | |
8ca2aa9c | 4050 | } |
9a76f1ff MB |
4051 | |
4052 | /* Put the speakers into mono mode? */ | |
4053 | if (pdata->spk_mono) | |
7f87e30e | 4054 | reg_cache[WM8962_CLASS_D_CONTROL_2] |
9a76f1ff | 4055 | |= WM8962_SPK_MONO; |
a4f28c00 MB |
4056 | |
4057 | /* Micbias setup, detection enable and detection | |
4058 | * threasholds. */ | |
4059 | if (pdata->mic_cfg) | |
4060 | snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4, | |
4061 | WM8962_MICDET_ENA | | |
4062 | WM8962_MICDET_THR_MASK | | |
4063 | WM8962_MICSHORT_THR_MASK | | |
4064 | WM8962_MICBIAS_LVL, | |
4065 | pdata->mic_cfg); | |
9a76f1ff MB |
4066 | } |
4067 | ||
4068 | /* Latch volume update bits */ | |
a1b3b5ee MB |
4069 | snd_soc_update_bits(codec, WM8962_LEFT_INPUT_VOLUME, |
4070 | WM8962_IN_VU, WM8962_IN_VU); | |
4071 | snd_soc_update_bits(codec, WM8962_RIGHT_INPUT_VOLUME, | |
4072 | WM8962_IN_VU, WM8962_IN_VU); | |
4073 | snd_soc_update_bits(codec, WM8962_LEFT_ADC_VOLUME, | |
4074 | WM8962_ADC_VU, WM8962_ADC_VU); | |
4075 | snd_soc_update_bits(codec, WM8962_RIGHT_ADC_VOLUME, | |
4076 | WM8962_ADC_VU, WM8962_ADC_VU); | |
4077 | snd_soc_update_bits(codec, WM8962_LEFT_DAC_VOLUME, | |
4078 | WM8962_DAC_VU, WM8962_DAC_VU); | |
4079 | snd_soc_update_bits(codec, WM8962_RIGHT_DAC_VOLUME, | |
4080 | WM8962_DAC_VU, WM8962_DAC_VU); | |
4081 | snd_soc_update_bits(codec, WM8962_SPKOUTL_VOLUME, | |
4082 | WM8962_SPKOUT_VU, WM8962_SPKOUT_VU); | |
4083 | snd_soc_update_bits(codec, WM8962_SPKOUTR_VOLUME, | |
4084 | WM8962_SPKOUT_VU, WM8962_SPKOUT_VU); | |
4085 | snd_soc_update_bits(codec, WM8962_HPOUTL_VOLUME, | |
4086 | WM8962_HPOUT_VU, WM8962_HPOUT_VU); | |
4087 | snd_soc_update_bits(codec, WM8962_HPOUTR_VOLUME, | |
4088 | WM8962_HPOUT_VU, WM8962_HPOUT_VU); | |
9a76f1ff | 4089 | |
8f63aaa8 MB |
4090 | /* Stereo control for EQ */ |
4091 | snd_soc_update_bits(codec, WM8962_EQ1, WM8962_EQ_SHARED_COEFF, 0); | |
4092 | ||
54d8d0ae | 4093 | wm8962_add_widgets(codec); |
9a76f1ff | 4094 | |
e47ac37c MB |
4095 | /* Save boards having to disable DMIC when not in use */ |
4096 | dmicclk = false; | |
4097 | dmicdat = false; | |
4098 | for (i = 0; i < WM8962_MAX_GPIO; i++) { | |
4099 | switch (snd_soc_read(codec, WM8962_GPIO_BASE + i) | |
4100 | & WM8962_GP2_FN_MASK) { | |
4101 | case WM8962_GPIO_FN_DMICCLK: | |
4102 | dmicclk = true; | |
4103 | break; | |
4104 | case WM8962_GPIO_FN_DMICDAT: | |
4105 | dmicdat = true; | |
4106 | break; | |
4107 | default: | |
4108 | break; | |
4109 | } | |
4110 | } | |
4111 | if (!dmicclk || !dmicdat) { | |
4112 | dev_dbg(codec->dev, "DMIC not in use, disabling\n"); | |
4113 | snd_soc_dapm_nc_pin(&codec->dapm, "DMICDAT"); | |
4114 | } | |
4115 | if (dmicclk != dmicdat) | |
4116 | dev_warn(codec->dev, "DMIC GPIOs partially configured\n"); | |
4117 | ||
9a76f1ff | 4118 | wm8962_init_beep(codec); |
3367b8d4 | 4119 | wm8962_init_gpio(codec); |
9a76f1ff | 4120 | |
c7356da9 | 4121 | if (wm8962->irq) { |
45e65504 MB |
4122 | if (pdata && pdata->irq_active_low) { |
4123 | trigger = IRQF_TRIGGER_LOW; | |
4124 | irq_pol = WM8962_IRQ_POL; | |
4125 | } else { | |
4126 | trigger = IRQF_TRIGGER_HIGH; | |
4127 | irq_pol = 0; | |
4128 | } | |
4129 | ||
4130 | snd_soc_update_bits(codec, WM8962_INTERRUPT_CONTROL, | |
4131 | WM8962_IRQ_POL, irq_pol); | |
4132 | ||
c7356da9 | 4133 | ret = request_threaded_irq(wm8962->irq, NULL, wm8962_irq, |
45e65504 MB |
4134 | trigger | IRQF_ONESHOT, |
4135 | "wm8962", codec); | |
4136 | if (ret != 0) { | |
4137 | dev_err(codec->dev, "Failed to request IRQ %d: %d\n", | |
c7356da9 MB |
4138 | wm8962->irq, ret); |
4139 | wm8962->irq = 0; | |
45e65504 MB |
4140 | /* Non-fatal */ |
4141 | } else { | |
3b8a6d80 | 4142 | /* Enable some IRQs by default */ |
45e65504 MB |
4143 | snd_soc_update_bits(codec, |
4144 | WM8962_INTERRUPT_STATUS_2_MASK, | |
3b8a6d80 | 4145 | WM8962_FLL_LOCK_EINT | |
45e65504 MB |
4146 | WM8962_TEMP_SHUT_EINT | |
4147 | WM8962_FIFOS_ERR_EINT, 0); | |
4148 | } | |
4149 | } | |
4150 | ||
9a76f1ff MB |
4151 | return 0; |
4152 | ||
4153 | err_enable: | |
4154 | regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); | |
4155 | err_get: | |
4156 | regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); | |
4157 | err: | |
9a76f1ff MB |
4158 | return ret; |
4159 | } | |
4160 | ||
54d8d0ae | 4161 | static int wm8962_remove(struct snd_soc_codec *codec) |
9a76f1ff | 4162 | { |
54d8d0ae | 4163 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
9a76f1ff MB |
4164 | int i; |
4165 | ||
c7356da9 MB |
4166 | if (wm8962->irq) |
4167 | free_irq(wm8962->irq, codec); | |
45e65504 | 4168 | |
7711308a MB |
4169 | cancel_delayed_work_sync(&wm8962->mic_work); |
4170 | ||
3367b8d4 | 4171 | wm8962_free_gpio(codec); |
54d8d0ae | 4172 | wm8962_free_beep(codec); |
9a76f1ff MB |
4173 | for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) |
4174 | regulator_unregister_notifier(wm8962->supplies[i].consumer, | |
4175 | &wm8962->disable_nb[i]); | |
4176 | regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); | |
54d8d0ae MB |
4177 | |
4178 | return 0; | |
9a76f1ff MB |
4179 | } |
4180 | ||
54d8d0ae MB |
4181 | static struct snd_soc_codec_driver soc_codec_dev_wm8962 = { |
4182 | .probe = wm8962_probe, | |
4183 | .remove = wm8962_remove, | |
54d8d0ae | 4184 | .set_bias_level = wm8962_set_bias_level, |
6946e037 | 4185 | .reg_cache_size = WM8962_MAX_REGISTER + 1, |
54d8d0ae MB |
4186 | .reg_word_size = sizeof(u16), |
4187 | .reg_cache_default = wm8962_reg, | |
4188 | .volatile_register = wm8962_volatile_register, | |
4189 | .readable_register = wm8962_readable_register, | |
92a4352c | 4190 | .set_pll = wm8962_set_fll, |
54d8d0ae MB |
4191 | }; |
4192 | ||
9a76f1ff MB |
4193 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
4194 | static __devinit int wm8962_i2c_probe(struct i2c_client *i2c, | |
4195 | const struct i2c_device_id *id) | |
4196 | { | |
4197 | struct wm8962_priv *wm8962; | |
54d8d0ae | 4198 | int ret; |
9a76f1ff MB |
4199 | |
4200 | wm8962 = kzalloc(sizeof(struct wm8962_priv), GFP_KERNEL); | |
4201 | if (wm8962 == NULL) | |
4202 | return -ENOMEM; | |
4203 | ||
9a76f1ff | 4204 | i2c_set_clientdata(i2c, wm8962); |
9a76f1ff | 4205 | |
c7356da9 MB |
4206 | wm8962->irq = i2c->irq; |
4207 | ||
54d8d0ae MB |
4208 | ret = snd_soc_register_codec(&i2c->dev, |
4209 | &soc_codec_dev_wm8962, &wm8962_dai, 1); | |
4210 | if (ret < 0) | |
4211 | kfree(wm8962); | |
9a76f1ff | 4212 | |
54d8d0ae | 4213 | return ret; |
9a76f1ff MB |
4214 | } |
4215 | ||
4216 | static __devexit int wm8962_i2c_remove(struct i2c_client *client) | |
4217 | { | |
54d8d0ae MB |
4218 | snd_soc_unregister_codec(&client->dev); |
4219 | kfree(i2c_get_clientdata(client)); | |
9a76f1ff MB |
4220 | return 0; |
4221 | } | |
4222 | ||
4223 | static const struct i2c_device_id wm8962_i2c_id[] = { | |
4224 | { "wm8962", 0 }, | |
4225 | { } | |
4226 | }; | |
4227 | MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id); | |
4228 | ||
4229 | static struct i2c_driver wm8962_i2c_driver = { | |
4230 | .driver = { | |
ea738bad | 4231 | .name = "wm8962", |
9a76f1ff MB |
4232 | .owner = THIS_MODULE, |
4233 | }, | |
4234 | .probe = wm8962_i2c_probe, | |
4235 | .remove = __devexit_p(wm8962_i2c_remove), | |
4236 | .id_table = wm8962_i2c_id, | |
4237 | }; | |
4238 | #endif | |
4239 | ||
4240 | static int __init wm8962_modinit(void) | |
4241 | { | |
4242 | int ret; | |
4243 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
4244 | ret = i2c_add_driver(&wm8962_i2c_driver); | |
4245 | if (ret != 0) { | |
4246 | printk(KERN_ERR "Failed to register WM8962 I2C driver: %d\n", | |
4247 | ret); | |
4248 | } | |
4249 | #endif | |
4250 | return 0; | |
4251 | } | |
4252 | module_init(wm8962_modinit); | |
4253 | ||
4254 | static void __exit wm8962_exit(void) | |
4255 | { | |
4256 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
4257 | i2c_del_driver(&wm8962_i2c_driver); | |
4258 | #endif | |
4259 | } | |
4260 | module_exit(wm8962_exit); | |
4261 | ||
4262 | MODULE_DESCRIPTION("ASoC WM8962 driver"); | |
4263 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
4264 | MODULE_LICENSE("GPL"); |