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9a76f1ff MB |
1 | /* |
2 | * wm8962.c -- WM8962 ALSA SoC Audio driver | |
3 | * | |
656baaeb | 4 | * Copyright 2010-2 Wolfson Microelectronics plc |
9a76f1ff MB |
5 | * |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/moduleparam.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/pm.h> | |
19 | #include <linux/gcd.h> | |
3367b8d4 | 20 | #include <linux/gpio.h> |
9a76f1ff MB |
21 | #include <linux/i2c.h> |
22 | #include <linux/input.h> | |
d23031a4 | 23 | #include <linux/pm_runtime.h> |
7b16f560 | 24 | #include <linux/regmap.h> |
9a76f1ff MB |
25 | #include <linux/regulator/consumer.h> |
26 | #include <linux/slab.h> | |
27 | #include <linux/workqueue.h> | |
28 | #include <sound/core.h> | |
7711308a | 29 | #include <sound/jack.h> |
9a76f1ff MB |
30 | #include <sound/pcm.h> |
31 | #include <sound/pcm_params.h> | |
32 | #include <sound/soc.h> | |
9a76f1ff MB |
33 | #include <sound/initval.h> |
34 | #include <sound/tlv.h> | |
35 | #include <sound/wm8962.h> | |
2bbb5d66 | 36 | #include <trace/events/asoc.h> |
9a76f1ff MB |
37 | |
38 | #include "wm8962.h" | |
39 | ||
9a76f1ff MB |
40 | #define WM8962_NUM_SUPPLIES 8 |
41 | static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = { | |
42 | "DCVDD", | |
43 | "DBVDD", | |
44 | "AVDD", | |
45 | "CPVDD", | |
46 | "MICVDD", | |
47 | "PLLVDD", | |
48 | "SPKVDD1", | |
49 | "SPKVDD2", | |
50 | }; | |
51 | ||
52 | /* codec private data */ | |
53 | struct wm8962_priv { | |
e75a52c6 | 54 | struct wm8962_pdata pdata; |
7b16f560 | 55 | struct regmap *regmap; |
54d8d0ae MB |
56 | struct snd_soc_codec *codec; |
57 | ||
9a76f1ff MB |
58 | int sysclk; |
59 | int sysclk_rate; | |
60 | ||
61 | int bclk; /* Desired BCLK */ | |
62 | int lrclk; | |
63 | ||
3b8a6d80 | 64 | struct completion fll_lock; |
9a76f1ff MB |
65 | int fll_src; |
66 | int fll_fref; | |
67 | int fll_fout; | |
68 | ||
6f88a4e5 MB |
69 | u16 dsp2_ena; |
70 | ||
7711308a MB |
71 | struct delayed_work mic_work; |
72 | struct snd_soc_jack *jack; | |
73 | ||
9a76f1ff MB |
74 | struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES]; |
75 | struct notifier_block disable_nb[WM8962_NUM_SUPPLIES]; | |
76 | ||
77 | #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE) | |
78 | struct input_dev *beep; | |
79 | struct work_struct beep_work; | |
80 | int beep_rate; | |
81 | #endif | |
3367b8d4 MB |
82 | |
83 | #ifdef CONFIG_GPIOLIB | |
84 | struct gpio_chip gpio_chip; | |
85 | #endif | |
c7356da9 MB |
86 | |
87 | int irq; | |
9a76f1ff MB |
88 | }; |
89 | ||
90 | /* We can't use the same notifier block for more than one supply and | |
91 | * there's no way I can see to get from a callback to the caller | |
92 | * except container_of(). | |
93 | */ | |
94 | #define WM8962_REGULATOR_EVENT(n) \ | |
95 | static int wm8962_regulator_event_##n(struct notifier_block *nb, \ | |
96 | unsigned long event, void *data) \ | |
97 | { \ | |
98 | struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \ | |
99 | disable_nb[n]); \ | |
100 | if (event & REGULATOR_EVENT_DISABLE) { \ | |
5539a102 | 101 | regcache_mark_dirty(wm8962->regmap); \ |
9a76f1ff MB |
102 | } \ |
103 | return 0; \ | |
104 | } | |
105 | ||
106 | WM8962_REGULATOR_EVENT(0) | |
107 | WM8962_REGULATOR_EVENT(1) | |
108 | WM8962_REGULATOR_EVENT(2) | |
109 | WM8962_REGULATOR_EVENT(3) | |
110 | WM8962_REGULATOR_EVENT(4) | |
111 | WM8962_REGULATOR_EVENT(5) | |
112 | WM8962_REGULATOR_EVENT(6) | |
113 | WM8962_REGULATOR_EVENT(7) | |
114 | ||
7b16f560 MB |
115 | static struct reg_default wm8962_reg[] = { |
116 | { 0, 0x009F }, /* R0 - Left Input volume */ | |
117 | { 1, 0x049F }, /* R1 - Right Input volume */ | |
118 | { 2, 0x0000 }, /* R2 - HPOUTL volume */ | |
119 | { 3, 0x0000 }, /* R3 - HPOUTR volume */ | |
ba106ce3 | 120 | |
7b16f560 MB |
121 | { 5, 0x0018 }, /* R5 - ADC & DAC Control 1 */ |
122 | { 6, 0x2008 }, /* R6 - ADC & DAC Control 2 */ | |
123 | { 7, 0x000A }, /* R7 - Audio Interface 0 */ | |
ba106ce3 | 124 | |
7b16f560 MB |
125 | { 9, 0x0300 }, /* R9 - Audio Interface 1 */ |
126 | { 10, 0x00C0 }, /* R10 - Left DAC volume */ | |
127 | { 11, 0x00C0 }, /* R11 - Right DAC volume */ | |
128 | ||
129 | { 14, 0x0040 }, /* R14 - Audio Interface 2 */ | |
130 | { 15, 0x6243 }, /* R15 - Software Reset */ | |
131 | ||
132 | { 17, 0x007B }, /* R17 - ALC1 */ | |
ba106ce3 | 133 | |
7b16f560 MB |
134 | { 19, 0x1C32 }, /* R19 - ALC3 */ |
135 | { 20, 0x3200 }, /* R20 - Noise Gate */ | |
136 | { 21, 0x00C0 }, /* R21 - Left ADC volume */ | |
137 | { 22, 0x00C0 }, /* R22 - Right ADC volume */ | |
138 | { 23, 0x0160 }, /* R23 - Additional control(1) */ | |
139 | { 24, 0x0000 }, /* R24 - Additional control(2) */ | |
140 | { 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */ | |
141 | { 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */ | |
142 | { 27, 0x0010 }, /* R27 - Additional Control (3) */ | |
143 | { 28, 0x0000 }, /* R28 - Anti-pop */ | |
144 | ||
145 | { 30, 0x005E }, /* R30 - Clocking 3 */ | |
146 | { 31, 0x0000 }, /* R31 - Input mixer control (1) */ | |
147 | { 32, 0x0145 }, /* R32 - Left input mixer volume */ | |
148 | { 33, 0x0145 }, /* R33 - Right input mixer volume */ | |
149 | { 34, 0x0009 }, /* R34 - Input mixer control (2) */ | |
150 | { 35, 0x0003 }, /* R35 - Input bias control */ | |
151 | { 37, 0x0008 }, /* R37 - Left input PGA control */ | |
152 | { 38, 0x0008 }, /* R38 - Right input PGA control */ | |
153 | ||
154 | { 40, 0x0000 }, /* R40 - SPKOUTL volume */ | |
155 | { 41, 0x0000 }, /* R41 - SPKOUTR volume */ | |
156 | ||
7b16f560 MB |
157 | { 51, 0x0003 }, /* R51 - Class D Control 2 */ |
158 | ||
159 | { 56, 0x0506 }, /* R56 - Clocking 4 */ | |
160 | { 57, 0x0000 }, /* R57 - DAC DSP Mixing (1) */ | |
161 | { 58, 0x0000 }, /* R58 - DAC DSP Mixing (2) */ | |
162 | ||
163 | { 60, 0x0300 }, /* R60 - DC Servo 0 */ | |
164 | { 61, 0x0300 }, /* R61 - DC Servo 1 */ | |
165 | ||
166 | { 64, 0x0810 }, /* R64 - DC Servo 4 */ | |
167 | ||
7b16f560 MB |
168 | { 68, 0x001B }, /* R68 - Analogue PGA Bias */ |
169 | { 69, 0x0000 }, /* R69 - Analogue HP 0 */ | |
170 | ||
171 | { 71, 0x01FB }, /* R71 - Analogue HP 2 */ | |
172 | { 72, 0x0000 }, /* R72 - Charge Pump 1 */ | |
173 | ||
174 | { 82, 0x0004 }, /* R82 - Charge Pump B */ | |
175 | ||
176 | { 87, 0x0000 }, /* R87 - Write Sequencer Control 1 */ | |
177 | ||
178 | { 90, 0x0000 }, /* R90 - Write Sequencer Control 2 */ | |
179 | ||
180 | { 93, 0x0000 }, /* R93 - Write Sequencer Control 3 */ | |
181 | { 94, 0x0000 }, /* R94 - Control Interface */ | |
182 | ||
183 | { 99, 0x0000 }, /* R99 - Mixer Enables */ | |
184 | { 100, 0x0000 }, /* R100 - Headphone Mixer (1) */ | |
185 | { 101, 0x0000 }, /* R101 - Headphone Mixer (2) */ | |
186 | { 102, 0x013F }, /* R102 - Headphone Mixer (3) */ | |
187 | { 103, 0x013F }, /* R103 - Headphone Mixer (4) */ | |
188 | ||
189 | { 105, 0x0000 }, /* R105 - Speaker Mixer (1) */ | |
190 | { 106, 0x0000 }, /* R106 - Speaker Mixer (2) */ | |
191 | { 107, 0x013F }, /* R107 - Speaker Mixer (3) */ | |
192 | { 108, 0x013F }, /* R108 - Speaker Mixer (4) */ | |
193 | { 109, 0x0003 }, /* R109 - Speaker Mixer (5) */ | |
194 | { 110, 0x0002 }, /* R110 - Beep Generator (1) */ | |
195 | ||
196 | { 115, 0x0006 }, /* R115 - Oscillator Trim (3) */ | |
197 | { 116, 0x0026 }, /* R116 - Oscillator Trim (4) */ | |
198 | ||
199 | { 119, 0x0000 }, /* R119 - Oscillator Trim (7) */ | |
200 | ||
201 | { 124, 0x0011 }, /* R124 - Analogue Clocking1 */ | |
202 | { 125, 0x004B }, /* R125 - Analogue Clocking2 */ | |
203 | { 126, 0x000D }, /* R126 - Analogue Clocking3 */ | |
204 | { 127, 0x0000 }, /* R127 - PLL Software Reset */ | |
205 | ||
7b16f560 MB |
206 | { 131, 0x0000 }, /* R131 - PLL 4 */ |
207 | ||
208 | { 136, 0x0067 }, /* R136 - PLL 9 */ | |
209 | { 137, 0x001C }, /* R137 - PLL 10 */ | |
210 | { 138, 0x0071 }, /* R138 - PLL 11 */ | |
211 | { 139, 0x00C7 }, /* R139 - PLL 12 */ | |
212 | { 140, 0x0067 }, /* R140 - PLL 13 */ | |
213 | { 141, 0x0048 }, /* R141 - PLL 14 */ | |
214 | { 142, 0x0022 }, /* R142 - PLL 15 */ | |
215 | { 143, 0x0097 }, /* R143 - PLL 16 */ | |
216 | ||
217 | { 155, 0x000C }, /* R155 - FLL Control (1) */ | |
218 | { 156, 0x0039 }, /* R156 - FLL Control (2) */ | |
219 | { 157, 0x0180 }, /* R157 - FLL Control (3) */ | |
220 | ||
221 | { 159, 0x0032 }, /* R159 - FLL Control (5) */ | |
222 | { 160, 0x0018 }, /* R160 - FLL Control (6) */ | |
223 | { 161, 0x007D }, /* R161 - FLL Control (7) */ | |
224 | { 162, 0x0008 }, /* R162 - FLL Control (8) */ | |
225 | ||
226 | { 252, 0x0005 }, /* R252 - General test 1 */ | |
227 | ||
228 | { 256, 0x0000 }, /* R256 - DF1 */ | |
229 | { 257, 0x0000 }, /* R257 - DF2 */ | |
230 | { 258, 0x0000 }, /* R258 - DF3 */ | |
231 | { 259, 0x0000 }, /* R259 - DF4 */ | |
232 | { 260, 0x0000 }, /* R260 - DF5 */ | |
233 | { 261, 0x0000 }, /* R261 - DF6 */ | |
234 | { 262, 0x0000 }, /* R262 - DF7 */ | |
235 | ||
236 | { 264, 0x0000 }, /* R264 - LHPF1 */ | |
237 | { 265, 0x0000 }, /* R265 - LHPF2 */ | |
238 | ||
239 | { 268, 0x0000 }, /* R268 - THREED1 */ | |
240 | { 269, 0x0000 }, /* R269 - THREED2 */ | |
241 | { 270, 0x0000 }, /* R270 - THREED3 */ | |
242 | { 271, 0x0000 }, /* R271 - THREED4 */ | |
243 | ||
244 | { 276, 0x000C }, /* R276 - DRC 1 */ | |
245 | { 277, 0x0925 }, /* R277 - DRC 2 */ | |
246 | { 278, 0x0000 }, /* R278 - DRC 3 */ | |
247 | { 279, 0x0000 }, /* R279 - DRC 4 */ | |
248 | { 280, 0x0000 }, /* R280 - DRC 5 */ | |
249 | ||
250 | { 285, 0x0000 }, /* R285 - Tloopback */ | |
251 | ||
252 | { 335, 0x0004 }, /* R335 - EQ1 */ | |
253 | { 336, 0x6318 }, /* R336 - EQ2 */ | |
254 | { 337, 0x6300 }, /* R337 - EQ3 */ | |
255 | { 338, 0x0FCA }, /* R338 - EQ4 */ | |
256 | { 339, 0x0400 }, /* R339 - EQ5 */ | |
257 | { 340, 0x00D8 }, /* R340 - EQ6 */ | |
258 | { 341, 0x1EB5 }, /* R341 - EQ7 */ | |
259 | { 342, 0xF145 }, /* R342 - EQ8 */ | |
260 | { 343, 0x0B75 }, /* R343 - EQ9 */ | |
261 | { 344, 0x01C5 }, /* R344 - EQ10 */ | |
262 | { 345, 0x1C58 }, /* R345 - EQ11 */ | |
263 | { 346, 0xF373 }, /* R346 - EQ12 */ | |
264 | { 347, 0x0A54 }, /* R347 - EQ13 */ | |
265 | { 348, 0x0558 }, /* R348 - EQ14 */ | |
266 | { 349, 0x168E }, /* R349 - EQ15 */ | |
267 | { 350, 0xF829 }, /* R350 - EQ16 */ | |
268 | { 351, 0x07AD }, /* R351 - EQ17 */ | |
269 | { 352, 0x1103 }, /* R352 - EQ18 */ | |
270 | { 353, 0x0564 }, /* R353 - EQ19 */ | |
271 | { 354, 0x0559 }, /* R354 - EQ20 */ | |
272 | { 355, 0x4000 }, /* R355 - EQ21 */ | |
273 | { 356, 0x6318 }, /* R356 - EQ22 */ | |
274 | { 357, 0x6300 }, /* R357 - EQ23 */ | |
275 | { 358, 0x0FCA }, /* R358 - EQ24 */ | |
276 | { 359, 0x0400 }, /* R359 - EQ25 */ | |
277 | { 360, 0x00D8 }, /* R360 - EQ26 */ | |
278 | { 361, 0x1EB5 }, /* R361 - EQ27 */ | |
279 | { 362, 0xF145 }, /* R362 - EQ28 */ | |
280 | { 363, 0x0B75 }, /* R363 - EQ29 */ | |
281 | { 364, 0x01C5 }, /* R364 - EQ30 */ | |
282 | { 365, 0x1C58 }, /* R365 - EQ31 */ | |
283 | { 366, 0xF373 }, /* R366 - EQ32 */ | |
284 | { 367, 0x0A54 }, /* R367 - EQ33 */ | |
285 | { 368, 0x0558 }, /* R368 - EQ34 */ | |
286 | { 369, 0x168E }, /* R369 - EQ35 */ | |
287 | { 370, 0xF829 }, /* R370 - EQ36 */ | |
288 | { 371, 0x07AD }, /* R371 - EQ37 */ | |
289 | { 372, 0x1103 }, /* R372 - EQ38 */ | |
290 | { 373, 0x0564 }, /* R373 - EQ39 */ | |
291 | { 374, 0x0559 }, /* R374 - EQ40 */ | |
292 | { 375, 0x4000 }, /* R375 - EQ41 */ | |
293 | ||
294 | { 513, 0x0000 }, /* R513 - GPIO 2 */ | |
295 | { 514, 0x0000 }, /* R514 - GPIO 3 */ | |
296 | ||
297 | { 516, 0x8100 }, /* R516 - GPIO 5 */ | |
298 | { 517, 0x8100 }, /* R517 - GPIO 6 */ | |
299 | ||
7b16f560 MB |
300 | { 568, 0x0030 }, /* R568 - Interrupt Status 1 Mask */ |
301 | { 569, 0xFFED }, /* R569 - Interrupt Status 2 Mask */ | |
302 | ||
303 | { 576, 0x0000 }, /* R576 - Interrupt Control */ | |
304 | ||
305 | { 584, 0x002D }, /* R584 - IRQ Debounce */ | |
306 | ||
307 | { 586, 0x0000 }, /* R586 - MICINT Source Pol */ | |
308 | ||
309 | { 768, 0x1C00 }, /* R768 - DSP2 Power Management */ | |
310 | ||
7b16f560 MB |
311 | { 8192, 0x0000 }, /* R8192 - DSP2 Instruction RAM 0 */ |
312 | ||
313 | { 9216, 0x0030 }, /* R9216 - DSP2 Address RAM 2 */ | |
314 | { 9217, 0x0000 }, /* R9217 - DSP2 Address RAM 1 */ | |
315 | { 9218, 0x0000 }, /* R9218 - DSP2 Address RAM 0 */ | |
316 | ||
317 | { 12288, 0x0000 }, /* R12288 - DSP2 Data1 RAM 1 */ | |
318 | { 12289, 0x0000 }, /* R12289 - DSP2 Data1 RAM 0 */ | |
319 | ||
320 | { 13312, 0x0000 }, /* R13312 - DSP2 Data2 RAM 1 */ | |
321 | { 13313, 0x0000 }, /* R13313 - DSP2 Data2 RAM 0 */ | |
322 | ||
323 | { 14336, 0x0000 }, /* R14336 - DSP2 Data3 RAM 1 */ | |
324 | { 14337, 0x0000 }, /* R14337 - DSP2 Data3 RAM 0 */ | |
325 | ||
326 | { 15360, 0x000A }, /* R15360 - DSP2 Coeff RAM 0 */ | |
327 | ||
328 | { 16384, 0x0000 }, /* R16384 - RETUNEADC_SHARED_COEFF_1 */ | |
329 | { 16385, 0x0000 }, /* R16385 - RETUNEADC_SHARED_COEFF_0 */ | |
330 | { 16386, 0x0000 }, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */ | |
331 | { 16387, 0x0000 }, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */ | |
332 | { 16388, 0x0000 }, /* R16388 - SOUNDSTAGE_ENABLES_1 */ | |
333 | { 16389, 0x0000 }, /* R16389 - SOUNDSTAGE_ENABLES_0 */ | |
334 | ||
335 | { 16896, 0x0002 }, /* R16896 - HDBASS_AI_1 */ | |
336 | { 16897, 0xBD12 }, /* R16897 - HDBASS_AI_0 */ | |
337 | { 16898, 0x007C }, /* R16898 - HDBASS_AR_1 */ | |
338 | { 16899, 0x586C }, /* R16899 - HDBASS_AR_0 */ | |
339 | { 16900, 0x0053 }, /* R16900 - HDBASS_B_1 */ | |
340 | { 16901, 0x8121 }, /* R16901 - HDBASS_B_0 */ | |
341 | { 16902, 0x003F }, /* R16902 - HDBASS_K_1 */ | |
342 | { 16903, 0x8BD8 }, /* R16903 - HDBASS_K_0 */ | |
343 | { 16904, 0x0032 }, /* R16904 - HDBASS_N1_1 */ | |
344 | { 16905, 0xF52D }, /* R16905 - HDBASS_N1_0 */ | |
345 | { 16906, 0x0065 }, /* R16906 - HDBASS_N2_1 */ | |
346 | { 16907, 0xAC8C }, /* R16907 - HDBASS_N2_0 */ | |
347 | { 16908, 0x006B }, /* R16908 - HDBASS_N3_1 */ | |
348 | { 16909, 0xE087 }, /* R16909 - HDBASS_N3_0 */ | |
349 | { 16910, 0x0072 }, /* R16910 - HDBASS_N4_1 */ | |
350 | { 16911, 0x1483 }, /* R16911 - HDBASS_N4_0 */ | |
351 | { 16912, 0x0072 }, /* R16912 - HDBASS_N5_1 */ | |
352 | { 16913, 0x1483 }, /* R16913 - HDBASS_N5_0 */ | |
353 | { 16914, 0x0043 }, /* R16914 - HDBASS_X1_1 */ | |
354 | { 16915, 0x3525 }, /* R16915 - HDBASS_X1_0 */ | |
355 | { 16916, 0x0006 }, /* R16916 - HDBASS_X2_1 */ | |
356 | { 16917, 0x6A4A }, /* R16917 - HDBASS_X2_0 */ | |
357 | { 16918, 0x0043 }, /* R16918 - HDBASS_X3_1 */ | |
358 | { 16919, 0x6079 }, /* R16919 - HDBASS_X3_0 */ | |
359 | { 16920, 0x0008 }, /* R16920 - HDBASS_ATK_1 */ | |
360 | { 16921, 0x0000 }, /* R16921 - HDBASS_ATK_0 */ | |
361 | { 16922, 0x0001 }, /* R16922 - HDBASS_DCY_1 */ | |
362 | { 16923, 0x0000 }, /* R16923 - HDBASS_DCY_0 */ | |
363 | { 16924, 0x0059 }, /* R16924 - HDBASS_PG_1 */ | |
364 | { 16925, 0x999A }, /* R16925 - HDBASS_PG_0 */ | |
365 | ||
366 | { 17048, 0x0083 }, /* R17408 - HPF_C_1 */ | |
367 | { 17049, 0x98AD }, /* R17409 - HPF_C_0 */ | |
368 | ||
369 | { 17920, 0x007F }, /* R17920 - ADCL_RETUNE_C1_1 */ | |
370 | { 17921, 0xFFFF }, /* R17921 - ADCL_RETUNE_C1_0 */ | |
371 | { 17922, 0x0000 }, /* R17922 - ADCL_RETUNE_C2_1 */ | |
372 | { 17923, 0x0000 }, /* R17923 - ADCL_RETUNE_C2_0 */ | |
373 | { 17924, 0x0000 }, /* R17924 - ADCL_RETUNE_C3_1 */ | |
374 | { 17925, 0x0000 }, /* R17925 - ADCL_RETUNE_C3_0 */ | |
375 | { 17926, 0x0000 }, /* R17926 - ADCL_RETUNE_C4_1 */ | |
376 | { 17927, 0x0000 }, /* R17927 - ADCL_RETUNE_C4_0 */ | |
377 | { 17928, 0x0000 }, /* R17928 - ADCL_RETUNE_C5_1 */ | |
378 | { 17929, 0x0000 }, /* R17929 - ADCL_RETUNE_C5_0 */ | |
379 | { 17930, 0x0000 }, /* R17930 - ADCL_RETUNE_C6_1 */ | |
380 | { 17931, 0x0000 }, /* R17931 - ADCL_RETUNE_C6_0 */ | |
381 | { 17932, 0x0000 }, /* R17932 - ADCL_RETUNE_C7_1 */ | |
382 | { 17933, 0x0000 }, /* R17933 - ADCL_RETUNE_C7_0 */ | |
383 | { 17934, 0x0000 }, /* R17934 - ADCL_RETUNE_C8_1 */ | |
384 | { 17935, 0x0000 }, /* R17935 - ADCL_RETUNE_C8_0 */ | |
385 | { 17936, 0x0000 }, /* R17936 - ADCL_RETUNE_C9_1 */ | |
386 | { 17937, 0x0000 }, /* R17937 - ADCL_RETUNE_C9_0 */ | |
387 | { 17938, 0x0000 }, /* R17938 - ADCL_RETUNE_C10_1 */ | |
388 | { 17939, 0x0000 }, /* R17939 - ADCL_RETUNE_C10_0 */ | |
389 | { 17940, 0x0000 }, /* R17940 - ADCL_RETUNE_C11_1 */ | |
390 | { 17941, 0x0000 }, /* R17941 - ADCL_RETUNE_C11_0 */ | |
391 | { 17942, 0x0000 }, /* R17942 - ADCL_RETUNE_C12_1 */ | |
392 | { 17943, 0x0000 }, /* R17943 - ADCL_RETUNE_C12_0 */ | |
393 | { 17944, 0x0000 }, /* R17944 - ADCL_RETUNE_C13_1 */ | |
394 | { 17945, 0x0000 }, /* R17945 - ADCL_RETUNE_C13_0 */ | |
395 | { 17946, 0x0000 }, /* R17946 - ADCL_RETUNE_C14_1 */ | |
396 | { 17947, 0x0000 }, /* R17947 - ADCL_RETUNE_C14_0 */ | |
397 | { 17948, 0x0000 }, /* R17948 - ADCL_RETUNE_C15_1 */ | |
398 | { 17949, 0x0000 }, /* R17949 - ADCL_RETUNE_C15_0 */ | |
399 | { 17950, 0x0000 }, /* R17950 - ADCL_RETUNE_C16_1 */ | |
400 | { 17951, 0x0000 }, /* R17951 - ADCL_RETUNE_C16_0 */ | |
401 | { 17952, 0x0000 }, /* R17952 - ADCL_RETUNE_C17_1 */ | |
402 | { 17953, 0x0000 }, /* R17953 - ADCL_RETUNE_C17_0 */ | |
403 | { 17954, 0x0000 }, /* R17954 - ADCL_RETUNE_C18_1 */ | |
404 | { 17955, 0x0000 }, /* R17955 - ADCL_RETUNE_C18_0 */ | |
405 | { 17956, 0x0000 }, /* R17956 - ADCL_RETUNE_C19_1 */ | |
406 | { 17957, 0x0000 }, /* R17957 - ADCL_RETUNE_C19_0 */ | |
407 | { 17958, 0x0000 }, /* R17958 - ADCL_RETUNE_C20_1 */ | |
408 | { 17959, 0x0000 }, /* R17959 - ADCL_RETUNE_C20_0 */ | |
409 | { 17960, 0x0000 }, /* R17960 - ADCL_RETUNE_C21_1 */ | |
410 | { 17961, 0x0000 }, /* R17961 - ADCL_RETUNE_C21_0 */ | |
411 | { 17962, 0x0000 }, /* R17962 - ADCL_RETUNE_C22_1 */ | |
412 | { 17963, 0x0000 }, /* R17963 - ADCL_RETUNE_C22_0 */ | |
413 | { 17964, 0x0000 }, /* R17964 - ADCL_RETUNE_C23_1 */ | |
414 | { 17965, 0x0000 }, /* R17965 - ADCL_RETUNE_C23_0 */ | |
415 | { 17966, 0x0000 }, /* R17966 - ADCL_RETUNE_C24_1 */ | |
416 | { 17967, 0x0000 }, /* R17967 - ADCL_RETUNE_C24_0 */ | |
417 | { 17968, 0x0000 }, /* R17968 - ADCL_RETUNE_C25_1 */ | |
418 | { 17969, 0x0000 }, /* R17969 - ADCL_RETUNE_C25_0 */ | |
419 | { 17970, 0x0000 }, /* R17970 - ADCL_RETUNE_C26_1 */ | |
420 | { 17971, 0x0000 }, /* R17971 - ADCL_RETUNE_C26_0 */ | |
421 | { 17972, 0x0000 }, /* R17972 - ADCL_RETUNE_C27_1 */ | |
422 | { 17973, 0x0000 }, /* R17973 - ADCL_RETUNE_C27_0 */ | |
423 | { 17974, 0x0000 }, /* R17974 - ADCL_RETUNE_C28_1 */ | |
424 | { 17975, 0x0000 }, /* R17975 - ADCL_RETUNE_C28_0 */ | |
425 | { 17976, 0x0000 }, /* R17976 - ADCL_RETUNE_C29_1 */ | |
426 | { 17977, 0x0000 }, /* R17977 - ADCL_RETUNE_C29_0 */ | |
427 | { 17978, 0x0000 }, /* R17978 - ADCL_RETUNE_C30_1 */ | |
428 | { 17979, 0x0000 }, /* R17979 - ADCL_RETUNE_C30_0 */ | |
429 | { 17980, 0x0000 }, /* R17980 - ADCL_RETUNE_C31_1 */ | |
430 | { 17981, 0x0000 }, /* R17981 - ADCL_RETUNE_C31_0 */ | |
431 | { 17982, 0x0000 }, /* R17982 - ADCL_RETUNE_C32_1 */ | |
432 | { 17983, 0x0000 }, /* R17983 - ADCL_RETUNE_C32_0 */ | |
433 | ||
434 | { 18432, 0x0020 }, /* R18432 - RETUNEADC_PG2_1 */ | |
435 | { 18433, 0x0000 }, /* R18433 - RETUNEADC_PG2_0 */ | |
436 | { 18434, 0x0040 }, /* R18434 - RETUNEADC_PG_1 */ | |
437 | { 18435, 0x0000 }, /* R18435 - RETUNEADC_PG_0 */ | |
438 | ||
439 | { 18944, 0x007F }, /* R18944 - ADCR_RETUNE_C1_1 */ | |
440 | { 18945, 0xFFFF }, /* R18945 - ADCR_RETUNE_C1_0 */ | |
441 | { 18946, 0x0000 }, /* R18946 - ADCR_RETUNE_C2_1 */ | |
442 | { 18947, 0x0000 }, /* R18947 - ADCR_RETUNE_C2_0 */ | |
443 | { 18948, 0x0000 }, /* R18948 - ADCR_RETUNE_C3_1 */ | |
444 | { 18949, 0x0000 }, /* R18949 - ADCR_RETUNE_C3_0 */ | |
445 | { 18950, 0x0000 }, /* R18950 - ADCR_RETUNE_C4_1 */ | |
446 | { 18951, 0x0000 }, /* R18951 - ADCR_RETUNE_C4_0 */ | |
447 | { 18952, 0x0000 }, /* R18952 - ADCR_RETUNE_C5_1 */ | |
448 | { 18953, 0x0000 }, /* R18953 - ADCR_RETUNE_C5_0 */ | |
449 | { 18954, 0x0000 }, /* R18954 - ADCR_RETUNE_C6_1 */ | |
450 | { 18955, 0x0000 }, /* R18955 - ADCR_RETUNE_C6_0 */ | |
451 | { 18956, 0x0000 }, /* R18956 - ADCR_RETUNE_C7_1 */ | |
452 | { 18957, 0x0000 }, /* R18957 - ADCR_RETUNE_C7_0 */ | |
453 | { 18958, 0x0000 }, /* R18958 - ADCR_RETUNE_C8_1 */ | |
454 | { 18959, 0x0000 }, /* R18959 - ADCR_RETUNE_C8_0 */ | |
455 | { 18960, 0x0000 }, /* R18960 - ADCR_RETUNE_C9_1 */ | |
456 | { 18961, 0x0000 }, /* R18961 - ADCR_RETUNE_C9_0 */ | |
457 | { 18962, 0x0000 }, /* R18962 - ADCR_RETUNE_C10_1 */ | |
458 | { 18963, 0x0000 }, /* R18963 - ADCR_RETUNE_C10_0 */ | |
459 | { 18964, 0x0000 }, /* R18964 - ADCR_RETUNE_C11_1 */ | |
460 | { 18965, 0x0000 }, /* R18965 - ADCR_RETUNE_C11_0 */ | |
461 | { 18966, 0x0000 }, /* R18966 - ADCR_RETUNE_C12_1 */ | |
462 | { 18967, 0x0000 }, /* R18967 - ADCR_RETUNE_C12_0 */ | |
463 | { 18968, 0x0000 }, /* R18968 - ADCR_RETUNE_C13_1 */ | |
464 | { 18969, 0x0000 }, /* R18969 - ADCR_RETUNE_C13_0 */ | |
465 | { 18970, 0x0000 }, /* R18970 - ADCR_RETUNE_C14_1 */ | |
466 | { 18971, 0x0000 }, /* R18971 - ADCR_RETUNE_C14_0 */ | |
467 | { 18972, 0x0000 }, /* R18972 - ADCR_RETUNE_C15_1 */ | |
468 | { 18973, 0x0000 }, /* R18973 - ADCR_RETUNE_C15_0 */ | |
469 | { 18974, 0x0000 }, /* R18974 - ADCR_RETUNE_C16_1 */ | |
470 | { 18975, 0x0000 }, /* R18975 - ADCR_RETUNE_C16_0 */ | |
471 | { 18976, 0x0000 }, /* R18976 - ADCR_RETUNE_C17_1 */ | |
472 | { 18977, 0x0000 }, /* R18977 - ADCR_RETUNE_C17_0 */ | |
473 | { 18978, 0x0000 }, /* R18978 - ADCR_RETUNE_C18_1 */ | |
474 | { 18979, 0x0000 }, /* R18979 - ADCR_RETUNE_C18_0 */ | |
475 | { 18980, 0x0000 }, /* R18980 - ADCR_RETUNE_C19_1 */ | |
476 | { 18981, 0x0000 }, /* R18981 - ADCR_RETUNE_C19_0 */ | |
477 | { 18982, 0x0000 }, /* R18982 - ADCR_RETUNE_C20_1 */ | |
478 | { 18983, 0x0000 }, /* R18983 - ADCR_RETUNE_C20_0 */ | |
479 | { 18984, 0x0000 }, /* R18984 - ADCR_RETUNE_C21_1 */ | |
480 | { 18985, 0x0000 }, /* R18985 - ADCR_RETUNE_C21_0 */ | |
481 | { 18986, 0x0000 }, /* R18986 - ADCR_RETUNE_C22_1 */ | |
482 | { 18987, 0x0000 }, /* R18987 - ADCR_RETUNE_C22_0 */ | |
483 | { 18988, 0x0000 }, /* R18988 - ADCR_RETUNE_C23_1 */ | |
484 | { 18989, 0x0000 }, /* R18989 - ADCR_RETUNE_C23_0 */ | |
485 | { 18990, 0x0000 }, /* R18990 - ADCR_RETUNE_C24_1 */ | |
486 | { 18991, 0x0000 }, /* R18991 - ADCR_RETUNE_C24_0 */ | |
487 | { 18992, 0x0000 }, /* R18992 - ADCR_RETUNE_C25_1 */ | |
488 | { 18993, 0x0000 }, /* R18993 - ADCR_RETUNE_C25_0 */ | |
489 | { 18994, 0x0000 }, /* R18994 - ADCR_RETUNE_C26_1 */ | |
490 | { 18995, 0x0000 }, /* R18995 - ADCR_RETUNE_C26_0 */ | |
491 | { 18996, 0x0000 }, /* R18996 - ADCR_RETUNE_C27_1 */ | |
492 | { 18997, 0x0000 }, /* R18997 - ADCR_RETUNE_C27_0 */ | |
493 | { 18998, 0x0000 }, /* R18998 - ADCR_RETUNE_C28_1 */ | |
494 | { 18999, 0x0000 }, /* R18999 - ADCR_RETUNE_C28_0 */ | |
495 | { 19000, 0x0000 }, /* R19000 - ADCR_RETUNE_C29_1 */ | |
496 | { 19001, 0x0000 }, /* R19001 - ADCR_RETUNE_C29_0 */ | |
497 | { 19002, 0x0000 }, /* R19002 - ADCR_RETUNE_C30_1 */ | |
498 | { 19003, 0x0000 }, /* R19003 - ADCR_RETUNE_C30_0 */ | |
499 | { 19004, 0x0000 }, /* R19004 - ADCR_RETUNE_C31_1 */ | |
500 | { 19005, 0x0000 }, /* R19005 - ADCR_RETUNE_C31_0 */ | |
501 | { 19006, 0x0000 }, /* R19006 - ADCR_RETUNE_C32_1 */ | |
502 | { 19007, 0x0000 }, /* R19007 - ADCR_RETUNE_C32_0 */ | |
503 | ||
504 | { 19456, 0x007F }, /* R19456 - DACL_RETUNE_C1_1 */ | |
505 | { 19457, 0xFFFF }, /* R19457 - DACL_RETUNE_C1_0 */ | |
506 | { 19458, 0x0000 }, /* R19458 - DACL_RETUNE_C2_1 */ | |
507 | { 19459, 0x0000 }, /* R19459 - DACL_RETUNE_C2_0 */ | |
508 | { 19460, 0x0000 }, /* R19460 - DACL_RETUNE_C3_1 */ | |
509 | { 19461, 0x0000 }, /* R19461 - DACL_RETUNE_C3_0 */ | |
510 | { 19462, 0x0000 }, /* R19462 - DACL_RETUNE_C4_1 */ | |
511 | { 19463, 0x0000 }, /* R19463 - DACL_RETUNE_C4_0 */ | |
512 | { 19464, 0x0000 }, /* R19464 - DACL_RETUNE_C5_1 */ | |
513 | { 19465, 0x0000 }, /* R19465 - DACL_RETUNE_C5_0 */ | |
514 | { 19466, 0x0000 }, /* R19466 - DACL_RETUNE_C6_1 */ | |
515 | { 19467, 0x0000 }, /* R19467 - DACL_RETUNE_C6_0 */ | |
516 | { 19468, 0x0000 }, /* R19468 - DACL_RETUNE_C7_1 */ | |
517 | { 19469, 0x0000 }, /* R19469 - DACL_RETUNE_C7_0 */ | |
518 | { 19470, 0x0000 }, /* R19470 - DACL_RETUNE_C8_1 */ | |
519 | { 19471, 0x0000 }, /* R19471 - DACL_RETUNE_C8_0 */ | |
520 | { 19472, 0x0000 }, /* R19472 - DACL_RETUNE_C9_1 */ | |
521 | { 19473, 0x0000 }, /* R19473 - DACL_RETUNE_C9_0 */ | |
522 | { 19474, 0x0000 }, /* R19474 - DACL_RETUNE_C10_1 */ | |
523 | { 19475, 0x0000 }, /* R19475 - DACL_RETUNE_C10_0 */ | |
524 | { 19476, 0x0000 }, /* R19476 - DACL_RETUNE_C11_1 */ | |
525 | { 19477, 0x0000 }, /* R19477 - DACL_RETUNE_C11_0 */ | |
526 | { 19478, 0x0000 }, /* R19478 - DACL_RETUNE_C12_1 */ | |
527 | { 19479, 0x0000 }, /* R19479 - DACL_RETUNE_C12_0 */ | |
528 | { 19480, 0x0000 }, /* R19480 - DACL_RETUNE_C13_1 */ | |
529 | { 19481, 0x0000 }, /* R19481 - DACL_RETUNE_C13_0 */ | |
530 | { 19482, 0x0000 }, /* R19482 - DACL_RETUNE_C14_1 */ | |
531 | { 19483, 0x0000 }, /* R19483 - DACL_RETUNE_C14_0 */ | |
532 | { 19484, 0x0000 }, /* R19484 - DACL_RETUNE_C15_1 */ | |
533 | { 19485, 0x0000 }, /* R19485 - DACL_RETUNE_C15_0 */ | |
534 | { 19486, 0x0000 }, /* R19486 - DACL_RETUNE_C16_1 */ | |
535 | { 19487, 0x0000 }, /* R19487 - DACL_RETUNE_C16_0 */ | |
536 | { 19488, 0x0000 }, /* R19488 - DACL_RETUNE_C17_1 */ | |
537 | { 19489, 0x0000 }, /* R19489 - DACL_RETUNE_C17_0 */ | |
538 | { 19490, 0x0000 }, /* R19490 - DACL_RETUNE_C18_1 */ | |
539 | { 19491, 0x0000 }, /* R19491 - DACL_RETUNE_C18_0 */ | |
540 | { 19492, 0x0000 }, /* R19492 - DACL_RETUNE_C19_1 */ | |
541 | { 19493, 0x0000 }, /* R19493 - DACL_RETUNE_C19_0 */ | |
542 | { 19494, 0x0000 }, /* R19494 - DACL_RETUNE_C20_1 */ | |
543 | { 19495, 0x0000 }, /* R19495 - DACL_RETUNE_C20_0 */ | |
544 | { 19496, 0x0000 }, /* R19496 - DACL_RETUNE_C21_1 */ | |
545 | { 19497, 0x0000 }, /* R19497 - DACL_RETUNE_C21_0 */ | |
546 | { 19498, 0x0000 }, /* R19498 - DACL_RETUNE_C22_1 */ | |
547 | { 19499, 0x0000 }, /* R19499 - DACL_RETUNE_C22_0 */ | |
548 | { 19500, 0x0000 }, /* R19500 - DACL_RETUNE_C23_1 */ | |
549 | { 19501, 0x0000 }, /* R19501 - DACL_RETUNE_C23_0 */ | |
550 | { 19502, 0x0000 }, /* R19502 - DACL_RETUNE_C24_1 */ | |
551 | { 19503, 0x0000 }, /* R19503 - DACL_RETUNE_C24_0 */ | |
552 | { 19504, 0x0000 }, /* R19504 - DACL_RETUNE_C25_1 */ | |
553 | { 19505, 0x0000 }, /* R19505 - DACL_RETUNE_C25_0 */ | |
554 | { 19506, 0x0000 }, /* R19506 - DACL_RETUNE_C26_1 */ | |
555 | { 19507, 0x0000 }, /* R19507 - DACL_RETUNE_C26_0 */ | |
556 | { 19508, 0x0000 }, /* R19508 - DACL_RETUNE_C27_1 */ | |
557 | { 19509, 0x0000 }, /* R19509 - DACL_RETUNE_C27_0 */ | |
558 | { 19510, 0x0000 }, /* R19510 - DACL_RETUNE_C28_1 */ | |
559 | { 19511, 0x0000 }, /* R19511 - DACL_RETUNE_C28_0 */ | |
560 | { 19512, 0x0000 }, /* R19512 - DACL_RETUNE_C29_1 */ | |
561 | { 19513, 0x0000 }, /* R19513 - DACL_RETUNE_C29_0 */ | |
562 | { 19514, 0x0000 }, /* R19514 - DACL_RETUNE_C30_1 */ | |
563 | { 19515, 0x0000 }, /* R19515 - DACL_RETUNE_C30_0 */ | |
564 | { 19516, 0x0000 }, /* R19516 - DACL_RETUNE_C31_1 */ | |
565 | { 19517, 0x0000 }, /* R19517 - DACL_RETUNE_C31_0 */ | |
566 | { 19518, 0x0000 }, /* R19518 - DACL_RETUNE_C32_1 */ | |
567 | { 19519, 0x0000 }, /* R19519 - DACL_RETUNE_C32_0 */ | |
568 | ||
569 | { 19968, 0x0020 }, /* R19968 - RETUNEDAC_PG2_1 */ | |
570 | { 19969, 0x0000 }, /* R19969 - RETUNEDAC_PG2_0 */ | |
571 | { 19970, 0x0040 }, /* R19970 - RETUNEDAC_PG_1 */ | |
572 | { 19971, 0x0000 }, /* R19971 - RETUNEDAC_PG_0 */ | |
573 | ||
574 | { 20480, 0x007F }, /* R20480 - DACR_RETUNE_C1_1 */ | |
575 | { 20481, 0xFFFF }, /* R20481 - DACR_RETUNE_C1_0 */ | |
576 | { 20482, 0x0000 }, /* R20482 - DACR_RETUNE_C2_1 */ | |
577 | { 20483, 0x0000 }, /* R20483 - DACR_RETUNE_C2_0 */ | |
578 | { 20484, 0x0000 }, /* R20484 - DACR_RETUNE_C3_1 */ | |
579 | { 20485, 0x0000 }, /* R20485 - DACR_RETUNE_C3_0 */ | |
580 | { 20486, 0x0000 }, /* R20486 - DACR_RETUNE_C4_1 */ | |
581 | { 20487, 0x0000 }, /* R20487 - DACR_RETUNE_C4_0 */ | |
582 | { 20488, 0x0000 }, /* R20488 - DACR_RETUNE_C5_1 */ | |
583 | { 20489, 0x0000 }, /* R20489 - DACR_RETUNE_C5_0 */ | |
584 | { 20490, 0x0000 }, /* R20490 - DACR_RETUNE_C6_1 */ | |
585 | { 20491, 0x0000 }, /* R20491 - DACR_RETUNE_C6_0 */ | |
586 | { 20492, 0x0000 }, /* R20492 - DACR_RETUNE_C7_1 */ | |
587 | { 20493, 0x0000 }, /* R20493 - DACR_RETUNE_C7_0 */ | |
588 | { 20494, 0x0000 }, /* R20494 - DACR_RETUNE_C8_1 */ | |
589 | { 20495, 0x0000 }, /* R20495 - DACR_RETUNE_C8_0 */ | |
590 | { 20496, 0x0000 }, /* R20496 - DACR_RETUNE_C9_1 */ | |
591 | { 20497, 0x0000 }, /* R20497 - DACR_RETUNE_C9_0 */ | |
592 | { 20498, 0x0000 }, /* R20498 - DACR_RETUNE_C10_1 */ | |
593 | { 20499, 0x0000 }, /* R20499 - DACR_RETUNE_C10_0 */ | |
594 | { 20500, 0x0000 }, /* R20500 - DACR_RETUNE_C11_1 */ | |
595 | { 20501, 0x0000 }, /* R20501 - DACR_RETUNE_C11_0 */ | |
596 | { 20502, 0x0000 }, /* R20502 - DACR_RETUNE_C12_1 */ | |
597 | { 20503, 0x0000 }, /* R20503 - DACR_RETUNE_C12_0 */ | |
598 | { 20504, 0x0000 }, /* R20504 - DACR_RETUNE_C13_1 */ | |
599 | { 20505, 0x0000 }, /* R20505 - DACR_RETUNE_C13_0 */ | |
600 | { 20506, 0x0000 }, /* R20506 - DACR_RETUNE_C14_1 */ | |
601 | { 20507, 0x0000 }, /* R20507 - DACR_RETUNE_C14_0 */ | |
602 | { 20508, 0x0000 }, /* R20508 - DACR_RETUNE_C15_1 */ | |
603 | { 20509, 0x0000 }, /* R20509 - DACR_RETUNE_C15_0 */ | |
604 | { 20510, 0x0000 }, /* R20510 - DACR_RETUNE_C16_1 */ | |
605 | { 20511, 0x0000 }, /* R20511 - DACR_RETUNE_C16_0 */ | |
606 | { 20512, 0x0000 }, /* R20512 - DACR_RETUNE_C17_1 */ | |
607 | { 20513, 0x0000 }, /* R20513 - DACR_RETUNE_C17_0 */ | |
608 | { 20514, 0x0000 }, /* R20514 - DACR_RETUNE_C18_1 */ | |
609 | { 20515, 0x0000 }, /* R20515 - DACR_RETUNE_C18_0 */ | |
610 | { 20516, 0x0000 }, /* R20516 - DACR_RETUNE_C19_1 */ | |
611 | { 20517, 0x0000 }, /* R20517 - DACR_RETUNE_C19_0 */ | |
612 | { 20518, 0x0000 }, /* R20518 - DACR_RETUNE_C20_1 */ | |
613 | { 20519, 0x0000 }, /* R20519 - DACR_RETUNE_C20_0 */ | |
614 | { 20520, 0x0000 }, /* R20520 - DACR_RETUNE_C21_1 */ | |
615 | { 20521, 0x0000 }, /* R20521 - DACR_RETUNE_C21_0 */ | |
616 | { 20522, 0x0000 }, /* R20522 - DACR_RETUNE_C22_1 */ | |
617 | { 20523, 0x0000 }, /* R20523 - DACR_RETUNE_C22_0 */ | |
618 | { 20524, 0x0000 }, /* R20524 - DACR_RETUNE_C23_1 */ | |
619 | { 20525, 0x0000 }, /* R20525 - DACR_RETUNE_C23_0 */ | |
620 | { 20526, 0x0000 }, /* R20526 - DACR_RETUNE_C24_1 */ | |
621 | { 20527, 0x0000 }, /* R20527 - DACR_RETUNE_C24_0 */ | |
622 | { 20528, 0x0000 }, /* R20528 - DACR_RETUNE_C25_1 */ | |
623 | { 20529, 0x0000 }, /* R20529 - DACR_RETUNE_C25_0 */ | |
624 | { 20530, 0x0000 }, /* R20530 - DACR_RETUNE_C26_1 */ | |
625 | { 20531, 0x0000 }, /* R20531 - DACR_RETUNE_C26_0 */ | |
626 | { 20532, 0x0000 }, /* R20532 - DACR_RETUNE_C27_1 */ | |
627 | { 20533, 0x0000 }, /* R20533 - DACR_RETUNE_C27_0 */ | |
628 | { 20534, 0x0000 }, /* R20534 - DACR_RETUNE_C28_1 */ | |
629 | { 20535, 0x0000 }, /* R20535 - DACR_RETUNE_C28_0 */ | |
630 | { 20536, 0x0000 }, /* R20536 - DACR_RETUNE_C29_1 */ | |
631 | { 20537, 0x0000 }, /* R20537 - DACR_RETUNE_C29_0 */ | |
632 | { 20538, 0x0000 }, /* R20538 - DACR_RETUNE_C30_1 */ | |
633 | { 20539, 0x0000 }, /* R20539 - DACR_RETUNE_C30_0 */ | |
634 | { 20540, 0x0000 }, /* R20540 - DACR_RETUNE_C31_1 */ | |
635 | { 20541, 0x0000 }, /* R20541 - DACR_RETUNE_C31_0 */ | |
636 | { 20542, 0x0000 }, /* R20542 - DACR_RETUNE_C32_1 */ | |
637 | { 20543, 0x0000 }, /* R20543 - DACR_RETUNE_C32_0 */ | |
638 | ||
639 | { 20992, 0x008C }, /* R20992 - VSS_XHD2_1 */ | |
640 | { 20993, 0x0200 }, /* R20993 - VSS_XHD2_0 */ | |
641 | { 20994, 0x0035 }, /* R20994 - VSS_XHD3_1 */ | |
642 | { 20995, 0x0700 }, /* R20995 - VSS_XHD3_0 */ | |
643 | { 20996, 0x003A }, /* R20996 - VSS_XHN1_1 */ | |
644 | { 20997, 0x4100 }, /* R20997 - VSS_XHN1_0 */ | |
645 | { 20998, 0x008B }, /* R20998 - VSS_XHN2_1 */ | |
646 | { 20999, 0x7D00 }, /* R20999 - VSS_XHN2_0 */ | |
647 | { 21000, 0x003A }, /* R21000 - VSS_XHN3_1 */ | |
648 | { 21001, 0x4100 }, /* R21001 - VSS_XHN3_0 */ | |
649 | { 21002, 0x008C }, /* R21002 - VSS_XLA_1 */ | |
650 | { 21003, 0xFEE8 }, /* R21003 - VSS_XLA_0 */ | |
651 | { 21004, 0x0078 }, /* R21004 - VSS_XLB_1 */ | |
652 | { 21005, 0x0000 }, /* R21005 - VSS_XLB_0 */ | |
653 | { 21006, 0x003F }, /* R21006 - VSS_XLG_1 */ | |
654 | { 21007, 0xB260 }, /* R21007 - VSS_XLG_0 */ | |
655 | { 21008, 0x002D }, /* R21008 - VSS_PG2_1 */ | |
656 | { 21009, 0x1818 }, /* R21009 - VSS_PG2_0 */ | |
657 | { 21010, 0x0020 }, /* R21010 - VSS_PG_1 */ | |
658 | { 21011, 0x0000 }, /* R21011 - VSS_PG_0 */ | |
659 | { 21012, 0x00F1 }, /* R21012 - VSS_XTD1_1 */ | |
660 | { 21013, 0x8340 }, /* R21013 - VSS_XTD1_0 */ | |
661 | { 21014, 0x00FB }, /* R21014 - VSS_XTD2_1 */ | |
662 | { 21015, 0x8300 }, /* R21015 - VSS_XTD2_0 */ | |
663 | { 21016, 0x00EE }, /* R21016 - VSS_XTD3_1 */ | |
664 | { 21017, 0xAEC0 }, /* R21017 - VSS_XTD3_0 */ | |
665 | { 21018, 0x00FB }, /* R21018 - VSS_XTD4_1 */ | |
666 | { 21019, 0xAC40 }, /* R21019 - VSS_XTD4_0 */ | |
667 | { 21020, 0x00F1 }, /* R21020 - VSS_XTD5_1 */ | |
668 | { 21021, 0x7F80 }, /* R21021 - VSS_XTD5_0 */ | |
669 | { 21022, 0x00F4 }, /* R21022 - VSS_XTD6_1 */ | |
670 | { 21023, 0x3B40 }, /* R21023 - VSS_XTD6_0 */ | |
671 | { 21024, 0x00F5 }, /* R21024 - VSS_XTD7_1 */ | |
672 | { 21025, 0xFB00 }, /* R21025 - VSS_XTD7_0 */ | |
673 | { 21026, 0x00EA }, /* R21026 - VSS_XTD8_1 */ | |
674 | { 21027, 0x10C0 }, /* R21027 - VSS_XTD8_0 */ | |
675 | { 21028, 0x00FC }, /* R21028 - VSS_XTD9_1 */ | |
676 | { 21029, 0xC580 }, /* R21029 - VSS_XTD9_0 */ | |
677 | { 21030, 0x00E2 }, /* R21030 - VSS_XTD10_1 */ | |
678 | { 21031, 0x75C0 }, /* R21031 - VSS_XTD10_0 */ | |
679 | { 21032, 0x0004 }, /* R21032 - VSS_XTD11_1 */ | |
680 | { 21033, 0xB480 }, /* R21033 - VSS_XTD11_0 */ | |
681 | { 21034, 0x00D4 }, /* R21034 - VSS_XTD12_1 */ | |
682 | { 21035, 0xF980 }, /* R21035 - VSS_XTD12_0 */ | |
683 | { 21036, 0x0004 }, /* R21036 - VSS_XTD13_1 */ | |
684 | { 21037, 0x9140 }, /* R21037 - VSS_XTD13_0 */ | |
685 | { 21038, 0x00D8 }, /* R21038 - VSS_XTD14_1 */ | |
686 | { 21039, 0xA480 }, /* R21039 - VSS_XTD14_0 */ | |
687 | { 21040, 0x0002 }, /* R21040 - VSS_XTD15_1 */ | |
688 | { 21041, 0x3DC0 }, /* R21041 - VSS_XTD15_0 */ | |
689 | { 21042, 0x00CF }, /* R21042 - VSS_XTD16_1 */ | |
690 | { 21043, 0x7A80 }, /* R21043 - VSS_XTD16_0 */ | |
691 | { 21044, 0x00DC }, /* R21044 - VSS_XTD17_1 */ | |
692 | { 21045, 0x0600 }, /* R21045 - VSS_XTD17_0 */ | |
693 | { 21046, 0x00F2 }, /* R21046 - VSS_XTD18_1 */ | |
694 | { 21047, 0xDAC0 }, /* R21047 - VSS_XTD18_0 */ | |
695 | { 21048, 0x00BA }, /* R21048 - VSS_XTD19_1 */ | |
696 | { 21049, 0xF340 }, /* R21049 - VSS_XTD19_0 */ | |
697 | { 21050, 0x000A }, /* R21050 - VSS_XTD20_1 */ | |
698 | { 21051, 0x7940 }, /* R21051 - VSS_XTD20_0 */ | |
699 | { 21052, 0x001C }, /* R21052 - VSS_XTD21_1 */ | |
700 | { 21053, 0x0680 }, /* R21053 - VSS_XTD21_0 */ | |
701 | { 21054, 0x00FD }, /* R21054 - VSS_XTD22_1 */ | |
702 | { 21055, 0x2D00 }, /* R21055 - VSS_XTD22_0 */ | |
703 | { 21056, 0x001C }, /* R21056 - VSS_XTD23_1 */ | |
704 | { 21057, 0xE840 }, /* R21057 - VSS_XTD23_0 */ | |
705 | { 21058, 0x000D }, /* R21058 - VSS_XTD24_1 */ | |
706 | { 21059, 0xDC40 }, /* R21059 - VSS_XTD24_0 */ | |
707 | { 21060, 0x00FC }, /* R21060 - VSS_XTD25_1 */ | |
708 | { 21061, 0x9D00 }, /* R21061 - VSS_XTD25_0 */ | |
709 | { 21062, 0x0009 }, /* R21062 - VSS_XTD26_1 */ | |
710 | { 21063, 0x5580 }, /* R21063 - VSS_XTD26_0 */ | |
711 | { 21064, 0x00FE }, /* R21064 - VSS_XTD27_1 */ | |
712 | { 21065, 0x7E80 }, /* R21065 - VSS_XTD27_0 */ | |
713 | { 21066, 0x000E }, /* R21066 - VSS_XTD28_1 */ | |
714 | { 21067, 0xAB40 }, /* R21067 - VSS_XTD28_0 */ | |
715 | { 21068, 0x00F9 }, /* R21068 - VSS_XTD29_1 */ | |
716 | { 21069, 0x9880 }, /* R21069 - VSS_XTD29_0 */ | |
717 | { 21070, 0x0009 }, /* R21070 - VSS_XTD30_1 */ | |
718 | { 21071, 0x87C0 }, /* R21071 - VSS_XTD30_0 */ | |
719 | { 21072, 0x00FD }, /* R21072 - VSS_XTD31_1 */ | |
720 | { 21073, 0x2C40 }, /* R21073 - VSS_XTD31_0 */ | |
721 | { 21074, 0x0009 }, /* R21074 - VSS_XTD32_1 */ | |
722 | { 21075, 0x4800 }, /* R21075 - VSS_XTD32_0 */ | |
723 | { 21076, 0x0003 }, /* R21076 - VSS_XTS1_1 */ | |
724 | { 21077, 0x5F40 }, /* R21077 - VSS_XTS1_0 */ | |
725 | { 21078, 0x0000 }, /* R21078 - VSS_XTS2_1 */ | |
726 | { 21079, 0x8700 }, /* R21079 - VSS_XTS2_0 */ | |
727 | { 21080, 0x00FA }, /* R21080 - VSS_XTS3_1 */ | |
728 | { 21081, 0xE4C0 }, /* R21081 - VSS_XTS3_0 */ | |
729 | { 21082, 0x0000 }, /* R21082 - VSS_XTS4_1 */ | |
730 | { 21083, 0x0B40 }, /* R21083 - VSS_XTS4_0 */ | |
731 | { 21084, 0x0004 }, /* R21084 - VSS_XTS5_1 */ | |
732 | { 21085, 0xE180 }, /* R21085 - VSS_XTS5_0 */ | |
733 | { 21086, 0x0001 }, /* R21086 - VSS_XTS6_1 */ | |
734 | { 21087, 0x1F40 }, /* R21087 - VSS_XTS6_0 */ | |
735 | { 21088, 0x00F8 }, /* R21088 - VSS_XTS7_1 */ | |
736 | { 21089, 0xB000 }, /* R21089 - VSS_XTS7_0 */ | |
737 | { 21090, 0x00FB }, /* R21090 - VSS_XTS8_1 */ | |
738 | { 21091, 0xCBC0 }, /* R21091 - VSS_XTS8_0 */ | |
739 | { 21092, 0x0004 }, /* R21092 - VSS_XTS9_1 */ | |
740 | { 21093, 0xF380 }, /* R21093 - VSS_XTS9_0 */ | |
741 | { 21094, 0x0007 }, /* R21094 - VSS_XTS10_1 */ | |
742 | { 21095, 0xDF40 }, /* R21095 - VSS_XTS10_0 */ | |
743 | { 21096, 0x00FF }, /* R21096 - VSS_XTS11_1 */ | |
744 | { 21097, 0x0700 }, /* R21097 - VSS_XTS11_0 */ | |
745 | { 21098, 0x00EF }, /* R21098 - VSS_XTS12_1 */ | |
746 | { 21099, 0xD700 }, /* R21099 - VSS_XTS12_0 */ | |
747 | { 21100, 0x00FB }, /* R21100 - VSS_XTS13_1 */ | |
748 | { 21101, 0xAF40 }, /* R21101 - VSS_XTS13_0 */ | |
749 | { 21102, 0x0010 }, /* R21102 - VSS_XTS14_1 */ | |
750 | { 21103, 0x8A80 }, /* R21103 - VSS_XTS14_0 */ | |
751 | { 21104, 0x0011 }, /* R21104 - VSS_XTS15_1 */ | |
752 | { 21105, 0x07C0 }, /* R21105 - VSS_XTS15_0 */ | |
753 | { 21106, 0x00E0 }, /* R21106 - VSS_XTS16_1 */ | |
754 | { 21107, 0x0800 }, /* R21107 - VSS_XTS16_0 */ | |
755 | { 21108, 0x00D2 }, /* R21108 - VSS_XTS17_1 */ | |
756 | { 21109, 0x7600 }, /* R21109 - VSS_XTS17_0 */ | |
757 | { 21110, 0x0020 }, /* R21110 - VSS_XTS18_1 */ | |
758 | { 21111, 0xCF40 }, /* R21111 - VSS_XTS18_0 */ | |
759 | { 21112, 0x0030 }, /* R21112 - VSS_XTS19_1 */ | |
760 | { 21113, 0x2340 }, /* R21113 - VSS_XTS19_0 */ | |
761 | { 21114, 0x00FD }, /* R21114 - VSS_XTS20_1 */ | |
762 | { 21115, 0x69C0 }, /* R21115 - VSS_XTS20_0 */ | |
763 | { 21116, 0x0028 }, /* R21116 - VSS_XTS21_1 */ | |
764 | { 21117, 0x3500 }, /* R21117 - VSS_XTS21_0 */ | |
765 | { 21118, 0x0006 }, /* R21118 - VSS_XTS22_1 */ | |
766 | { 21119, 0x3300 }, /* R21119 - VSS_XTS22_0 */ | |
767 | { 21120, 0x00D9 }, /* R21120 - VSS_XTS23_1 */ | |
768 | { 21121, 0xF6C0 }, /* R21121 - VSS_XTS23_0 */ | |
769 | { 21122, 0x00F3 }, /* R21122 - VSS_XTS24_1 */ | |
770 | { 21123, 0x3340 }, /* R21123 - VSS_XTS24_0 */ | |
771 | { 21124, 0x000F }, /* R21124 - VSS_XTS25_1 */ | |
772 | { 21125, 0x4200 }, /* R21125 - VSS_XTS25_0 */ | |
773 | { 21126, 0x0004 }, /* R21126 - VSS_XTS26_1 */ | |
774 | { 21127, 0x0C80 }, /* R21127 - VSS_XTS26_0 */ | |
775 | { 21128, 0x00FB }, /* R21128 - VSS_XTS27_1 */ | |
776 | { 21129, 0x3F80 }, /* R21129 - VSS_XTS27_0 */ | |
777 | { 21130, 0x00F7 }, /* R21130 - VSS_XTS28_1 */ | |
778 | { 21131, 0x57C0 }, /* R21131 - VSS_XTS28_0 */ | |
779 | { 21132, 0x0003 }, /* R21132 - VSS_XTS29_1 */ | |
780 | { 21133, 0x5400 }, /* R21133 - VSS_XTS29_0 */ | |
781 | { 21134, 0x0000 }, /* R21134 - VSS_XTS30_1 */ | |
782 | { 21135, 0xC6C0 }, /* R21135 - VSS_XTS30_0 */ | |
783 | { 21136, 0x0003 }, /* R21136 - VSS_XTS31_1 */ | |
784 | { 21137, 0x12C0 }, /* R21137 - VSS_XTS31_0 */ | |
785 | { 21138, 0x00FD }, /* R21138 - VSS_XTS32_1 */ | |
786 | { 21139, 0x8580 }, /* R21139 - VSS_XTS32_0 */ | |
f57f6c04 MB |
787 | }; |
788 | ||
7b16f560 | 789 | static bool wm8962_volatile_register(struct device *dev, unsigned int reg) |
9a76f1ff | 790 | { |
cef6d1d4 MB |
791 | switch (reg) { |
792 | case WM8962_CLOCKING1: | |
793 | case WM8962_CLOCKING2: | |
794 | case WM8962_SOFTWARE_RESET: | |
795 | case WM8962_ALC2: | |
796 | case WM8962_THERMAL_SHUTDOWN_STATUS: | |
797 | case WM8962_ADDITIONAL_CONTROL_4: | |
798 | case WM8962_CLASS_D_CONTROL_1: | |
799 | case WM8962_DC_SERVO_6: | |
800 | case WM8962_INTERRUPT_STATUS_1: | |
801 | case WM8962_INTERRUPT_STATUS_2: | |
802 | case WM8962_DSP2_EXECCONTROL: | |
803 | return true; | |
804 | default: | |
805 | return false; | |
806 | } | |
9a76f1ff MB |
807 | } |
808 | ||
7b16f560 | 809 | static bool wm8962_readable_register(struct device *dev, unsigned int reg) |
9a76f1ff | 810 | { |
cef6d1d4 MB |
811 | switch (reg) { |
812 | case WM8962_LEFT_INPUT_VOLUME: | |
813 | case WM8962_RIGHT_INPUT_VOLUME: | |
814 | case WM8962_HPOUTL_VOLUME: | |
815 | case WM8962_HPOUTR_VOLUME: | |
816 | case WM8962_CLOCKING1: | |
817 | case WM8962_ADC_DAC_CONTROL_1: | |
818 | case WM8962_ADC_DAC_CONTROL_2: | |
819 | case WM8962_AUDIO_INTERFACE_0: | |
820 | case WM8962_CLOCKING2: | |
821 | case WM8962_AUDIO_INTERFACE_1: | |
822 | case WM8962_LEFT_DAC_VOLUME: | |
823 | case WM8962_RIGHT_DAC_VOLUME: | |
824 | case WM8962_AUDIO_INTERFACE_2: | |
825 | case WM8962_SOFTWARE_RESET: | |
826 | case WM8962_ALC1: | |
827 | case WM8962_ALC2: | |
828 | case WM8962_ALC3: | |
829 | case WM8962_NOISE_GATE: | |
830 | case WM8962_LEFT_ADC_VOLUME: | |
831 | case WM8962_RIGHT_ADC_VOLUME: | |
832 | case WM8962_ADDITIONAL_CONTROL_1: | |
833 | case WM8962_ADDITIONAL_CONTROL_2: | |
834 | case WM8962_PWR_MGMT_1: | |
835 | case WM8962_PWR_MGMT_2: | |
836 | case WM8962_ADDITIONAL_CONTROL_3: | |
837 | case WM8962_ANTI_POP: | |
838 | case WM8962_CLOCKING_3: | |
839 | case WM8962_INPUT_MIXER_CONTROL_1: | |
840 | case WM8962_LEFT_INPUT_MIXER_VOLUME: | |
841 | case WM8962_RIGHT_INPUT_MIXER_VOLUME: | |
842 | case WM8962_INPUT_MIXER_CONTROL_2: | |
843 | case WM8962_INPUT_BIAS_CONTROL: | |
844 | case WM8962_LEFT_INPUT_PGA_CONTROL: | |
845 | case WM8962_RIGHT_INPUT_PGA_CONTROL: | |
846 | case WM8962_SPKOUTL_VOLUME: | |
847 | case WM8962_SPKOUTR_VOLUME: | |
848 | case WM8962_THERMAL_SHUTDOWN_STATUS: | |
849 | case WM8962_ADDITIONAL_CONTROL_4: | |
850 | case WM8962_CLASS_D_CONTROL_1: | |
851 | case WM8962_CLASS_D_CONTROL_2: | |
852 | case WM8962_CLOCKING_4: | |
853 | case WM8962_DAC_DSP_MIXING_1: | |
854 | case WM8962_DAC_DSP_MIXING_2: | |
855 | case WM8962_DC_SERVO_0: | |
856 | case WM8962_DC_SERVO_1: | |
857 | case WM8962_DC_SERVO_4: | |
858 | case WM8962_DC_SERVO_6: | |
859 | case WM8962_ANALOGUE_PGA_BIAS: | |
860 | case WM8962_ANALOGUE_HP_0: | |
861 | case WM8962_ANALOGUE_HP_2: | |
862 | case WM8962_CHARGE_PUMP_1: | |
863 | case WM8962_CHARGE_PUMP_B: | |
864 | case WM8962_WRITE_SEQUENCER_CONTROL_1: | |
865 | case WM8962_WRITE_SEQUENCER_CONTROL_2: | |
866 | case WM8962_WRITE_SEQUENCER_CONTROL_3: | |
867 | case WM8962_CONTROL_INTERFACE: | |
868 | case WM8962_MIXER_ENABLES: | |
869 | case WM8962_HEADPHONE_MIXER_1: | |
870 | case WM8962_HEADPHONE_MIXER_2: | |
871 | case WM8962_HEADPHONE_MIXER_3: | |
872 | case WM8962_HEADPHONE_MIXER_4: | |
873 | case WM8962_SPEAKER_MIXER_1: | |
874 | case WM8962_SPEAKER_MIXER_2: | |
875 | case WM8962_SPEAKER_MIXER_3: | |
876 | case WM8962_SPEAKER_MIXER_4: | |
877 | case WM8962_SPEAKER_MIXER_5: | |
878 | case WM8962_BEEP_GENERATOR_1: | |
879 | case WM8962_OSCILLATOR_TRIM_3: | |
880 | case WM8962_OSCILLATOR_TRIM_4: | |
881 | case WM8962_OSCILLATOR_TRIM_7: | |
882 | case WM8962_ANALOGUE_CLOCKING1: | |
883 | case WM8962_ANALOGUE_CLOCKING2: | |
884 | case WM8962_ANALOGUE_CLOCKING3: | |
885 | case WM8962_PLL_SOFTWARE_RESET: | |
886 | case WM8962_PLL2: | |
887 | case WM8962_PLL_4: | |
888 | case WM8962_PLL_9: | |
889 | case WM8962_PLL_10: | |
890 | case WM8962_PLL_11: | |
891 | case WM8962_PLL_12: | |
892 | case WM8962_PLL_13: | |
893 | case WM8962_PLL_14: | |
894 | case WM8962_PLL_15: | |
895 | case WM8962_PLL_16: | |
896 | case WM8962_FLL_CONTROL_1: | |
897 | case WM8962_FLL_CONTROL_2: | |
898 | case WM8962_FLL_CONTROL_3: | |
899 | case WM8962_FLL_CONTROL_5: | |
900 | case WM8962_FLL_CONTROL_6: | |
901 | case WM8962_FLL_CONTROL_7: | |
902 | case WM8962_FLL_CONTROL_8: | |
903 | case WM8962_GENERAL_TEST_1: | |
904 | case WM8962_DF1: | |
905 | case WM8962_DF2: | |
906 | case WM8962_DF3: | |
907 | case WM8962_DF4: | |
908 | case WM8962_DF5: | |
909 | case WM8962_DF6: | |
910 | case WM8962_DF7: | |
911 | case WM8962_LHPF1: | |
912 | case WM8962_LHPF2: | |
913 | case WM8962_THREED1: | |
914 | case WM8962_THREED2: | |
915 | case WM8962_THREED3: | |
916 | case WM8962_THREED4: | |
917 | case WM8962_DRC_1: | |
918 | case WM8962_DRC_2: | |
919 | case WM8962_DRC_3: | |
920 | case WM8962_DRC_4: | |
921 | case WM8962_DRC_5: | |
922 | case WM8962_TLOOPBACK: | |
923 | case WM8962_EQ1: | |
924 | case WM8962_EQ2: | |
925 | case WM8962_EQ3: | |
926 | case WM8962_EQ4: | |
927 | case WM8962_EQ5: | |
928 | case WM8962_EQ6: | |
929 | case WM8962_EQ7: | |
930 | case WM8962_EQ8: | |
931 | case WM8962_EQ9: | |
932 | case WM8962_EQ10: | |
933 | case WM8962_EQ11: | |
934 | case WM8962_EQ12: | |
935 | case WM8962_EQ13: | |
936 | case WM8962_EQ14: | |
937 | case WM8962_EQ15: | |
938 | case WM8962_EQ16: | |
939 | case WM8962_EQ17: | |
940 | case WM8962_EQ18: | |
941 | case WM8962_EQ19: | |
942 | case WM8962_EQ20: | |
943 | case WM8962_EQ21: | |
944 | case WM8962_EQ22: | |
945 | case WM8962_EQ23: | |
946 | case WM8962_EQ24: | |
947 | case WM8962_EQ25: | |
948 | case WM8962_EQ26: | |
949 | case WM8962_EQ27: | |
950 | case WM8962_EQ28: | |
951 | case WM8962_EQ29: | |
952 | case WM8962_EQ30: | |
953 | case WM8962_EQ31: | |
954 | case WM8962_EQ32: | |
955 | case WM8962_EQ33: | |
956 | case WM8962_EQ34: | |
957 | case WM8962_EQ35: | |
958 | case WM8962_EQ36: | |
959 | case WM8962_EQ37: | |
960 | case WM8962_EQ38: | |
961 | case WM8962_EQ39: | |
962 | case WM8962_EQ40: | |
963 | case WM8962_EQ41: | |
964 | case WM8962_GPIO_BASE: | |
965 | case WM8962_GPIO_2: | |
966 | case WM8962_GPIO_3: | |
967 | case WM8962_GPIO_5: | |
968 | case WM8962_GPIO_6: | |
969 | case WM8962_INTERRUPT_STATUS_1: | |
970 | case WM8962_INTERRUPT_STATUS_2: | |
971 | case WM8962_INTERRUPT_STATUS_1_MASK: | |
972 | case WM8962_INTERRUPT_STATUS_2_MASK: | |
973 | case WM8962_INTERRUPT_CONTROL: | |
974 | case WM8962_IRQ_DEBOUNCE: | |
975 | case WM8962_MICINT_SOURCE_POL: | |
976 | case WM8962_DSP2_POWER_MANAGEMENT: | |
977 | case WM8962_DSP2_EXECCONTROL: | |
978 | case WM8962_DSP2_INSTRUCTION_RAM_0: | |
979 | case WM8962_DSP2_ADDRESS_RAM_2: | |
980 | case WM8962_DSP2_ADDRESS_RAM_1: | |
981 | case WM8962_DSP2_ADDRESS_RAM_0: | |
982 | case WM8962_DSP2_DATA1_RAM_1: | |
983 | case WM8962_DSP2_DATA1_RAM_0: | |
984 | case WM8962_DSP2_DATA2_RAM_1: | |
985 | case WM8962_DSP2_DATA2_RAM_0: | |
986 | case WM8962_DSP2_DATA3_RAM_1: | |
987 | case WM8962_DSP2_DATA3_RAM_0: | |
988 | case WM8962_DSP2_COEFF_RAM_0: | |
989 | case WM8962_RETUNEADC_SHARED_COEFF_1: | |
990 | case WM8962_RETUNEADC_SHARED_COEFF_0: | |
991 | case WM8962_RETUNEDAC_SHARED_COEFF_1: | |
992 | case WM8962_RETUNEDAC_SHARED_COEFF_0: | |
993 | case WM8962_SOUNDSTAGE_ENABLES_1: | |
994 | case WM8962_SOUNDSTAGE_ENABLES_0: | |
995 | case WM8962_HDBASS_AI_1: | |
996 | case WM8962_HDBASS_AI_0: | |
997 | case WM8962_HDBASS_AR_1: | |
998 | case WM8962_HDBASS_AR_0: | |
999 | case WM8962_HDBASS_B_1: | |
1000 | case WM8962_HDBASS_B_0: | |
1001 | case WM8962_HDBASS_K_1: | |
1002 | case WM8962_HDBASS_K_0: | |
1003 | case WM8962_HDBASS_N1_1: | |
1004 | case WM8962_HDBASS_N1_0: | |
1005 | case WM8962_HDBASS_N2_1: | |
1006 | case WM8962_HDBASS_N2_0: | |
1007 | case WM8962_HDBASS_N3_1: | |
1008 | case WM8962_HDBASS_N3_0: | |
1009 | case WM8962_HDBASS_N4_1: | |
1010 | case WM8962_HDBASS_N4_0: | |
1011 | case WM8962_HDBASS_N5_1: | |
1012 | case WM8962_HDBASS_N5_0: | |
1013 | case WM8962_HDBASS_X1_1: | |
1014 | case WM8962_HDBASS_X1_0: | |
1015 | case WM8962_HDBASS_X2_1: | |
1016 | case WM8962_HDBASS_X2_0: | |
1017 | case WM8962_HDBASS_X3_1: | |
1018 | case WM8962_HDBASS_X3_0: | |
1019 | case WM8962_HDBASS_ATK_1: | |
1020 | case WM8962_HDBASS_ATK_0: | |
1021 | case WM8962_HDBASS_DCY_1: | |
1022 | case WM8962_HDBASS_DCY_0: | |
1023 | case WM8962_HDBASS_PG_1: | |
1024 | case WM8962_HDBASS_PG_0: | |
1025 | case WM8962_HPF_C_1: | |
1026 | case WM8962_HPF_C_0: | |
1027 | case WM8962_ADCL_RETUNE_C1_1: | |
1028 | case WM8962_ADCL_RETUNE_C1_0: | |
1029 | case WM8962_ADCL_RETUNE_C2_1: | |
1030 | case WM8962_ADCL_RETUNE_C2_0: | |
1031 | case WM8962_ADCL_RETUNE_C3_1: | |
1032 | case WM8962_ADCL_RETUNE_C3_0: | |
1033 | case WM8962_ADCL_RETUNE_C4_1: | |
1034 | case WM8962_ADCL_RETUNE_C4_0: | |
1035 | case WM8962_ADCL_RETUNE_C5_1: | |
1036 | case WM8962_ADCL_RETUNE_C5_0: | |
1037 | case WM8962_ADCL_RETUNE_C6_1: | |
1038 | case WM8962_ADCL_RETUNE_C6_0: | |
1039 | case WM8962_ADCL_RETUNE_C7_1: | |
1040 | case WM8962_ADCL_RETUNE_C7_0: | |
1041 | case WM8962_ADCL_RETUNE_C8_1: | |
1042 | case WM8962_ADCL_RETUNE_C8_0: | |
1043 | case WM8962_ADCL_RETUNE_C9_1: | |
1044 | case WM8962_ADCL_RETUNE_C9_0: | |
1045 | case WM8962_ADCL_RETUNE_C10_1: | |
1046 | case WM8962_ADCL_RETUNE_C10_0: | |
1047 | case WM8962_ADCL_RETUNE_C11_1: | |
1048 | case WM8962_ADCL_RETUNE_C11_0: | |
1049 | case WM8962_ADCL_RETUNE_C12_1: | |
1050 | case WM8962_ADCL_RETUNE_C12_0: | |
1051 | case WM8962_ADCL_RETUNE_C13_1: | |
1052 | case WM8962_ADCL_RETUNE_C13_0: | |
1053 | case WM8962_ADCL_RETUNE_C14_1: | |
1054 | case WM8962_ADCL_RETUNE_C14_0: | |
1055 | case WM8962_ADCL_RETUNE_C15_1: | |
1056 | case WM8962_ADCL_RETUNE_C15_0: | |
1057 | case WM8962_ADCL_RETUNE_C16_1: | |
1058 | case WM8962_ADCL_RETUNE_C16_0: | |
1059 | case WM8962_ADCL_RETUNE_C17_1: | |
1060 | case WM8962_ADCL_RETUNE_C17_0: | |
1061 | case WM8962_ADCL_RETUNE_C18_1: | |
1062 | case WM8962_ADCL_RETUNE_C18_0: | |
1063 | case WM8962_ADCL_RETUNE_C19_1: | |
1064 | case WM8962_ADCL_RETUNE_C19_0: | |
1065 | case WM8962_ADCL_RETUNE_C20_1: | |
1066 | case WM8962_ADCL_RETUNE_C20_0: | |
1067 | case WM8962_ADCL_RETUNE_C21_1: | |
1068 | case WM8962_ADCL_RETUNE_C21_0: | |
1069 | case WM8962_ADCL_RETUNE_C22_1: | |
1070 | case WM8962_ADCL_RETUNE_C22_0: | |
1071 | case WM8962_ADCL_RETUNE_C23_1: | |
1072 | case WM8962_ADCL_RETUNE_C23_0: | |
1073 | case WM8962_ADCL_RETUNE_C24_1: | |
1074 | case WM8962_ADCL_RETUNE_C24_0: | |
1075 | case WM8962_ADCL_RETUNE_C25_1: | |
1076 | case WM8962_ADCL_RETUNE_C25_0: | |
1077 | case WM8962_ADCL_RETUNE_C26_1: | |
1078 | case WM8962_ADCL_RETUNE_C26_0: | |
1079 | case WM8962_ADCL_RETUNE_C27_1: | |
1080 | case WM8962_ADCL_RETUNE_C27_0: | |
1081 | case WM8962_ADCL_RETUNE_C28_1: | |
1082 | case WM8962_ADCL_RETUNE_C28_0: | |
1083 | case WM8962_ADCL_RETUNE_C29_1: | |
1084 | case WM8962_ADCL_RETUNE_C29_0: | |
1085 | case WM8962_ADCL_RETUNE_C30_1: | |
1086 | case WM8962_ADCL_RETUNE_C30_0: | |
1087 | case WM8962_ADCL_RETUNE_C31_1: | |
1088 | case WM8962_ADCL_RETUNE_C31_0: | |
1089 | case WM8962_ADCL_RETUNE_C32_1: | |
1090 | case WM8962_ADCL_RETUNE_C32_0: | |
1091 | case WM8962_RETUNEADC_PG2_1: | |
1092 | case WM8962_RETUNEADC_PG2_0: | |
1093 | case WM8962_RETUNEADC_PG_1: | |
1094 | case WM8962_RETUNEADC_PG_0: | |
1095 | case WM8962_ADCR_RETUNE_C1_1: | |
1096 | case WM8962_ADCR_RETUNE_C1_0: | |
1097 | case WM8962_ADCR_RETUNE_C2_1: | |
1098 | case WM8962_ADCR_RETUNE_C2_0: | |
1099 | case WM8962_ADCR_RETUNE_C3_1: | |
1100 | case WM8962_ADCR_RETUNE_C3_0: | |
1101 | case WM8962_ADCR_RETUNE_C4_1: | |
1102 | case WM8962_ADCR_RETUNE_C4_0: | |
1103 | case WM8962_ADCR_RETUNE_C5_1: | |
1104 | case WM8962_ADCR_RETUNE_C5_0: | |
1105 | case WM8962_ADCR_RETUNE_C6_1: | |
1106 | case WM8962_ADCR_RETUNE_C6_0: | |
1107 | case WM8962_ADCR_RETUNE_C7_1: | |
1108 | case WM8962_ADCR_RETUNE_C7_0: | |
1109 | case WM8962_ADCR_RETUNE_C8_1: | |
1110 | case WM8962_ADCR_RETUNE_C8_0: | |
1111 | case WM8962_ADCR_RETUNE_C9_1: | |
1112 | case WM8962_ADCR_RETUNE_C9_0: | |
1113 | case WM8962_ADCR_RETUNE_C10_1: | |
1114 | case WM8962_ADCR_RETUNE_C10_0: | |
1115 | case WM8962_ADCR_RETUNE_C11_1: | |
1116 | case WM8962_ADCR_RETUNE_C11_0: | |
1117 | case WM8962_ADCR_RETUNE_C12_1: | |
1118 | case WM8962_ADCR_RETUNE_C12_0: | |
1119 | case WM8962_ADCR_RETUNE_C13_1: | |
1120 | case WM8962_ADCR_RETUNE_C13_0: | |
1121 | case WM8962_ADCR_RETUNE_C14_1: | |
1122 | case WM8962_ADCR_RETUNE_C14_0: | |
1123 | case WM8962_ADCR_RETUNE_C15_1: | |
1124 | case WM8962_ADCR_RETUNE_C15_0: | |
1125 | case WM8962_ADCR_RETUNE_C16_1: | |
1126 | case WM8962_ADCR_RETUNE_C16_0: | |
1127 | case WM8962_ADCR_RETUNE_C17_1: | |
1128 | case WM8962_ADCR_RETUNE_C17_0: | |
1129 | case WM8962_ADCR_RETUNE_C18_1: | |
1130 | case WM8962_ADCR_RETUNE_C18_0: | |
1131 | case WM8962_ADCR_RETUNE_C19_1: | |
1132 | case WM8962_ADCR_RETUNE_C19_0: | |
1133 | case WM8962_ADCR_RETUNE_C20_1: | |
1134 | case WM8962_ADCR_RETUNE_C20_0: | |
1135 | case WM8962_ADCR_RETUNE_C21_1: | |
1136 | case WM8962_ADCR_RETUNE_C21_0: | |
1137 | case WM8962_ADCR_RETUNE_C22_1: | |
1138 | case WM8962_ADCR_RETUNE_C22_0: | |
1139 | case WM8962_ADCR_RETUNE_C23_1: | |
1140 | case WM8962_ADCR_RETUNE_C23_0: | |
1141 | case WM8962_ADCR_RETUNE_C24_1: | |
1142 | case WM8962_ADCR_RETUNE_C24_0: | |
1143 | case WM8962_ADCR_RETUNE_C25_1: | |
1144 | case WM8962_ADCR_RETUNE_C25_0: | |
1145 | case WM8962_ADCR_RETUNE_C26_1: | |
1146 | case WM8962_ADCR_RETUNE_C26_0: | |
1147 | case WM8962_ADCR_RETUNE_C27_1: | |
1148 | case WM8962_ADCR_RETUNE_C27_0: | |
1149 | case WM8962_ADCR_RETUNE_C28_1: | |
1150 | case WM8962_ADCR_RETUNE_C28_0: | |
1151 | case WM8962_ADCR_RETUNE_C29_1: | |
1152 | case WM8962_ADCR_RETUNE_C29_0: | |
1153 | case WM8962_ADCR_RETUNE_C30_1: | |
1154 | case WM8962_ADCR_RETUNE_C30_0: | |
1155 | case WM8962_ADCR_RETUNE_C31_1: | |
1156 | case WM8962_ADCR_RETUNE_C31_0: | |
1157 | case WM8962_ADCR_RETUNE_C32_1: | |
1158 | case WM8962_ADCR_RETUNE_C32_0: | |
1159 | case WM8962_DACL_RETUNE_C1_1: | |
1160 | case WM8962_DACL_RETUNE_C1_0: | |
1161 | case WM8962_DACL_RETUNE_C2_1: | |
1162 | case WM8962_DACL_RETUNE_C2_0: | |
1163 | case WM8962_DACL_RETUNE_C3_1: | |
1164 | case WM8962_DACL_RETUNE_C3_0: | |
1165 | case WM8962_DACL_RETUNE_C4_1: | |
1166 | case WM8962_DACL_RETUNE_C4_0: | |
1167 | case WM8962_DACL_RETUNE_C5_1: | |
1168 | case WM8962_DACL_RETUNE_C5_0: | |
1169 | case WM8962_DACL_RETUNE_C6_1: | |
1170 | case WM8962_DACL_RETUNE_C6_0: | |
1171 | case WM8962_DACL_RETUNE_C7_1: | |
1172 | case WM8962_DACL_RETUNE_C7_0: | |
1173 | case WM8962_DACL_RETUNE_C8_1: | |
1174 | case WM8962_DACL_RETUNE_C8_0: | |
1175 | case WM8962_DACL_RETUNE_C9_1: | |
1176 | case WM8962_DACL_RETUNE_C9_0: | |
1177 | case WM8962_DACL_RETUNE_C10_1: | |
1178 | case WM8962_DACL_RETUNE_C10_0: | |
1179 | case WM8962_DACL_RETUNE_C11_1: | |
1180 | case WM8962_DACL_RETUNE_C11_0: | |
1181 | case WM8962_DACL_RETUNE_C12_1: | |
1182 | case WM8962_DACL_RETUNE_C12_0: | |
1183 | case WM8962_DACL_RETUNE_C13_1: | |
1184 | case WM8962_DACL_RETUNE_C13_0: | |
1185 | case WM8962_DACL_RETUNE_C14_1: | |
1186 | case WM8962_DACL_RETUNE_C14_0: | |
1187 | case WM8962_DACL_RETUNE_C15_1: | |
1188 | case WM8962_DACL_RETUNE_C15_0: | |
1189 | case WM8962_DACL_RETUNE_C16_1: | |
1190 | case WM8962_DACL_RETUNE_C16_0: | |
1191 | case WM8962_DACL_RETUNE_C17_1: | |
1192 | case WM8962_DACL_RETUNE_C17_0: | |
1193 | case WM8962_DACL_RETUNE_C18_1: | |
1194 | case WM8962_DACL_RETUNE_C18_0: | |
1195 | case WM8962_DACL_RETUNE_C19_1: | |
1196 | case WM8962_DACL_RETUNE_C19_0: | |
1197 | case WM8962_DACL_RETUNE_C20_1: | |
1198 | case WM8962_DACL_RETUNE_C20_0: | |
1199 | case WM8962_DACL_RETUNE_C21_1: | |
1200 | case WM8962_DACL_RETUNE_C21_0: | |
1201 | case WM8962_DACL_RETUNE_C22_1: | |
1202 | case WM8962_DACL_RETUNE_C22_0: | |
1203 | case WM8962_DACL_RETUNE_C23_1: | |
1204 | case WM8962_DACL_RETUNE_C23_0: | |
1205 | case WM8962_DACL_RETUNE_C24_1: | |
1206 | case WM8962_DACL_RETUNE_C24_0: | |
1207 | case WM8962_DACL_RETUNE_C25_1: | |
1208 | case WM8962_DACL_RETUNE_C25_0: | |
1209 | case WM8962_DACL_RETUNE_C26_1: | |
1210 | case WM8962_DACL_RETUNE_C26_0: | |
1211 | case WM8962_DACL_RETUNE_C27_1: | |
1212 | case WM8962_DACL_RETUNE_C27_0: | |
1213 | case WM8962_DACL_RETUNE_C28_1: | |
1214 | case WM8962_DACL_RETUNE_C28_0: | |
1215 | case WM8962_DACL_RETUNE_C29_1: | |
1216 | case WM8962_DACL_RETUNE_C29_0: | |
1217 | case WM8962_DACL_RETUNE_C30_1: | |
1218 | case WM8962_DACL_RETUNE_C30_0: | |
1219 | case WM8962_DACL_RETUNE_C31_1: | |
1220 | case WM8962_DACL_RETUNE_C31_0: | |
1221 | case WM8962_DACL_RETUNE_C32_1: | |
1222 | case WM8962_DACL_RETUNE_C32_0: | |
1223 | case WM8962_RETUNEDAC_PG2_1: | |
1224 | case WM8962_RETUNEDAC_PG2_0: | |
1225 | case WM8962_RETUNEDAC_PG_1: | |
1226 | case WM8962_RETUNEDAC_PG_0: | |
1227 | case WM8962_DACR_RETUNE_C1_1: | |
1228 | case WM8962_DACR_RETUNE_C1_0: | |
1229 | case WM8962_DACR_RETUNE_C2_1: | |
1230 | case WM8962_DACR_RETUNE_C2_0: | |
1231 | case WM8962_DACR_RETUNE_C3_1: | |
1232 | case WM8962_DACR_RETUNE_C3_0: | |
1233 | case WM8962_DACR_RETUNE_C4_1: | |
1234 | case WM8962_DACR_RETUNE_C4_0: | |
1235 | case WM8962_DACR_RETUNE_C5_1: | |
1236 | case WM8962_DACR_RETUNE_C5_0: | |
1237 | case WM8962_DACR_RETUNE_C6_1: | |
1238 | case WM8962_DACR_RETUNE_C6_0: | |
1239 | case WM8962_DACR_RETUNE_C7_1: | |
1240 | case WM8962_DACR_RETUNE_C7_0: | |
1241 | case WM8962_DACR_RETUNE_C8_1: | |
1242 | case WM8962_DACR_RETUNE_C8_0: | |
1243 | case WM8962_DACR_RETUNE_C9_1: | |
1244 | case WM8962_DACR_RETUNE_C9_0: | |
1245 | case WM8962_DACR_RETUNE_C10_1: | |
1246 | case WM8962_DACR_RETUNE_C10_0: | |
1247 | case WM8962_DACR_RETUNE_C11_1: | |
1248 | case WM8962_DACR_RETUNE_C11_0: | |
1249 | case WM8962_DACR_RETUNE_C12_1: | |
1250 | case WM8962_DACR_RETUNE_C12_0: | |
1251 | case WM8962_DACR_RETUNE_C13_1: | |
1252 | case WM8962_DACR_RETUNE_C13_0: | |
1253 | case WM8962_DACR_RETUNE_C14_1: | |
1254 | case WM8962_DACR_RETUNE_C14_0: | |
1255 | case WM8962_DACR_RETUNE_C15_1: | |
1256 | case WM8962_DACR_RETUNE_C15_0: | |
1257 | case WM8962_DACR_RETUNE_C16_1: | |
1258 | case WM8962_DACR_RETUNE_C16_0: | |
1259 | case WM8962_DACR_RETUNE_C17_1: | |
1260 | case WM8962_DACR_RETUNE_C17_0: | |
1261 | case WM8962_DACR_RETUNE_C18_1: | |
1262 | case WM8962_DACR_RETUNE_C18_0: | |
1263 | case WM8962_DACR_RETUNE_C19_1: | |
1264 | case WM8962_DACR_RETUNE_C19_0: | |
1265 | case WM8962_DACR_RETUNE_C20_1: | |
1266 | case WM8962_DACR_RETUNE_C20_0: | |
1267 | case WM8962_DACR_RETUNE_C21_1: | |
1268 | case WM8962_DACR_RETUNE_C21_0: | |
1269 | case WM8962_DACR_RETUNE_C22_1: | |
1270 | case WM8962_DACR_RETUNE_C22_0: | |
1271 | case WM8962_DACR_RETUNE_C23_1: | |
1272 | case WM8962_DACR_RETUNE_C23_0: | |
1273 | case WM8962_DACR_RETUNE_C24_1: | |
1274 | case WM8962_DACR_RETUNE_C24_0: | |
1275 | case WM8962_DACR_RETUNE_C25_1: | |
1276 | case WM8962_DACR_RETUNE_C25_0: | |
1277 | case WM8962_DACR_RETUNE_C26_1: | |
1278 | case WM8962_DACR_RETUNE_C26_0: | |
1279 | case WM8962_DACR_RETUNE_C27_1: | |
1280 | case WM8962_DACR_RETUNE_C27_0: | |
1281 | case WM8962_DACR_RETUNE_C28_1: | |
1282 | case WM8962_DACR_RETUNE_C28_0: | |
1283 | case WM8962_DACR_RETUNE_C29_1: | |
1284 | case WM8962_DACR_RETUNE_C29_0: | |
1285 | case WM8962_DACR_RETUNE_C30_1: | |
1286 | case WM8962_DACR_RETUNE_C30_0: | |
1287 | case WM8962_DACR_RETUNE_C31_1: | |
1288 | case WM8962_DACR_RETUNE_C31_0: | |
1289 | case WM8962_DACR_RETUNE_C32_1: | |
1290 | case WM8962_DACR_RETUNE_C32_0: | |
1291 | case WM8962_VSS_XHD2_1: | |
1292 | case WM8962_VSS_XHD2_0: | |
1293 | case WM8962_VSS_XHD3_1: | |
1294 | case WM8962_VSS_XHD3_0: | |
1295 | case WM8962_VSS_XHN1_1: | |
1296 | case WM8962_VSS_XHN1_0: | |
1297 | case WM8962_VSS_XHN2_1: | |
1298 | case WM8962_VSS_XHN2_0: | |
1299 | case WM8962_VSS_XHN3_1: | |
1300 | case WM8962_VSS_XHN3_0: | |
1301 | case WM8962_VSS_XLA_1: | |
1302 | case WM8962_VSS_XLA_0: | |
1303 | case WM8962_VSS_XLB_1: | |
1304 | case WM8962_VSS_XLB_0: | |
1305 | case WM8962_VSS_XLG_1: | |
1306 | case WM8962_VSS_XLG_0: | |
1307 | case WM8962_VSS_PG2_1: | |
1308 | case WM8962_VSS_PG2_0: | |
1309 | case WM8962_VSS_PG_1: | |
1310 | case WM8962_VSS_PG_0: | |
1311 | case WM8962_VSS_XTD1_1: | |
1312 | case WM8962_VSS_XTD1_0: | |
1313 | case WM8962_VSS_XTD2_1: | |
1314 | case WM8962_VSS_XTD2_0: | |
1315 | case WM8962_VSS_XTD3_1: | |
1316 | case WM8962_VSS_XTD3_0: | |
1317 | case WM8962_VSS_XTD4_1: | |
1318 | case WM8962_VSS_XTD4_0: | |
1319 | case WM8962_VSS_XTD5_1: | |
1320 | case WM8962_VSS_XTD5_0: | |
1321 | case WM8962_VSS_XTD6_1: | |
1322 | case WM8962_VSS_XTD6_0: | |
1323 | case WM8962_VSS_XTD7_1: | |
1324 | case WM8962_VSS_XTD7_0: | |
1325 | case WM8962_VSS_XTD8_1: | |
1326 | case WM8962_VSS_XTD8_0: | |
1327 | case WM8962_VSS_XTD9_1: | |
1328 | case WM8962_VSS_XTD9_0: | |
1329 | case WM8962_VSS_XTD10_1: | |
1330 | case WM8962_VSS_XTD10_0: | |
1331 | case WM8962_VSS_XTD11_1: | |
1332 | case WM8962_VSS_XTD11_0: | |
1333 | case WM8962_VSS_XTD12_1: | |
1334 | case WM8962_VSS_XTD12_0: | |
1335 | case WM8962_VSS_XTD13_1: | |
1336 | case WM8962_VSS_XTD13_0: | |
1337 | case WM8962_VSS_XTD14_1: | |
1338 | case WM8962_VSS_XTD14_0: | |
1339 | case WM8962_VSS_XTD15_1: | |
1340 | case WM8962_VSS_XTD15_0: | |
1341 | case WM8962_VSS_XTD16_1: | |
1342 | case WM8962_VSS_XTD16_0: | |
1343 | case WM8962_VSS_XTD17_1: | |
1344 | case WM8962_VSS_XTD17_0: | |
1345 | case WM8962_VSS_XTD18_1: | |
1346 | case WM8962_VSS_XTD18_0: | |
1347 | case WM8962_VSS_XTD19_1: | |
1348 | case WM8962_VSS_XTD19_0: | |
1349 | case WM8962_VSS_XTD20_1: | |
1350 | case WM8962_VSS_XTD20_0: | |
1351 | case WM8962_VSS_XTD21_1: | |
1352 | case WM8962_VSS_XTD21_0: | |
1353 | case WM8962_VSS_XTD22_1: | |
1354 | case WM8962_VSS_XTD22_0: | |
1355 | case WM8962_VSS_XTD23_1: | |
1356 | case WM8962_VSS_XTD23_0: | |
1357 | case WM8962_VSS_XTD24_1: | |
1358 | case WM8962_VSS_XTD24_0: | |
1359 | case WM8962_VSS_XTD25_1: | |
1360 | case WM8962_VSS_XTD25_0: | |
1361 | case WM8962_VSS_XTD26_1: | |
1362 | case WM8962_VSS_XTD26_0: | |
1363 | case WM8962_VSS_XTD27_1: | |
1364 | case WM8962_VSS_XTD27_0: | |
1365 | case WM8962_VSS_XTD28_1: | |
1366 | case WM8962_VSS_XTD28_0: | |
1367 | case WM8962_VSS_XTD29_1: | |
1368 | case WM8962_VSS_XTD29_0: | |
1369 | case WM8962_VSS_XTD30_1: | |
1370 | case WM8962_VSS_XTD30_0: | |
1371 | case WM8962_VSS_XTD31_1: | |
1372 | case WM8962_VSS_XTD31_0: | |
1373 | case WM8962_VSS_XTD32_1: | |
1374 | case WM8962_VSS_XTD32_0: | |
1375 | case WM8962_VSS_XTS1_1: | |
1376 | case WM8962_VSS_XTS1_0: | |
1377 | case WM8962_VSS_XTS2_1: | |
1378 | case WM8962_VSS_XTS2_0: | |
1379 | case WM8962_VSS_XTS3_1: | |
1380 | case WM8962_VSS_XTS3_0: | |
1381 | case WM8962_VSS_XTS4_1: | |
1382 | case WM8962_VSS_XTS4_0: | |
1383 | case WM8962_VSS_XTS5_1: | |
1384 | case WM8962_VSS_XTS5_0: | |
1385 | case WM8962_VSS_XTS6_1: | |
1386 | case WM8962_VSS_XTS6_0: | |
1387 | case WM8962_VSS_XTS7_1: | |
1388 | case WM8962_VSS_XTS7_0: | |
1389 | case WM8962_VSS_XTS8_1: | |
1390 | case WM8962_VSS_XTS8_0: | |
1391 | case WM8962_VSS_XTS9_1: | |
1392 | case WM8962_VSS_XTS9_0: | |
1393 | case WM8962_VSS_XTS10_1: | |
1394 | case WM8962_VSS_XTS10_0: | |
1395 | case WM8962_VSS_XTS11_1: | |
1396 | case WM8962_VSS_XTS11_0: | |
1397 | case WM8962_VSS_XTS12_1: | |
1398 | case WM8962_VSS_XTS12_0: | |
1399 | case WM8962_VSS_XTS13_1: | |
1400 | case WM8962_VSS_XTS13_0: | |
1401 | case WM8962_VSS_XTS14_1: | |
1402 | case WM8962_VSS_XTS14_0: | |
1403 | case WM8962_VSS_XTS15_1: | |
1404 | case WM8962_VSS_XTS15_0: | |
1405 | case WM8962_VSS_XTS16_1: | |
1406 | case WM8962_VSS_XTS16_0: | |
1407 | case WM8962_VSS_XTS17_1: | |
1408 | case WM8962_VSS_XTS17_0: | |
1409 | case WM8962_VSS_XTS18_1: | |
1410 | case WM8962_VSS_XTS18_0: | |
1411 | case WM8962_VSS_XTS19_1: | |
1412 | case WM8962_VSS_XTS19_0: | |
1413 | case WM8962_VSS_XTS20_1: | |
1414 | case WM8962_VSS_XTS20_0: | |
1415 | case WM8962_VSS_XTS21_1: | |
1416 | case WM8962_VSS_XTS21_0: | |
1417 | case WM8962_VSS_XTS22_1: | |
1418 | case WM8962_VSS_XTS22_0: | |
1419 | case WM8962_VSS_XTS23_1: | |
1420 | case WM8962_VSS_XTS23_0: | |
1421 | case WM8962_VSS_XTS24_1: | |
1422 | case WM8962_VSS_XTS24_0: | |
1423 | case WM8962_VSS_XTS25_1: | |
1424 | case WM8962_VSS_XTS25_0: | |
1425 | case WM8962_VSS_XTS26_1: | |
1426 | case WM8962_VSS_XTS26_0: | |
1427 | case WM8962_VSS_XTS27_1: | |
1428 | case WM8962_VSS_XTS27_0: | |
1429 | case WM8962_VSS_XTS28_1: | |
1430 | case WM8962_VSS_XTS28_0: | |
1431 | case WM8962_VSS_XTS29_1: | |
1432 | case WM8962_VSS_XTS29_0: | |
1433 | case WM8962_VSS_XTS30_1: | |
1434 | case WM8962_VSS_XTS30_0: | |
1435 | case WM8962_VSS_XTS31_1: | |
1436 | case WM8962_VSS_XTS31_0: | |
1437 | case WM8962_VSS_XTS32_1: | |
1438 | case WM8962_VSS_XTS32_0: | |
1439 | return true; | |
1440 | default: | |
1441 | return false; | |
1442 | } | |
9a76f1ff MB |
1443 | } |
1444 | ||
7b16f560 | 1445 | static int wm8962_reset(struct wm8962_priv *wm8962) |
9a76f1ff | 1446 | { |
4f4488ab MB |
1447 | int ret; |
1448 | ||
7b16f560 | 1449 | ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243); |
4f4488ab MB |
1450 | if (ret != 0) |
1451 | return ret; | |
1452 | ||
7b16f560 | 1453 | return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0); |
9a76f1ff MB |
1454 | } |
1455 | ||
1456 | static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0); | |
1457 | static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0); | |
1458 | static const unsigned int mixinpga_tlv[] = { | |
43e9dc7b | 1459 | TLV_DB_RANGE_HEAD(5), |
9a76f1ff MB |
1460 | 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0), |
1461 | 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0), | |
1462 | 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0), | |
1463 | 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0), | |
1464 | 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0), | |
1465 | }; | |
1466 | static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1); | |
1467 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); | |
1468 | static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); | |
1469 | static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0); | |
1470 | static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); | |
1471 | static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1); | |
1472 | static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0); | |
1473 | static const unsigned int classd_tlv[] = { | |
43e9dc7b | 1474 | TLV_DB_RANGE_HEAD(2), |
9a76f1ff MB |
1475 | 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0), |
1476 | 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0), | |
1477 | }; | |
8f63aaa8 | 1478 | static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); |
9a76f1ff | 1479 | |
6f88a4e5 MB |
1480 | static int wm8962_dsp2_write_config(struct snd_soc_codec *codec) |
1481 | { | |
26b427a7 MB |
1482 | return regcache_sync_region(codec->control_data, |
1483 | WM8962_HDBASS_AI_1, WM8962_MAX_REGISTER); | |
6f88a4e5 MB |
1484 | } |
1485 | ||
1486 | static int wm8962_dsp2_set_enable(struct snd_soc_codec *codec, u16 val) | |
1487 | { | |
1488 | u16 adcl = snd_soc_read(codec, WM8962_LEFT_ADC_VOLUME); | |
1489 | u16 adcr = snd_soc_read(codec, WM8962_RIGHT_ADC_VOLUME); | |
1490 | u16 dac = snd_soc_read(codec, WM8962_ADC_DAC_CONTROL_1); | |
1491 | ||
1492 | /* Mute the ADCs and DACs */ | |
1493 | snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, 0); | |
1494 | snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU); | |
1495 | snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1, | |
1496 | WM8962_DAC_MUTE, WM8962_DAC_MUTE); | |
1497 | ||
1498 | snd_soc_write(codec, WM8962_SOUNDSTAGE_ENABLES_0, val); | |
1499 | ||
1500 | /* Restore the ADCs and DACs */ | |
1501 | snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, adcl); | |
1502 | snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, adcr); | |
1503 | snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1, | |
1504 | WM8962_DAC_MUTE, dac); | |
1505 | ||
1506 | return 0; | |
1507 | } | |
1508 | ||
1509 | static int wm8962_dsp2_start(struct snd_soc_codec *codec) | |
1510 | { | |
1511 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
1512 | ||
1513 | wm8962_dsp2_write_config(codec); | |
1514 | ||
1515 | snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR); | |
1516 | ||
1517 | wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena); | |
1518 | ||
1519 | return 0; | |
1520 | } | |
1521 | ||
1522 | static int wm8962_dsp2_stop(struct snd_soc_codec *codec) | |
1523 | { | |
1524 | wm8962_dsp2_set_enable(codec, 0); | |
1525 | ||
1526 | snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP); | |
1527 | ||
1528 | return 0; | |
1529 | } | |
1530 | ||
1531 | #define WM8962_DSP2_ENABLE(xname, xshift) \ | |
1532 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
1533 | .info = wm8962_dsp2_ena_info, \ | |
1534 | .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \ | |
1535 | .private_value = xshift } | |
1536 | ||
1537 | static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol, | |
1538 | struct snd_ctl_elem_info *uinfo) | |
1539 | { | |
1540 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; | |
1541 | ||
1542 | uinfo->count = 1; | |
1543 | uinfo->value.integer.min = 0; | |
1544 | uinfo->value.integer.max = 1; | |
1545 | ||
1546 | return 0; | |
1547 | } | |
1548 | ||
1549 | static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol, | |
1550 | struct snd_ctl_elem_value *ucontrol) | |
1551 | { | |
1552 | int shift = kcontrol->private_value; | |
1553 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
1554 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
1555 | ||
1556 | ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift); | |
1557 | ||
1558 | return 0; | |
1559 | } | |
1560 | ||
1561 | static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol, | |
1562 | struct snd_ctl_elem_value *ucontrol) | |
1563 | { | |
1564 | int shift = kcontrol->private_value; | |
1565 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
1566 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
1567 | int old = wm8962->dsp2_ena; | |
1568 | int ret = 0; | |
1569 | int dsp2_running = snd_soc_read(codec, WM8962_DSP2_POWER_MANAGEMENT) & | |
1570 | WM8962_DSP2_ENA; | |
1571 | ||
1572 | mutex_lock(&codec->mutex); | |
1573 | ||
1574 | if (ucontrol->value.integer.value[0]) | |
1575 | wm8962->dsp2_ena |= 1 << shift; | |
1576 | else | |
1577 | wm8962->dsp2_ena &= ~(1 << shift); | |
1578 | ||
1579 | if (wm8962->dsp2_ena == old) | |
1580 | goto out; | |
1581 | ||
1582 | ret = 1; | |
1583 | ||
1584 | if (dsp2_running) { | |
1585 | if (wm8962->dsp2_ena) | |
1586 | wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena); | |
1587 | else | |
1588 | wm8962_dsp2_stop(codec); | |
1589 | } | |
1590 | ||
1591 | out: | |
1592 | mutex_unlock(&codec->mutex); | |
1593 | ||
1594 | return ret; | |
1595 | } | |
1596 | ||
9a76f1ff MB |
1597 | /* The VU bits for the headphones are in a different register to the mute |
1598 | * bits and only take effect on the PGA if it is actually powered. | |
1599 | */ | |
1600 | static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol, | |
1601 | struct snd_ctl_elem_value *ucontrol) | |
1602 | { | |
1603 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
9a76f1ff MB |
1604 | int ret; |
1605 | ||
1606 | /* Apply the update (if any) */ | |
1607 | ret = snd_soc_put_volsw(kcontrol, ucontrol); | |
1608 | if (ret == 0) | |
1609 | return 0; | |
1610 | ||
1611 | /* If the left PGA is enabled hit that VU bit... */ | |
2e7ee15c NC |
1612 | ret = snd_soc_read(codec, WM8962_PWR_MGMT_2); |
1613 | if (ret & WM8962_HPOUTL_PGA_ENA) { | |
1614 | snd_soc_write(codec, WM8962_HPOUTL_VOLUME, | |
1615 | snd_soc_read(codec, WM8962_HPOUTL_VOLUME)); | |
1616 | return 1; | |
1617 | } | |
9a76f1ff MB |
1618 | |
1619 | /* ...otherwise the right. The VU is stereo. */ | |
2e7ee15c NC |
1620 | if (ret & WM8962_HPOUTR_PGA_ENA) |
1621 | snd_soc_write(codec, WM8962_HPOUTR_VOLUME, | |
1622 | snd_soc_read(codec, WM8962_HPOUTR_VOLUME)); | |
9a76f1ff | 1623 | |
2e7ee15c | 1624 | return 1; |
9a76f1ff MB |
1625 | } |
1626 | ||
1627 | /* The VU bits for the speakers are in a different register to the mute | |
1628 | * bits and only take effect on the PGA if it is actually powered. | |
1629 | */ | |
1630 | static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol, | |
1631 | struct snd_ctl_elem_value *ucontrol) | |
1632 | { | |
1633 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
9a76f1ff MB |
1634 | int ret; |
1635 | ||
1636 | /* Apply the update (if any) */ | |
1637 | ret = snd_soc_put_volsw(kcontrol, ucontrol); | |
1638 | if (ret == 0) | |
1639 | return 0; | |
1640 | ||
1641 | /* If the left PGA is enabled hit that VU bit... */ | |
38f3f31a MB |
1642 | ret = snd_soc_read(codec, WM8962_PWR_MGMT_2); |
1643 | if (ret & WM8962_SPKOUTL_PGA_ENA) { | |
1644 | snd_soc_write(codec, WM8962_SPKOUTL_VOLUME, | |
1645 | snd_soc_read(codec, WM8962_SPKOUTL_VOLUME)); | |
1646 | return 1; | |
1647 | } | |
9a76f1ff MB |
1648 | |
1649 | /* ...otherwise the right. The VU is stereo. */ | |
38f3f31a MB |
1650 | if (ret & WM8962_SPKOUTR_PGA_ENA) |
1651 | snd_soc_write(codec, WM8962_SPKOUTR_VOLUME, | |
1652 | snd_soc_read(codec, WM8962_SPKOUTR_VOLUME)); | |
9a76f1ff | 1653 | |
38f3f31a | 1654 | return 1; |
9a76f1ff MB |
1655 | } |
1656 | ||
6be449e5 MB |
1657 | static const char *cap_hpf_mode_text[] = { |
1658 | "Hi-fi", "Application" | |
1659 | }; | |
1660 | ||
1661 | static const struct soc_enum cap_hpf_mode = | |
1662 | SOC_ENUM_SINGLE(WM8962_ADC_DAC_CONTROL_2, 10, 2, cap_hpf_mode_text); | |
1663 | ||
1ab63da7 MB |
1664 | |
1665 | static const char *cap_lhpf_mode_text[] = { | |
1666 | "LPF", "HPF" | |
1667 | }; | |
1668 | ||
1669 | static const struct soc_enum cap_lhpf_mode = | |
1670 | SOC_ENUM_SINGLE(WM8962_LHPF1, 1, 2, cap_lhpf_mode_text); | |
1671 | ||
9a76f1ff MB |
1672 | static const struct snd_kcontrol_new wm8962_snd_controls[] = { |
1673 | SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1), | |
1674 | ||
1675 | SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0, | |
1676 | mixin_tlv), | |
1677 | SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0, | |
1678 | mixinpga_tlv), | |
1679 | SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0, | |
1680 | mixin_tlv), | |
1681 | ||
1682 | SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0, | |
1683 | mixin_tlv), | |
1684 | SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0, | |
1685 | mixinpga_tlv), | |
1686 | SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0, | |
1687 | mixin_tlv), | |
1688 | ||
1689 | SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME, | |
1690 | WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv), | |
1691 | SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME, | |
1692 | WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv), | |
1693 | SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME, | |
1694 | WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1), | |
1695 | SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME, | |
1696 | WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1), | |
6be449e5 MB |
1697 | SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1), |
1698 | SOC_ENUM("Capture HPF Mode", cap_hpf_mode), | |
1699 | SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0), | |
1ab63da7 MB |
1700 | SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0), |
1701 | SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode), | |
9a76f1ff MB |
1702 | |
1703 | SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1, | |
1704 | WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv), | |
1705 | ||
1706 | SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME, | |
1707 | WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv), | |
1708 | SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0), | |
5f52ee48 MB |
1709 | SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0), |
1710 | SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0), | |
9a76f1ff MB |
1711 | |
1712 | SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1, | |
1713 | 5, 1, 0), | |
1714 | ||
1715 | SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv), | |
1716 | ||
1717 | SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME, | |
1718 | WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv), | |
1719 | SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1, | |
1720 | snd_soc_get_volsw, wm8962_put_hp_sw), | |
1721 | SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME, | |
1722 | 7, 1, 0), | |
1723 | SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0, | |
1724 | hp_tlv), | |
1725 | ||
1726 | SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3, | |
1727 | WM8962_HEADPHONE_MIXER_4, 8, 1, 1), | |
1728 | ||
1729 | SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3, | |
1730 | 3, 7, 0, bypass_tlv), | |
1731 | SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3, | |
1732 | 0, 7, 0, bypass_tlv), | |
1733 | SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3, | |
1734 | 7, 1, 1, inmix_tlv), | |
1735 | SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3, | |
1736 | 6, 1, 1, inmix_tlv), | |
1737 | ||
1738 | SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4, | |
1739 | 3, 7, 0, bypass_tlv), | |
1740 | SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4, | |
1741 | 0, 7, 0, bypass_tlv), | |
1742 | SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4, | |
1743 | 7, 1, 1, inmix_tlv), | |
1744 | SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4, | |
1745 | 6, 1, 1, inmix_tlv), | |
1746 | ||
1747 | SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0, | |
1748 | classd_tlv), | |
8f63aaa8 MB |
1749 | |
1750 | SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0), | |
1751 | SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22, | |
1752 | WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv), | |
1753 | SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22, | |
1754 | WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv), | |
1755 | SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22, | |
1756 | WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv), | |
1757 | SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23, | |
1758 | WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv), | |
1759 | SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23, | |
1760 | WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv), | |
6f88a4e5 | 1761 | |
69e5a39f MB |
1762 | SOC_SINGLE("3D Switch", WM8962_THREED1, 0, 1, 0), |
1763 | SND_SOC_BYTES_MASK("3D Coefficients", WM8962_THREED1, 4, WM8962_THREED_ENA), | |
1764 | ||
acf31d43 MB |
1765 | SOC_SINGLE("DF1 Switch", WM8962_DF1, 0, 1, 0), |
1766 | SND_SOC_BYTES_MASK("DF1 Coefficients", WM8962_DF1, 7, WM8962_DF1_ENA), | |
1767 | ||
fd0ca45b MB |
1768 | SOC_SINGLE("DRC Switch", WM8962_DRC_1, 0, 1, 0), |
1769 | SND_SOC_BYTES_MASK("DRC Coefficients", WM8962_DRC_1, 5, WM8962_DRC_ENA), | |
1770 | ||
6f88a4e5 | 1771 | WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT), |
5462fccd | 1772 | SND_SOC_BYTES("VSS Coefficients", WM8962_VSS_XHD2_1, 148), |
6f88a4e5 MB |
1773 | WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT), |
1774 | WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT), | |
93a86bea | 1775 | SND_SOC_BYTES("HPF Coefficients", WM8962_LHPF2, 1), |
6f88a4e5 | 1776 | WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT), |
5462fccd | 1777 | SND_SOC_BYTES("HD Bass Coefficients", WM8962_HDBASS_AI_1, 30), |
9a76f1ff MB |
1778 | }; |
1779 | ||
1780 | static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = { | |
1781 | SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv), | |
1782 | SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1, | |
1783 | snd_soc_get_volsw, wm8962_put_spk_sw), | |
1784 | SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0), | |
1785 | ||
1786 | SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1), | |
1787 | SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3, | |
1788 | 3, 7, 0, bypass_tlv), | |
1789 | SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3, | |
1790 | 0, 7, 0, bypass_tlv), | |
1791 | SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3, | |
1792 | 7, 1, 1, inmix_tlv), | |
1793 | SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3, | |
1794 | 6, 1, 1, inmix_tlv), | |
1795 | SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5, | |
1796 | 7, 1, 0, inmix_tlv), | |
1797 | SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5, | |
1798 | 6, 1, 0, inmix_tlv), | |
1799 | }; | |
1800 | ||
1801 | static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = { | |
1802 | SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, | |
1803 | WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv), | |
1804 | SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1, | |
1805 | snd_soc_get_volsw, wm8962_put_spk_sw), | |
1806 | SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME, | |
1807 | 7, 1, 0), | |
1808 | ||
1809 | SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, | |
1810 | WM8962_SPEAKER_MIXER_4, 8, 1, 1), | |
1811 | ||
1812 | SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3, | |
1813 | 3, 7, 0, bypass_tlv), | |
1814 | SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3, | |
1815 | 0, 7, 0, bypass_tlv), | |
1816 | SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3, | |
1817 | 7, 1, 1, inmix_tlv), | |
1818 | SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3, | |
1819 | 6, 1, 1, inmix_tlv), | |
1820 | SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5, | |
1821 | 7, 1, 0, inmix_tlv), | |
1822 | SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5, | |
1823 | 6, 1, 0, inmix_tlv), | |
1824 | ||
1825 | SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4, | |
1826 | 3, 7, 0, bypass_tlv), | |
1827 | SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4, | |
1828 | 0, 7, 0, bypass_tlv), | |
1829 | SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4, | |
1830 | 7, 1, 1, inmix_tlv), | |
1831 | SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4, | |
1832 | 6, 1, 1, inmix_tlv), | |
1833 | SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5, | |
1834 | 5, 1, 0, inmix_tlv), | |
1835 | SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5, | |
1836 | 4, 1, 0, inmix_tlv), | |
1837 | }; | |
1838 | ||
9a76f1ff MB |
1839 | static int cp_event(struct snd_soc_dapm_widget *w, |
1840 | struct snd_kcontrol *kcontrol, int event) | |
1841 | { | |
1842 | switch (event) { | |
1843 | case SND_SOC_DAPM_POST_PMU: | |
1844 | msleep(5); | |
1845 | break; | |
1846 | ||
1847 | default: | |
1848 | BUG(); | |
1849 | return -EINVAL; | |
1850 | } | |
1851 | ||
1852 | return 0; | |
1853 | } | |
1854 | ||
1855 | static int hp_event(struct snd_soc_dapm_widget *w, | |
1856 | struct snd_kcontrol *kcontrol, int event) | |
1857 | { | |
1858 | struct snd_soc_codec *codec = w->codec; | |
1859 | int timeout; | |
1860 | int reg; | |
1861 | int expected = (WM8962_DCS_STARTUP_DONE_HP1L | | |
1862 | WM8962_DCS_STARTUP_DONE_HP1R); | |
1863 | ||
1864 | switch (event) { | |
1865 | case SND_SOC_DAPM_POST_PMU: | |
1866 | snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, | |
1867 | WM8962_HP1L_ENA | WM8962_HP1R_ENA, | |
1868 | WM8962_HP1L_ENA | WM8962_HP1R_ENA); | |
1869 | udelay(20); | |
1870 | ||
1871 | snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, | |
1872 | WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY, | |
1873 | WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY); | |
1874 | ||
1875 | /* Start the DC servo */ | |
1876 | snd_soc_update_bits(codec, WM8962_DC_SERVO_1, | |
1877 | WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | | |
1878 | WM8962_HP1L_DCS_STARTUP | | |
1879 | WM8962_HP1R_DCS_STARTUP, | |
1880 | WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | | |
1881 | WM8962_HP1L_DCS_STARTUP | | |
1882 | WM8962_HP1R_DCS_STARTUP); | |
1883 | ||
1884 | /* Wait for it to complete, should be well under 100ms */ | |
1885 | timeout = 0; | |
1886 | do { | |
1887 | msleep(1); | |
1888 | reg = snd_soc_read(codec, WM8962_DC_SERVO_6); | |
1889 | if (reg < 0) { | |
1890 | dev_err(codec->dev, | |
1891 | "Failed to read DCS status: %d\n", | |
1892 | reg); | |
1893 | continue; | |
1894 | } | |
1895 | dev_dbg(codec->dev, "DCS status: %x\n", reg); | |
1896 | } while (++timeout < 200 && (reg & expected) != expected); | |
1897 | ||
1898 | if ((reg & expected) != expected) | |
1899 | dev_err(codec->dev, "DC servo timed out\n"); | |
1900 | else | |
1901 | dev_dbg(codec->dev, "DC servo complete after %dms\n", | |
1902 | timeout); | |
1903 | ||
1904 | snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, | |
1905 | WM8962_HP1L_ENA_OUTP | | |
1906 | WM8962_HP1R_ENA_OUTP, | |
1907 | WM8962_HP1L_ENA_OUTP | | |
1908 | WM8962_HP1R_ENA_OUTP); | |
1909 | udelay(20); | |
1910 | ||
1911 | snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, | |
1912 | WM8962_HP1L_RMV_SHORT | | |
1913 | WM8962_HP1R_RMV_SHORT, | |
1914 | WM8962_HP1L_RMV_SHORT | | |
1915 | WM8962_HP1R_RMV_SHORT); | |
1916 | break; | |
1917 | ||
1918 | case SND_SOC_DAPM_PRE_PMD: | |
1919 | snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, | |
1920 | WM8962_HP1L_RMV_SHORT | | |
1921 | WM8962_HP1R_RMV_SHORT, 0); | |
1922 | ||
1923 | udelay(20); | |
1924 | ||
1925 | snd_soc_update_bits(codec, WM8962_DC_SERVO_1, | |
1926 | WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | | |
1927 | WM8962_HP1L_DCS_STARTUP | | |
1928 | WM8962_HP1R_DCS_STARTUP, | |
1929 | 0); | |
1930 | ||
1931 | snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, | |
1932 | WM8962_HP1L_ENA | WM8962_HP1R_ENA | | |
1933 | WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY | | |
1934 | WM8962_HP1L_ENA_OUTP | | |
1935 | WM8962_HP1R_ENA_OUTP, 0); | |
1936 | ||
1937 | break; | |
1938 | ||
1939 | default: | |
1940 | BUG(); | |
1941 | return -EINVAL; | |
1942 | ||
1943 | } | |
1944 | ||
1945 | return 0; | |
1946 | } | |
1947 | ||
1948 | /* VU bits for the output PGAs only take effect while the PGA is powered */ | |
1949 | static int out_pga_event(struct snd_soc_dapm_widget *w, | |
1950 | struct snd_kcontrol *kcontrol, int event) | |
1951 | { | |
1952 | struct snd_soc_codec *codec = w->codec; | |
9a76f1ff MB |
1953 | int reg; |
1954 | ||
1955 | switch (w->shift) { | |
1956 | case WM8962_HPOUTR_PGA_ENA_SHIFT: | |
1957 | reg = WM8962_HPOUTR_VOLUME; | |
1958 | break; | |
1959 | case WM8962_HPOUTL_PGA_ENA_SHIFT: | |
1960 | reg = WM8962_HPOUTL_VOLUME; | |
1961 | break; | |
1962 | case WM8962_SPKOUTR_PGA_ENA_SHIFT: | |
1963 | reg = WM8962_SPKOUTR_VOLUME; | |
1964 | break; | |
1965 | case WM8962_SPKOUTL_PGA_ENA_SHIFT: | |
1966 | reg = WM8962_SPKOUTL_VOLUME; | |
1967 | break; | |
1968 | default: | |
1969 | BUG(); | |
1970 | return -EINVAL; | |
1971 | } | |
1972 | ||
1973 | switch (event) { | |
1974 | case SND_SOC_DAPM_POST_PMU: | |
38f3f31a | 1975 | return snd_soc_write(codec, reg, snd_soc_read(codec, reg)); |
9a76f1ff MB |
1976 | default: |
1977 | BUG(); | |
1978 | return -EINVAL; | |
1979 | } | |
1980 | } | |
1981 | ||
6f88a4e5 MB |
1982 | static int dsp2_event(struct snd_soc_dapm_widget *w, |
1983 | struct snd_kcontrol *kcontrol, int event) | |
1984 | { | |
1985 | struct snd_soc_codec *codec = w->codec; | |
1986 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
1987 | ||
1988 | switch (event) { | |
1989 | case SND_SOC_DAPM_POST_PMU: | |
1990 | if (wm8962->dsp2_ena) | |
1991 | wm8962_dsp2_start(codec); | |
1992 | break; | |
1993 | ||
1994 | case SND_SOC_DAPM_PRE_PMD: | |
1995 | if (wm8962->dsp2_ena) | |
1996 | wm8962_dsp2_stop(codec); | |
1997 | break; | |
1998 | ||
1999 | default: | |
2000 | BUG(); | |
2001 | return -EINVAL; | |
2002 | } | |
2003 | ||
2004 | return 0; | |
2005 | } | |
2006 | ||
31794bc3 | 2007 | static const char *st_text[] = { "None", "Left", "Right" }; |
9a76f1ff MB |
2008 | |
2009 | static const struct soc_enum str_enum = | |
2010 | SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text); | |
2011 | ||
2012 | static const struct snd_kcontrol_new str_mux = | |
2013 | SOC_DAPM_ENUM("Right Sidetone", str_enum); | |
2014 | ||
2015 | static const struct soc_enum stl_enum = | |
2016 | SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text); | |
2017 | ||
2018 | static const struct snd_kcontrol_new stl_mux = | |
2019 | SOC_DAPM_ENUM("Left Sidetone", stl_enum); | |
2020 | ||
2021 | static const char *outmux_text[] = { "DAC", "Mixer" }; | |
2022 | ||
2023 | static const struct soc_enum spkoutr_enum = | |
2024 | SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text); | |
2025 | ||
2026 | static const struct snd_kcontrol_new spkoutr_mux = | |
2027 | SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum); | |
2028 | ||
2029 | static const struct soc_enum spkoutl_enum = | |
2030 | SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text); | |
2031 | ||
2032 | static const struct snd_kcontrol_new spkoutl_mux = | |
2033 | SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum); | |
2034 | ||
2035 | static const struct soc_enum hpoutr_enum = | |
2036 | SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text); | |
2037 | ||
2038 | static const struct snd_kcontrol_new hpoutr_mux = | |
2039 | SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum); | |
2040 | ||
2041 | static const struct soc_enum hpoutl_enum = | |
2042 | SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text); | |
2043 | ||
2044 | static const struct snd_kcontrol_new hpoutl_mux = | |
2045 | SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum); | |
2046 | ||
2047 | static const struct snd_kcontrol_new inpgal[] = { | |
2048 | SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0), | |
2049 | SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0), | |
2050 | SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0), | |
2051 | SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0), | |
2052 | }; | |
2053 | ||
2054 | static const struct snd_kcontrol_new inpgar[] = { | |
2055 | SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0), | |
2056 | SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0), | |
2057 | SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0), | |
2058 | SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0), | |
2059 | }; | |
2060 | ||
2061 | static const struct snd_kcontrol_new mixinl[] = { | |
2062 | SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0), | |
2063 | SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0), | |
2064 | SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0), | |
2065 | }; | |
2066 | ||
2067 | static const struct snd_kcontrol_new mixinr[] = { | |
2068 | SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0), | |
2069 | SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0), | |
2070 | SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0), | |
2071 | }; | |
2072 | ||
2073 | static const struct snd_kcontrol_new hpmixl[] = { | |
2074 | SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0), | |
2075 | SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0), | |
2076 | SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0), | |
2077 | SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0), | |
2078 | SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0), | |
2079 | SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0), | |
2080 | }; | |
2081 | ||
2082 | static const struct snd_kcontrol_new hpmixr[] = { | |
2083 | SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0), | |
2084 | SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0), | |
2085 | SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0), | |
2086 | SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0), | |
2087 | SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0), | |
2088 | SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0), | |
2089 | }; | |
2090 | ||
2091 | static const struct snd_kcontrol_new spkmixl[] = { | |
2092 | SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0), | |
2093 | SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0), | |
2094 | SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0), | |
2095 | SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0), | |
2096 | SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0), | |
2097 | SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0), | |
2098 | }; | |
2099 | ||
2100 | static const struct snd_kcontrol_new spkmixr[] = { | |
2101 | SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0), | |
2102 | SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0), | |
2103 | SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0), | |
2104 | SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0), | |
2105 | SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0), | |
2106 | SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0), | |
2107 | }; | |
2108 | ||
2109 | static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = { | |
2110 | SND_SOC_DAPM_INPUT("IN1L"), | |
2111 | SND_SOC_DAPM_INPUT("IN1R"), | |
2112 | SND_SOC_DAPM_INPUT("IN2L"), | |
2113 | SND_SOC_DAPM_INPUT("IN2R"), | |
2114 | SND_SOC_DAPM_INPUT("IN3L"), | |
2115 | SND_SOC_DAPM_INPUT("IN3R"), | |
2116 | SND_SOC_DAPM_INPUT("IN4L"), | |
2117 | SND_SOC_DAPM_INPUT("IN4R"), | |
36c6b54c | 2118 | SND_SOC_DAPM_SIGGEN("Beep"), |
e47ac37c | 2119 | SND_SOC_DAPM_INPUT("DMICDAT"), |
9a76f1ff | 2120 | |
086d7f80 | 2121 | SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0), |
a4f28c00 | 2122 | |
9a76f1ff | 2123 | SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0), |
a968d9db | 2124 | SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, NULL, 0), |
9a76f1ff MB |
2125 | SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event, |
2126 | SND_SOC_DAPM_POST_PMU), | |
2127 | SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0), | |
6f88a4e5 MB |
2128 | SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT, |
2129 | WM8962_DSP2_ENA_SHIFT, 0, dsp2_event, | |
2130 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
94b88e64 MB |
2131 | SND_SOC_DAPM_SUPPLY("TEMP_HP", WM8962_ADDITIONAL_CONTROL_4, 2, 0, NULL, 0), |
2132 | SND_SOC_DAPM_SUPPLY("TEMP_SPK", WM8962_ADDITIONAL_CONTROL_4, 1, 0, NULL, 0), | |
9a76f1ff MB |
2133 | |
2134 | SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0, | |
2135 | inpgal, ARRAY_SIZE(inpgal)), | |
2136 | SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0, | |
2137 | inpgar, ARRAY_SIZE(inpgar)), | |
2138 | SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0, | |
2139 | mixinl, ARRAY_SIZE(mixinl)), | |
2140 | SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0, | |
2141 | mixinr, ARRAY_SIZE(mixinr)), | |
2142 | ||
3f7d55a1 | 2143 | SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0), |
e47ac37c | 2144 | |
9a76f1ff MB |
2145 | SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0), |
2146 | SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0), | |
2147 | ||
2148 | SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux), | |
2149 | SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux), | |
2150 | ||
2151 | SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0), | |
2152 | SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0), | |
2153 | ||
2154 | SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2155 | SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2156 | ||
2157 | SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0, | |
2158 | hpmixl, ARRAY_SIZE(hpmixl)), | |
2159 | SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0, | |
2160 | hpmixr, ARRAY_SIZE(hpmixr)), | |
2161 | ||
2162 | SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux, | |
2163 | out_pga_event, SND_SOC_DAPM_POST_PMU), | |
2164 | SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux, | |
2165 | out_pga_event, SND_SOC_DAPM_POST_PMU), | |
2166 | ||
2167 | SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event, | |
2168 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
2169 | ||
2170 | SND_SOC_DAPM_OUTPUT("HPOUTL"), | |
2171 | SND_SOC_DAPM_OUTPUT("HPOUTR"), | |
2172 | }; | |
2173 | ||
2174 | static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = { | |
2175 | SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0, | |
2176 | spkmixl, ARRAY_SIZE(spkmixl)), | |
2177 | SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux, | |
2178 | out_pga_event, SND_SOC_DAPM_POST_PMU), | |
2179 | SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0), | |
2180 | SND_SOC_DAPM_OUTPUT("SPKOUT"), | |
2181 | }; | |
2182 | ||
2183 | static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = { | |
2184 | SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0, | |
2185 | spkmixl, ARRAY_SIZE(spkmixl)), | |
2186 | SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0, | |
2187 | spkmixr, ARRAY_SIZE(spkmixr)), | |
2188 | ||
2189 | SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux, | |
2190 | out_pga_event, SND_SOC_DAPM_POST_PMU), | |
2191 | SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux, | |
2192 | out_pga_event, SND_SOC_DAPM_POST_PMU), | |
2193 | ||
2194 | SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0), | |
2195 | SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0), | |
2196 | ||
2197 | SND_SOC_DAPM_OUTPUT("SPKOUTL"), | |
2198 | SND_SOC_DAPM_OUTPUT("SPKOUTR"), | |
2199 | }; | |
2200 | ||
2201 | static const struct snd_soc_dapm_route wm8962_intercon[] = { | |
2202 | { "INPGAL", "IN1L Switch", "IN1L" }, | |
2203 | { "INPGAL", "IN2L Switch", "IN2L" }, | |
2204 | { "INPGAL", "IN3L Switch", "IN3L" }, | |
2205 | { "INPGAL", "IN4L Switch", "IN4L" }, | |
2206 | ||
2207 | { "INPGAR", "IN1R Switch", "IN1R" }, | |
2208 | { "INPGAR", "IN2R Switch", "IN2R" }, | |
2209 | { "INPGAR", "IN3R Switch", "IN3R" }, | |
2210 | { "INPGAR", "IN4R Switch", "IN4R" }, | |
2211 | ||
2212 | { "MIXINL", "IN2L Switch", "IN2L" }, | |
2213 | { "MIXINL", "IN3L Switch", "IN3L" }, | |
2214 | { "MIXINL", "PGA Switch", "INPGAL" }, | |
2215 | ||
2216 | { "MIXINR", "IN2R Switch", "IN2R" }, | |
2217 | { "MIXINR", "IN3R Switch", "IN3R" }, | |
2218 | { "MIXINR", "PGA Switch", "INPGAR" }, | |
2219 | ||
821f4206 MB |
2220 | { "MICBIAS", NULL, "SYSCLK" }, |
2221 | ||
3f7d55a1 | 2222 | { "DMIC_ENA", NULL, "DMICDAT" }, |
e47ac37c | 2223 | |
9a76f1ff MB |
2224 | { "ADCL", NULL, "SYSCLK" }, |
2225 | { "ADCL", NULL, "TOCLK" }, | |
2226 | { "ADCL", NULL, "MIXINL" }, | |
3f7d55a1 | 2227 | { "ADCL", NULL, "DMIC_ENA" }, |
6f88a4e5 | 2228 | { "ADCL", NULL, "DSP2" }, |
9a76f1ff MB |
2229 | |
2230 | { "ADCR", NULL, "SYSCLK" }, | |
2231 | { "ADCR", NULL, "TOCLK" }, | |
2232 | { "ADCR", NULL, "MIXINR" }, | |
3f7d55a1 | 2233 | { "ADCR", NULL, "DMIC_ENA" }, |
6f88a4e5 | 2234 | { "ADCR", NULL, "DSP2" }, |
9a76f1ff MB |
2235 | |
2236 | { "STL", "Left", "ADCL" }, | |
2237 | { "STL", "Right", "ADCR" }, | |
1355ab14 | 2238 | { "STL", NULL, "Class G" }, |
9a76f1ff MB |
2239 | |
2240 | { "STR", "Left", "ADCL" }, | |
2241 | { "STR", "Right", "ADCR" }, | |
1355ab14 | 2242 | { "STR", NULL, "Class G" }, |
9a76f1ff MB |
2243 | |
2244 | { "DACL", NULL, "SYSCLK" }, | |
2245 | { "DACL", NULL, "TOCLK" }, | |
2246 | { "DACL", NULL, "Beep" }, | |
2247 | { "DACL", NULL, "STL" }, | |
6f88a4e5 | 2248 | { "DACL", NULL, "DSP2" }, |
9a76f1ff MB |
2249 | |
2250 | { "DACR", NULL, "SYSCLK" }, | |
2251 | { "DACR", NULL, "TOCLK" }, | |
2252 | { "DACR", NULL, "Beep" }, | |
2253 | { "DACR", NULL, "STR" }, | |
6f88a4e5 | 2254 | { "DACR", NULL, "DSP2" }, |
9a76f1ff MB |
2255 | |
2256 | { "HPMIXL", "IN4L Switch", "IN4L" }, | |
2257 | { "HPMIXL", "IN4R Switch", "IN4R" }, | |
2258 | { "HPMIXL", "DACL Switch", "DACL" }, | |
2259 | { "HPMIXL", "DACR Switch", "DACR" }, | |
2260 | { "HPMIXL", "MIXINL Switch", "MIXINL" }, | |
2261 | { "HPMIXL", "MIXINR Switch", "MIXINR" }, | |
2262 | ||
2263 | { "HPMIXR", "IN4L Switch", "IN4L" }, | |
2264 | { "HPMIXR", "IN4R Switch", "IN4R" }, | |
2265 | { "HPMIXR", "DACL Switch", "DACL" }, | |
2266 | { "HPMIXR", "DACR Switch", "DACR" }, | |
2267 | { "HPMIXR", "MIXINL Switch", "MIXINL" }, | |
2268 | { "HPMIXR", "MIXINR Switch", "MIXINR" }, | |
2269 | ||
2270 | { "Left Bypass", NULL, "HPMIXL" }, | |
2271 | { "Left Bypass", NULL, "Class G" }, | |
2272 | ||
2273 | { "Right Bypass", NULL, "HPMIXR" }, | |
2274 | { "Right Bypass", NULL, "Class G" }, | |
2275 | ||
2276 | { "HPOUTL PGA", "Mixer", "Left Bypass" }, | |
2277 | { "HPOUTL PGA", "DAC", "DACL" }, | |
2278 | ||
2279 | { "HPOUTR PGA", "Mixer", "Right Bypass" }, | |
2280 | { "HPOUTR PGA", "DAC", "DACR" }, | |
2281 | ||
2282 | { "HPOUT", NULL, "HPOUTL PGA" }, | |
2283 | { "HPOUT", NULL, "HPOUTR PGA" }, | |
2284 | { "HPOUT", NULL, "Charge Pump" }, | |
2285 | { "HPOUT", NULL, "SYSCLK" }, | |
2286 | { "HPOUT", NULL, "TOCLK" }, | |
2287 | ||
2288 | { "HPOUTL", NULL, "HPOUT" }, | |
2289 | { "HPOUTR", NULL, "HPOUT" }, | |
94b88e64 MB |
2290 | |
2291 | { "HPOUTL", NULL, "TEMP_HP" }, | |
2292 | { "HPOUTR", NULL, "TEMP_HP" }, | |
9a76f1ff MB |
2293 | }; |
2294 | ||
2295 | static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = { | |
2296 | { "Speaker Mixer", "IN4L Switch", "IN4L" }, | |
2297 | { "Speaker Mixer", "IN4R Switch", "IN4R" }, | |
2298 | { "Speaker Mixer", "DACL Switch", "DACL" }, | |
2299 | { "Speaker Mixer", "DACR Switch", "DACR" }, | |
2300 | { "Speaker Mixer", "MIXINL Switch", "MIXINL" }, | |
2301 | { "Speaker Mixer", "MIXINR Switch", "MIXINR" }, | |
2302 | ||
2303 | { "Speaker PGA", "Mixer", "Speaker Mixer" }, | |
2304 | { "Speaker PGA", "DAC", "DACL" }, | |
2305 | ||
2306 | { "Speaker Output", NULL, "Speaker PGA" }, | |
2307 | { "Speaker Output", NULL, "SYSCLK" }, | |
2308 | { "Speaker Output", NULL, "TOCLK" }, | |
94b88e64 | 2309 | { "Speaker Output", NULL, "TEMP_SPK" }, |
9a76f1ff MB |
2310 | |
2311 | { "SPKOUT", NULL, "Speaker Output" }, | |
2312 | }; | |
2313 | ||
2314 | static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = { | |
2315 | { "SPKOUTL Mixer", "IN4L Switch", "IN4L" }, | |
2316 | { "SPKOUTL Mixer", "IN4R Switch", "IN4R" }, | |
2317 | { "SPKOUTL Mixer", "DACL Switch", "DACL" }, | |
2318 | { "SPKOUTL Mixer", "DACR Switch", "DACR" }, | |
2319 | { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" }, | |
2320 | { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" }, | |
2321 | ||
2322 | { "SPKOUTR Mixer", "IN4L Switch", "IN4L" }, | |
2323 | { "SPKOUTR Mixer", "IN4R Switch", "IN4R" }, | |
2324 | { "SPKOUTR Mixer", "DACL Switch", "DACL" }, | |
2325 | { "SPKOUTR Mixer", "DACR Switch", "DACR" }, | |
2326 | { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" }, | |
2327 | { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" }, | |
2328 | ||
2329 | { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" }, | |
2330 | { "SPKOUTL PGA", "DAC", "DACL" }, | |
2331 | ||
2332 | { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" }, | |
2333 | { "SPKOUTR PGA", "DAC", "DACR" }, | |
2334 | ||
2335 | { "SPKOUTL Output", NULL, "SPKOUTL PGA" }, | |
2336 | { "SPKOUTL Output", NULL, "SYSCLK" }, | |
2337 | { "SPKOUTL Output", NULL, "TOCLK" }, | |
94b88e64 | 2338 | { "SPKOUTL Output", NULL, "TEMP_SPK" }, |
9a76f1ff MB |
2339 | |
2340 | { "SPKOUTR Output", NULL, "SPKOUTR PGA" }, | |
2341 | { "SPKOUTR Output", NULL, "SYSCLK" }, | |
2342 | { "SPKOUTR Output", NULL, "TOCLK" }, | |
94b88e64 | 2343 | { "SPKOUTR Output", NULL, "TEMP_SPK" }, |
9a76f1ff MB |
2344 | |
2345 | { "SPKOUTL", NULL, "SPKOUTL Output" }, | |
2346 | { "SPKOUTR", NULL, "SPKOUTR Output" }, | |
2347 | }; | |
2348 | ||
2349 | static int wm8962_add_widgets(struct snd_soc_codec *codec) | |
2350 | { | |
e75a52c6 NC |
2351 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
2352 | struct wm8962_pdata *pdata = &wm8962->pdata; | |
ce6120cc | 2353 | struct snd_soc_dapm_context *dapm = &codec->dapm; |
9a76f1ff | 2354 | |
022658be | 2355 | snd_soc_add_codec_controls(codec, wm8962_snd_controls, |
9a76f1ff | 2356 | ARRAY_SIZE(wm8962_snd_controls)); |
e75a52c6 | 2357 | if (pdata->spk_mono) |
022658be | 2358 | snd_soc_add_codec_controls(codec, wm8962_spk_mono_controls, |
9a76f1ff MB |
2359 | ARRAY_SIZE(wm8962_spk_mono_controls)); |
2360 | else | |
022658be | 2361 | snd_soc_add_codec_controls(codec, wm8962_spk_stereo_controls, |
9a76f1ff MB |
2362 | ARRAY_SIZE(wm8962_spk_stereo_controls)); |
2363 | ||
2364 | ||
ce6120cc | 2365 | snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets, |
9a76f1ff | 2366 | ARRAY_SIZE(wm8962_dapm_widgets)); |
e75a52c6 | 2367 | if (pdata->spk_mono) |
ce6120cc | 2368 | snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets, |
9a76f1ff MB |
2369 | ARRAY_SIZE(wm8962_dapm_spk_mono_widgets)); |
2370 | else | |
ce6120cc | 2371 | snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets, |
9a76f1ff MB |
2372 | ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets)); |
2373 | ||
ce6120cc | 2374 | snd_soc_dapm_add_routes(dapm, wm8962_intercon, |
9a76f1ff | 2375 | ARRAY_SIZE(wm8962_intercon)); |
e75a52c6 | 2376 | if (pdata->spk_mono) |
ce6120cc | 2377 | snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon, |
9a76f1ff MB |
2378 | ARRAY_SIZE(wm8962_spk_mono_intercon)); |
2379 | else | |
ce6120cc | 2380 | snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon, |
9a76f1ff MB |
2381 | ARRAY_SIZE(wm8962_spk_stereo_intercon)); |
2382 | ||
2383 | ||
ce6120cc | 2384 | snd_soc_dapm_disable_pin(dapm, "Beep"); |
9a76f1ff MB |
2385 | |
2386 | return 0; | |
2387 | } | |
2388 | ||
9a76f1ff MB |
2389 | /* -1 for reserved values */ |
2390 | static const int bclk_divs[] = { | |
2391 | 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32 | |
2392 | }; | |
2393 | ||
417ceff9 | 2394 | static const int sysclk_rates[] = { |
07fabd1b | 2395 | 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 3072, 6144 |
417ceff9 MB |
2396 | }; |
2397 | ||
9a76f1ff MB |
2398 | static void wm8962_configure_bclk(struct snd_soc_codec *codec) |
2399 | { | |
2400 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
2401 | int dspclk, i; | |
2402 | int clocking2 = 0; | |
417ceff9 | 2403 | int clocking4 = 0; |
9a76f1ff MB |
2404 | int aif2 = 0; |
2405 | ||
417ceff9 MB |
2406 | if (!wm8962->sysclk_rate) { |
2407 | dev_dbg(codec->dev, "No SYSCLK configured\n"); | |
9a76f1ff MB |
2408 | return; |
2409 | } | |
2410 | ||
417ceff9 MB |
2411 | if (!wm8962->bclk || !wm8962->lrclk) { |
2412 | dev_dbg(codec->dev, "No audio clocks configured\n"); | |
2413 | return; | |
2414 | } | |
2415 | ||
2416 | for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) { | |
2417 | if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) { | |
2418 | clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT; | |
2419 | break; | |
2420 | } | |
2421 | } | |
2422 | ||
2423 | if (i == ARRAY_SIZE(sysclk_rates)) { | |
2424 | dev_err(codec->dev, "Unsupported sysclk ratio %d\n", | |
2425 | wm8962->sysclk_rate / wm8962->lrclk); | |
2426 | return; | |
2427 | } | |
2428 | ||
eeba1f8b MB |
2429 | dev_dbg(codec->dev, "Selected sysclk ratio %d\n", sysclk_rates[i]); |
2430 | ||
417ceff9 MB |
2431 | snd_soc_update_bits(codec, WM8962_CLOCKING_4, |
2432 | WM8962_SYSCLK_RATE_MASK, clocking4); | |
2433 | ||
9a76f1ff MB |
2434 | dspclk = snd_soc_read(codec, WM8962_CLOCKING1); |
2435 | if (dspclk < 0) { | |
2436 | dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk); | |
2437 | return; | |
2438 | } | |
2439 | ||
2440 | dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT; | |
2441 | switch (dspclk) { | |
2442 | case 0: | |
2443 | dspclk = wm8962->sysclk_rate; | |
2444 | break; | |
2445 | case 1: | |
2446 | dspclk = wm8962->sysclk_rate / 2; | |
2447 | break; | |
2448 | case 2: | |
2449 | dspclk = wm8962->sysclk_rate / 4; | |
2450 | break; | |
2451 | default: | |
2452 | dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n"); | |
2453 | dspclk = wm8962->sysclk; | |
2454 | } | |
2455 | ||
2456 | dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk); | |
2457 | ||
2458 | /* We're expecting an exact match */ | |
2459 | for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { | |
2460 | if (bclk_divs[i] < 0) | |
2461 | continue; | |
2462 | ||
2463 | if (dspclk / bclk_divs[i] == wm8962->bclk) { | |
2464 | dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n", | |
2465 | bclk_divs[i], wm8962->bclk); | |
2466 | clocking2 |= i; | |
2467 | break; | |
2468 | } | |
2469 | } | |
2470 | if (i == ARRAY_SIZE(bclk_divs)) { | |
2471 | dev_err(codec->dev, "Unsupported BCLK ratio %d\n", | |
2472 | dspclk / wm8962->bclk); | |
2473 | return; | |
2474 | } | |
2475 | ||
2476 | aif2 |= wm8962->bclk / wm8962->lrclk; | |
2477 | dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n", | |
2478 | wm8962->bclk / wm8962->lrclk, wm8962->lrclk); | |
2479 | ||
2480 | snd_soc_update_bits(codec, WM8962_CLOCKING2, | |
2481 | WM8962_BCLK_DIV_MASK, clocking2); | |
2482 | snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2, | |
2483 | WM8962_AIF_RATE_MASK, aif2); | |
2484 | } | |
2485 | ||
2486 | static int wm8962_set_bias_level(struct snd_soc_codec *codec, | |
2487 | enum snd_soc_bias_level level) | |
2488 | { | |
ce6120cc | 2489 | if (level == codec->dapm.bias_level) |
9a76f1ff MB |
2490 | return 0; |
2491 | ||
2492 | switch (level) { | |
2493 | case SND_SOC_BIAS_ON: | |
2494 | break; | |
2495 | ||
2496 | case SND_SOC_BIAS_PREPARE: | |
2497 | /* VMID 2*50k */ | |
2498 | snd_soc_update_bits(codec, WM8962_PWR_MGMT_1, | |
2499 | WM8962_VMID_SEL_MASK, 0x80); | |
417ceff9 MB |
2500 | |
2501 | wm8962_configure_bclk(codec); | |
9a76f1ff MB |
2502 | break; |
2503 | ||
2504 | case SND_SOC_BIAS_STANDBY: | |
9a76f1ff MB |
2505 | /* VMID 2*250k */ |
2506 | snd_soc_update_bits(codec, WM8962_PWR_MGMT_1, | |
2507 | WM8962_VMID_SEL_MASK, 0x100); | |
9d40e558 MB |
2508 | |
2509 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) | |
2510 | msleep(100); | |
9a76f1ff MB |
2511 | break; |
2512 | ||
2513 | case SND_SOC_BIAS_OFF: | |
9a76f1ff MB |
2514 | break; |
2515 | } | |
d23031a4 | 2516 | |
ce6120cc | 2517 | codec->dapm.bias_level = level; |
9a76f1ff MB |
2518 | return 0; |
2519 | } | |
2520 | ||
2521 | static const struct { | |
2522 | int rate; | |
2523 | int reg; | |
2524 | } sr_vals[] = { | |
2525 | { 48000, 0 }, | |
2526 | { 44100, 0 }, | |
2527 | { 32000, 1 }, | |
2528 | { 22050, 2 }, | |
2529 | { 24000, 2 }, | |
2530 | { 16000, 3 }, | |
2531 | { 11025, 4 }, | |
2532 | { 12000, 4 }, | |
2533 | { 8000, 5 }, | |
2534 | { 88200, 6 }, | |
2535 | { 96000, 6 }, | |
2536 | }; | |
2537 | ||
9a76f1ff MB |
2538 | static int wm8962_hw_params(struct snd_pcm_substream *substream, |
2539 | struct snd_pcm_hw_params *params, | |
2540 | struct snd_soc_dai *dai) | |
2541 | { | |
e6968a17 | 2542 | struct snd_soc_codec *codec = dai->codec; |
9a76f1ff | 2543 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
9a76f1ff MB |
2544 | int i; |
2545 | int aif0 = 0; | |
2546 | int adctl3 = 0; | |
9a76f1ff MB |
2547 | |
2548 | wm8962->bclk = snd_soc_params_to_bclk(params); | |
4c6c0b5e MB |
2549 | if (params_channels(params) == 1) |
2550 | wm8962->bclk *= 2; | |
2551 | ||
9a76f1ff MB |
2552 | wm8962->lrclk = params_rate(params); |
2553 | ||
2554 | for (i = 0; i < ARRAY_SIZE(sr_vals); i++) { | |
417ceff9 | 2555 | if (sr_vals[i].rate == wm8962->lrclk) { |
9a76f1ff MB |
2556 | adctl3 |= sr_vals[i].reg; |
2557 | break; | |
2558 | } | |
2559 | } | |
2560 | if (i == ARRAY_SIZE(sr_vals)) { | |
417ceff9 | 2561 | dev_err(codec->dev, "Unsupported rate %dHz\n", wm8962->lrclk); |
9a76f1ff MB |
2562 | return -EINVAL; |
2563 | } | |
2564 | ||
417ceff9 | 2565 | if (wm8962->lrclk % 8000 == 0) |
9a76f1ff MB |
2566 | adctl3 |= WM8962_SAMPLE_RATE_INT_MODE; |
2567 | ||
9a76f1ff MB |
2568 | switch (params_format(params)) { |
2569 | case SNDRV_PCM_FORMAT_S16_LE: | |
2570 | break; | |
2571 | case SNDRV_PCM_FORMAT_S20_3LE: | |
2b6712b1 | 2572 | aif0 |= 0x4; |
9a76f1ff MB |
2573 | break; |
2574 | case SNDRV_PCM_FORMAT_S24_LE: | |
2b6712b1 | 2575 | aif0 |= 0x8; |
9a76f1ff MB |
2576 | break; |
2577 | case SNDRV_PCM_FORMAT_S32_LE: | |
2b6712b1 | 2578 | aif0 |= 0xc; |
9a76f1ff MB |
2579 | break; |
2580 | default: | |
2581 | return -EINVAL; | |
2582 | } | |
2583 | ||
2584 | snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0, | |
2585 | WM8962_WL_MASK, aif0); | |
2586 | snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3, | |
2587 | WM8962_SAMPLE_RATE_INT_MODE | | |
2588 | WM8962_SAMPLE_RATE_MASK, adctl3); | |
9a76f1ff | 2589 | |
081413f2 MB |
2590 | dev_dbg(codec->dev, "hw_params set BCLK %dHz LRCLK %dHz\n", |
2591 | wm8962->bclk, wm8962->lrclk); | |
2592 | ||
1993502d MB |
2593 | if (codec->dapm.bias_level == SND_SOC_BIAS_ON) |
2594 | wm8962_configure_bclk(codec); | |
9a76f1ff MB |
2595 | |
2596 | return 0; | |
2597 | } | |
2598 | ||
2599 | static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, | |
2600 | unsigned int freq, int dir) | |
2601 | { | |
2602 | struct snd_soc_codec *codec = dai->codec; | |
2603 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
2604 | int src; | |
2605 | ||
2606 | switch (clk_id) { | |
2607 | case WM8962_SYSCLK_MCLK: | |
2608 | wm8962->sysclk = WM8962_SYSCLK_MCLK; | |
2609 | src = 0; | |
2610 | break; | |
2611 | case WM8962_SYSCLK_FLL: | |
2612 | wm8962->sysclk = WM8962_SYSCLK_FLL; | |
2613 | src = 1 << WM8962_SYSCLK_SRC_SHIFT; | |
9a76f1ff MB |
2614 | break; |
2615 | default: | |
2616 | return -EINVAL; | |
2617 | } | |
2618 | ||
2619 | snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK, | |
2620 | src); | |
2621 | ||
2622 | wm8962->sysclk_rate = freq; | |
2623 | ||
2624 | return 0; | |
2625 | } | |
2626 | ||
2627 | static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
2628 | { | |
2629 | struct snd_soc_codec *codec = dai->codec; | |
2630 | int aif0 = 0; | |
2631 | ||
2632 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
9a76f1ff | 2633 | case SND_SOC_DAIFMT_DSP_B: |
fbc7c62a SG |
2634 | aif0 |= WM8962_LRCLK_INV | 3; |
2635 | case SND_SOC_DAIFMT_DSP_A: | |
9a76f1ff MB |
2636 | aif0 |= 3; |
2637 | ||
2638 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
2639 | case SND_SOC_DAIFMT_NB_NF: | |
2640 | case SND_SOC_DAIFMT_IB_NF: | |
2641 | break; | |
2642 | default: | |
2643 | return -EINVAL; | |
2644 | } | |
2645 | break; | |
2646 | ||
2647 | case SND_SOC_DAIFMT_RIGHT_J: | |
2648 | break; | |
2649 | case SND_SOC_DAIFMT_LEFT_J: | |
2650 | aif0 |= 1; | |
2651 | break; | |
2652 | case SND_SOC_DAIFMT_I2S: | |
2653 | aif0 |= 2; | |
2654 | break; | |
2655 | default: | |
2656 | return -EINVAL; | |
2657 | } | |
2658 | ||
2659 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
2660 | case SND_SOC_DAIFMT_NB_NF: | |
2661 | break; | |
2662 | case SND_SOC_DAIFMT_IB_NF: | |
2663 | aif0 |= WM8962_BCLK_INV; | |
2664 | break; | |
2665 | case SND_SOC_DAIFMT_NB_IF: | |
2666 | aif0 |= WM8962_LRCLK_INV; | |
2667 | break; | |
2668 | case SND_SOC_DAIFMT_IB_IF: | |
2669 | aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV; | |
2670 | break; | |
2671 | default: | |
2672 | return -EINVAL; | |
2673 | } | |
2674 | ||
2675 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
2676 | case SND_SOC_DAIFMT_CBM_CFM: | |
2677 | aif0 |= WM8962_MSTR; | |
2678 | break; | |
2679 | case SND_SOC_DAIFMT_CBS_CFS: | |
2680 | break; | |
2681 | default: | |
2682 | return -EINVAL; | |
2683 | } | |
2684 | ||
2685 | snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0, | |
2686 | WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR | | |
2687 | WM8962_LRCLK_INV, aif0); | |
2688 | ||
2689 | return 0; | |
2690 | } | |
2691 | ||
2692 | struct _fll_div { | |
2693 | u16 fll_fratio; | |
2694 | u16 fll_outdiv; | |
2695 | u16 fll_refclk_div; | |
2696 | u16 n; | |
2697 | u16 theta; | |
2698 | u16 lambda; | |
2699 | }; | |
2700 | ||
2701 | /* The size in bits of the FLL divide multiplied by 10 | |
2702 | * to allow rounding later */ | |
2703 | #define FIXED_FLL_SIZE ((1 << 16) * 10) | |
2704 | ||
2705 | static struct { | |
2706 | unsigned int min; | |
2707 | unsigned int max; | |
2708 | u16 fll_fratio; | |
2709 | int ratio; | |
2710 | } fll_fratios[] = { | |
2711 | { 0, 64000, 4, 16 }, | |
2712 | { 64000, 128000, 3, 8 }, | |
2713 | { 128000, 256000, 2, 4 }, | |
2714 | { 256000, 1000000, 1, 2 }, | |
2715 | { 1000000, 13500000, 0, 1 }, | |
2716 | }; | |
2717 | ||
2718 | static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, | |
2719 | unsigned int Fout) | |
2720 | { | |
2721 | unsigned int target; | |
2722 | unsigned int div; | |
2723 | unsigned int fratio, gcd_fll; | |
2724 | int i; | |
2725 | ||
2726 | /* Fref must be <=13.5MHz */ | |
2727 | div = 1; | |
2728 | fll_div->fll_refclk_div = 0; | |
2729 | while ((Fref / div) > 13500000) { | |
2730 | div *= 2; | |
2731 | fll_div->fll_refclk_div++; | |
2732 | ||
2733 | if (div > 4) { | |
2734 | pr_err("Can't scale %dMHz input down to <=13.5MHz\n", | |
2735 | Fref); | |
2736 | return -EINVAL; | |
2737 | } | |
2738 | } | |
2739 | ||
2740 | pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout); | |
2741 | ||
2742 | /* Apply the division for our remaining calculations */ | |
2743 | Fref /= div; | |
2744 | ||
2745 | /* Fvco should be 90-100MHz; don't check the upper bound */ | |
2746 | div = 2; | |
2747 | while (Fout * div < 90000000) { | |
2748 | div++; | |
2749 | if (div > 64) { | |
2750 | pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", | |
2751 | Fout); | |
2752 | return -EINVAL; | |
2753 | } | |
2754 | } | |
2755 | target = Fout * div; | |
2756 | fll_div->fll_outdiv = div - 1; | |
2757 | ||
2758 | pr_debug("FLL Fvco=%dHz\n", target); | |
2759 | ||
25985edc | 2760 | /* Find an appropriate FLL_FRATIO and factor it out of the target */ |
9a76f1ff MB |
2761 | for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { |
2762 | if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { | |
2763 | fll_div->fll_fratio = fll_fratios[i].fll_fratio; | |
2764 | fratio = fll_fratios[i].ratio; | |
2765 | break; | |
2766 | } | |
2767 | } | |
2768 | if (i == ARRAY_SIZE(fll_fratios)) { | |
2769 | pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); | |
2770 | return -EINVAL; | |
2771 | } | |
2772 | ||
2773 | fll_div->n = target / (fratio * Fref); | |
2774 | ||
2775 | if (target % Fref == 0) { | |
2776 | fll_div->theta = 0; | |
2777 | fll_div->lambda = 0; | |
2778 | } else { | |
2779 | gcd_fll = gcd(target, fratio * Fref); | |
2780 | ||
2781 | fll_div->theta = (target - (fll_div->n * fratio * Fref)) | |
2782 | / gcd_fll; | |
2783 | fll_div->lambda = (fratio * Fref) / gcd_fll; | |
2784 | } | |
2785 | ||
2786 | pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n", | |
2787 | fll_div->n, fll_div->theta, fll_div->lambda); | |
2788 | pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n", | |
2789 | fll_div->fll_fratio, fll_div->fll_outdiv, | |
2790 | fll_div->fll_refclk_div); | |
2791 | ||
2792 | return 0; | |
2793 | } | |
2794 | ||
92a4352c | 2795 | static int wm8962_set_fll(struct snd_soc_codec *codec, int fll_id, int source, |
9a76f1ff MB |
2796 | unsigned int Fref, unsigned int Fout) |
2797 | { | |
9a76f1ff MB |
2798 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
2799 | struct _fll_div fll_div; | |
3b8a6d80 | 2800 | unsigned long timeout; |
9a76f1ff | 2801 | int ret; |
a968d9db | 2802 | int fll1 = 0; |
9a76f1ff MB |
2803 | |
2804 | /* Any change? */ | |
2805 | if (source == wm8962->fll_src && Fref == wm8962->fll_fref && | |
2806 | Fout == wm8962->fll_fout) | |
2807 | return 0; | |
2808 | ||
2809 | if (Fout == 0) { | |
2810 | dev_dbg(codec->dev, "FLL disabled\n"); | |
2811 | ||
2812 | wm8962->fll_fref = 0; | |
2813 | wm8962->fll_fout = 0; | |
2814 | ||
2815 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, | |
2816 | WM8962_FLL_ENA, 0); | |
2817 | ||
d23031a4 MB |
2818 | pm_runtime_put(codec->dev); |
2819 | ||
9a76f1ff MB |
2820 | return 0; |
2821 | } | |
2822 | ||
2823 | ret = fll_factors(&fll_div, Fref, Fout); | |
2824 | if (ret != 0) | |
2825 | return ret; | |
2826 | ||
a968d9db MB |
2827 | /* Parameters good, disable so we can reprogram */ |
2828 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0); | |
2829 | ||
9a76f1ff MB |
2830 | switch (fll_id) { |
2831 | case WM8962_FLL_MCLK: | |
2832 | case WM8962_FLL_BCLK: | |
2833 | case WM8962_FLL_OSC: | |
2834 | fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT; | |
2835 | break; | |
2836 | case WM8962_FLL_INT: | |
2837 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, | |
2838 | WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA); | |
2839 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5, | |
2840 | WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO); | |
2841 | break; | |
2842 | default: | |
2843 | dev_err(codec->dev, "Unknown FLL source %d\n", ret); | |
2844 | return -EINVAL; | |
2845 | } | |
2846 | ||
2847 | if (fll_div.theta || fll_div.lambda) | |
2848 | fll1 |= WM8962_FLL_FRAC; | |
2849 | ||
2850 | /* Stop the FLL while we reconfigure */ | |
2851 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0); | |
2852 | ||
2853 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2, | |
2854 | WM8962_FLL_OUTDIV_MASK | | |
2855 | WM8962_FLL_REFCLK_DIV_MASK, | |
2856 | (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) | | |
2857 | (fll_div.fll_refclk_div)); | |
2858 | ||
2859 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3, | |
2860 | WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio); | |
2861 | ||
2862 | snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta); | |
2863 | snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda); | |
2864 | snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n); | |
2865 | ||
4df0cb2f MB |
2866 | try_wait_for_completion(&wm8962->fll_lock); |
2867 | ||
d23031a4 | 2868 | pm_runtime_get_sync(codec->dev); |
2a761cde | 2869 | |
9a76f1ff MB |
2870 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, |
2871 | WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK | | |
a968d9db | 2872 | WM8962_FLL_ENA, fll1 | WM8962_FLL_ENA); |
9a76f1ff MB |
2873 | |
2874 | dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); | |
2875 | ||
649a1a0e | 2876 | ret = 0; |
3b8a6d80 | 2877 | |
346f1d40 MB |
2878 | /* This should be a massive overestimate but go even |
2879 | * higher if we'll error out | |
2880 | */ | |
2881 | if (wm8962->irq) | |
2882 | timeout = msecs_to_jiffies(5); | |
2883 | else | |
2884 | timeout = msecs_to_jiffies(1); | |
649a1a0e | 2885 | |
346f1d40 MB |
2886 | timeout = wait_for_completion_timeout(&wm8962->fll_lock, |
2887 | timeout); | |
649a1a0e | 2888 | |
346f1d40 MB |
2889 | if (timeout == 0 && wm8962->irq) { |
2890 | dev_err(codec->dev, "FLL lock timed out"); | |
2891 | ret = -ETIMEDOUT; | |
649a1a0e | 2892 | } |
3b8a6d80 | 2893 | |
9a76f1ff MB |
2894 | wm8962->fll_fref = Fref; |
2895 | wm8962->fll_fout = Fout; | |
2896 | wm8962->fll_src = source; | |
2897 | ||
649a1a0e | 2898 | return ret; |
9a76f1ff MB |
2899 | } |
2900 | ||
2901 | static int wm8962_mute(struct snd_soc_dai *dai, int mute) | |
2902 | { | |
2903 | struct snd_soc_codec *codec = dai->codec; | |
2904 | int val; | |
2905 | ||
2906 | if (mute) | |
2907 | val = WM8962_DAC_MUTE; | |
2908 | else | |
2909 | val = 0; | |
2910 | ||
2911 | return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1, | |
2912 | WM8962_DAC_MUTE, val); | |
2913 | } | |
2914 | ||
2915 | #define WM8962_RATES SNDRV_PCM_RATE_8000_96000 | |
2916 | ||
2917 | #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
2918 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
2919 | ||
85e7652d | 2920 | static const struct snd_soc_dai_ops wm8962_dai_ops = { |
9a76f1ff MB |
2921 | .hw_params = wm8962_hw_params, |
2922 | .set_sysclk = wm8962_set_dai_sysclk, | |
2923 | .set_fmt = wm8962_set_dai_fmt, | |
9a76f1ff MB |
2924 | .digital_mute = wm8962_mute, |
2925 | }; | |
2926 | ||
54d8d0ae MB |
2927 | static struct snd_soc_dai_driver wm8962_dai = { |
2928 | .name = "wm8962", | |
9a76f1ff MB |
2929 | .playback = { |
2930 | .stream_name = "Playback", | |
4c6c0b5e | 2931 | .channels_min = 1, |
9a76f1ff MB |
2932 | .channels_max = 2, |
2933 | .rates = WM8962_RATES, | |
2934 | .formats = WM8962_FORMATS, | |
2935 | }, | |
2936 | .capture = { | |
2937 | .stream_name = "Capture", | |
4c6c0b5e | 2938 | .channels_min = 1, |
9a76f1ff MB |
2939 | .channels_max = 2, |
2940 | .rates = WM8962_RATES, | |
2941 | .formats = WM8962_FORMATS, | |
2942 | }, | |
2943 | .ops = &wm8962_dai_ops, | |
2944 | .symmetric_rates = 1, | |
2945 | }; | |
9a76f1ff | 2946 | |
7711308a MB |
2947 | static void wm8962_mic_work(struct work_struct *work) |
2948 | { | |
2949 | struct wm8962_priv *wm8962 = container_of(work, | |
2950 | struct wm8962_priv, | |
2951 | mic_work.work); | |
2952 | struct snd_soc_codec *codec = wm8962->codec; | |
2953 | int status = 0; | |
2954 | int irq_pol = 0; | |
2955 | int reg; | |
2956 | ||
2957 | reg = snd_soc_read(codec, WM8962_ADDITIONAL_CONTROL_4); | |
2958 | ||
2959 | if (reg & WM8962_MICDET_STS) { | |
2960 | status |= SND_JACK_MICROPHONE; | |
2961 | irq_pol |= WM8962_MICD_IRQ_POL; | |
2962 | } | |
2963 | ||
2964 | if (reg & WM8962_MICSHORT_STS) { | |
2965 | status |= SND_JACK_BTN_0; | |
2966 | irq_pol |= WM8962_MICSCD_IRQ_POL; | |
2967 | } | |
2968 | ||
2969 | snd_soc_jack_report(wm8962->jack, status, | |
2970 | SND_JACK_MICROPHONE | SND_JACK_BTN_0); | |
2971 | ||
2972 | snd_soc_update_bits(codec, WM8962_MICINT_SOURCE_POL, | |
2973 | WM8962_MICSCD_IRQ_POL | | |
2974 | WM8962_MICD_IRQ_POL, irq_pol); | |
2975 | } | |
2976 | ||
45e65504 MB |
2977 | static irqreturn_t wm8962_irq(int irq, void *data) |
2978 | { | |
0512615d MB |
2979 | struct device *dev = data; |
2980 | struct wm8962_priv *wm8962 = dev_get_drvdata(dev); | |
2981 | unsigned int mask; | |
2982 | unsigned int active; | |
2983 | int reg, ret; | |
45e65504 | 2984 | |
0512615d MB |
2985 | ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK, |
2986 | &mask); | |
2987 | if (ret != 0) { | |
2988 | dev_err(dev, "Failed to read interrupt mask: %d\n", | |
2989 | ret); | |
2990 | return IRQ_NONE; | |
2991 | } | |
45e65504 | 2992 | |
0512615d MB |
2993 | ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, &active); |
2994 | if (ret != 0) { | |
2995 | dev_err(dev, "Failed to read interrupt: %d\n", ret); | |
2996 | return IRQ_NONE; | |
2997 | } | |
45e65504 | 2998 | |
45e65504 MB |
2999 | active &= ~mask; |
3000 | ||
e6ef5870 MB |
3001 | if (!active) |
3002 | return IRQ_NONE; | |
3003 | ||
3198b9eb | 3004 | /* Acknowledge the interrupts */ |
0512615d MB |
3005 | ret = regmap_write(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, active); |
3006 | if (ret != 0) | |
3007 | dev_warn(dev, "Failed to ack interrupt: %d\n", ret); | |
3198b9eb | 3008 | |
3b8a6d80 | 3009 | if (active & WM8962_FLL_LOCK_EINT) { |
0512615d | 3010 | dev_dbg(dev, "FLL locked\n"); |
3b8a6d80 MB |
3011 | complete(&wm8962->fll_lock); |
3012 | } | |
3013 | ||
45e65504 | 3014 | if (active & WM8962_FIFOS_ERR_EINT) |
0512615d | 3015 | dev_err(dev, "FIFO error\n"); |
45e65504 | 3016 | |
fbf04076 | 3017 | if (active & WM8962_TEMP_SHUT_EINT) { |
0512615d | 3018 | dev_crit(dev, "Thermal shutdown\n"); |
45e65504 | 3019 | |
0512615d MB |
3020 | ret = regmap_read(wm8962->regmap, |
3021 | WM8962_THERMAL_SHUTDOWN_STATUS, ®); | |
3022 | if (ret != 0) { | |
3023 | dev_warn(dev, "Failed to read thermal status: %d\n", | |
3024 | ret); | |
3025 | reg = 0; | |
3026 | } | |
fbf04076 MB |
3027 | |
3028 | if (reg & WM8962_TEMP_ERR_HP) | |
0512615d | 3029 | dev_crit(dev, "Headphone thermal error\n"); |
fbf04076 | 3030 | if (reg & WM8962_TEMP_WARN_HP) |
0512615d | 3031 | dev_crit(dev, "Headphone thermal warning\n"); |
fbf04076 | 3032 | if (reg & WM8962_TEMP_ERR_SPK) |
0512615d | 3033 | dev_crit(dev, "Speaker thermal error\n"); |
fbf04076 | 3034 | if (reg & WM8962_TEMP_WARN_SPK) |
0512615d | 3035 | dev_crit(dev, "Speaker thermal warning\n"); |
fbf04076 MB |
3036 | } |
3037 | ||
7711308a | 3038 | if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) { |
0512615d | 3039 | dev_dbg(dev, "Microphone event detected\n"); |
7711308a | 3040 | |
6dc47e97 | 3041 | #ifndef CONFIG_SND_SOC_WM8962_MODULE |
0512615d | 3042 | trace_snd_soc_jack_irq(dev_name(dev)); |
1435b940 | 3043 | #endif |
2bbb5d66 | 3044 | |
0512615d | 3045 | pm_wakeup_event(dev, 300); |
11e16eb3 | 3046 | |
da72c961 MB |
3047 | queue_delayed_work(system_power_efficient_wq, |
3048 | &wm8962->mic_work, | |
3049 | msecs_to_jiffies(250)); | |
7711308a MB |
3050 | } |
3051 | ||
45e65504 MB |
3052 | return IRQ_HANDLED; |
3053 | } | |
3054 | ||
7711308a MB |
3055 | /** |
3056 | * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ | |
3057 | * | |
3058 | * @codec: WM8962 codec | |
3059 | * @jack: jack to report detection events on | |
3060 | * | |
3061 | * Enable microphone detection via IRQ on the WM8962. If GPIOs are | |
3062 | * being used to bring out signals to the processor then only platform | |
3063 | * data configuration is needed for WM8962 and processor GPIOs should | |
3064 | * be configured using snd_soc_jack_add_gpios() instead. | |
3065 | * | |
3066 | * If no jack is supplied detection will be disabled. | |
3067 | */ | |
3068 | int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack) | |
3069 | { | |
3070 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
3071 | int irq_mask, enable; | |
3072 | ||
3073 | wm8962->jack = jack; | |
3074 | if (jack) { | |
3075 | irq_mask = 0; | |
3076 | enable = WM8962_MICDET_ENA; | |
3077 | } else { | |
3078 | irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT; | |
3079 | enable = 0; | |
3080 | } | |
3081 | ||
3082 | snd_soc_update_bits(codec, WM8962_INTERRUPT_STATUS_2_MASK, | |
3083 | WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask); | |
3084 | snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4, | |
3085 | WM8962_MICDET_ENA, enable); | |
3086 | ||
3087 | /* Send an initial empty report */ | |
3088 | snd_soc_jack_report(wm8962->jack, 0, | |
3089 | SND_JACK_MICROPHONE | SND_JACK_BTN_0); | |
3090 | ||
a5ef9884 | 3091 | if (jack) { |
db0e5543 | 3092 | snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK"); |
a5ef9884 | 3093 | snd_soc_dapm_force_enable_pin(&codec->dapm, "MICBIAS"); |
00ae3b86 MB |
3094 | } else { |
3095 | snd_soc_dapm_disable_pin(&codec->dapm, "SYSCLK"); | |
3096 | snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS"); | |
a5ef9884 | 3097 | } |
db0e5543 | 3098 | |
7711308a MB |
3099 | return 0; |
3100 | } | |
3101 | EXPORT_SYMBOL_GPL(wm8962_mic_detect); | |
3102 | ||
9a76f1ff MB |
3103 | #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE) |
3104 | static int beep_rates[] = { | |
3105 | 500, 1000, 2000, 4000, | |
3106 | }; | |
3107 | ||
3108 | static void wm8962_beep_work(struct work_struct *work) | |
3109 | { | |
3110 | struct wm8962_priv *wm8962 = | |
3111 | container_of(work, struct wm8962_priv, beep_work); | |
54d8d0ae | 3112 | struct snd_soc_codec *codec = wm8962->codec; |
ce6120cc | 3113 | struct snd_soc_dapm_context *dapm = &codec->dapm; |
9a76f1ff MB |
3114 | int i; |
3115 | int reg = 0; | |
3116 | int best = 0; | |
3117 | ||
3118 | if (wm8962->beep_rate) { | |
3119 | for (i = 0; i < ARRAY_SIZE(beep_rates); i++) { | |
3120 | if (abs(wm8962->beep_rate - beep_rates[i]) < | |
3121 | abs(wm8962->beep_rate - beep_rates[best])) | |
3122 | best = i; | |
3123 | } | |
3124 | ||
3125 | dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n", | |
3126 | beep_rates[best], wm8962->beep_rate); | |
3127 | ||
3128 | reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT); | |
3129 | ||
ce6120cc | 3130 | snd_soc_dapm_enable_pin(dapm, "Beep"); |
9a76f1ff MB |
3131 | } else { |
3132 | dev_dbg(codec->dev, "Disabling beep\n"); | |
ce6120cc | 3133 | snd_soc_dapm_disable_pin(dapm, "Beep"); |
9a76f1ff MB |
3134 | } |
3135 | ||
3136 | snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, | |
3137 | WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg); | |
3138 | ||
ce6120cc | 3139 | snd_soc_dapm_sync(dapm); |
9a76f1ff MB |
3140 | } |
3141 | ||
3142 | /* For usability define a way of injecting beep events for the device - | |
3143 | * many systems will not have a keyboard. | |
3144 | */ | |
3145 | static int wm8962_beep_event(struct input_dev *dev, unsigned int type, | |
3146 | unsigned int code, int hz) | |
3147 | { | |
3148 | struct snd_soc_codec *codec = input_get_drvdata(dev); | |
3149 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
3150 | ||
3151 | dev_dbg(codec->dev, "Beep event %x %x\n", code, hz); | |
3152 | ||
3153 | switch (code) { | |
3154 | case SND_BELL: | |
3155 | if (hz) | |
3156 | hz = 1000; | |
3157 | case SND_TONE: | |
3158 | break; | |
3159 | default: | |
3160 | return -1; | |
3161 | } | |
3162 | ||
3163 | /* Kick the beep from a workqueue */ | |
3164 | wm8962->beep_rate = hz; | |
3165 | schedule_work(&wm8962->beep_work); | |
3166 | return 0; | |
3167 | } | |
3168 | ||
3169 | static ssize_t wm8962_beep_set(struct device *dev, | |
3170 | struct device_attribute *attr, | |
3171 | const char *buf, size_t count) | |
3172 | { | |
3173 | struct wm8962_priv *wm8962 = dev_get_drvdata(dev); | |
3174 | long int time; | |
74a557e2 | 3175 | int ret; |
9a76f1ff | 3176 | |
b785a492 | 3177 | ret = kstrtol(buf, 10, &time); |
74a557e2 MB |
3178 | if (ret != 0) |
3179 | return ret; | |
9a76f1ff MB |
3180 | |
3181 | input_event(wm8962->beep, EV_SND, SND_TONE, time); | |
3182 | ||
3183 | return count; | |
3184 | } | |
3185 | ||
3186 | static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set); | |
3187 | ||
3188 | static void wm8962_init_beep(struct snd_soc_codec *codec) | |
3189 | { | |
3190 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
3191 | int ret; | |
3192 | ||
a2ce6475 | 3193 | wm8962->beep = devm_input_allocate_device(codec->dev); |
9a76f1ff MB |
3194 | if (!wm8962->beep) { |
3195 | dev_err(codec->dev, "Failed to allocate beep device\n"); | |
3196 | return; | |
3197 | } | |
3198 | ||
3199 | INIT_WORK(&wm8962->beep_work, wm8962_beep_work); | |
3200 | wm8962->beep_rate = 0; | |
3201 | ||
3202 | wm8962->beep->name = "WM8962 Beep Generator"; | |
3203 | wm8962->beep->phys = dev_name(codec->dev); | |
3204 | wm8962->beep->id.bustype = BUS_I2C; | |
3205 | ||
3206 | wm8962->beep->evbit[0] = BIT_MASK(EV_SND); | |
3207 | wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE); | |
3208 | wm8962->beep->event = wm8962_beep_event; | |
3209 | wm8962->beep->dev.parent = codec->dev; | |
3210 | input_set_drvdata(wm8962->beep, codec); | |
3211 | ||
3212 | ret = input_register_device(wm8962->beep); | |
3213 | if (ret != 0) { | |
9a76f1ff MB |
3214 | wm8962->beep = NULL; |
3215 | dev_err(codec->dev, "Failed to register beep device\n"); | |
3216 | } | |
3217 | ||
3218 | ret = device_create_file(codec->dev, &dev_attr_beep); | |
3219 | if (ret != 0) { | |
3220 | dev_err(codec->dev, "Failed to create keyclick file: %d\n", | |
3221 | ret); | |
3222 | } | |
3223 | } | |
3224 | ||
3225 | static void wm8962_free_beep(struct snd_soc_codec *codec) | |
3226 | { | |
3227 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
3228 | ||
3229 | device_remove_file(codec->dev, &dev_attr_beep); | |
9a76f1ff MB |
3230 | cancel_work_sync(&wm8962->beep_work); |
3231 | wm8962->beep = NULL; | |
3232 | ||
3233 | snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0); | |
3234 | } | |
3235 | #else | |
3236 | static void wm8962_init_beep(struct snd_soc_codec *codec) | |
3237 | { | |
3238 | } | |
3239 | ||
3240 | static void wm8962_free_beep(struct snd_soc_codec *codec) | |
3241 | { | |
3242 | } | |
3243 | #endif | |
3244 | ||
8ca2aa9c MB |
3245 | static void wm8962_set_gpio_mode(struct snd_soc_codec *codec, int gpio) |
3246 | { | |
3247 | int mask = 0; | |
3248 | int val = 0; | |
3249 | ||
3250 | /* Some of the GPIOs are behind MFP configuration and need to | |
3251 | * be put into GPIO mode. */ | |
3252 | switch (gpio) { | |
3253 | case 2: | |
3254 | mask = WM8962_CLKOUT2_SEL_MASK; | |
3255 | val = 1 << WM8962_CLKOUT2_SEL_SHIFT; | |
3256 | break; | |
3257 | case 3: | |
3258 | mask = WM8962_CLKOUT3_SEL_MASK; | |
3259 | val = 1 << WM8962_CLKOUT3_SEL_SHIFT; | |
3260 | break; | |
3261 | default: | |
3262 | break; | |
3263 | } | |
3264 | ||
3265 | if (mask) | |
3266 | snd_soc_update_bits(codec, WM8962_ANALOGUE_CLOCKING1, | |
3267 | mask, val); | |
3268 | } | |
3269 | ||
3367b8d4 MB |
3270 | #ifdef CONFIG_GPIOLIB |
3271 | static inline struct wm8962_priv *gpio_to_wm8962(struct gpio_chip *chip) | |
3272 | { | |
3273 | return container_of(chip, struct wm8962_priv, gpio_chip); | |
3274 | } | |
3275 | ||
3276 | static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset) | |
3277 | { | |
3278 | struct wm8962_priv *wm8962 = gpio_to_wm8962(chip); | |
3279 | struct snd_soc_codec *codec = wm8962->codec; | |
3367b8d4 MB |
3280 | |
3281 | /* The WM8962 GPIOs aren't linearly numbered. For simplicity | |
3282 | * we export linear numbers and error out if the unsupported | |
3283 | * ones are requsted. | |
3284 | */ | |
3285 | switch (offset + 1) { | |
3286 | case 2: | |
3367b8d4 | 3287 | case 3: |
3367b8d4 MB |
3288 | case 5: |
3289 | case 6: | |
3290 | break; | |
3291 | default: | |
3292 | return -EINVAL; | |
3293 | } | |
3294 | ||
8ca2aa9c | 3295 | wm8962_set_gpio_mode(codec, offset + 1); |
3367b8d4 MB |
3296 | |
3297 | return 0; | |
3298 | } | |
3299 | ||
3300 | static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
3301 | { | |
3302 | struct wm8962_priv *wm8962 = gpio_to_wm8962(chip); | |
3303 | struct snd_soc_codec *codec = wm8962->codec; | |
3304 | ||
3305 | snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset, | |
d71bb810 | 3306 | WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT); |
3367b8d4 MB |
3307 | } |
3308 | ||
3309 | static int wm8962_gpio_direction_out(struct gpio_chip *chip, | |
3310 | unsigned offset, int value) | |
3311 | { | |
3312 | struct wm8962_priv *wm8962 = gpio_to_wm8962(chip); | |
3313 | struct snd_soc_codec *codec = wm8962->codec; | |
fe75fe0e | 3314 | int ret, val; |
3367b8d4 MB |
3315 | |
3316 | /* Force function 1 (logic output) */ | |
3317 | val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT); | |
3318 | ||
fe75fe0e AL |
3319 | ret = snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset, |
3320 | WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val); | |
3321 | if (ret < 0) | |
3322 | return ret; | |
3323 | ||
3324 | return 0; | |
3367b8d4 MB |
3325 | } |
3326 | ||
3327 | static struct gpio_chip wm8962_template_chip = { | |
3328 | .label = "wm8962", | |
3329 | .owner = THIS_MODULE, | |
3330 | .request = wm8962_gpio_request, | |
3331 | .direction_output = wm8962_gpio_direction_out, | |
3332 | .set = wm8962_gpio_set, | |
3333 | .can_sleep = 1, | |
3334 | }; | |
3335 | ||
3336 | static void wm8962_init_gpio(struct snd_soc_codec *codec) | |
3337 | { | |
3338 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
e75a52c6 | 3339 | struct wm8962_pdata *pdata = &wm8962->pdata; |
3367b8d4 MB |
3340 | int ret; |
3341 | ||
3342 | wm8962->gpio_chip = wm8962_template_chip; | |
3343 | wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO; | |
3344 | wm8962->gpio_chip.dev = codec->dev; | |
3345 | ||
e75a52c6 | 3346 | if (pdata->gpio_base) |
3367b8d4 MB |
3347 | wm8962->gpio_chip.base = pdata->gpio_base; |
3348 | else | |
3349 | wm8962->gpio_chip.base = -1; | |
3350 | ||
3351 | ret = gpiochip_add(&wm8962->gpio_chip); | |
3352 | if (ret != 0) | |
3353 | dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret); | |
3354 | } | |
3355 | ||
3356 | static void wm8962_free_gpio(struct snd_soc_codec *codec) | |
3357 | { | |
3358 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); | |
3359 | int ret; | |
3360 | ||
3361 | ret = gpiochip_remove(&wm8962->gpio_chip); | |
3362 | if (ret != 0) | |
3363 | dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret); | |
3364 | } | |
3365 | #else | |
3366 | static void wm8962_init_gpio(struct snd_soc_codec *codec) | |
3367 | { | |
3368 | } | |
3369 | ||
3370 | static void wm8962_free_gpio(struct snd_soc_codec *codec) | |
3371 | { | |
3372 | } | |
3373 | #endif | |
3374 | ||
54d8d0ae | 3375 | static int wm8962_probe(struct snd_soc_codec *codec) |
9a76f1ff MB |
3376 | { |
3377 | int ret; | |
54d8d0ae | 3378 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
4642aabd | 3379 | struct wm8962_pdata *pdata = &wm8962->pdata; |
ca50410b | 3380 | int i; |
e47ac37c | 3381 | bool dmicclk, dmicdat; |
9a76f1ff | 3382 | |
54d8d0ae | 3383 | wm8962->codec = codec; |
7b16f560 | 3384 | codec->control_data = wm8962->regmap; |
9a76f1ff | 3385 | |
7b16f560 | 3386 | ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP); |
9a76f1ff MB |
3387 | if (ret != 0) { |
3388 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); | |
7b16f560 | 3389 | return ret; |
9a76f1ff MB |
3390 | } |
3391 | ||
3392 | wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0; | |
3393 | wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1; | |
3394 | wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2; | |
3395 | wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3; | |
3396 | wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4; | |
3397 | wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5; | |
3398 | wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6; | |
3399 | wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7; | |
3400 | ||
3401 | /* This should really be moved into the regulator core */ | |
3402 | for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) { | |
3403 | ret = regulator_register_notifier(wm8962->supplies[i].consumer, | |
3404 | &wm8962->disable_nb[i]); | |
3405 | if (ret != 0) { | |
3406 | dev_err(codec->dev, | |
3407 | "Failed to register regulator notifier: %d\n", | |
3408 | ret); | |
3409 | } | |
3410 | } | |
3411 | ||
9a76f1ff MB |
3412 | /* SYSCLK defaults to on; make sure it is off so we can safely |
3413 | * write to registers if the device is declocked. | |
3414 | */ | |
3415 | snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0); | |
3416 | ||
a115c728 MB |
3417 | /* Ensure we have soft control over all registers */ |
3418 | snd_soc_update_bits(codec, WM8962_CLOCKING2, | |
3419 | WM8962_CLKREG_OVD, WM8962_CLKREG_OVD); | |
3420 | ||
2af8de8c MB |
3421 | /* Ensure that the oscillator and PLLs are disabled */ |
3422 | snd_soc_update_bits(codec, WM8962_PLL2, | |
3423 | WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA, | |
3424 | 0); | |
3425 | ||
e75a52c6 NC |
3426 | /* Apply static configuration for GPIOs */ |
3427 | for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++) | |
3428 | if (pdata->gpio_init[i]) { | |
3429 | wm8962_set_gpio_mode(codec, i + 1); | |
3430 | snd_soc_write(codec, 0x200 + i, | |
3431 | pdata->gpio_init[i] & 0xffff); | |
3432 | } | |
9a76f1ff | 3433 | |
384b8345 | 3434 | |
e75a52c6 NC |
3435 | /* Put the speakers into mono mode? */ |
3436 | if (pdata->spk_mono) | |
384b8345 | 3437 | snd_soc_update_bits(codec, WM8962_CLASS_D_CONTROL_2, |
2e7ee15c NC |
3438 | WM8962_SPK_MONO_MASK, WM8962_SPK_MONO); |
3439 | ||
e75a52c6 NC |
3440 | /* Micbias setup, detection enable and detection |
3441 | * threasholds. */ | |
3442 | if (pdata->mic_cfg) | |
3443 | snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4, | |
3444 | WM8962_MICDET_ENA | | |
3445 | WM8962_MICDET_THR_MASK | | |
3446 | WM8962_MICSHORT_THR_MASK | | |
3447 | WM8962_MICBIAS_LVL, | |
3448 | pdata->mic_cfg); | |
9a76f1ff MB |
3449 | |
3450 | /* Latch volume update bits */ | |
a1b3b5ee MB |
3451 | snd_soc_update_bits(codec, WM8962_LEFT_INPUT_VOLUME, |
3452 | WM8962_IN_VU, WM8962_IN_VU); | |
3453 | snd_soc_update_bits(codec, WM8962_RIGHT_INPUT_VOLUME, | |
3454 | WM8962_IN_VU, WM8962_IN_VU); | |
3455 | snd_soc_update_bits(codec, WM8962_LEFT_ADC_VOLUME, | |
3456 | WM8962_ADC_VU, WM8962_ADC_VU); | |
3457 | snd_soc_update_bits(codec, WM8962_RIGHT_ADC_VOLUME, | |
3458 | WM8962_ADC_VU, WM8962_ADC_VU); | |
3459 | snd_soc_update_bits(codec, WM8962_LEFT_DAC_VOLUME, | |
3460 | WM8962_DAC_VU, WM8962_DAC_VU); | |
3461 | snd_soc_update_bits(codec, WM8962_RIGHT_DAC_VOLUME, | |
3462 | WM8962_DAC_VU, WM8962_DAC_VU); | |
3463 | snd_soc_update_bits(codec, WM8962_SPKOUTL_VOLUME, | |
3464 | WM8962_SPKOUT_VU, WM8962_SPKOUT_VU); | |
3465 | snd_soc_update_bits(codec, WM8962_SPKOUTR_VOLUME, | |
3466 | WM8962_SPKOUT_VU, WM8962_SPKOUT_VU); | |
3467 | snd_soc_update_bits(codec, WM8962_HPOUTL_VOLUME, | |
3468 | WM8962_HPOUT_VU, WM8962_HPOUT_VU); | |
3469 | snd_soc_update_bits(codec, WM8962_HPOUTR_VOLUME, | |
3470 | WM8962_HPOUT_VU, WM8962_HPOUT_VU); | |
9a76f1ff | 3471 | |
8f63aaa8 MB |
3472 | /* Stereo control for EQ */ |
3473 | snd_soc_update_bits(codec, WM8962_EQ1, WM8962_EQ_SHARED_COEFF, 0); | |
3474 | ||
0469e7b9 MB |
3475 | /* Don't debouce interrupts so we don't need SYSCLK */ |
3476 | snd_soc_update_bits(codec, WM8962_IRQ_DEBOUNCE, | |
3477 | WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB | | |
3478 | WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB, | |
3479 | 0); | |
3480 | ||
54d8d0ae | 3481 | wm8962_add_widgets(codec); |
9a76f1ff | 3482 | |
e47ac37c MB |
3483 | /* Save boards having to disable DMIC when not in use */ |
3484 | dmicclk = false; | |
3485 | dmicdat = false; | |
3486 | for (i = 0; i < WM8962_MAX_GPIO; i++) { | |
3487 | switch (snd_soc_read(codec, WM8962_GPIO_BASE + i) | |
3488 | & WM8962_GP2_FN_MASK) { | |
3489 | case WM8962_GPIO_FN_DMICCLK: | |
3490 | dmicclk = true; | |
3491 | break; | |
3492 | case WM8962_GPIO_FN_DMICDAT: | |
3493 | dmicdat = true; | |
3494 | break; | |
3495 | default: | |
3496 | break; | |
3497 | } | |
3498 | } | |
3499 | if (!dmicclk || !dmicdat) { | |
3500 | dev_dbg(codec->dev, "DMIC not in use, disabling\n"); | |
3501 | snd_soc_dapm_nc_pin(&codec->dapm, "DMICDAT"); | |
3502 | } | |
3503 | if (dmicclk != dmicdat) | |
3504 | dev_warn(codec->dev, "DMIC GPIOs partially configured\n"); | |
3505 | ||
9a76f1ff | 3506 | wm8962_init_beep(codec); |
3367b8d4 | 3507 | wm8962_init_gpio(codec); |
9a76f1ff MB |
3508 | |
3509 | return 0; | |
9a76f1ff MB |
3510 | } |
3511 | ||
54d8d0ae | 3512 | static int wm8962_remove(struct snd_soc_codec *codec) |
9a76f1ff | 3513 | { |
54d8d0ae | 3514 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
9a76f1ff MB |
3515 | int i; |
3516 | ||
7711308a MB |
3517 | cancel_delayed_work_sync(&wm8962->mic_work); |
3518 | ||
3367b8d4 | 3519 | wm8962_free_gpio(codec); |
54d8d0ae | 3520 | wm8962_free_beep(codec); |
9a76f1ff MB |
3521 | for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) |
3522 | regulator_unregister_notifier(wm8962->supplies[i].consumer, | |
3523 | &wm8962->disable_nb[i]); | |
54d8d0ae MB |
3524 | |
3525 | return 0; | |
9a76f1ff MB |
3526 | } |
3527 | ||
54d8d0ae MB |
3528 | static struct snd_soc_codec_driver soc_codec_dev_wm8962 = { |
3529 | .probe = wm8962_probe, | |
3530 | .remove = wm8962_remove, | |
54d8d0ae | 3531 | .set_bias_level = wm8962_set_bias_level, |
92a4352c | 3532 | .set_pll = wm8962_set_fll, |
2693efd6 | 3533 | .idle_bias_off = true, |
54d8d0ae MB |
3534 | }; |
3535 | ||
182c51ce MB |
3536 | /* Improve power consumption for IN4 DC measurement mode */ |
3537 | static const struct reg_default wm8962_dc_measure[] = { | |
3538 | { 0xfd, 0x1 }, | |
3539 | { 0xcc, 0x40 }, | |
3540 | { 0xfd, 0 }, | |
54d8d0ae MB |
3541 | }; |
3542 | ||
7b16f560 MB |
3543 | static const struct regmap_config wm8962_regmap = { |
3544 | .reg_bits = 16, | |
3545 | .val_bits = 16, | |
3546 | ||
3547 | .max_register = WM8962_MAX_REGISTER, | |
3548 | .reg_defaults = wm8962_reg, | |
3549 | .num_reg_defaults = ARRAY_SIZE(wm8962_reg), | |
3550 | .volatile_reg = wm8962_volatile_register, | |
3551 | .readable_reg = wm8962_readable_register, | |
3552 | .cache_type = REGCACHE_RBTREE, | |
3553 | }; | |
3554 | ||
d74e9e70 NC |
3555 | static int wm8962_set_pdata_from_of(struct i2c_client *i2c, |
3556 | struct wm8962_pdata *pdata) | |
3557 | { | |
3558 | const struct device_node *np = i2c->dev.of_node; | |
3559 | u32 val32; | |
3560 | int i; | |
3561 | ||
3562 | if (of_property_read_bool(np, "spk-mono")) | |
3563 | pdata->spk_mono = true; | |
3564 | ||
3565 | if (of_property_read_u32(np, "mic-cfg", &val32) >= 0) | |
3566 | pdata->mic_cfg = val32; | |
3567 | ||
3568 | if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_init, | |
3569 | ARRAY_SIZE(pdata->gpio_init)) >= 0) | |
3570 | for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++) { | |
3571 | /* | |
3572 | * The range of GPIO register value is [0x0, 0xffff] | |
3573 | * While the default value of each register is 0x0 | |
3574 | * Any other value will be regarded as default value | |
3575 | */ | |
3576 | if (pdata->gpio_init[i] > 0xffff) | |
3577 | pdata->gpio_init[i] = 0x0; | |
3578 | } | |
3579 | ||
3580 | return 0; | |
3581 | } | |
3582 | ||
7a79e94e BP |
3583 | static int wm8962_i2c_probe(struct i2c_client *i2c, |
3584 | const struct i2c_device_id *id) | |
9a76f1ff | 3585 | { |
182c51ce | 3586 | struct wm8962_pdata *pdata = dev_get_platdata(&i2c->dev); |
9a76f1ff | 3587 | struct wm8962_priv *wm8962; |
7b16f560 | 3588 | unsigned int reg; |
ca50410b | 3589 | int ret, i, irq_pol, trigger; |
9a76f1ff | 3590 | |
be086aa8 MB |
3591 | wm8962 = devm_kzalloc(&i2c->dev, sizeof(struct wm8962_priv), |
3592 | GFP_KERNEL); | |
9a76f1ff MB |
3593 | if (wm8962 == NULL) |
3594 | return -ENOMEM; | |
3595 | ||
9a76f1ff | 3596 | i2c_set_clientdata(i2c, wm8962); |
9a76f1ff | 3597 | |
7b16f560 MB |
3598 | INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work); |
3599 | init_completion(&wm8962->fll_lock); | |
c7356da9 MB |
3600 | wm8962->irq = i2c->irq; |
3601 | ||
e75a52c6 | 3602 | /* If platform data was supplied, update the default data in priv */ |
d74e9e70 | 3603 | if (pdata) { |
e75a52c6 | 3604 | memcpy(&wm8962->pdata, pdata, sizeof(struct wm8962_pdata)); |
d74e9e70 NC |
3605 | } else if (i2c->dev.of_node) { |
3606 | ret = wm8962_set_pdata_from_of(i2c, &wm8962->pdata); | |
3607 | if (ret != 0) | |
3608 | return ret; | |
3609 | } | |
e75a52c6 | 3610 | |
7b16f560 MB |
3611 | for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) |
3612 | wm8962->supplies[i].supply = wm8962_supply_names[i]; | |
3613 | ||
92437cbb | 3614 | ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies), |
7b16f560 MB |
3615 | wm8962->supplies); |
3616 | if (ret != 0) { | |
3617 | dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); | |
be086aa8 | 3618 | goto err; |
7b16f560 MB |
3619 | } |
3620 | ||
3621 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies), | |
3622 | wm8962->supplies); | |
3623 | if (ret != 0) { | |
3624 | dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); | |
92437cbb | 3625 | return ret; |
7b16f560 MB |
3626 | } |
3627 | ||
b439c6d0 | 3628 | wm8962->regmap = devm_regmap_init_i2c(i2c, &wm8962_regmap); |
7b16f560 MB |
3629 | if (IS_ERR(wm8962->regmap)) { |
3630 | ret = PTR_ERR(wm8962->regmap); | |
3631 | dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); | |
3632 | goto err_enable; | |
3633 | } | |
3634 | ||
3635 | /* | |
3636 | * We haven't marked the chip revision as volatile due to | |
3637 | * sharing a register with the right input volume; explicitly | |
3638 | * bypass the cache to read it. | |
3639 | */ | |
3640 | regcache_cache_bypass(wm8962->regmap, true); | |
3641 | ||
3642 | ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, ®); | |
3643 | if (ret < 0) { | |
3644 | dev_err(&i2c->dev, "Failed to read ID register\n"); | |
b439c6d0 | 3645 | goto err_enable; |
7b16f560 MB |
3646 | } |
3647 | if (reg != 0x6243) { | |
3648 | dev_err(&i2c->dev, | |
905b4195 | 3649 | "Device is not a WM8962, ID %x != 0x6243\n", reg); |
7b16f560 | 3650 | ret = -EINVAL; |
b439c6d0 | 3651 | goto err_enable; |
7b16f560 MB |
3652 | } |
3653 | ||
3654 | ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, ®); | |
3655 | if (ret < 0) { | |
3656 | dev_err(&i2c->dev, "Failed to read device revision: %d\n", | |
3657 | ret); | |
b439c6d0 | 3658 | goto err_enable; |
7b16f560 MB |
3659 | } |
3660 | ||
3661 | dev_info(&i2c->dev, "customer id %x revision %c\n", | |
3662 | (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT, | |
3663 | ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT) | |
3664 | + 'A'); | |
3665 | ||
3666 | regcache_cache_bypass(wm8962->regmap, false); | |
3667 | ||
3668 | ret = wm8962_reset(wm8962); | |
3669 | if (ret < 0) { | |
3670 | dev_err(&i2c->dev, "Failed to issue reset\n"); | |
b439c6d0 | 3671 | goto err_enable; |
7b16f560 MB |
3672 | } |
3673 | ||
e75a52c6 | 3674 | if (wm8962->pdata.in4_dc_measure) { |
182c51ce MB |
3675 | ret = regmap_register_patch(wm8962->regmap, |
3676 | wm8962_dc_measure, | |
3677 | ARRAY_SIZE(wm8962_dc_measure)); | |
3678 | if (ret != 0) | |
3679 | dev_err(&i2c->dev, | |
3680 | "Failed to configure for DC mesurement: %d\n", | |
3681 | ret); | |
3682 | } | |
3683 | ||
ca50410b MB |
3684 | if (wm8962->irq) { |
3685 | if (pdata->irq_active_low) { | |
3686 | trigger = IRQF_TRIGGER_LOW; | |
3687 | irq_pol = WM8962_IRQ_POL; | |
3688 | } else { | |
3689 | trigger = IRQF_TRIGGER_HIGH; | |
3690 | irq_pol = 0; | |
3691 | } | |
3692 | ||
3693 | regmap_update_bits(wm8962->regmap, WM8962_INTERRUPT_CONTROL, | |
3694 | WM8962_IRQ_POL, irq_pol); | |
3695 | ||
3696 | ret = devm_request_threaded_irq(&i2c->dev, wm8962->irq, NULL, | |
3697 | wm8962_irq, | |
3698 | trigger | IRQF_ONESHOT, | |
3699 | "wm8962", &i2c->dev); | |
3700 | if (ret != 0) { | |
3701 | dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n", | |
3702 | wm8962->irq, ret); | |
3703 | wm8962->irq = 0; | |
3704 | /* Non-fatal */ | |
3705 | } else { | |
3706 | /* Enable some IRQs by default */ | |
3707 | regmap_update_bits(wm8962->regmap, | |
3708 | WM8962_INTERRUPT_STATUS_2_MASK, | |
3709 | WM8962_FLL_LOCK_EINT | | |
3710 | WM8962_TEMP_SHUT_EINT | | |
3711 | WM8962_FIFOS_ERR_EINT, 0); | |
3712 | } | |
3713 | } | |
3714 | ||
d23031a4 MB |
3715 | pm_runtime_enable(&i2c->dev); |
3716 | pm_request_idle(&i2c->dev); | |
7b16f560 | 3717 | |
54d8d0ae MB |
3718 | ret = snd_soc_register_codec(&i2c->dev, |
3719 | &soc_codec_dev_wm8962, &wm8962_dai, 1); | |
3720 | if (ret < 0) | |
b439c6d0 | 3721 | goto err_enable; |
7b16f560 MB |
3722 | |
3723 | /* The drivers should power up as needed */ | |
3724 | regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); | |
3725 | ||
3726 | return 0; | |
9a76f1ff | 3727 | |
7b16f560 MB |
3728 | err_enable: |
3729 | regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); | |
be086aa8 | 3730 | err: |
54d8d0ae | 3731 | return ret; |
9a76f1ff MB |
3732 | } |
3733 | ||
7a79e94e | 3734 | static int wm8962_i2c_remove(struct i2c_client *client) |
9a76f1ff | 3735 | { |
54d8d0ae | 3736 | snd_soc_unregister_codec(&client->dev); |
9a76f1ff MB |
3737 | return 0; |
3738 | } | |
3739 | ||
d23031a4 MB |
3740 | #ifdef CONFIG_PM_RUNTIME |
3741 | static int wm8962_runtime_resume(struct device *dev) | |
3742 | { | |
3743 | struct wm8962_priv *wm8962 = dev_get_drvdata(dev); | |
3744 | int ret; | |
3745 | ||
3746 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies), | |
3747 | wm8962->supplies); | |
3748 | if (ret != 0) { | |
3749 | dev_err(dev, | |
3750 | "Failed to enable supplies: %d\n", ret); | |
3751 | return ret; | |
3752 | } | |
3753 | ||
3754 | regcache_cache_only(wm8962->regmap, false); | |
e4dd7678 MB |
3755 | |
3756 | wm8962_reset(wm8962); | |
3757 | ||
9c24b167 MB |
3758 | /* SYSCLK defaults to on; make sure it is off so we can safely |
3759 | * write to registers if the device is declocked. | |
3760 | */ | |
3761 | regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2, | |
3762 | WM8962_SYSCLK_ENA, 0); | |
3763 | ||
3764 | /* Ensure we have soft control over all registers */ | |
3765 | regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2, | |
3766 | WM8962_CLKREG_OVD, WM8962_CLKREG_OVD); | |
3767 | ||
3768 | /* Ensure that the oscillator and PLLs are disabled */ | |
3769 | regmap_update_bits(wm8962->regmap, WM8962_PLL2, | |
3770 | WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA, | |
3771 | 0); | |
3772 | ||
d23031a4 MB |
3773 | regcache_sync(wm8962->regmap); |
3774 | ||
f5055f93 NC |
3775 | regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP, |
3776 | WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA, | |
3777 | WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA); | |
3778 | ||
3779 | /* Bias enable at 2*5k (fast start-up) */ | |
3780 | regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1, | |
3781 | WM8962_BIAS_ENA | WM8962_VMID_SEL_MASK, | |
3782 | WM8962_BIAS_ENA | 0x180); | |
3783 | ||
3784 | msleep(5); | |
3785 | ||
d23031a4 MB |
3786 | return 0; |
3787 | } | |
3788 | ||
3789 | static int wm8962_runtime_suspend(struct device *dev) | |
3790 | { | |
3791 | struct wm8962_priv *wm8962 = dev_get_drvdata(dev); | |
3792 | ||
d23031a4 MB |
3793 | regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1, |
3794 | WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0); | |
3795 | ||
3796 | regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP, | |
3797 | WM8962_STARTUP_BIAS_ENA | | |
3798 | WM8962_VMID_BUF_ENA, 0); | |
3799 | ||
3800 | regcache_cache_only(wm8962->regmap, true); | |
3801 | ||
3802 | regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), | |
3803 | wm8962->supplies); | |
3804 | ||
3805 | return 0; | |
3806 | } | |
3807 | #endif | |
3808 | ||
3809 | static struct dev_pm_ops wm8962_pm = { | |
3810 | SET_RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL) | |
3811 | }; | |
3812 | ||
9a76f1ff MB |
3813 | static const struct i2c_device_id wm8962_i2c_id[] = { |
3814 | { "wm8962", 0 }, | |
3815 | { } | |
3816 | }; | |
3817 | MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id); | |
3818 | ||
5ce56832 FE |
3819 | static const struct of_device_id wm8962_of_match[] = { |
3820 | { .compatible = "wlf,wm8962", }, | |
3821 | { } | |
3822 | }; | |
3823 | MODULE_DEVICE_TABLE(of, wm8962_of_match); | |
3824 | ||
9a76f1ff MB |
3825 | static struct i2c_driver wm8962_i2c_driver = { |
3826 | .driver = { | |
ea738bad | 3827 | .name = "wm8962", |
9a76f1ff | 3828 | .owner = THIS_MODULE, |
5ce56832 | 3829 | .of_match_table = wm8962_of_match, |
d23031a4 | 3830 | .pm = &wm8962_pm, |
9a76f1ff MB |
3831 | }, |
3832 | .probe = wm8962_i2c_probe, | |
7a79e94e | 3833 | .remove = wm8962_i2c_remove, |
9a76f1ff MB |
3834 | .id_table = wm8962_i2c_id, |
3835 | }; | |
9a76f1ff | 3836 | |
9d50a764 | 3837 | module_i2c_driver(wm8962_i2c_driver); |
9a76f1ff MB |
3838 | |
3839 | MODULE_DESCRIPTION("ASoC WM8962 driver"); | |
3840 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
3841 | MODULE_LICENSE("GPL"); |