Commit | Line | Data |
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1fd4f2a5 ED |
1 | /* |
2 | * Copyright (C) 2001 MandrakeSoft S.A. | |
221d059d | 3 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
1fd4f2a5 ED |
4 | * |
5 | * MandrakeSoft S.A. | |
6 | * 43, rue d'Aboukir | |
7 | * 75002 Paris - France | |
8 | * http://www.linux-mandrake.com/ | |
9 | * http://www.mandrakesoft.com/ | |
10 | * | |
11 | * This library is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU Lesser General Public | |
13 | * License as published by the Free Software Foundation; either | |
14 | * version 2 of the License, or (at your option) any later version. | |
15 | * | |
16 | * This library is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * Lesser General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU Lesser General Public | |
22 | * License along with this library; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
24 | * | |
25 | * Yunhong Jiang <yunhong.jiang@intel.com> | |
26 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
27 | * Based on Xen 3.1 code. | |
28 | */ | |
29 | ||
edf88417 | 30 | #include <linux/kvm_host.h> |
1fd4f2a5 ED |
31 | #include <linux/kvm.h> |
32 | #include <linux/mm.h> | |
33 | #include <linux/highmem.h> | |
34 | #include <linux/smp.h> | |
35 | #include <linux/hrtimer.h> | |
36 | #include <linux/io.h> | |
5a0e3ad6 | 37 | #include <linux/slab.h> |
c7c9c56c | 38 | #include <linux/export.h> |
1fd4f2a5 | 39 | #include <asm/processor.h> |
1fd4f2a5 ED |
40 | #include <asm/page.h> |
41 | #include <asm/current.h> | |
1000ff8d | 42 | #include <trace/events/kvm.h> |
82470196 ZX |
43 | |
44 | #include "ioapic.h" | |
45 | #include "lapic.h" | |
f5244726 | 46 | #include "irq.h" |
82470196 | 47 | |
e25e3ed5 LV |
48 | #if 0 |
49 | #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) | |
50 | #else | |
1fd4f2a5 | 51 | #define ioapic_debug(fmt, arg...) |
e25e3ed5 | 52 | #endif |
0b10a1c8 | 53 | static int ioapic_service(struct kvm_ioapic *vioapic, int irq, |
aa2fbe6d | 54 | bool line_status); |
1fd4f2a5 ED |
55 | |
56 | static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic, | |
57 | unsigned long addr, | |
58 | unsigned long length) | |
59 | { | |
60 | unsigned long result = 0; | |
61 | ||
62 | switch (ioapic->ioregsel) { | |
63 | case IOAPIC_REG_VERSION: | |
64 | result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16) | |
65 | | (IOAPIC_VERSION_ID & 0xff)); | |
66 | break; | |
67 | ||
68 | case IOAPIC_REG_APIC_ID: | |
69 | case IOAPIC_REG_ARB_ID: | |
70 | result = ((ioapic->id & 0xf) << 24); | |
71 | break; | |
72 | ||
73 | default: | |
74 | { | |
75 | u32 redir_index = (ioapic->ioregsel - 0x10) >> 1; | |
76 | u64 redir_content; | |
77 | ||
a2c118bf AH |
78 | if (redir_index < IOAPIC_NUM_PINS) |
79 | redir_content = | |
80 | ioapic->redirtbl[redir_index].bits; | |
81 | else | |
82 | redir_content = ~0ULL; | |
1fd4f2a5 | 83 | |
1fd4f2a5 ED |
84 | result = (ioapic->ioregsel & 0x1) ? |
85 | (redir_content >> 32) & 0xffffffff : | |
86 | redir_content & 0xffffffff; | |
87 | break; | |
88 | } | |
89 | } | |
90 | ||
91 | return result; | |
92 | } | |
93 | ||
10606919 YZ |
94 | static void rtc_irq_eoi_tracking_reset(struct kvm_ioapic *ioapic) |
95 | { | |
96 | ioapic->rtc_status.pending_eoi = 0; | |
97 | bitmap_zero(ioapic->rtc_status.dest_map, KVM_MAX_VCPUS); | |
98 | } | |
99 | ||
4009b249 PB |
100 | static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic); |
101 | ||
102 | static void rtc_status_pending_eoi_check_valid(struct kvm_ioapic *ioapic) | |
103 | { | |
104 | if (WARN_ON(ioapic->rtc_status.pending_eoi < 0)) | |
105 | kvm_rtc_eoi_tracking_restore_all(ioapic); | |
106 | } | |
107 | ||
10606919 YZ |
108 | static void __rtc_irq_eoi_tracking_restore_one(struct kvm_vcpu *vcpu) |
109 | { | |
110 | bool new_val, old_val; | |
111 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; | |
112 | union kvm_ioapic_redirect_entry *e; | |
113 | ||
114 | e = &ioapic->redirtbl[RTC_GSI]; | |
115 | if (!kvm_apic_match_dest(vcpu, NULL, 0, e->fields.dest_id, | |
116 | e->fields.dest_mode)) | |
117 | return; | |
118 | ||
119 | new_val = kvm_apic_pending_eoi(vcpu, e->fields.vector); | |
120 | old_val = test_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map); | |
121 | ||
122 | if (new_val == old_val) | |
123 | return; | |
124 | ||
125 | if (new_val) { | |
126 | __set_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map); | |
127 | ioapic->rtc_status.pending_eoi++; | |
128 | } else { | |
129 | __clear_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map); | |
130 | ioapic->rtc_status.pending_eoi--; | |
4009b249 | 131 | rtc_status_pending_eoi_check_valid(ioapic); |
10606919 | 132 | } |
10606919 YZ |
133 | } |
134 | ||
135 | void kvm_rtc_eoi_tracking_restore_one(struct kvm_vcpu *vcpu) | |
136 | { | |
137 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; | |
138 | ||
139 | spin_lock(&ioapic->lock); | |
140 | __rtc_irq_eoi_tracking_restore_one(vcpu); | |
141 | spin_unlock(&ioapic->lock); | |
142 | } | |
143 | ||
144 | static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic) | |
145 | { | |
146 | struct kvm_vcpu *vcpu; | |
147 | int i; | |
148 | ||
149 | if (RTC_GSI >= IOAPIC_NUM_PINS) | |
150 | return; | |
151 | ||
152 | rtc_irq_eoi_tracking_reset(ioapic); | |
153 | kvm_for_each_vcpu(i, vcpu, ioapic->kvm) | |
154 | __rtc_irq_eoi_tracking_restore_one(vcpu); | |
155 | } | |
156 | ||
2c2bf011 YZ |
157 | static void rtc_irq_eoi(struct kvm_ioapic *ioapic, struct kvm_vcpu *vcpu) |
158 | { | |
4009b249 | 159 | if (test_and_clear_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map)) { |
2c2bf011 | 160 | --ioapic->rtc_status.pending_eoi; |
4009b249 PB |
161 | rtc_status_pending_eoi_check_valid(ioapic); |
162 | } | |
2c2bf011 YZ |
163 | } |
164 | ||
165 | static bool rtc_irq_check_coalesced(struct kvm_ioapic *ioapic) | |
166 | { | |
167 | if (ioapic->rtc_status.pending_eoi > 0) | |
168 | return true; /* coalesced */ | |
169 | ||
170 | return false; | |
171 | } | |
172 | ||
44847dea PB |
173 | static int ioapic_set_irq(struct kvm_ioapic *ioapic, unsigned int irq, |
174 | int irq_level, bool line_status) | |
175 | { | |
176 | union kvm_ioapic_redirect_entry entry; | |
177 | u32 mask = 1 << irq; | |
178 | u32 old_irr; | |
179 | int edge, ret; | |
180 | ||
181 | entry = ioapic->redirtbl[irq]; | |
182 | edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG); | |
183 | ||
184 | if (!irq_level) { | |
185 | ioapic->irr &= ~mask; | |
186 | ret = 1; | |
187 | goto out; | |
188 | } | |
189 | ||
190 | /* | |
191 | * Return 0 for coalesced interrupts; for edge-triggered interrupts, | |
192 | * this only happens if a previous edge has not been delivered due | |
193 | * do masking. For level interrupts, the remote_irr field tells | |
194 | * us if the interrupt is waiting for an EOI. | |
195 | * | |
196 | * RTC is special: it is edge-triggered, but userspace likes to know | |
197 | * if it has been already ack-ed via EOI because coalesced RTC | |
198 | * interrupts lead to time drift in Windows guests. So we track | |
199 | * EOI manually for the RTC interrupt. | |
200 | */ | |
201 | if (irq == RTC_GSI && line_status && | |
202 | rtc_irq_check_coalesced(ioapic)) { | |
203 | ret = 0; | |
204 | goto out; | |
205 | } | |
206 | ||
207 | old_irr = ioapic->irr; | |
208 | ioapic->irr |= mask; | |
209 | if ((edge && old_irr == ioapic->irr) || | |
210 | (!edge && entry.fields.remote_irr)) { | |
211 | ret = 0; | |
212 | goto out; | |
213 | } | |
214 | ||
215 | ret = ioapic_service(ioapic, irq, line_status); | |
216 | ||
217 | out: | |
218 | trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0); | |
219 | return ret; | |
220 | } | |
221 | ||
673f7b42 PB |
222 | static void kvm_ioapic_inject_all(struct kvm_ioapic *ioapic, unsigned long irr) |
223 | { | |
224 | u32 idx; | |
225 | ||
226 | rtc_irq_eoi_tracking_reset(ioapic); | |
227 | for_each_set_bit(idx, &irr, IOAPIC_NUM_PINS) | |
228 | ioapic_set_irq(ioapic, idx, 1, true); | |
229 | ||
230 | kvm_rtc_eoi_tracking_restore_all(ioapic); | |
231 | } | |
232 | ||
233 | ||
46a929bc AK |
234 | static void update_handled_vectors(struct kvm_ioapic *ioapic) |
235 | { | |
236 | DECLARE_BITMAP(handled_vectors, 256); | |
237 | int i; | |
238 | ||
239 | memset(handled_vectors, 0, sizeof(handled_vectors)); | |
240 | for (i = 0; i < IOAPIC_NUM_PINS; ++i) | |
241 | __set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors); | |
242 | memcpy(ioapic->handled_vectors, handled_vectors, | |
243 | sizeof(handled_vectors)); | |
244 | smp_wmb(); | |
245 | } | |
246 | ||
cf9e65b7 YZ |
247 | void kvm_ioapic_scan_entry(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap, |
248 | u32 *tmr) | |
c7c9c56c YZ |
249 | { |
250 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; | |
251 | union kvm_ioapic_redirect_entry *e; | |
c7c9c56c YZ |
252 | int index; |
253 | ||
254 | spin_lock(&ioapic->lock); | |
c7c9c56c YZ |
255 | for (index = 0; index < IOAPIC_NUM_PINS; index++) { |
256 | e = &ioapic->redirtbl[index]; | |
257 | if (!e->fields.mask && | |
258 | (e->fields.trig_mode == IOAPIC_LEVEL_TRIG || | |
259 | kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC, | |
f3bff631 | 260 | index) || index == RTC_GSI)) { |
44944d4d | 261 | if (kvm_apic_match_dest(vcpu, NULL, 0, |
cf9e65b7 YZ |
262 | e->fields.dest_id, e->fields.dest_mode)) { |
263 | __set_bit(e->fields.vector, | |
264 | (unsigned long *)eoi_exit_bitmap); | |
265 | if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG) | |
266 | __set_bit(e->fields.vector, | |
267 | (unsigned long *)tmr); | |
268 | } | |
c7c9c56c YZ |
269 | } |
270 | } | |
271 | spin_unlock(&ioapic->lock); | |
272 | } | |
c7c9c56c | 273 | |
3d81bc7e YZ |
274 | #ifdef CONFIG_X86 |
275 | void kvm_vcpu_request_scan_ioapic(struct kvm *kvm) | |
c7c9c56c YZ |
276 | { |
277 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; | |
278 | ||
3d81bc7e | 279 | if (!ioapic) |
c7c9c56c | 280 | return; |
3d81bc7e | 281 | kvm_make_scan_ioapic_request(kvm); |
c7c9c56c | 282 | } |
3d81bc7e YZ |
283 | #else |
284 | void kvm_vcpu_request_scan_ioapic(struct kvm *kvm) | |
285 | { | |
286 | return; | |
287 | } | |
288 | #endif | |
c7c9c56c | 289 | |
1fd4f2a5 ED |
290 | static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val) |
291 | { | |
292 | unsigned index; | |
75858a84 | 293 | bool mask_before, mask_after; |
70f93dae | 294 | union kvm_ioapic_redirect_entry *e; |
1fd4f2a5 ED |
295 | |
296 | switch (ioapic->ioregsel) { | |
297 | case IOAPIC_REG_VERSION: | |
298 | /* Writes are ignored. */ | |
299 | break; | |
300 | ||
301 | case IOAPIC_REG_APIC_ID: | |
302 | ioapic->id = (val >> 24) & 0xf; | |
303 | break; | |
304 | ||
305 | case IOAPIC_REG_ARB_ID: | |
306 | break; | |
307 | ||
308 | default: | |
309 | index = (ioapic->ioregsel - 0x10) >> 1; | |
310 | ||
e25e3ed5 | 311 | ioapic_debug("change redir index %x val %x\n", index, val); |
1fd4f2a5 ED |
312 | if (index >= IOAPIC_NUM_PINS) |
313 | return; | |
70f93dae GN |
314 | e = &ioapic->redirtbl[index]; |
315 | mask_before = e->fields.mask; | |
1fd4f2a5 | 316 | if (ioapic->ioregsel & 1) { |
70f93dae GN |
317 | e->bits &= 0xffffffff; |
318 | e->bits |= (u64) val << 32; | |
1fd4f2a5 | 319 | } else { |
70f93dae GN |
320 | e->bits &= ~0xffffffffULL; |
321 | e->bits |= (u32) val; | |
322 | e->fields.remote_irr = 0; | |
1fd4f2a5 | 323 | } |
46a929bc | 324 | update_handled_vectors(ioapic); |
70f93dae | 325 | mask_after = e->fields.mask; |
75858a84 | 326 | if (mask_before != mask_after) |
4a994358 | 327 | kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after); |
70f93dae | 328 | if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG |
b4a2f5e7 | 329 | && ioapic->irr & (1 << index)) |
aa2fbe6d | 330 | ioapic_service(ioapic, index, false); |
3d81bc7e | 331 | kvm_vcpu_request_scan_ioapic(ioapic->kvm); |
1fd4f2a5 ED |
332 | break; |
333 | } | |
334 | } | |
335 | ||
0b10a1c8 | 336 | static int ioapic_service(struct kvm_ioapic *ioapic, int irq, bool line_status) |
a53c17d2 | 337 | { |
58c2dde1 GN |
338 | union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq]; |
339 | struct kvm_lapic_irq irqe; | |
2c2bf011 | 340 | int ret; |
a53c17d2 | 341 | |
0b10a1c8 PB |
342 | if (entry->fields.mask) |
343 | return -1; | |
344 | ||
a53c17d2 GN |
345 | ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x " |
346 | "vector=%x trig_mode=%x\n", | |
a38f84ca | 347 | entry->fields.dest_id, entry->fields.dest_mode, |
58c2dde1 GN |
348 | entry->fields.delivery_mode, entry->fields.vector, |
349 | entry->fields.trig_mode); | |
350 | ||
351 | irqe.dest_id = entry->fields.dest_id; | |
352 | irqe.vector = entry->fields.vector; | |
353 | irqe.dest_mode = entry->fields.dest_mode; | |
354 | irqe.trig_mode = entry->fields.trig_mode; | |
355 | irqe.delivery_mode = entry->fields.delivery_mode << 8; | |
356 | irqe.level = 1; | |
357 | irqe.shorthand = 0; | |
a53c17d2 | 358 | |
0bc830b0 PB |
359 | if (irqe.trig_mode == IOAPIC_EDGE_TRIG) |
360 | ioapic->irr &= ~(1 << irq); | |
361 | ||
2c2bf011 | 362 | if (irq == RTC_GSI && line_status) { |
4009b249 PB |
363 | /* |
364 | * pending_eoi cannot ever become negative (see | |
365 | * rtc_status_pending_eoi_check_valid) and the caller | |
366 | * ensures that it is only called if it is >= zero, namely | |
367 | * if rtc_irq_check_coalesced returns false). | |
368 | */ | |
2c2bf011 YZ |
369 | BUG_ON(ioapic->rtc_status.pending_eoi != 0); |
370 | ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, | |
371 | ioapic->rtc_status.dest_map); | |
5678de3f | 372 | ioapic->rtc_status.pending_eoi = (ret < 0 ? 0 : ret); |
2c2bf011 YZ |
373 | } else |
374 | ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, NULL); | |
375 | ||
0b10a1c8 PB |
376 | if (ret && irqe.trig_mode == IOAPIC_LEVEL_TRIG) |
377 | entry->fields.remote_irr = 1; | |
378 | ||
2c2bf011 | 379 | return ret; |
a53c17d2 GN |
380 | } |
381 | ||
1a577b72 | 382 | int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id, |
aa2fbe6d | 383 | int level, bool line_status) |
1fd4f2a5 | 384 | { |
28a6fdab MT |
385 | int ret, irq_level; |
386 | ||
387 | BUG_ON(irq < 0 || irq >= IOAPIC_NUM_PINS); | |
1fd4f2a5 | 388 | |
46a47b1e | 389 | spin_lock(&ioapic->lock); |
28a6fdab MT |
390 | irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq], |
391 | irq_source_id, level); | |
44847dea | 392 | ret = ioapic_set_irq(ioapic, irq, irq_level, line_status); |
2c2bf011 | 393 | |
46a47b1e | 394 | spin_unlock(&ioapic->lock); |
eba0226b | 395 | |
4925663a | 396 | return ret; |
1fd4f2a5 ED |
397 | } |
398 | ||
1a577b72 MT |
399 | void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id) |
400 | { | |
401 | int i; | |
402 | ||
403 | spin_lock(&ioapic->lock); | |
404 | for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++) | |
405 | __clear_bit(irq_source_id, &ioapic->irq_states[i]); | |
406 | spin_unlock(&ioapic->lock); | |
407 | } | |
408 | ||
1fcc7890 YZ |
409 | static void __kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, |
410 | struct kvm_ioapic *ioapic, int vector, int trigger_mode) | |
1fd4f2a5 | 411 | { |
eba0226b GN |
412 | int i; |
413 | ||
414 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
415 | union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i]; | |
1fd4f2a5 | 416 | |
eba0226b GN |
417 | if (ent->fields.vector != vector) |
418 | continue; | |
1fd4f2a5 | 419 | |
2c2bf011 YZ |
420 | if (i == RTC_GSI) |
421 | rtc_irq_eoi(ioapic, vcpu); | |
eba0226b GN |
422 | /* |
423 | * We are dropping lock while calling ack notifiers because ack | |
424 | * notifier callbacks for assigned devices call into IOAPIC | |
425 | * recursively. Since remote_irr is cleared only after call | |
426 | * to notifiers if the same vector will be delivered while lock | |
427 | * is dropped it will be put into irr and will be delivered | |
428 | * after ack notifier returns. | |
429 | */ | |
46a47b1e | 430 | spin_unlock(&ioapic->lock); |
eba0226b | 431 | kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i); |
46a47b1e | 432 | spin_lock(&ioapic->lock); |
eba0226b GN |
433 | |
434 | if (trigger_mode != IOAPIC_LEVEL_TRIG) | |
435 | continue; | |
f5244726 | 436 | |
f5244726 MT |
437 | ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG); |
438 | ent->fields.remote_irr = 0; | |
0b10a1c8 | 439 | if (ioapic->irr & (1 << i)) |
aa2fbe6d | 440 | ioapic_service(ioapic, i, false); |
f5244726 | 441 | } |
1fd4f2a5 ED |
442 | } |
443 | ||
a0c9a822 MT |
444 | bool kvm_ioapic_handles_vector(struct kvm *kvm, int vector) |
445 | { | |
446 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; | |
447 | smp_rmb(); | |
448 | return test_bit(vector, ioapic->handled_vectors); | |
449 | } | |
450 | ||
1fcc7890 | 451 | void kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, int vector, int trigger_mode) |
4fa6b9c5 | 452 | { |
1fcc7890 | 453 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; |
4fa6b9c5 | 454 | |
46a47b1e | 455 | spin_lock(&ioapic->lock); |
1fcc7890 | 456 | __kvm_ioapic_update_eoi(vcpu, ioapic, vector, trigger_mode); |
46a47b1e | 457 | spin_unlock(&ioapic->lock); |
4fa6b9c5 AK |
458 | } |
459 | ||
d76685c4 GH |
460 | static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev) |
461 | { | |
462 | return container_of(dev, struct kvm_ioapic, dev); | |
463 | } | |
464 | ||
bda9020e | 465 | static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr) |
1fd4f2a5 | 466 | { |
1fd4f2a5 ED |
467 | return ((addr >= ioapic->base_address && |
468 | (addr < ioapic->base_address + IOAPIC_MEM_LENGTH))); | |
469 | } | |
470 | ||
bda9020e MT |
471 | static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len, |
472 | void *val) | |
1fd4f2a5 | 473 | { |
d76685c4 | 474 | struct kvm_ioapic *ioapic = to_ioapic(this); |
1fd4f2a5 | 475 | u32 result; |
bda9020e MT |
476 | if (!ioapic_in_range(ioapic, addr)) |
477 | return -EOPNOTSUPP; | |
1fd4f2a5 | 478 | |
e25e3ed5 | 479 | ioapic_debug("addr %lx\n", (unsigned long)addr); |
1fd4f2a5 ED |
480 | ASSERT(!(addr & 0xf)); /* check alignment */ |
481 | ||
482 | addr &= 0xff; | |
46a47b1e | 483 | spin_lock(&ioapic->lock); |
1fd4f2a5 ED |
484 | switch (addr) { |
485 | case IOAPIC_REG_SELECT: | |
486 | result = ioapic->ioregsel; | |
487 | break; | |
488 | ||
489 | case IOAPIC_REG_WINDOW: | |
490 | result = ioapic_read_indirect(ioapic, addr, len); | |
491 | break; | |
492 | ||
493 | default: | |
494 | result = 0; | |
495 | break; | |
496 | } | |
46a47b1e | 497 | spin_unlock(&ioapic->lock); |
eba0226b | 498 | |
1fd4f2a5 ED |
499 | switch (len) { |
500 | case 8: | |
501 | *(u64 *) val = result; | |
502 | break; | |
503 | case 1: | |
504 | case 2: | |
505 | case 4: | |
506 | memcpy(val, (char *)&result, len); | |
507 | break; | |
508 | default: | |
509 | printk(KERN_WARNING "ioapic: wrong length %d\n", len); | |
510 | } | |
bda9020e | 511 | return 0; |
1fd4f2a5 ED |
512 | } |
513 | ||
bda9020e MT |
514 | static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len, |
515 | const void *val) | |
1fd4f2a5 | 516 | { |
d76685c4 | 517 | struct kvm_ioapic *ioapic = to_ioapic(this); |
1fd4f2a5 | 518 | u32 data; |
bda9020e MT |
519 | if (!ioapic_in_range(ioapic, addr)) |
520 | return -EOPNOTSUPP; | |
1fd4f2a5 | 521 | |
e25e3ed5 LV |
522 | ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n", |
523 | (void*)addr, len, val); | |
1fd4f2a5 | 524 | ASSERT(!(addr & 0xf)); /* check alignment */ |
60eead79 | 525 | |
d77fe635 JS |
526 | switch (len) { |
527 | case 8: | |
528 | case 4: | |
1fd4f2a5 | 529 | data = *(u32 *) val; |
d77fe635 JS |
530 | break; |
531 | case 2: | |
532 | data = *(u16 *) val; | |
533 | break; | |
534 | case 1: | |
535 | data = *(u8 *) val; | |
536 | break; | |
537 | default: | |
1fd4f2a5 | 538 | printk(KERN_WARNING "ioapic: Unsupported size %d\n", len); |
eba0226b | 539 | return 0; |
1fd4f2a5 ED |
540 | } |
541 | ||
542 | addr &= 0xff; | |
46a47b1e | 543 | spin_lock(&ioapic->lock); |
1fd4f2a5 ED |
544 | switch (addr) { |
545 | case IOAPIC_REG_SELECT: | |
d77fe635 | 546 | ioapic->ioregsel = data & 0xFF; /* 8-bit register */ |
1fd4f2a5 ED |
547 | break; |
548 | ||
549 | case IOAPIC_REG_WINDOW: | |
550 | ioapic_write_indirect(ioapic, data); | |
551 | break; | |
b1fd3d30 ZX |
552 | #ifdef CONFIG_IA64 |
553 | case IOAPIC_REG_EOI: | |
1fcc7890 | 554 | __kvm_ioapic_update_eoi(NULL, ioapic, data, IOAPIC_LEVEL_TRIG); |
b1fd3d30 ZX |
555 | break; |
556 | #endif | |
1fd4f2a5 ED |
557 | |
558 | default: | |
559 | break; | |
560 | } | |
46a47b1e | 561 | spin_unlock(&ioapic->lock); |
bda9020e | 562 | return 0; |
1fd4f2a5 ED |
563 | } |
564 | ||
7940876e | 565 | static void kvm_ioapic_reset(struct kvm_ioapic *ioapic) |
8c392696 ED |
566 | { |
567 | int i; | |
568 | ||
569 | for (i = 0; i < IOAPIC_NUM_PINS; i++) | |
570 | ioapic->redirtbl[i].fields.mask = 1; | |
571 | ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS; | |
572 | ioapic->ioregsel = 0; | |
573 | ioapic->irr = 0; | |
574 | ioapic->id = 0; | |
10606919 | 575 | rtc_irq_eoi_tracking_reset(ioapic); |
46a929bc | 576 | update_handled_vectors(ioapic); |
8c392696 ED |
577 | } |
578 | ||
d76685c4 GH |
579 | static const struct kvm_io_device_ops ioapic_mmio_ops = { |
580 | .read = ioapic_mmio_read, | |
581 | .write = ioapic_mmio_write, | |
d76685c4 GH |
582 | }; |
583 | ||
1fd4f2a5 ED |
584 | int kvm_ioapic_init(struct kvm *kvm) |
585 | { | |
586 | struct kvm_ioapic *ioapic; | |
090b7aff | 587 | int ret; |
1fd4f2a5 ED |
588 | |
589 | ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL); | |
590 | if (!ioapic) | |
591 | return -ENOMEM; | |
46a47b1e | 592 | spin_lock_init(&ioapic->lock); |
d7deeeb0 | 593 | kvm->arch.vioapic = ioapic; |
8c392696 | 594 | kvm_ioapic_reset(ioapic); |
d76685c4 | 595 | kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops); |
1fd4f2a5 | 596 | ioapic->kvm = kvm; |
79fac95e | 597 | mutex_lock(&kvm->slots_lock); |
743eeb0b SL |
598 | ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address, |
599 | IOAPIC_MEM_LENGTH, &ioapic->dev); | |
79fac95e | 600 | mutex_unlock(&kvm->slots_lock); |
1ae77bad WY |
601 | if (ret < 0) { |
602 | kvm->arch.vioapic = NULL; | |
090b7aff | 603 | kfree(ioapic); |
1ae77bad | 604 | } |
090b7aff GH |
605 | |
606 | return ret; | |
1fd4f2a5 | 607 | } |
75858a84 | 608 | |
72bb2fcd WY |
609 | void kvm_ioapic_destroy(struct kvm *kvm) |
610 | { | |
611 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; | |
612 | ||
613 | if (ioapic) { | |
614 | kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev); | |
615 | kvm->arch.vioapic = NULL; | |
616 | kfree(ioapic); | |
617 | } | |
618 | } | |
619 | ||
eba0226b GN |
620 | int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state) |
621 | { | |
622 | struct kvm_ioapic *ioapic = ioapic_irqchip(kvm); | |
623 | if (!ioapic) | |
624 | return -EINVAL; | |
625 | ||
46a47b1e | 626 | spin_lock(&ioapic->lock); |
eba0226b | 627 | memcpy(state, ioapic, sizeof(struct kvm_ioapic_state)); |
46a47b1e | 628 | spin_unlock(&ioapic->lock); |
eba0226b GN |
629 | return 0; |
630 | } | |
631 | ||
632 | int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state) | |
633 | { | |
634 | struct kvm_ioapic *ioapic = ioapic_irqchip(kvm); | |
635 | if (!ioapic) | |
636 | return -EINVAL; | |
637 | ||
46a47b1e | 638 | spin_lock(&ioapic->lock); |
eba0226b | 639 | memcpy(ioapic, state, sizeof(struct kvm_ioapic_state)); |
673f7b42 | 640 | ioapic->irr = 0; |
46a929bc | 641 | update_handled_vectors(ioapic); |
3d81bc7e | 642 | kvm_vcpu_request_scan_ioapic(kvm); |
673f7b42 | 643 | kvm_ioapic_inject_all(ioapic, state->irr); |
46a47b1e | 644 | spin_unlock(&ioapic->lock); |
eba0226b GN |
645 | return 0; |
646 | } |