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[deliverable/linux.git] / arch / arm / boot / dts / berlin2cd.dtsi
1 /*
2 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
3 *
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 *
6 * based on GPL'ed 2.6 kernel sources
7 * (c) Marvell International Ltd.
8 *
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
12 * whole.
13 *
14 * a) This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42 #include "skeleton.dtsi"
43 #include <dt-bindings/clock/berlin2.h>
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45
46 / {
47 model = "Marvell Armada 1500-mini (BG2CD) SoC";
48 compatible = "marvell,berlin2cd", "marvell,berlin";
49
50 aliases {
51 serial0 = &uart0;
52 serial1 = &uart1;
53 };
54
55 cpus {
56 #address-cells = <1>;
57 #size-cells = <0>;
58
59 cpu@0 {
60 compatible = "arm,cortex-a9";
61 device_type = "cpu";
62 next-level-cache = <&l2>;
63 reg = <0>;
64 };
65 };
66
67 refclk: oscillator {
68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <25000000>;
71 };
72
73 soc {
74 compatible = "simple-bus";
75 #address-cells = <1>;
76 #size-cells = <1>;
77 interrupt-parent = <&gic>;
78
79 ranges = <0 0xf7000000 0x1000000>;
80
81 pmu {
82 compatible = "arm,cortex-a9-pmu";
83 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
84 };
85
86 sdhci0: sdhci@ab0000 {
87 compatible = "mrvl,pxav3-mmc";
88 reg = <0xab0000 0x200>;
89 clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
90 clock-names = "io", "core";
91 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
92 status = "disabled";
93 };
94
95 l2: l2-cache-controller@ac0000 {
96 compatible = "arm,pl310-cache";
97 reg = <0xac0000 0x1000>;
98 cache-unified;
99 cache-level = <2>;
100 };
101
102 gic: interrupt-controller@ad1000 {
103 compatible = "arm,cortex-a9-gic";
104 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
105 interrupt-controller;
106 #interrupt-cells = <3>;
107 };
108
109 local-timer@ad0600 {
110 compatible = "arm,cortex-a9-twd-timer";
111 reg = <0xad0600 0x20>;
112 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
113 clocks = <&chip_clk CLKID_TWD>;
114 };
115
116 usb_phy0: usb-phy@b74000 {
117 compatible = "marvell,berlin2cd-usb-phy";
118 reg = <0xb74000 0x128>;
119 #phy-cells = <0>;
120 resets = <&chip_rst 0x178 23>;
121 status = "disabled";
122 };
123
124 usb_phy1: usb-phy@b78000 {
125 compatible = "marvell,berlin2cd-usb-phy";
126 reg = <0xb78000 0x128>;
127 #phy-cells = <0>;
128 resets = <&chip_rst 0x178 24>;
129 status = "disabled";
130 };
131
132 eth1: ethernet@b90000 {
133 compatible = "marvell,pxa168-eth";
134 reg = <0xb90000 0x10000>;
135 clocks = <&chip_clk CLKID_GETH1>;
136 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
137 /* set by bootloader */
138 local-mac-address = [00 00 00 00 00 00];
139 #address-cells = <1>;
140 #size-cells = <0>;
141 phy-connection-type = "mii";
142 phy-handle = <&ethphy1>;
143 status = "disabled";
144
145 ethphy1: ethernet-phy@0 {
146 reg = <0>;
147 };
148 };
149
150 eth0: ethernet@e50000 {
151 compatible = "marvell,pxa168-eth";
152 reg = <0xe50000 0x10000>;
153 clocks = <&chip_clk CLKID_GETH0>;
154 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
155 /* set by bootloader */
156 local-mac-address = [00 00 00 00 00 00];
157 #address-cells = <1>;
158 #size-cells = <0>;
159 phy-connection-type = "mii";
160 phy-handle = <&ethphy0>;
161 status = "disabled";
162
163 ethphy0: ethernet-phy@0 {
164 reg = <0>;
165 };
166 };
167
168 apb@e80000 {
169 compatible = "simple-bus";
170 #address-cells = <1>;
171 #size-cells = <1>;
172
173 ranges = <0 0xe80000 0x10000>;
174 interrupt-parent = <&aic>;
175
176 gpio0: gpio@0400 {
177 compatible = "snps,dw-apb-gpio";
178 reg = <0x0400 0x400>;
179 #address-cells = <1>;
180 #size-cells = <0>;
181
182 porta: gpio-port@0 {
183 compatible = "snps,dw-apb-gpio-port";
184 gpio-controller;
185 #gpio-cells = <2>;
186 snps,nr-gpios = <8>;
187 reg = <0>;
188 interrupt-controller;
189 #interrupt-cells = <2>;
190 interrupts = <0>;
191 };
192 };
193
194 gpio1: gpio@0800 {
195 compatible = "snps,dw-apb-gpio";
196 reg = <0x0800 0x400>;
197 #address-cells = <1>;
198 #size-cells = <0>;
199
200 portb: gpio-port@1 {
201 compatible = "snps,dw-apb-gpio-port";
202 gpio-controller;
203 #gpio-cells = <2>;
204 snps,nr-gpios = <8>;
205 reg = <0>;
206 interrupt-controller;
207 #interrupt-cells = <2>;
208 interrupts = <1>;
209 };
210 };
211
212 gpio2: gpio@0c00 {
213 compatible = "snps,dw-apb-gpio";
214 reg = <0x0c00 0x400>;
215 #address-cells = <1>;
216 #size-cells = <0>;
217
218 portc: gpio-port@2 {
219 compatible = "snps,dw-apb-gpio-port";
220 gpio-controller;
221 #gpio-cells = <2>;
222 snps,nr-gpios = <8>;
223 reg = <0>;
224 interrupt-controller;
225 #interrupt-cells = <2>;
226 interrupts = <2>;
227 };
228 };
229
230 gpio3: gpio@1000 {
231 compatible = "snps,dw-apb-gpio";
232 reg = <0x1000 0x400>;
233 #address-cells = <1>;
234 #size-cells = <0>;
235
236 portd: gpio-port@3 {
237 compatible = "snps,dw-apb-gpio-port";
238 gpio-controller;
239 #gpio-cells = <2>;
240 snps,nr-gpios = <8>;
241 reg = <0>;
242 interrupt-controller;
243 #interrupt-cells = <2>;
244 interrupts = <3>;
245 };
246 };
247
248 timer0: timer@2c00 {
249 compatible = "snps,dw-apb-timer";
250 reg = <0x2c00 0x14>;
251 interrupts = <8>;
252 clocks = <&chip_clk CLKID_CFG>;
253 clock-names = "timer";
254 status = "okay";
255 };
256
257 timer1: timer@2c14 {
258 compatible = "snps,dw-apb-timer";
259 reg = <0x2c14 0x14>;
260 interrupts = <9>;
261 clocks = <&chip_clk CLKID_CFG>;
262 clock-names = "timer";
263 status = "okay";
264 };
265
266 timer2: timer@2c28 {
267 compatible = "snps,dw-apb-timer";
268 reg = <0x2c28 0x14>;
269 interrupts = <10>;
270 clocks = <&chip_clk CLKID_CFG>;
271 clock-names = "timer";
272 status = "disabled";
273 };
274
275 timer3: timer@2c3c {
276 compatible = "snps,dw-apb-timer";
277 reg = <0x2c3c 0x14>;
278 interrupts = <11>;
279 clocks = <&chip_clk CLKID_CFG>;
280 clock-names = "timer";
281 status = "disabled";
282 };
283
284 timer4: timer@2c50 {
285 compatible = "snps,dw-apb-timer";
286 reg = <0x2c50 0x14>;
287 interrupts = <12>;
288 clocks = <&chip_clk CLKID_CFG>;
289 clock-names = "timer";
290 status = "disabled";
291 };
292
293 timer5: timer@2c64 {
294 compatible = "snps,dw-apb-timer";
295 reg = <0x2c64 0x14>;
296 interrupts = <13>;
297 clocks = <&chip_clk CLKID_CFG>;
298 clock-names = "timer";
299 status = "disabled";
300 };
301
302 timer6: timer@2c78 {
303 compatible = "snps,dw-apb-timer";
304 reg = <0x2c78 0x14>;
305 interrupts = <14>;
306 clocks = <&chip_clk CLKID_CFG>;
307 clock-names = "timer";
308 status = "disabled";
309 };
310
311 timer7: timer@2c8c {
312 compatible = "snps,dw-apb-timer";
313 reg = <0x2c8c 0x14>;
314 interrupts = <15>;
315 clocks = <&chip_clk CLKID_CFG>;
316 clock-names = "timer";
317 status = "disabled";
318 };
319
320 aic: interrupt-controller@3000 {
321 compatible = "snps,dw-apb-ictl";
322 reg = <0x3000 0xc00>;
323 interrupt-controller;
324 #interrupt-cells = <1>;
325 interrupt-parent = <&gic>;
326 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
327 };
328 };
329
330 chip: chip-control@ea0000 {
331 compatible = "simple-mfd", "syscon";
332 reg = <0xea0000 0x400>;
333
334 chip_clk: clock {
335 compatible = "marvell,berlin2-clk";
336 #clock-cells = <1>;
337 clocks = <&refclk>;
338 clock-names = "refclk";
339 };
340
341 soc_pinctrl: pin-controller {
342 compatible = "marvell,berlin2cd-soc-pinctrl";
343
344 uart0_pmux: uart0-pmux {
345 groups = "G6";
346 function = "uart0";
347 };
348 };
349
350 chip_rst: reset {
351 compatible = "marvell,berlin2-reset";
352 #reset-cells = <2>;
353 };
354 };
355
356 usb0: usb@ed0000 {
357 compatible = "chipidea,usb2";
358 reg = <0xed0000 0x200>;
359 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&chip_clk CLKID_USB0>;
361 phys = <&usb_phy0>;
362 phy-names = "usb-phy";
363 status = "disabled";
364 };
365
366 usb1: usb@ee0000 {
367 compatible = "chipidea,usb2";
368 reg = <0xee0000 0x200>;
369 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&chip_clk CLKID_USB1>;
371 phys = <&usb_phy1>;
372 phy-names = "usb-phy";
373 status = "disabled";
374 };
375
376 apb@fc0000 {
377 compatible = "simple-bus";
378 #address-cells = <1>;
379 #size-cells = <1>;
380
381 ranges = <0 0xfc0000 0x10000>;
382 interrupt-parent = <&sic>;
383
384 sm_gpio1: gpio@5000 {
385 compatible = "snps,dw-apb-gpio";
386 reg = <0x5000 0x400>;
387 #address-cells = <1>;
388 #size-cells = <0>;
389
390 portf: gpio-port@5 {
391 compatible = "snps,dw-apb-gpio-port";
392 gpio-controller;
393 #gpio-cells = <2>;
394 snps,nr-gpios = <8>;
395 reg = <0>;
396 };
397 };
398
399 sm_gpio0: gpio@c000 {
400 compatible = "snps,dw-apb-gpio";
401 reg = <0xc000 0x400>;
402 #address-cells = <1>;
403 #size-cells = <0>;
404
405 porte: gpio-port@4 {
406 compatible = "snps,dw-apb-gpio-port";
407 gpio-controller;
408 #gpio-cells = <2>;
409 snps,nr-gpios = <8>;
410 reg = <0>;
411 };
412 };
413
414 uart0: serial@9000 {
415 compatible = "snps,dw-apb-uart";
416 reg = <0x9000 0x100>;
417 reg-shift = <2>;
418 reg-io-width = <1>;
419 interrupts = <8>;
420 clocks = <&refclk>;
421 pinctrl-0 = <&uart0_pmux>;
422 pinctrl-names = "default";
423 status = "disabled";
424 };
425
426 uart1: serial@a000 {
427 compatible = "snps,dw-apb-uart";
428 reg = <0xa000 0x100>;
429 reg-shift = <2>;
430 reg-io-width = <1>;
431 interrupts = <9>;
432 clocks = <&refclk>;
433 status = "disabled";
434 };
435
436 sysctrl: system-controller@d000 {
437 compatible = "simple-mfd", "syscon";
438 reg = <0xd000 0x100>;
439
440 sys_pinctrl: pin-controller {
441 compatible = "marvell,berlin2cd-system-pinctrl";
442 };
443 };
444
445 sic: interrupt-controller@e000 {
446 compatible = "snps,dw-apb-ictl";
447 reg = <0xe000 0x400>;
448 interrupt-controller;
449 #interrupt-cells = <1>;
450 interrupt-parent = <&gic>;
451 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
452 };
453 };
454 };
455 };
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