arch/arm/mach-exynos/clock.c

   1 /* linux/arch/arm/mach-exynos4/clock.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * EXYNOS4 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/err.h>
  15 #include <linux/io.h>
  16 #include <linux/syscore_ops.h>
  17
  18 #include <plat/cpu-freq.h>
  19 #include <plat/clock.h>
  20 #include <plat/cpu.h>
  21 #include <plat/pll.h>
  22 #include <plat/s5p-clock.h>
  23 #include <plat/clock-clksrc.h>
  24 #include <plat/pm.h>
  25
  26 #include <mach/map.h>
  27 #include <mach/regs-clock.h>
  28 #include <mach/sysmmu.h>
  29 #include <mach/exynos4-clock.h>
  30
  31 #include "common.h"
  32
  33 static struct sleep_save exynos4_clock_save[] = {
  34         SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
  35         SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
  36         SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
  37         SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
  38         SAVE_ITEM(S5P_CLKSRC_TOP0),
  39         SAVE_ITEM(S5P_CLKSRC_TOP1),
  40         SAVE_ITEM(S5P_CLKSRC_CAM),
  41         SAVE_ITEM(S5P_CLKSRC_TV),
  42         SAVE_ITEM(S5P_CLKSRC_MFC),
  43         SAVE_ITEM(S5P_CLKSRC_G3D),
  44         SAVE_ITEM(S5P_CLKSRC_LCD0),
  45         SAVE_ITEM(S5P_CLKSRC_MAUDIO),
  46         SAVE_ITEM(S5P_CLKSRC_FSYS),
  47         SAVE_ITEM(S5P_CLKSRC_PERIL0),
  48         SAVE_ITEM(S5P_CLKSRC_PERIL1),
  49         SAVE_ITEM(S5P_CLKDIV_CAM),
  50         SAVE_ITEM(S5P_CLKDIV_TV),
  51         SAVE_ITEM(S5P_CLKDIV_MFC),
  52         SAVE_ITEM(S5P_CLKDIV_G3D),
  53         SAVE_ITEM(S5P_CLKDIV_LCD0),
  54         SAVE_ITEM(S5P_CLKDIV_MAUDIO),
  55         SAVE_ITEM(S5P_CLKDIV_FSYS0),
  56         SAVE_ITEM(S5P_CLKDIV_FSYS1),
  57         SAVE_ITEM(S5P_CLKDIV_FSYS2),
  58         SAVE_ITEM(S5P_CLKDIV_FSYS3),
  59         SAVE_ITEM(S5P_CLKDIV_PERIL0),
  60         SAVE_ITEM(S5P_CLKDIV_PERIL1),
  61         SAVE_ITEM(S5P_CLKDIV_PERIL2),
  62         SAVE_ITEM(S5P_CLKDIV_PERIL3),
  63         SAVE_ITEM(S5P_CLKDIV_PERIL4),
  64         SAVE_ITEM(S5P_CLKDIV_PERIL5),
  65         SAVE_ITEM(S5P_CLKDIV_TOP),
  66         SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
  67         SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
  68         SAVE_ITEM(S5P_CLKSRC_MASK_TV),
  69         SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
  70         SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
  71         SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
  72         SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
  73         SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
  74         SAVE_ITEM(S5P_CLKDIV2_RATIO),
  75         SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
  76         SAVE_ITEM(S5P_CLKGATE_IP_CAM),
  77         SAVE_ITEM(S5P_CLKGATE_IP_TV),
  78         SAVE_ITEM(S5P_CLKGATE_IP_MFC),
  79         SAVE_ITEM(S5P_CLKGATE_IP_G3D),
  80         SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
  81         SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
  82         SAVE_ITEM(S5P_CLKGATE_IP_GPS),
  83         SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
  84         SAVE_ITEM(S5P_CLKGATE_BLOCK),
  85         SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
  86         SAVE_ITEM(S5P_CLKSRC_DMC),
  87         SAVE_ITEM(S5P_CLKDIV_DMC0),
  88         SAVE_ITEM(S5P_CLKDIV_DMC1),
  89         SAVE_ITEM(S5P_CLKGATE_IP_DMC),
  90         SAVE_ITEM(S5P_CLKSRC_CPU),
  91         SAVE_ITEM(S5P_CLKDIV_CPU),
  92         SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
  93         SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
  94         SAVE_ITEM(S5P_CLKGATE_IP_CPU),
  95 };
  96
  97 struct clk clk_sclk_hdmi27m = {
  98         .name           = "sclk_hdmi27m",
  99         .rate           = 27000000,
 100 };
 101
 102 struct clk clk_sclk_hdmiphy = {
 103         .name           = "sclk_hdmiphy",
 104 };
 105
 106 struct clk clk_sclk_usbphy0 = {
 107         .name           = "sclk_usbphy0",
 108         .rate           = 27000000,
 109 };
 110
 111 struct clk clk_sclk_usbphy1 = {
 112         .name           = "sclk_usbphy1",
 113 };
 114
 115 static struct clk dummy_apb_pclk = {
 116         .name           = "apb_pclk",
 117         .id             = -1,
 118 };
 119
 120 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
 121 {
 122         return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
 123 }
 124
 125 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
 126 {
 127         return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
 128 }
 129
 130 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
 131 {
 132         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
 133 }
 134
 135 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 136 {
 137         return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
 138 }
 139
 140 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
 141 {
 142         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
 143 }
 144
 145 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
 146 {
 147         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
 148 }
 149
 150 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 151 {
 152         return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
 153 }
 154
 155 static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
 156 {
 157         return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
 158 }
 159
 160 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
 161 {
 162         return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
 163 }
 164
 165 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
 166 {
 167         return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
 168 }
 169
 170 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
 171 {
 172         return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
 173 }
 174
 175 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
 176 {
 177         return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
 178 }
 179
 180 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
 181 {
 182         return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
 183 }
 184
 185 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 186 {
 187         return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
 188 }
 189
 190 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
 191 {
 192         return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
 193 }
 194
 195 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
 196 {
 197         return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
 198 }
 199
 200 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
 201 {
 202         return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
 203 }
 204
 205 static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
 206 {
 207         return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
 208 }
 209
 210 /* Core list of CMU_CPU side */
 211
 212 static struct clksrc_clk clk_mout_apll = {
 213         .clk    = {
 214                 .name           = "mout_apll",
 215         },
 216         .sources        = &clk_src_apll,
 217         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
 218 };
 219
 220 struct clksrc_clk clk_sclk_apll = {
 221         .clk    = {
 222                 .name           = "sclk_apll",
 223                 .parent         = &clk_mout_apll.clk,
 224         },
 225         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
 226 };
 227
 228 struct clksrc_clk clk_mout_epll = {
 229         .clk    = {
 230                 .name           = "mout_epll",
 231         },
 232         .sources        = &clk_src_epll,
 233         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
 234 };
 235
 236 struct clksrc_clk clk_mout_mpll = {
 237         .clk = {
 238                 .name           = "mout_mpll",
 239         },
 240         .sources        = &clk_src_mpll,
 241
 242         /* reg_src will be added in each SoCs' clock */
 243 };
 244
 245 static struct clk *clkset_moutcore_list[] = {
 246         [0] = &clk_mout_apll.clk,
 247         [1] = &clk_mout_mpll.clk,
 248 };
 249
 250 static struct clksrc_sources clkset_moutcore = {
 251         .sources        = clkset_moutcore_list,
 252         .nr_sources     = ARRAY_SIZE(clkset_moutcore_list),
 253 };
 254
 255 static struct clksrc_clk clk_moutcore = {
 256         .clk    = {
 257                 .name           = "moutcore",
 258         },
 259         .sources        = &clkset_moutcore,
 260         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
 261 };
 262
 263 static struct clksrc_clk clk_coreclk = {
 264         .clk    = {
 265                 .name           = "core_clk",
 266                 .parent         = &clk_moutcore.clk,
 267         },
 268         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
 269 };
 270
 271 static struct clksrc_clk clk_armclk = {
 272         .clk    = {
 273                 .name           = "armclk",
 274                 .parent         = &clk_coreclk.clk,
 275         },
 276 };
 277
 278 static struct clksrc_clk clk_aclk_corem0 = {
 279         .clk    = {
 280                 .name           = "aclk_corem0",
 281                 .parent         = &clk_coreclk.clk,
 282         },
 283         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
 284 };
 285
 286 static struct clksrc_clk clk_aclk_cores = {
 287         .clk    = {
 288                 .name           = "aclk_cores",
 289                 .parent         = &clk_coreclk.clk,
 290         },
 291         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
 292 };
 293
 294 static struct clksrc_clk clk_aclk_corem1 = {
 295         .clk    = {
 296                 .name           = "aclk_corem1",
 297                 .parent         = &clk_coreclk.clk,
 298         },
 299         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
 300 };
 301
 302 static struct clksrc_clk clk_periphclk = {
 303         .clk    = {
 304                 .name           = "periphclk",
 305                 .parent         = &clk_coreclk.clk,
 306         },
 307         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
 308 };
 309
 310 /* Core list of CMU_CORE side */
 311
 312 struct clk *clkset_corebus_list[] = {
 313         [0] = &clk_mout_mpll.clk,
 314         [1] = &clk_sclk_apll.clk,
 315 };
 316
 317 struct clksrc_sources clkset_mout_corebus = {
 318         .sources        = clkset_corebus_list,
 319         .nr_sources     = ARRAY_SIZE(clkset_corebus_list),
 320 };
 321
 322 static struct clksrc_clk clk_mout_corebus = {
 323         .clk    = {
 324                 .name           = "mout_corebus",
 325         },
 326         .sources        = &clkset_mout_corebus,
 327         .reg_src        = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
 328 };
 329
 330 static struct clksrc_clk clk_sclk_dmc = {
 331         .clk    = {
 332                 .name           = "sclk_dmc",
 333                 .parent         = &clk_mout_corebus.clk,
 334         },
 335         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
 336 };
 337
 338 static struct clksrc_clk clk_aclk_cored = {
 339         .clk    = {
 340                 .name           = "aclk_cored",
 341                 .parent         = &clk_sclk_dmc.clk,
 342         },
 343         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
 344 };
 345
 346 static struct clksrc_clk clk_aclk_corep = {
 347         .clk    = {
 348                 .name           = "aclk_corep",
 349                 .parent         = &clk_aclk_cored.clk,
 350         },
 351         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
 352 };
 353
 354 static struct clksrc_clk clk_aclk_acp = {
 355         .clk    = {
 356                 .name           = "aclk_acp",
 357                 .parent         = &clk_mout_corebus.clk,
 358         },
 359         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
 360 };
 361
 362 static struct clksrc_clk clk_pclk_acp = {
 363         .clk    = {
 364                 .name           = "pclk_acp",
 365                 .parent         = &clk_aclk_acp.clk,
 366         },
 367         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
 368 };
 369
 370 /* Core list of CMU_TOP side */
 371
 372 struct clk *clkset_aclk_top_list[] = {
 373         [0] = &clk_mout_mpll.clk,
 374         [1] = &clk_sclk_apll.clk,
 375 };
 376
 377 struct clksrc_sources clkset_aclk = {
 378         .sources        = clkset_aclk_top_list,
 379         .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
 380 };
 381
 382 static struct clksrc_clk clk_aclk_200 = {
 383         .clk    = {
 384                 .name           = "aclk_200",
 385         },
 386         .sources        = &clkset_aclk,
 387         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
 388         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
 389 };
 390
 391 static struct clksrc_clk clk_aclk_100 = {
 392         .clk    = {
 393                 .name           = "aclk_100",
 394         },
 395         .sources        = &clkset_aclk,
 396         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
 397         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
 398 };
 399
 400 static struct clksrc_clk clk_aclk_160 = {
 401         .clk    = {
 402                 .name           = "aclk_160",
 403         },
 404         .sources        = &clkset_aclk,
 405         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
 406         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
 407 };
 408
 409 struct clksrc_clk clk_aclk_133 = {
 410         .clk    = {
 411                 .name           = "aclk_133",
 412         },
 413         .sources        = &clkset_aclk,
 414         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
 415         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
 416 };
 417
 418 static struct clk *clkset_vpllsrc_list[] = {
 419         [0] = &clk_fin_vpll,
 420         [1] = &clk_sclk_hdmi27m,
 421 };
 422
 423 static struct clksrc_sources clkset_vpllsrc = {
 424         .sources        = clkset_vpllsrc_list,
 425         .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
 426 };
 427
 428 static struct clksrc_clk clk_vpllsrc = {
 429         .clk    = {
 430                 .name           = "vpll_src",
 431                 .enable         = exynos4_clksrc_mask_top_ctrl,
 432                 .ctrlbit        = (1 << 0),
 433         },
 434         .sources        = &clkset_vpllsrc,
 435         .reg_src        = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
 436 };
 437
 438 static struct clk *clkset_sclk_vpll_list[] = {
 439         [0] = &clk_vpllsrc.clk,
 440         [1] = &clk_fout_vpll,
 441 };
 442
 443 static struct clksrc_sources clkset_sclk_vpll = {
 444         .sources        = clkset_sclk_vpll_list,
 445         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 446 };
 447
 448 struct clksrc_clk clk_sclk_vpll = {
 449         .clk    = {
 450                 .name           = "sclk_vpll",
 451         },
 452         .sources        = &clkset_sclk_vpll,
 453         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
 454 };
 455
 456 static struct clk init_clocks_off[] = {
 457         {
 458                 .name           = "timers",
 459                 .parent         = &clk_aclk_100.clk,
 460                 .enable         = exynos4_clk_ip_peril_ctrl,
 461                 .ctrlbit        = (1<<24),
 462         }, {
 463                 .name           = "csis",
 464                 .devname        = "s5p-mipi-csis.0",
 465                 .enable         = exynos4_clk_ip_cam_ctrl,
 466                 .ctrlbit        = (1 << 4),
 467         }, {
 468                 .name           = "csis",
 469                 .devname        = "s5p-mipi-csis.1",
 470                 .enable         = exynos4_clk_ip_cam_ctrl,
 471                 .ctrlbit        = (1 << 5),
 472         }, {
 473                 .name           = "fimc",
 474                 .devname        = "exynos4-fimc.0",
 475                 .enable         = exynos4_clk_ip_cam_ctrl,
 476                 .ctrlbit        = (1 << 0),
 477         }, {
 478                 .name           = "fimc",
 479                 .devname        = "exynos4-fimc.1",
 480                 .enable         = exynos4_clk_ip_cam_ctrl,
 481                 .ctrlbit        = (1 << 1),
 482         }, {
 483                 .name           = "fimc",
 484                 .devname        = "exynos4-fimc.2",
 485                 .enable         = exynos4_clk_ip_cam_ctrl,
 486                 .ctrlbit        = (1 << 2),
 487         }, {
 488                 .name           = "fimc",
 489                 .devname        = "exynos4-fimc.3",
 490                 .enable         = exynos4_clk_ip_cam_ctrl,
 491                 .ctrlbit        = (1 << 3),
 492         }, {
 493                 .name           = "fimd",
 494                 .devname        = "exynos4-fb.0",
 495                 .enable         = exynos4_clk_ip_lcd0_ctrl,
 496                 .ctrlbit        = (1 << 0),
 497         }, {
 498                 .name           = "hsmmc",
 499                 .devname        = "s3c-sdhci.0",
 500                 .parent         = &clk_aclk_133.clk,
 501                 .enable         = exynos4_clk_ip_fsys_ctrl,
 502                 .ctrlbit        = (1 << 5),
 503         }, {
 504                 .name           = "hsmmc",
 505                 .devname        = "s3c-sdhci.1",
 506                 .parent         = &clk_aclk_133.clk,
 507                 .enable         = exynos4_clk_ip_fsys_ctrl,
 508                 .ctrlbit        = (1 << 6),
 509         }, {
 510                 .name           = "hsmmc",
 511                 .devname        = "s3c-sdhci.2",
 512                 .parent         = &clk_aclk_133.clk,
 513                 .enable         = exynos4_clk_ip_fsys_ctrl,
 514                 .ctrlbit        = (1 << 7),
 515         }, {
 516                 .name           = "hsmmc",
 517                 .devname        = "s3c-sdhci.3",
 518                 .parent         = &clk_aclk_133.clk,
 519                 .enable         = exynos4_clk_ip_fsys_ctrl,
 520                 .ctrlbit        = (1 << 8),
 521         }, {
 522                 .name           = "dwmmc",
 523                 .parent         = &clk_aclk_133.clk,
 524                 .enable         = exynos4_clk_ip_fsys_ctrl,
 525                 .ctrlbit        = (1 << 9),
 526         }, {
 527                 .name           = "dac",
 528                 .devname        = "s5p-sdo",
 529                 .enable         = exynos4_clk_ip_tv_ctrl,
 530                 .ctrlbit        = (1 << 2),
 531         }, {
 532                 .name           = "mixer",
 533                 .devname        = "s5p-mixer",
 534                 .enable         = exynos4_clk_ip_tv_ctrl,
 535                 .ctrlbit        = (1 << 1),
 536         }, {
 537                 .name           = "vp",
 538                 .devname        = "s5p-mixer",
 539                 .enable         = exynos4_clk_ip_tv_ctrl,
 540                 .ctrlbit        = (1 << 0),
 541         }, {
 542                 .name           = "hdmi",
 543                 .devname        = "exynos4-hdmi",
 544                 .enable         = exynos4_clk_ip_tv_ctrl,
 545                 .ctrlbit        = (1 << 3),
 546         }, {
 547                 .name           = "hdmiphy",
 548                 .devname        = "exynos4-hdmi",
 549                 .enable         = exynos4_clk_hdmiphy_ctrl,
 550                 .ctrlbit        = (1 << 0),
 551         }, {
 552                 .name           = "dacphy",
 553                 .devname        = "s5p-sdo",
 554                 .enable         = exynos4_clk_dac_ctrl,
 555                 .ctrlbit        = (1 << 0),
 556         }, {
 557                 .name           = "adc",
 558                 .enable         = exynos4_clk_ip_peril_ctrl,
 559                 .ctrlbit        = (1 << 15),
 560         }, {
 561                 .name           = "keypad",
 562                 .enable         = exynos4_clk_ip_perir_ctrl,
 563                 .ctrlbit        = (1 << 16),
 564         }, {
 565                 .name           = "rtc",
 566                 .enable         = exynos4_clk_ip_perir_ctrl,
 567                 .ctrlbit        = (1 << 15),
 568         }, {
 569                 .name           = "watchdog",
 570                 .parent         = &clk_aclk_100.clk,
 571                 .enable         = exynos4_clk_ip_perir_ctrl,
 572                 .ctrlbit        = (1 << 14),
 573         }, {
 574                 .name           = "usbhost",
 575                 .enable         = exynos4_clk_ip_fsys_ctrl ,
 576                 .ctrlbit        = (1 << 12),
 577         }, {
 578                 .name           = "otg",
 579                 .enable         = exynos4_clk_ip_fsys_ctrl,
 580                 .ctrlbit        = (1 << 13),
 581         }, {
 582                 .name           = "spi",
 583                 .devname        = "s3c64xx-spi.0",
 584                 .enable         = exynos4_clk_ip_peril_ctrl,
 585                 .ctrlbit        = (1 << 16),
 586         }, {
 587                 .name           = "spi",
 588                 .devname        = "s3c64xx-spi.1",
 589                 .enable         = exynos4_clk_ip_peril_ctrl,
 590                 .ctrlbit        = (1 << 17),
 591         }, {
 592                 .name           = "spi",
 593                 .devname        = "s3c64xx-spi.2",
 594                 .enable         = exynos4_clk_ip_peril_ctrl,
 595                 .ctrlbit        = (1 << 18),
 596         }, {
 597                 .name           = "iis",
 598                 .devname        = "samsung-i2s.0",
 599                 .enable         = exynos4_clk_ip_peril_ctrl,
 600                 .ctrlbit        = (1 << 19),
 601         }, {
 602                 .name           = "iis",
 603                 .devname        = "samsung-i2s.1",
 604                 .enable         = exynos4_clk_ip_peril_ctrl,
 605                 .ctrlbit        = (1 << 20),
 606         }, {
 607                 .name           = "iis",
 608                 .devname        = "samsung-i2s.2",
 609                 .enable         = exynos4_clk_ip_peril_ctrl,
 610                 .ctrlbit        = (1 << 21),
 611         }, {
 612                 .name           = "ac97",
 613                 .devname        = "samsung-ac97",
 614                 .enable         = exynos4_clk_ip_peril_ctrl,
 615                 .ctrlbit        = (1 << 27),
 616         }, {
 617                 .name           = "fimg2d",
 618                 .enable         = exynos4_clk_ip_image_ctrl,
 619                 .ctrlbit        = (1 << 0),
 620         }, {
 621                 .name           = "mfc",
 622                 .devname        = "s5p-mfc",
 623                 .enable         = exynos4_clk_ip_mfc_ctrl,
 624                 .ctrlbit        = (1 << 0),
 625         }, {
 626                 .name           = "i2c",
 627                 .devname        = "s3c2440-i2c.0",
 628                 .parent         = &clk_aclk_100.clk,
 629                 .enable         = exynos4_clk_ip_peril_ctrl,
 630                 .ctrlbit        = (1 << 6),
 631         }, {
 632                 .name           = "i2c",
 633                 .devname        = "s3c2440-i2c.1",
 634                 .parent         = &clk_aclk_100.clk,
 635                 .enable         = exynos4_clk_ip_peril_ctrl,
 636                 .ctrlbit        = (1 << 7),
 637         }, {
 638                 .name           = "i2c",
 639                 .devname        = "s3c2440-i2c.2",
 640                 .parent         = &clk_aclk_100.clk,
 641                 .enable         = exynos4_clk_ip_peril_ctrl,
 642                 .ctrlbit        = (1 << 8),
 643         }, {
 644                 .name           = "i2c",
 645                 .devname        = "s3c2440-i2c.3",
 646                 .parent         = &clk_aclk_100.clk,
 647                 .enable         = exynos4_clk_ip_peril_ctrl,
 648                 .ctrlbit        = (1 << 9),
 649         }, {
 650                 .name           = "i2c",
 651                 .devname        = "s3c2440-i2c.4",
 652                 .parent         = &clk_aclk_100.clk,
 653                 .enable         = exynos4_clk_ip_peril_ctrl,
 654                 .ctrlbit        = (1 << 10),
 655         }, {
 656                 .name           = "i2c",
 657                 .devname        = "s3c2440-i2c.5",
 658                 .parent         = &clk_aclk_100.clk,
 659                 .enable         = exynos4_clk_ip_peril_ctrl,
 660                 .ctrlbit        = (1 << 11),
 661         }, {
 662                 .name           = "i2c",
 663                 .devname        = "s3c2440-i2c.6",
 664                 .parent         = &clk_aclk_100.clk,
 665                 .enable         = exynos4_clk_ip_peril_ctrl,
 666                 .ctrlbit        = (1 << 12),
 667         }, {
 668                 .name           = "i2c",
 669                 .devname        = "s3c2440-i2c.7",
 670                 .parent         = &clk_aclk_100.clk,
 671                 .enable         = exynos4_clk_ip_peril_ctrl,
 672                 .ctrlbit        = (1 << 13),
 673         }, {
 674                 .name           = "i2c",
 675                 .devname        = "s3c2440-hdmiphy-i2c",
 676                 .parent         = &clk_aclk_100.clk,
 677                 .enable         = exynos4_clk_ip_peril_ctrl,
 678                 .ctrlbit        = (1 << 14),
 679         }, {
 680                 .name           = "SYSMMU_MDMA",
 681                 .enable         = exynos4_clk_ip_image_ctrl,
 682                 .ctrlbit        = (1 << 5),
 683         }, {
 684                 .name           = "SYSMMU_FIMC0",
 685                 .enable         = exynos4_clk_ip_cam_ctrl,
 686                 .ctrlbit        = (1 << 7),
 687         }, {
 688                 .name           = "SYSMMU_FIMC1",
 689                 .enable         = exynos4_clk_ip_cam_ctrl,
 690                 .ctrlbit        = (1 << 8),
 691         }, {
 692                 .name           = "SYSMMU_FIMC2",
 693                 .enable         = exynos4_clk_ip_cam_ctrl,
 694                 .ctrlbit        = (1 << 9),
 695         }, {
 696                 .name           = "SYSMMU_FIMC3",
 697                 .enable         = exynos4_clk_ip_cam_ctrl,
 698                 .ctrlbit        = (1 << 10),
 699         }, {
 700                 .name           = "SYSMMU_JPEG",
 701                 .enable         = exynos4_clk_ip_cam_ctrl,
 702                 .ctrlbit        = (1 << 11),
 703         }, {
 704                 .name           = "SYSMMU_FIMD0",
 705                 .enable         = exynos4_clk_ip_lcd0_ctrl,
 706                 .ctrlbit        = (1 << 4),
 707         }, {
 708                 .name           = "SYSMMU_FIMD1",
 709                 .enable         = exynos4_clk_ip_lcd1_ctrl,
 710                 .ctrlbit        = (1 << 4),
 711         }, {
 712                 .name           = "SYSMMU_PCIe",
 713                 .enable         = exynos4_clk_ip_fsys_ctrl,
 714                 .ctrlbit        = (1 << 18),
 715         }, {
 716                 .name           = "SYSMMU_G2D",
 717                 .enable         = exynos4_clk_ip_image_ctrl,
 718                 .ctrlbit        = (1 << 3),
 719         }, {
 720                 .name           = "SYSMMU_ROTATOR",
 721                 .enable         = exynos4_clk_ip_image_ctrl,
 722                 .ctrlbit        = (1 << 4),
 723         }, {
 724                 .name           = "SYSMMU_TV",
 725                 .enable         = exynos4_clk_ip_tv_ctrl,
 726                 .ctrlbit        = (1 << 4),
 727         }, {
 728                 .name           = "SYSMMU_MFC_L",
 729                 .enable         = exynos4_clk_ip_mfc_ctrl,
 730                 .ctrlbit        = (1 << 1),
 731         }, {
 732                 .name           = "SYSMMU_MFC_R",
 733                 .enable         = exynos4_clk_ip_mfc_ctrl,
 734                 .ctrlbit        = (1 << 2),
 735         }
 736 };
 737
 738 static struct clk init_clocks[] = {
 739         {
 740                 .name           = "uart",
 741                 .devname        = "s5pv210-uart.0",
 742                 .enable         = exynos4_clk_ip_peril_ctrl,
 743                 .ctrlbit        = (1 << 0),
 744         }, {
 745                 .name           = "uart",
 746                 .devname        = "s5pv210-uart.1",
 747                 .enable         = exynos4_clk_ip_peril_ctrl,
 748                 .ctrlbit        = (1 << 1),
 749         }, {
 750                 .name           = "uart",
 751                 .devname        = "s5pv210-uart.2",
 752                 .enable         = exynos4_clk_ip_peril_ctrl,
 753                 .ctrlbit        = (1 << 2),
 754         }, {
 755                 .name           = "uart",
 756                 .devname        = "s5pv210-uart.3",
 757                 .enable         = exynos4_clk_ip_peril_ctrl,
 758                 .ctrlbit        = (1 << 3),
 759         }, {
 760                 .name           = "uart",
 761                 .devname        = "s5pv210-uart.4",
 762                 .enable         = exynos4_clk_ip_peril_ctrl,
 763                 .ctrlbit        = (1 << 4),
 764         }, {
 765                 .name           = "uart",
 766                 .devname        = "s5pv210-uart.5",
 767                 .enable         = exynos4_clk_ip_peril_ctrl,
 768                 .ctrlbit        = (1 << 5),
 769         }
 770 };
 771
 772 static struct clk clk_pdma0 = {
 773         .name           = "dma",
 774         .devname        = "dma-pl330.0",
 775         .enable         = exynos4_clk_ip_fsys_ctrl,
 776         .ctrlbit        = (1 << 0),
 777 };
 778
 779 static struct clk clk_pdma1 = {
 780         .name           = "dma",
 781         .devname        = "dma-pl330.1",
 782         .enable         = exynos4_clk_ip_fsys_ctrl,
 783         .ctrlbit        = (1 << 1),
 784 };
 785
 786 struct clk *clkset_group_list[] = {
 787         [0] = &clk_ext_xtal_mux,
 788         [1] = &clk_xusbxti,
 789         [2] = &clk_sclk_hdmi27m,
 790         [3] = &clk_sclk_usbphy0,
 791         [4] = &clk_sclk_usbphy1,
 792         [5] = &clk_sclk_hdmiphy,
 793         [6] = &clk_mout_mpll.clk,
 794         [7] = &clk_mout_epll.clk,
 795         [8] = &clk_sclk_vpll.clk,
 796 };
 797
 798 struct clksrc_sources clkset_group = {
 799         .sources        = clkset_group_list,
 800         .nr_sources     = ARRAY_SIZE(clkset_group_list),
 801 };
 802
 803 static struct clk *clkset_mout_g2d0_list[] = {
 804         [0] = &clk_mout_mpll.clk,
 805         [1] = &clk_sclk_apll.clk,
 806 };
 807
 808 static struct clksrc_sources clkset_mout_g2d0 = {
 809         .sources        = clkset_mout_g2d0_list,
 810         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d0_list),
 811 };
 812
 813 static struct clksrc_clk clk_mout_g2d0 = {
 814         .clk    = {
 815                 .name           = "mout_g2d0",
 816         },
 817         .sources        = &clkset_mout_g2d0,
 818         .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
 819 };
 820
 821 static struct clk *clkset_mout_g2d1_list[] = {
 822         [0] = &clk_mout_epll.clk,
 823         [1] = &clk_sclk_vpll.clk,
 824 };
 825
 826 static struct clksrc_sources clkset_mout_g2d1 = {
 827         .sources        = clkset_mout_g2d1_list,
 828         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d1_list),
 829 };
 830
 831 static struct clksrc_clk clk_mout_g2d1 = {
 832         .clk    = {
 833                 .name           = "mout_g2d1",
 834         },
 835         .sources        = &clkset_mout_g2d1,
 836         .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
 837 };
 838
 839 static struct clk *clkset_mout_g2d_list[] = {
 840         [0] = &clk_mout_g2d0.clk,
 841         [1] = &clk_mout_g2d1.clk,
 842 };
 843
 844 static struct clksrc_sources clkset_mout_g2d = {
 845         .sources        = clkset_mout_g2d_list,
 846         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d_list),
 847 };
 848
 849 static struct clk *clkset_mout_mfc0_list[] = {
 850         [0] = &clk_mout_mpll.clk,
 851         [1] = &clk_sclk_apll.clk,
 852 };
 853
 854 static struct clksrc_sources clkset_mout_mfc0 = {
 855         .sources        = clkset_mout_mfc0_list,
 856         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc0_list),
 857 };
 858
 859 static struct clksrc_clk clk_mout_mfc0 = {
 860         .clk    = {
 861                 .name           = "mout_mfc0",
 862         },
 863         .sources        = &clkset_mout_mfc0,
 864         .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
 865 };
 866
 867 static struct clk *clkset_mout_mfc1_list[] = {
 868         [0] = &clk_mout_epll.clk,
 869         [1] = &clk_sclk_vpll.clk,
 870 };
 871
 872 static struct clksrc_sources clkset_mout_mfc1 = {
 873         .sources        = clkset_mout_mfc1_list,
 874         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc1_list),
 875 };
 876
 877 static struct clksrc_clk clk_mout_mfc1 = {
 878         .clk    = {
 879                 .name           = "mout_mfc1",
 880         },
 881         .sources        = &clkset_mout_mfc1,
 882         .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
 883 };
 884
 885 static struct clk *clkset_mout_mfc_list[] = {
 886         [0] = &clk_mout_mfc0.clk,
 887         [1] = &clk_mout_mfc1.clk,
 888 };
 889
 890 static struct clksrc_sources clkset_mout_mfc = {
 891         .sources        = clkset_mout_mfc_list,
 892         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc_list),
 893 };
 894
 895 static struct clk *clkset_sclk_dac_list[] = {
 896         [0] = &clk_sclk_vpll.clk,
 897         [1] = &clk_sclk_hdmiphy,
 898 };
 899
 900 static struct clksrc_sources clkset_sclk_dac = {
 901         .sources        = clkset_sclk_dac_list,
 902         .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
 903 };
 904
 905 static struct clksrc_clk clk_sclk_dac = {
 906         .clk            = {
 907                 .name           = "sclk_dac",
 908                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 909                 .ctrlbit        = (1 << 8),
 910         },
 911         .sources = &clkset_sclk_dac,
 912         .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
 913 };
 914
 915 static struct clksrc_clk clk_sclk_pixel = {
 916         .clk            = {
 917                 .name           = "sclk_pixel",
 918                 .parent = &clk_sclk_vpll.clk,
 919         },
 920         .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
 921 };
 922
 923 static struct clk *clkset_sclk_hdmi_list[] = {
 924         [0] = &clk_sclk_pixel.clk,
 925         [1] = &clk_sclk_hdmiphy,
 926 };
 927
 928 static struct clksrc_sources clkset_sclk_hdmi = {
 929         .sources        = clkset_sclk_hdmi_list,
 930         .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
 931 };
 932
 933 static struct clksrc_clk clk_sclk_hdmi = {
 934         .clk            = {
 935                 .name           = "sclk_hdmi",
 936                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 937                 .ctrlbit        = (1 << 0),
 938         },
 939         .sources = &clkset_sclk_hdmi,
 940         .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
 941 };
 942
 943 static struct clk *clkset_sclk_mixer_list[] = {
 944         [0] = &clk_sclk_dac.clk,
 945         [1] = &clk_sclk_hdmi.clk,
 946 };
 947
 948 static struct clksrc_sources clkset_sclk_mixer = {
 949         .sources        = clkset_sclk_mixer_list,
 950         .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
 951 };
 952
 953 static struct clksrc_clk clk_sclk_mixer = {
 954         .clk            = {
 955                 .name           = "sclk_mixer",
 956                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 957                 .ctrlbit        = (1 << 4),
 958         },
 959         .sources = &clkset_sclk_mixer,
 960         .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
 961 };
 962
 963 static struct clksrc_clk *sclk_tv[] = {
 964         &clk_sclk_dac,
 965         &clk_sclk_pixel,
 966         &clk_sclk_hdmi,
 967         &clk_sclk_mixer,
 968 };
 969
 970 static struct clksrc_clk clk_dout_mmc0 = {
 971         .clk            = {
 972                 .name           = "dout_mmc0",
 973         },
 974         .sources = &clkset_group,
 975         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
 976         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
 977 };
 978
 979 static struct clksrc_clk clk_dout_mmc1 = {
 980         .clk            = {
 981                 .name           = "dout_mmc1",
 982         },
 983         .sources = &clkset_group,
 984         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
 985         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
 986 };
 987
 988 static struct clksrc_clk clk_dout_mmc2 = {
 989         .clk            = {
 990                 .name           = "dout_mmc2",
 991         },
 992         .sources = &clkset_group,
 993         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
 994         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
 995 };
 996
 997 static struct clksrc_clk clk_dout_mmc3 = {
 998         .clk            = {
 999                 .name           = "dout_mmc3",
1000         },
1001         .sources = &clkset_group,
1002         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
1003         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1004 };
1005
1006 static struct clksrc_clk clk_dout_mmc4 = {
1007         .clk            = {
1008                 .name           = "dout_mmc4",
1009         },
1010         .sources = &clkset_group,
1011         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
1012         .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1013 };
1014
1015 static struct clksrc_clk clksrcs[] = {
1016         {
1017                 .clk            = {
1018                         .name           = "sclk_pwm",
1019                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
1020                         .ctrlbit        = (1 << 24),
1021                 },
1022                 .sources = &clkset_group,
1023                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1024                 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1025         }, {
1026                 .clk            = {
1027                         .name           = "sclk_csis",
1028                         .devname        = "s5p-mipi-csis.0",
1029                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1030                         .ctrlbit        = (1 << 24),
1031                 },
1032                 .sources = &clkset_group,
1033                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
1034                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
1035         }, {
1036                 .clk            = {
1037                         .name           = "sclk_csis",
1038                         .devname        = "s5p-mipi-csis.1",
1039                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1040                         .ctrlbit        = (1 << 28),
1041                 },
1042                 .sources = &clkset_group,
1043                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
1044                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
1045         }, {
1046                 .clk            = {
1047                         .name           = "sclk_cam0",
1048                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1049                         .ctrlbit        = (1 << 16),
1050                 },
1051                 .sources = &clkset_group,
1052                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
1053                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
1054         }, {
1055                 .clk            = {
1056                         .name           = "sclk_cam1",
1057                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1058                         .ctrlbit        = (1 << 20),
1059                 },
1060                 .sources = &clkset_group,
1061                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
1062                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
1063         }, {
1064                 .clk            = {
1065                         .name           = "sclk_fimc",
1066                         .devname        = "exynos4-fimc.0",
1067                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1068                         .ctrlbit        = (1 << 0),
1069                 },
1070                 .sources = &clkset_group,
1071                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
1072                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
1073         }, {
1074                 .clk            = {
1075                         .name           = "sclk_fimc",
1076                         .devname        = "exynos4-fimc.1",
1077                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1078                         .ctrlbit        = (1 << 4),
1079                 },
1080                 .sources = &clkset_group,
1081                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
1082                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
1083         }, {
1084                 .clk            = {
1085                         .name           = "sclk_fimc",
1086                         .devname        = "exynos4-fimc.2",
1087                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1088                         .ctrlbit        = (1 << 8),
1089                 },
1090                 .sources = &clkset_group,
1091                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
1092                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
1093         }, {
1094                 .clk            = {
1095                         .name           = "sclk_fimc",
1096                         .devname        = "exynos4-fimc.3",
1097                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1098                         .ctrlbit        = (1 << 12),
1099                 },
1100                 .sources = &clkset_group,
1101                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
1102                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
1103         }, {
1104                 .clk            = {
1105                         .name           = "sclk_fimd",
1106                         .devname        = "exynos4-fb.0",
1107                         .enable         = exynos4_clksrc_mask_lcd0_ctrl,
1108                         .ctrlbit        = (1 << 0),
1109                 },
1110                 .sources = &clkset_group,
1111                 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
1112                 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
1113         }, {
1114                 .clk            = {
1115                         .name           = "sclk_spi",
1116                         .devname        = "s3c64xx-spi.0",
1117                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
1118                         .ctrlbit        = (1 << 16),
1119                 },
1120                 .sources = &clkset_group,
1121                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1122                 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1123         }, {
1124                 .clk            = {
1125                         .name           = "sclk_spi",
1126                         .devname        = "s3c64xx-spi.1",
1127                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
1128                         .ctrlbit        = (1 << 20),
1129                 },
1130                 .sources = &clkset_group,
1131                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1132                 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1133         }, {
1134                 .clk            = {
1135                         .name           = "sclk_spi",
1136                         .devname        = "s3c64xx-spi.2",
1137                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
1138                         .ctrlbit        = (1 << 24),
1139                 },
1140                 .sources = &clkset_group,
1141                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1142                 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1143         }, {
1144                 .clk            = {
1145                         .name           = "sclk_fimg2d",
1146                 },
1147                 .sources = &clkset_mout_g2d,
1148                 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1149                 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1150         }, {
1151                 .clk            = {
1152                         .name           = "sclk_mfc",
1153                         .devname        = "s5p-mfc",
1154                 },
1155                 .sources = &clkset_mout_mfc,
1156                 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
1157                 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1158         }, {
1159                 .clk            = {
1160                         .name           = "sclk_dwmmc",
1161                         .parent         = &clk_dout_mmc4.clk,
1162                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1163                         .ctrlbit        = (1 << 16),
1164                 },
1165                 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1166         }
1167 };
1168
1169 static struct clksrc_clk clk_sclk_uart0 = {
1170         .clk    = {
1171                 .name           = "uclk1",
1172                 .devname        = "exynos4210-uart.0",
1173                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1174                 .ctrlbit        = (1 << 0),
1175         },
1176         .sources = &clkset_group,
1177         .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1178         .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1179 };
1180
1181 static struct clksrc_clk clk_sclk_uart1 = {
1182         .clk            = {
1183                 .name           = "uclk1",
1184                 .devname        = "exynos4210-uart.1",
1185                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1186                 .ctrlbit        = (1 << 4),
1187         },
1188         .sources = &clkset_group,
1189         .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1190         .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1191 };
1192
1193 static struct clksrc_clk clk_sclk_uart2 = {
1194         .clk            = {
1195                 .name           = "uclk1",
1196                 .devname        = "exynos4210-uart.2",
1197                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1198                 .ctrlbit        = (1 << 8),
1199         },
1200         .sources = &clkset_group,
1201         .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1202         .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1203 };
1204
1205 static struct clksrc_clk clk_sclk_uart3 = {
1206         .clk            = {
1207                 .name           = "uclk1",
1208                 .devname        = "exynos4210-uart.3",
1209                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1210                 .ctrlbit        = (1 << 12),
1211         },
1212         .sources = &clkset_group,
1213         .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1214         .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1215 };
1216
1217 static struct clksrc_clk clk_sclk_mmc0 = {
1218         .clk            = {
1219                 .name           = "sclk_mmc",
1220                 .devname        = "s3c-sdhci.0",
1221                 .parent         = &clk_dout_mmc0.clk,
1222                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1223                 .ctrlbit        = (1 << 0),
1224         },
1225         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1226 };
1227
1228 static struct clksrc_clk clk_sclk_mmc1 = {
1229         .clk            = {
1230                 .name           = "sclk_mmc",
1231                 .devname        = "s3c-sdhci.1",
1232                 .parent         = &clk_dout_mmc1.clk,
1233                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1234                 .ctrlbit        = (1 << 4),
1235         },
1236         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1237 };
1238
1239 static struct clksrc_clk clk_sclk_mmc2 = {
1240         .clk            = {
1241                 .name           = "sclk_mmc",
1242                 .devname        = "s3c-sdhci.2",
1243                 .parent         = &clk_dout_mmc2.clk,
1244                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1245                 .ctrlbit        = (1 << 8),
1246         },
1247         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1248 };
1249
1250 static struct clksrc_clk clk_sclk_mmc3 = {
1251         .clk            = {
1252                 .name           = "sclk_mmc",
1253                 .devname        = "s3c-sdhci.3",
1254                 .parent         = &clk_dout_mmc3.clk,
1255                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1256                 .ctrlbit        = (1 << 12),
1257         },
1258         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1259 };
1260
1261 /* Clock initialization code */
1262 static struct clksrc_clk *sysclks[] = {
1263         &clk_mout_apll,
1264         &clk_sclk_apll,
1265         &clk_mout_epll,
1266         &clk_mout_mpll,
1267         &clk_moutcore,
1268         &clk_coreclk,
1269         &clk_armclk,
1270         &clk_aclk_corem0,
1271         &clk_aclk_cores,
1272         &clk_aclk_corem1,
1273         &clk_periphclk,
1274         &clk_mout_corebus,
1275         &clk_sclk_dmc,
1276         &clk_aclk_cored,
1277         &clk_aclk_corep,
1278         &clk_aclk_acp,
1279         &clk_pclk_acp,
1280         &clk_vpllsrc,
1281         &clk_sclk_vpll,
1282         &clk_aclk_200,
1283         &clk_aclk_100,
1284         &clk_aclk_160,
1285         &clk_aclk_133,
1286         &clk_dout_mmc0,
1287         &clk_dout_mmc1,
1288         &clk_dout_mmc2,
1289         &clk_dout_mmc3,
1290         &clk_dout_mmc4,
1291         &clk_mout_mfc0,
1292         &clk_mout_mfc1,
1293 };
1294
1295 static struct clk *clk_cdev[] = {
1296         &clk_pdma0,
1297         &clk_pdma1,
1298 };
1299
1300 static struct clksrc_clk *clksrc_cdev[] = {
1301         &clk_sclk_uart0,
1302         &clk_sclk_uart1,
1303         &clk_sclk_uart2,
1304         &clk_sclk_uart3,
1305         &clk_sclk_mmc0,
1306         &clk_sclk_mmc1,
1307         &clk_sclk_mmc2,
1308         &clk_sclk_mmc3,
1309 };
1310
1311 static struct clk_lookup exynos4_clk_lookup[] = {
1312         CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk),
1313         CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
1314         CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
1315         CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
1316         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1317         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1318         CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1319         CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1320         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
1321         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
1322 };
1323
1324 static int xtal_rate;
1325
1326 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1327 {
1328         if (soc_is_exynos4210())
1329                 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
1330                                         pll_4508);
1331         else if (soc_is_exynos4212() || soc_is_exynos4412())
1332                 return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
1333         else
1334                 return 0;
1335 }
1336
1337 static struct clk_ops exynos4_fout_apll_ops = {
1338         .get_rate = exynos4_fout_apll_get_rate,
1339 };
1340
1341 static u32 vpll_div[][8] = {
1342         {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
1343         { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1344 };
1345
1346 static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1347 {
1348         return clk->rate;
1349 }
1350
1351 static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1352 {
1353         unsigned int vpll_con0, vpll_con1 = 0;
1354         unsigned int i;
1355
1356         /* Return if nothing changed */
1357         if (clk->rate == rate)
1358                 return 0;
1359
1360         vpll_con0 = __raw_readl(S5P_VPLL_CON0);
1361         vpll_con0 &= ~(0x1 << 27 |                                      \
1362                         PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
1363                         PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
1364                         PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1365
1366         vpll_con1 = __raw_readl(S5P_VPLL_CON1);
1367         vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
1368                         PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1369                         PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1370
1371         for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
1372                 if (vpll_div[i][0] == rate) {
1373                         vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1374                         vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1375                         vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1376                         vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1377                         vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1378                         vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1379                         vpll_con0 |= vpll_div[i][7] << 27;
1380                         break;
1381                 }
1382         }
1383
1384         if (i == ARRAY_SIZE(vpll_div)) {
1385                 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1386                                 __func__);
1387                 return -EINVAL;
1388         }
1389
1390         __raw_writel(vpll_con0, S5P_VPLL_CON0);
1391         __raw_writel(vpll_con1, S5P_VPLL_CON1);
1392
1393         /* Wait for VPLL lock */
1394         while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1395                 continue;
1396
1397         clk->rate = rate;
1398         return 0;
1399 }
1400
1401 static struct clk_ops exynos4_vpll_ops = {
1402         .get_rate = exynos4_vpll_get_rate,
1403         .set_rate = exynos4_vpll_set_rate,
1404 };
1405
1406 void __init_or_cpufreq exynos4_setup_clocks(void)
1407 {
1408         struct clk *xtal_clk;
1409         unsigned long apll = 0;
1410         unsigned long mpll = 0;
1411         unsigned long epll = 0;
1412         unsigned long vpll = 0;
1413         unsigned long vpllsrc;
1414         unsigned long xtal;
1415         unsigned long armclk;
1416         unsigned long sclk_dmc;
1417         unsigned long aclk_200;
1418         unsigned long aclk_100;
1419         unsigned long aclk_160;
1420         unsigned long aclk_133;
1421         unsigned int ptr;
1422
1423         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1424
1425         xtal_clk = clk_get(NULL, "xtal");
1426         BUG_ON(IS_ERR(xtal_clk));
1427
1428         xtal = clk_get_rate(xtal_clk);
1429
1430         xtal_rate = xtal;
1431
1432         clk_put(xtal_clk);
1433
1434         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1435
1436         if (soc_is_exynos4210()) {
1437                 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
1438                                         pll_4508);
1439                 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
1440                                         pll_4508);
1441                 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1442                                         __raw_readl(S5P_EPLL_CON1), pll_4600);
1443
1444                 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1445                 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1446                                         __raw_readl(S5P_VPLL_CON1), pll_4650c);
1447         } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1448                 apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
1449                 mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
1450                 epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
1451                                         __raw_readl(S5P_EPLL_CON1));
1452
1453                 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1454                 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1455                                         __raw_readl(S5P_VPLL_CON1));
1456         } else {
1457                 /* nothing */
1458         }
1459
1460         clk_fout_apll.ops = &exynos4_fout_apll_ops;
1461         clk_fout_mpll.rate = mpll;
1462         clk_fout_epll.rate = epll;
1463         clk_fout_vpll.ops = &exynos4_vpll_ops;
1464         clk_fout_vpll.rate = vpll;
1465
1466         printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1467                         apll, mpll, epll, vpll);
1468
1469         armclk = clk_get_rate(&clk_armclk.clk);
1470         sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1471
1472         aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1473         aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1474         aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1475         aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1476
1477         printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1478                          "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1479                         armclk, sclk_dmc, aclk_200,
1480                         aclk_100, aclk_160, aclk_133);
1481
1482         clk_f.rate = armclk;
1483         clk_h.rate = sclk_dmc;
1484         clk_p.rate = aclk_100;
1485
1486         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1487                 s3c_set_clksrc(&clksrcs[ptr], true);
1488 }
1489
1490 static struct clk *clks[] __initdata = {
1491         &clk_sclk_hdmi27m,
1492         &clk_sclk_hdmiphy,
1493         &clk_sclk_usbphy0,
1494         &clk_sclk_usbphy1,
1495 };
1496
1497 #ifdef CONFIG_PM_SLEEP
1498 static int exynos4_clock_suspend(void)
1499 {
1500         s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1501         return 0;
1502 }
1503
1504 static void exynos4_clock_resume(void)
1505 {
1506         s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1507 }
1508
1509 #else
1510 #define exynos4_clock_suspend NULL
1511 #define exynos4_clock_resume NULL
1512 #endif
1513
1514 struct syscore_ops exynos4_clock_syscore_ops = {
1515         .suspend        = exynos4_clock_suspend,
1516         .resume         = exynos4_clock_resume,
1517 };
1518
1519 void __init exynos4_register_clocks(void)
1520 {
1521         int ptr;
1522
1523         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1524
1525         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1526                 s3c_register_clksrc(sysclks[ptr], 1);
1527
1528         for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1529                 s3c_register_clksrc(sclk_tv[ptr], 1);
1530
1531         for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1532                 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1533
1534         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1535         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1536
1537         s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1538         for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1539                 s3c_disable_clocks(clk_cdev[ptr], 1);
1540
1541         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1542         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1543         clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1544
1545         register_syscore_ops(&exynos4_clock_syscore_ops);
1546         s3c24xx_register_clock(&dummy_apb_pclk);
1547
1548         s3c_pwmclk_init();
1549 }