91a542df579177e76432c92217630e8412b1ddf4
2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
3 * Author: Tony Xie <tony.xie@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #ifndef __MACH_ROCKCHIP_PM_H
16 #define __MACH_ROCKCHIP_PM_H
18 extern unsigned long rkpm_bootdata_cpusp
;
19 extern unsigned long rkpm_bootdata_cpu_code
;
20 extern unsigned long rkpm_bootdata_l2ctlr_f
;
21 extern unsigned long rkpm_bootdata_l2ctlr
;
22 extern unsigned long rkpm_bootdata_ddr_code
;
23 extern unsigned long rkpm_bootdata_ddr_data
;
24 extern unsigned long rk3288_bootram_sz
;
26 void rockchip_slp_cpu_resume(void);
27 #ifdef CONFIG_PM_SLEEP
28 void __init
rockchip_suspend_init(void);
30 static inline void rockchip_suspend_init(void)
35 /****** following is rk3288 defined **********/
36 #define RK3288_PMU_WAKEUP_CFG0 0x00
37 #define RK3288_PMU_WAKEUP_CFG1 0x04
38 #define RK3288_PMU_PWRMODE_CON 0x18
39 #define RK3288_PMU_OSC_CNT 0x20
40 #define RK3288_PMU_PLL_CNT 0x24
41 #define RK3288_PMU_STABL_CNT 0x28
42 #define RK3288_PMU_DDR0IO_PWRON_CNT 0x2c
43 #define RK3288_PMU_DDR1IO_PWRON_CNT 0x30
44 #define RK3288_PMU_CORE_PWRDWN_CNT 0x34
45 #define RK3288_PMU_CORE_PWRUP_CNT 0x38
46 #define RK3288_PMU_GPU_PWRDWN_CNT 0x3c
47 #define RK3288_PMU_GPU_PWRUP_CNT 0x40
48 #define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44
49 #define RK3288_PMU_PWRMODE_CON1 0x90
51 #define RK3288_SGRF_SOC_CON0 (0x0000)
52 #define RK3288_SGRF_FAST_BOOT_ADDR (0x0120)
53 #define SGRF_FAST_BOOT_EN BIT(8)
54 #define SGRF_FAST_BOOT_EN_WRITE BIT(24)
56 #define RK3288_CRU_MODE_CON 0x50
57 #define RK3288_CRU_SEL0_CON 0x60
58 #define RK3288_CRU_SEL1_CON 0x64
59 #define RK3288_CRU_SEL10_CON 0x88
60 #define RK3288_CRU_SEL33_CON 0xe4
61 #define RK3288_CRU_SEL37_CON 0xf4
63 /* PMU_WAKEUP_CFG1 bits */
64 #define PMU_ARMINT_WAKEUP_EN BIT(0)
66 /* wait 30ms for OSC stable and 30ms for pmic stable */
67 #define OSC_STABL_CNT_THRESH (32 * 30)
68 #define PMU_STABL_CNT_THRESH (32 * 30)
70 enum rk3288_pwr_mode_con
{
72 PMU_CLK_CORE_SRC_GATE_EN
,
73 PMU_GLOBAL_INT_DISABLE
,
79 PMU_CHIP_PD_EN
, /* POWER OFF PIN ENABLE */
92 PMU_DDR0IO_RET_DE_REQ
,
96 enum rk3288_pwr_mode_con1
{
109 #endif /* __MACH_ROCKCHIP_PM_H */
This page took 0.038487 seconds and 4 git commands to generate.