2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __ARM64_KVM_MMU_H__
19 #define __ARM64_KVM_MMU_H__
22 #include <asm/memory.h>
23 #include <asm/cpufeature.h>
26 * As ARMv8.0 only has the TTBR0_EL2 register, we cannot express
27 * "negative" addresses. This makes it impossible to directly share
28 * mappings with the kernel.
30 * Instead, give the HYP mode its own VA region at a fixed offset from
31 * the kernel by just masking the top bits (which are all ones for a
32 * kernel address). We need to find out how many bits to mask.
34 * We want to build a set of page tables that cover both parts of the
35 * idmap (the trampoline page used to initialize EL2), and our normal
36 * runtime VA space, at the same time.
38 * Given that the kernel uses VA_BITS for its entire address space,
39 * and that half of that space (VA_BITS - 1) is used for the linear
40 * mapping, we can also limit the EL2 space to (VA_BITS - 1).
42 * The main question is "Within the VA_BITS space, does EL2 use the
43 * top or the bottom half of that space to shadow the kernel's linear
44 * mapping?". As we need to idmap the trampoline page, this is
45 * determined by the range in which this page lives.
47 * If the page is in the bottom half, we have to use the top half. If
48 * the page is in the top half, we have to use the bottom half:
50 * T = __virt_to_phys(__hyp_idmap_text_start)
51 * if (T & BIT(VA_BITS - 1))
52 * HYP_VA_MIN = 0 //idmap in upper half
54 * HYP_VA_MIN = 1 << (VA_BITS - 1)
55 * HYP_VA_MAX = HYP_VA_MIN + (1 << (VA_BITS - 1)) - 1
57 * This of course assumes that the trampoline page exists within the
58 * VA_BITS range. If it doesn't, then it means we're in the odd case
59 * where the kernel idmap (as well as HYP) uses more levels than the
60 * kernel runtime page tables (as seen when the kernel is configured
61 * for 4k pages, 39bits VA, and yet memory lives just above that
62 * limit, forcing the idmap to use 4 levels of page tables while the
63 * kernel itself only uses 3). In this particular case, it doesn't
64 * matter which side of VA_BITS we use, as we're guaranteed not to
65 * conflict with anything.
67 * When using VHE, there are no separate hyp mappings and all KVM
68 * functionality is already mapped as part of the main kernel
69 * mappings, and none of this applies in that case.
72 #define HYP_PAGE_OFFSET_HIGH_MASK ((UL(1) << VA_BITS) - 1)
73 #define HYP_PAGE_OFFSET_LOW_MASK ((UL(1) << (VA_BITS - 1)) - 1)
77 #include <asm/alternative.h>
78 #include <asm/cpufeature.h>
81 * Convert a kernel VA into a HYP VA.
82 * reg: VA to be converted.
84 * This generates the following sequences:
86 * and x0, x0, #HYP_PAGE_OFFSET_HIGH_MASK
89 * and x0, x0, #HYP_PAGE_OFFSET_HIGH_MASK
90 * and x0, x0, #HYP_PAGE_OFFSET_LOW_MASK
95 * The "low mask" version works because the mask is a strict subset of
96 * the "high mask", hence performing the first mask for nothing.
97 * Should be completely invisible on any viable CPU.
99 .macro kern_hyp_va reg
100 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
101 and \reg
, \reg
, #HYP_PAGE_OFFSET_HIGH_MASK
102 alternative_else_nop_endif
103 alternative_if ARM64_HYP_OFFSET_LOW
104 and \reg
, \reg
, #HYP_PAGE_OFFSET_LOW_MASK
105 alternative_else_nop_endif
110 #include <asm/pgalloc.h>
111 #include <asm/cachetype.h>
112 #include <asm/cacheflush.h>
113 #include <asm/mmu_context.h>
114 #include <asm/pgtable.h>
116 static inline unsigned long __kern_hyp_va(unsigned long v
)
118 asm volatile(ALTERNATIVE("and %0, %0, %1",
120 ARM64_HAS_VIRT_HOST_EXTN
)
122 : "i" (HYP_PAGE_OFFSET_HIGH_MASK
));
123 asm volatile(ALTERNATIVE("nop",
125 ARM64_HYP_OFFSET_LOW
)
127 : "i" (HYP_PAGE_OFFSET_LOW_MASK
));
131 #define kern_hyp_va(v) (typeof(v))(__kern_hyp_va((unsigned long)(v)))
134 * We currently only support a 40bit IPA.
136 #define KVM_PHYS_SHIFT (40)
137 #define KVM_PHYS_SIZE (1UL << KVM_PHYS_SHIFT)
138 #define KVM_PHYS_MASK (KVM_PHYS_SIZE - 1UL)
140 #include <asm/stage2_pgtable.h>
142 int create_hyp_mappings(void *from
, void *to
, pgprot_t prot
);
143 int create_hyp_io_mappings(void *from
, void *to
, phys_addr_t
);
144 void free_hyp_pgds(void);
146 void stage2_unmap_vm(struct kvm
*kvm
);
147 int kvm_alloc_stage2_pgd(struct kvm
*kvm
);
148 void kvm_free_stage2_pgd(struct kvm
*kvm
);
149 int kvm_phys_addr_ioremap(struct kvm
*kvm
, phys_addr_t guest_ipa
,
150 phys_addr_t pa
, unsigned long size
, bool writable
);
152 int kvm_handle_guest_abort(struct kvm_vcpu
*vcpu
, struct kvm_run
*run
);
154 void kvm_mmu_free_memory_caches(struct kvm_vcpu
*vcpu
);
156 phys_addr_t
kvm_mmu_get_httbr(void);
157 phys_addr_t
kvm_get_idmap_vector(void);
158 phys_addr_t
kvm_get_idmap_start(void);
159 int kvm_mmu_init(void);
160 void kvm_clear_hyp_idmap(void);
162 #define kvm_set_pte(ptep, pte) set_pte(ptep, pte)
163 #define kvm_set_pmd(pmdp, pmd) set_pmd(pmdp, pmd)
165 static inline void kvm_clean_pgd(pgd_t
*pgd
) {}
166 static inline void kvm_clean_pmd(pmd_t
*pmd
) {}
167 static inline void kvm_clean_pmd_entry(pmd_t
*pmd
) {}
168 static inline void kvm_clean_pte(pte_t
*pte
) {}
169 static inline void kvm_clean_pte_entry(pte_t
*pte
) {}
171 static inline pte_t
kvm_s2pte_mkwrite(pte_t pte
)
173 pte_val(pte
) |= PTE_S2_RDWR
;
177 static inline pmd_t
kvm_s2pmd_mkwrite(pmd_t pmd
)
179 pmd_val(pmd
) |= PMD_S2_RDWR
;
183 static inline void kvm_set_s2pte_readonly(pte_t
*pte
)
188 asm volatile("// kvm_set_s2pte_readonly\n"
189 " prfm pstl1strm, %2\n"
191 " and %0, %0, %3 // clear PTE_S2_RDWR\n"
192 " orr %0, %0, %4 // set PTE_S2_RDONLY\n"
193 " stxr %w1, %0, %2\n"
195 : "=&r" (pteval
), "=&r" (tmp
), "+Q" (pte_val(*pte
))
196 : "L" (~PTE_S2_RDWR
), "L" (PTE_S2_RDONLY
));
199 static inline bool kvm_s2pte_readonly(pte_t
*pte
)
201 return (pte_val(*pte
) & PTE_S2_RDWR
) == PTE_S2_RDONLY
;
204 static inline void kvm_set_s2pmd_readonly(pmd_t
*pmd
)
206 kvm_set_s2pte_readonly((pte_t
*)pmd
);
209 static inline bool kvm_s2pmd_readonly(pmd_t
*pmd
)
211 return kvm_s2pte_readonly((pte_t
*)pmd
);
214 static inline bool kvm_page_empty(void *ptr
)
216 struct page
*ptr_page
= virt_to_page(ptr
);
217 return page_count(ptr_page
) == 1;
220 #define hyp_pte_table_empty(ptep) kvm_page_empty(ptep)
222 #ifdef __PAGETABLE_PMD_FOLDED
223 #define hyp_pmd_table_empty(pmdp) (0)
225 #define hyp_pmd_table_empty(pmdp) kvm_page_empty(pmdp)
228 #ifdef __PAGETABLE_PUD_FOLDED
229 #define hyp_pud_table_empty(pudp) (0)
231 #define hyp_pud_table_empty(pudp) kvm_page_empty(pudp)
236 #define kvm_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
238 static inline bool vcpu_has_cache_enabled(struct kvm_vcpu
*vcpu
)
240 return (vcpu_sys_reg(vcpu
, SCTLR_EL1
) & 0b101) == 0b101;
243 static inline void __coherent_cache_guest_page(struct kvm_vcpu
*vcpu
,
248 void *va
= page_address(pfn_to_page(pfn
));
250 if (!vcpu_has_cache_enabled(vcpu
) || ipa_uncached
)
251 kvm_flush_dcache_to_poc(va
, size
);
253 if (!icache_is_aliasing()) { /* PIPT */
254 flush_icache_range((unsigned long)va
,
255 (unsigned long)va
+ size
);
256 } else if (!icache_is_aivivt()) { /* non ASID-tagged VIVT */
257 /* any kind of VIPT cache */
258 __flush_icache_all();
262 static inline void __kvm_flush_dcache_pte(pte_t pte
)
264 struct page
*page
= pte_page(pte
);
265 kvm_flush_dcache_to_poc(page_address(page
), PAGE_SIZE
);
268 static inline void __kvm_flush_dcache_pmd(pmd_t pmd
)
270 struct page
*page
= pmd_page(pmd
);
271 kvm_flush_dcache_to_poc(page_address(page
), PMD_SIZE
);
274 static inline void __kvm_flush_dcache_pud(pud_t pud
)
276 struct page
*page
= pud_page(pud
);
277 kvm_flush_dcache_to_poc(page_address(page
), PUD_SIZE
);
280 #define kvm_virt_to_phys(x) __virt_to_phys((unsigned long)(x))
282 void kvm_set_way_flush(struct kvm_vcpu
*vcpu
);
283 void kvm_toggle_cache(struct kvm_vcpu
*vcpu
, bool was_enabled
);
285 static inline bool __kvm_cpu_uses_extended_idmap(void)
287 return __cpu_uses_extended_idmap();
290 static inline void __kvm_extend_hypmap(pgd_t
*boot_hyp_pgd
,
292 pgd_t
*merged_hyp_pgd
,
293 unsigned long hyp_idmap_start
)
298 * Use the first entry to access the HYP mappings. It is
299 * guaranteed to be free, otherwise we wouldn't use an
302 VM_BUG_ON(pgd_val(merged_hyp_pgd
[0]));
303 merged_hyp_pgd
[0] = __pgd(__pa(hyp_pgd
) | PMD_TYPE_TABLE
);
306 * Create another extended level entry that points to the boot HYP map,
307 * which contains an ID mapping of the HYP init code. We essentially
308 * merge the boot and runtime HYP maps by doing so, but they don't
309 * overlap anyway, so this is fine.
311 idmap_idx
= hyp_idmap_start
>> VA_BITS
;
312 VM_BUG_ON(pgd_val(merged_hyp_pgd
[idmap_idx
]));
313 merged_hyp_pgd
[idmap_idx
] = __pgd(__pa(boot_hyp_pgd
) | PMD_TYPE_TABLE
);
316 static inline unsigned int kvm_get_vmid_bits(void)
318 int reg
= read_system_reg(SYS_ID_AA64MMFR1_EL1
);
320 return (cpuid_feature_extract_unsigned_field(reg
, ID_AA64MMFR1_VMIDBITS_SHIFT
) == 2) ? 16 : 8;
323 #endif /* __ASSEMBLY__ */
324 #endif /* __ARM64_KVM_MMU_H__ */