arch/blackfin/Kconfig

   1 #
   2 # For a description of the syntax of this configuration file,
   3 # see Documentation/kbuild/kconfig-language.txt.
   4 #
   5
   6 mainmenu "Blackfin Kernel Configuration"
   7
   8 config MMU
   9         def_bool n
  10
  11 config FPU
  12         def_bool n
  13
  14 config RWSEM_GENERIC_SPINLOCK
  15         def_bool y
  16
  17 config RWSEM_XCHGADD_ALGORITHM
  18         def_bool n
  19
  20 config BLACKFIN
  21         def_bool y
  22         select HAVE_FUNCTION_GRAPH_TRACER
  23         select HAVE_FUNCTION_TRACER
  24         select HAVE_IDE
  25         select HAVE_KERNEL_GZIP
  26         select HAVE_KERNEL_BZIP2
  27         select HAVE_KERNEL_LZMA
  28         select HAVE_OPROFILE
  29         select ARCH_WANT_OPTIONAL_GPIOLIB
  30
  31 config GENERIC_BUG
  32         def_bool y
  33         depends on BUG
  34
  35 config ZONE_DMA
  36         def_bool y
  37
  38 config GENERIC_FIND_NEXT_BIT
  39         def_bool y
  40
  41 config GENERIC_HWEIGHT
  42         def_bool y
  43
  44 config GENERIC_HARDIRQS
  45         def_bool y
  46
  47 config GENERIC_IRQ_PROBE
  48         def_bool y
  49
  50 config GENERIC_GPIO
  51         def_bool y
  52
  53 config FORCE_MAX_ZONEORDER
  54         int
  55         default "14"
  56
  57 config GENERIC_CALIBRATE_DELAY
  58         def_bool y
  59
  60 config LOCKDEP_SUPPORT
  61         def_bool y
  62
  63 config STACKTRACE_SUPPORT
  64         def_bool y
  65
  66 config TRACE_IRQFLAGS_SUPPORT
  67         def_bool y
  68
  69 source "init/Kconfig"
  70
  71 source "kernel/Kconfig.preempt"
  72
  73 source "kernel/Kconfig.freezer"
  74
  75 menu "Blackfin Processor Options"
  76
  77 comment "Processor and Board Settings"
  78
  79 choice
  80         prompt "CPU"
  81         default BF533
  82
  83 config BF512
  84         bool "BF512"
  85         help
  86           BF512 Processor Support.
  87
  88 config BF514
  89         bool "BF514"
  90         help
  91           BF514 Processor Support.
  92
  93 config BF516
  94         bool "BF516"
  95         help
  96           BF516 Processor Support.
  97
  98 config BF518
  99         bool "BF518"
 100         help
 101           BF518 Processor Support.
 102
 103 config BF522
 104         bool "BF522"
 105         help
 106           BF522 Processor Support.
 107
 108 config BF523
 109         bool "BF523"
 110         help
 111           BF523 Processor Support.
 112
 113 config BF524
 114         bool "BF524"
 115         help
 116           BF524 Processor Support.
 117
 118 config BF525
 119         bool "BF525"
 120         help
 121           BF525 Processor Support.
 122
 123 config BF526
 124         bool "BF526"
 125         help
 126           BF526 Processor Support.
 127
 128 config BF527
 129         bool "BF527"
 130         help
 131           BF527 Processor Support.
 132
 133 config BF531
 134         bool "BF531"
 135         help
 136           BF531 Processor Support.
 137
 138 config BF532
 139         bool "BF532"
 140         help
 141           BF532 Processor Support.
 142
 143 config BF533
 144         bool "BF533"
 145         help
 146           BF533 Processor Support.
 147
 148 config BF534
 149         bool "BF534"
 150         help
 151           BF534 Processor Support.
 152
 153 config BF536
 154         bool "BF536"
 155         help
 156           BF536 Processor Support.
 157
 158 config BF537
 159         bool "BF537"
 160         help
 161           BF537 Processor Support.
 162
 163 config BF538
 164         bool "BF538"
 165         help
 166           BF538 Processor Support.
 167
 168 config BF539
 169         bool "BF539"
 170         help
 171           BF539 Processor Support.
 172
 173 config BF542
 174         bool "BF542"
 175         help
 176           BF542 Processor Support.
 177
 178 config BF542M
 179         bool "BF542m"
 180         help
 181           BF542 Processor Support.
 182
 183 config BF544
 184         bool "BF544"
 185         help
 186           BF544 Processor Support.
 187
 188 config BF544M
 189         bool "BF544m"
 190         help
 191           BF544 Processor Support.
 192
 193 config BF547
 194         bool "BF547"
 195         help
 196           BF547 Processor Support.
 197
 198 config BF547M
 199         bool "BF547m"
 200         help
 201           BF547 Processor Support.
 202
 203 config BF548
 204         bool "BF548"
 205         help
 206           BF548 Processor Support.
 207
 208 config BF548M
 209         bool "BF548m"
 210         help
 211           BF548 Processor Support.
 212
 213 config BF549
 214         bool "BF549"
 215         help
 216           BF549 Processor Support.
 217
 218 config BF549M
 219         bool "BF549m"
 220         help
 221           BF549 Processor Support.
 222
 223 config BF561
 224         bool "BF561"
 225         help
 226           BF561 Processor Support.
 227
 228 endchoice
 229
 230 config SMP
 231         depends on BF561
 232         select GENERIC_TIME
 233         bool "Symmetric multi-processing support"
 234         ---help---
 235           This enables support for systems with more than one CPU,
 236           like the dual core BF561. If you have a system with only one
 237           CPU, say N. If you have a system with more than one CPU, say Y.
 238
 239           If you don't know what to do here, say N.
 240
 241 config NR_CPUS
 242         int
 243         depends on SMP
 244         default 2 if BF561
 245
 246 config IRQ_PER_CPU
 247         bool
 248         depends on SMP
 249         default y
 250
 251 config BF_REV_MIN
 252         int
 253         default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
 254         default 2 if (BF537 || BF536 || BF534)
 255         default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
 256         default 4 if (BF538 || BF539)
 257
 258 config BF_REV_MAX
 259         int
 260         default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
 261         default 3 if (BF537 || BF536 || BF534 || BF54xM)
 262         default 5 if (BF561 || BF538 || BF539)
 263         default 6 if (BF533 || BF532 || BF531)
 264
 265 choice
 266         prompt "Silicon Rev"
 267         default BF_REV_0_0 if (BF51x || BF52x)
 268         default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
 269         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
 270
 271 config BF_REV_0_0
 272         bool "0.0"
 273         depends on (BF51x || BF52x || (BF54x && !BF54xM))
 274
 275 config BF_REV_0_1
 276         bool "0.1"
 277         depends on (BF51x || BF52x || (BF54x && !BF54xM))
 278
 279 config BF_REV_0_2
 280         bool "0.2"
 281         depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
 282
 283 config BF_REV_0_3
 284         bool "0.3"
 285         depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 286
 287 config BF_REV_0_4
 288         bool "0.4"
 289         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 290
 291 config BF_REV_0_5
 292         bool "0.5"
 293         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 294
 295 config BF_REV_0_6
 296         bool "0.6"
 297         depends on (BF533 || BF532 || BF531)
 298
 299 config BF_REV_ANY
 300         bool "any"
 301
 302 config BF_REV_NONE
 303         bool "none"
 304
 305 endchoice
 306
 307 config BF51x
 308         bool
 309         depends on (BF512 || BF514 || BF516 || BF518)
 310         default y
 311
 312 config BF52x
 313         bool
 314         depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
 315         default y
 316
 317 config BF53x
 318         bool
 319         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 320         default y
 321
 322 config BF54xM
 323         bool
 324         depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
 325         default y
 326
 327 config BF54x
 328         bool
 329         depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
 330         default y
 331
 332 config MEM_GENERIC_BOARD
 333         bool
 334         depends on GENERIC_BOARD
 335         default y
 336
 337 config MEM_MT48LC64M4A2FB_7E
 338         bool
 339         depends on (BFIN533_STAMP)
 340         default y
 341
 342 config MEM_MT48LC16M16A2TG_75
 343         bool
 344         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 345                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
 346                 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
 347         default y
 348
 349 config MEM_MT48LC32M8A2_75
 350         bool
 351         depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 352         default y
 353
 354 config MEM_MT48LC8M32B2B5_7
 355         bool
 356         depends on (BFIN561_BLUETECHNIX_CM)
 357         default y
 358
 359 config MEM_MT48LC32M16A2TG_75
 360         bool
 361         depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP)
 362         default y
 363
 364 config MEM_MT48LC32M8A2_75
 365         bool
 366         depends on (BFIN518F_EZBRD)
 367         default y
 368
 369 config MEM_MT48H32M16LFCJ_75
 370         bool
 371         depends on (BFIN526_EZBRD)
 372         default y
 373
 374 source "arch/blackfin/mach-bf518/Kconfig"
 375 source "arch/blackfin/mach-bf527/Kconfig"
 376 source "arch/blackfin/mach-bf533/Kconfig"
 377 source "arch/blackfin/mach-bf561/Kconfig"
 378 source "arch/blackfin/mach-bf537/Kconfig"
 379 source "arch/blackfin/mach-bf538/Kconfig"
 380 source "arch/blackfin/mach-bf548/Kconfig"
 381
 382 menu "Board customizations"
 383
 384 config CMDLINE_BOOL
 385         bool "Default bootloader kernel arguments"
 386
 387 config CMDLINE
 388         string "Initial kernel command string"
 389         depends on CMDLINE_BOOL
 390         default "console=ttyBF0,57600"
 391         help
 392           If you don't have a boot loader capable of passing a command line string
 393           to the kernel, you may specify one here. As a minimum, you should specify
 394           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 395
 396 config BOOT_LOAD
 397         hex "Kernel load address for booting"
 398         default "0x1000"
 399         range 0x1000 0x20000000
 400         help
 401           This option allows you to set the load address of the kernel.
 402           This can be useful if you are on a board which has a small amount
 403           of memory or you wish to reserve some memory at the beginning of
 404           the address space.
 405
 406           Note that you need to keep this value above 4k (0x1000) as this
 407           memory region is used to capture NULL pointer references as well
 408           as some core kernel functions.
 409
 410 config ROM_BASE
 411         hex "Kernel ROM Base"
 412         depends on ROMKERNEL
 413         default "0x20040000"
 414         range 0x20000000 0x20400000 if !(BF54x || BF561)
 415         range 0x20000000 0x30000000 if (BF54x || BF561)
 416         help
 417
 418 comment "Clock/PLL Setup"
 419
 420 config CLKIN_HZ
 421         int "Frequency of the crystal on the board in Hz"
 422         default "10000000" if BFIN532_IP0X
 423         default "11059200" if BFIN533_STAMP
 424         default "24576000" if PNAV10
 425         default "25000000" # most people use this
 426         default "27000000" if BFIN533_EZKIT
 427         default "30000000" if BFIN561_EZKIT
 428         help
 429           The frequency of CLKIN crystal oscillator on the board in Hz.
 430           Warning: This value should match the crystal on the board. Otherwise,
 431           peripherals won't work properly.
 432
 433 config BFIN_KERNEL_CLOCK
 434         bool "Re-program Clocks while Kernel boots?"
 435         default n
 436         help
 437           This option decides if kernel clocks are re-programed from the
 438           bootloader settings. If the clocks are not set, the SDRAM settings
 439           are also not changed, and the Bootloader does 100% of the hardware
 440           configuration.
 441
 442 config PLL_BYPASS
 443         bool "Bypass PLL"
 444         depends on BFIN_KERNEL_CLOCK
 445         default n
 446
 447 config CLKIN_HALF
 448         bool "Half Clock In"
 449         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 450         default n
 451         help
 452           If this is set the clock will be divided by 2, before it goes to the PLL.
 453
 454 config VCO_MULT
 455         int "VCO Multiplier"
 456         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 457         range 1 64
 458         default "22" if BFIN533_EZKIT
 459         default "45" if BFIN533_STAMP
 460         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 461         default "22" if BFIN533_BLUETECHNIX_CM
 462         default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 463         default "20" if BFIN561_EZKIT
 464         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 465         help
 466           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 467           PLL Frequency = (Crystal Frequency) * (this setting)
 468
 469 choice
 470         prompt "Core Clock Divider"
 471         depends on BFIN_KERNEL_CLOCK
 472         default CCLK_DIV_1
 473         help
 474           This sets the frequency of the core. It can be 1, 2, 4 or 8
 475           Core Frequency = (PLL frequency) / (this setting)
 476
 477 config CCLK_DIV_1
 478         bool "1"
 479
 480 config CCLK_DIV_2
 481         bool "2"
 482
 483 config CCLK_DIV_4
 484         bool "4"
 485
 486 config CCLK_DIV_8
 487         bool "8"
 488 endchoice
 489
 490 config SCLK_DIV
 491         int "System Clock Divider"
 492         depends on BFIN_KERNEL_CLOCK
 493         range 1 15
 494         default 5
 495         help
 496           This sets the frequency of the system clock (including SDRAM or DDR).
 497           This can be between 1 and 15
 498           System Clock = (PLL frequency) / (this setting)
 499
 500 choice
 501         prompt "DDR SDRAM Chip Type"
 502         depends on BFIN_KERNEL_CLOCK
 503         depends on BF54x
 504         default MEM_MT46V32M16_5B
 505
 506 config MEM_MT46V32M16_6T
 507         bool "MT46V32M16_6T"
 508
 509 config MEM_MT46V32M16_5B
 510         bool "MT46V32M16_5B"
 511 endchoice
 512
 513 choice
 514         prompt "DDR/SDRAM Timing"
 515         depends on BFIN_KERNEL_CLOCK
 516         default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 517         help
 518           This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 519           The calculated SDRAM timing parameters may not be 100%
 520           accurate - This option is therefore marked experimental.
 521
 522 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 523         bool "Calculate Timings (EXPERIMENTAL)"
 524         depends on EXPERIMENTAL
 525
 526 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 527         bool "Provide accurate Timings based on target SCLK"
 528         help
 529           Please consult the Blackfin Hardware Reference Manuals as well
 530           as the memory device datasheet.
 531           http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 532 endchoice
 533
 534 menu "Memory Init Control"
 535         depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 536
 537 config MEM_DDRCTL0
 538         depends on BF54x
 539         hex "DDRCTL0"
 540         default 0x0
 541
 542 config MEM_DDRCTL1
 543         depends on BF54x
 544         hex "DDRCTL1"
 545         default 0x0
 546
 547 config MEM_DDRCTL2
 548         depends on BF54x
 549         hex "DDRCTL2"
 550         default 0x0
 551
 552 config MEM_EBIU_DDRQUE
 553         depends on BF54x
 554         hex "DDRQUE"
 555         default 0x0
 556
 557 config MEM_SDRRC
 558         depends on !BF54x
 559         hex "SDRRC"
 560         default 0x0
 561
 562 config MEM_SDGCTL
 563         depends on !BF54x
 564         hex "SDGCTL"
 565         default 0x0
 566 endmenu
 567
 568 #
 569 # Max & Min Speeds for various Chips
 570 #
 571 config MAX_VCO_HZ
 572         int
 573         default 400000000 if BF512
 574         default 400000000 if BF514
 575         default 400000000 if BF516
 576         default 400000000 if BF518
 577         default 600000000 if BF522
 578         default 400000000 if BF523
 579         default 400000000 if BF524
 580         default 600000000 if BF525
 581         default 400000000 if BF526
 582         default 600000000 if BF527
 583         default 400000000 if BF531
 584         default 400000000 if BF532
 585         default 750000000 if BF533
 586         default 500000000 if BF534
 587         default 400000000 if BF536
 588         default 600000000 if BF537
 589         default 533333333 if BF538
 590         default 533333333 if BF539
 591         default 600000000 if BF542
 592         default 533333333 if BF544
 593         default 600000000 if BF547
 594         default 600000000 if BF548
 595         default 533333333 if BF549
 596         default 600000000 if BF561
 597
 598 config MIN_VCO_HZ
 599         int
 600         default 50000000
 601
 602 config MAX_SCLK_HZ
 603         int
 604         default 133333333
 605
 606 config MIN_SCLK_HZ
 607         int
 608         default 27000000
 609
 610 comment "Kernel Timer/Scheduler"
 611
 612 source kernel/Kconfig.hz
 613
 614 config GENERIC_TIME
 615         bool "Generic time"
 616         default y
 617
 618 config GENERIC_CLOCKEVENTS
 619         bool "Generic clock events"
 620         depends on GENERIC_TIME
 621         default y
 622
 623 choice
 624         prompt "Kernel Tick Source"
 625         depends on GENERIC_CLOCKEVENTS
 626         default TICKSOURCE_CORETMR
 627
 628 config TICKSOURCE_GPTMR0
 629         bool "Gptimer0 (SCLK domain)"
 630         select BFIN_GPTIMERS
 631
 632 config TICKSOURCE_CORETMR
 633         bool "Core timer (CCLK domain)"
 634
 635 endchoice
 636
 637 config CYCLES_CLOCKSOURCE
 638         bool "Use 'CYCLES' as a clocksource"
 639         depends on GENERIC_CLOCKEVENTS
 640         depends on !BFIN_SCRATCH_REG_CYCLES
 641         depends on !SMP
 642         help
 643           If you say Y here, you will enable support for using the 'cycles'
 644           registers as a clock source.  Doing so means you will be unable to
 645           safely write to the 'cycles' register during runtime.  You will
 646           still be able to read it (such as for performance monitoring), but
 647           writing the registers will most likely crash the kernel.
 648
 649 config GPTMR0_CLOCKSOURCE
 650         bool "Use GPTimer0 as a clocksource (higher rating)"
 651         select BFIN_GPTIMERS
 652         depends on GENERIC_CLOCKEVENTS
 653         depends on !TICKSOURCE_GPTMR0
 654
 655 source kernel/time/Kconfig
 656
 657 comment "Misc"
 658
 659 choice
 660         prompt "Blackfin Exception Scratch Register"
 661         default BFIN_SCRATCH_REG_RETN
 662         help
 663           Select the resource to reserve for the Exception handler:
 664             - RETN: Non-Maskable Interrupt (NMI)
 665             - RETE: Exception Return (JTAG/ICE)
 666             - CYCLES: Performance counter
 667
 668           If you are unsure, please select "RETN".
 669
 670 config BFIN_SCRATCH_REG_RETN
 671         bool "RETN"
 672         help
 673           Use the RETN register in the Blackfin exception handler
 674           as a stack scratch register.  This means you cannot
 675           safely use NMI on the Blackfin while running Linux, but
 676           you can debug the system with a JTAG ICE and use the
 677           CYCLES performance registers.
 678
 679           If you are unsure, please select "RETN".
 680
 681 config BFIN_SCRATCH_REG_RETE
 682         bool "RETE"
 683         help
 684           Use the RETE register in the Blackfin exception handler
 685           as a stack scratch register.  This means you cannot
 686           safely use a JTAG ICE while debugging a Blackfin board,
 687           but you can safely use the CYCLES performance registers
 688           and the NMI.
 689
 690           If you are unsure, please select "RETN".
 691
 692 config BFIN_SCRATCH_REG_CYCLES
 693         bool "CYCLES"
 694         help
 695           Use the CYCLES register in the Blackfin exception handler
 696           as a stack scratch register.  This means you cannot
 697           safely use the CYCLES performance registers on a Blackfin
 698           board at anytime, but you can debug the system with a JTAG
 699           ICE and use the NMI.
 700
 701           If you are unsure, please select "RETN".
 702
 703 endchoice
 704
 705 endmenu
 706
 707
 708 menu "Blackfin Kernel Optimizations"
 709         depends on !SMP
 710
 711 comment "Memory Optimizations"
 712
 713 config I_ENTRY_L1
 714         bool "Locate interrupt entry code in L1 Memory"
 715         default y
 716         help
 717           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 718           into L1 instruction memory. (less latency)
 719
 720 config EXCPT_IRQ_SYSC_L1
 721         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 722         default y
 723         help
 724           If enabled, the entire ASM lowlevel exception and interrupt entry code
 725           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 726           (less latency)
 727
 728 config DO_IRQ_L1
 729         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 730         default y
 731         help
 732           If enabled, the frequently called do_irq dispatcher function is linked
 733           into L1 instruction memory. (less latency)
 734
 735 config CORE_TIMER_IRQ_L1
 736         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 737         default y
 738         help
 739           If enabled, the frequently called timer_interrupt() function is linked
 740           into L1 instruction memory. (less latency)
 741
 742 config IDLE_L1
 743         bool "Locate frequently idle function in L1 Memory"
 744         default y
 745         help
 746           If enabled, the frequently called idle function is linked
 747           into L1 instruction memory. (less latency)
 748
 749 config SCHEDULE_L1
 750         bool "Locate kernel schedule function in L1 Memory"
 751         default y
 752         help
 753           If enabled, the frequently called kernel schedule is linked
 754           into L1 instruction memory. (less latency)
 755
 756 config ARITHMETIC_OPS_L1
 757         bool "Locate kernel owned arithmetic functions in L1 Memory"
 758         default y
 759         help
 760           If enabled, arithmetic functions are linked
 761           into L1 instruction memory. (less latency)
 762
 763 config ACCESS_OK_L1
 764         bool "Locate access_ok function in L1 Memory"
 765         default y
 766         help
 767           If enabled, the access_ok function is linked
 768           into L1 instruction memory. (less latency)
 769
 770 config MEMSET_L1
 771         bool "Locate memset function in L1 Memory"
 772         default y
 773         help
 774           If enabled, the memset function is linked
 775           into L1 instruction memory. (less latency)
 776
 777 config MEMCPY_L1
 778         bool "Locate memcpy function in L1 Memory"
 779         default y
 780         help
 781           If enabled, the memcpy function is linked
 782           into L1 instruction memory. (less latency)
 783
 784 config SYS_BFIN_SPINLOCK_L1
 785         bool "Locate sys_bfin_spinlock function in L1 Memory"
 786         default y
 787         help
 788           If enabled, sys_bfin_spinlock function is linked
 789           into L1 instruction memory. (less latency)
 790
 791 config IP_CHECKSUM_L1
 792         bool "Locate IP Checksum function in L1 Memory"
 793         default n
 794         help
 795           If enabled, the IP Checksum function is linked
 796           into L1 instruction memory. (less latency)
 797
 798 config CACHELINE_ALIGNED_L1
 799         bool "Locate cacheline_aligned data to L1 Data Memory"
 800         default y if !BF54x
 801         default n if BF54x
 802         depends on !BF531
 803         help
 804           If enabled, cacheline_aligned data is linked
 805           into L1 data memory. (less latency)
 806
 807 config SYSCALL_TAB_L1
 808         bool "Locate Syscall Table L1 Data Memory"
 809         default n
 810         depends on !BF531
 811         help
 812           If enabled, the Syscall LUT is linked
 813           into L1 data memory. (less latency)
 814
 815 config CPLB_SWITCH_TAB_L1
 816         bool "Locate CPLB Switch Tables L1 Data Memory"
 817         default n
 818         depends on !BF531
 819         help
 820           If enabled, the CPLB Switch Tables are linked
 821           into L1 data memory. (less latency)
 822
 823 config APP_STACK_L1
 824         bool "Support locating application stack in L1 Scratch Memory"
 825         default y
 826         help
 827           If enabled the application stack can be located in L1
 828           scratch memory (less latency).
 829
 830           Currently only works with FLAT binaries.
 831
 832 config EXCEPTION_L1_SCRATCH
 833         bool "Locate exception stack in L1 Scratch Memory"
 834         default n
 835         depends on !APP_STACK_L1
 836         help
 837           Whenever an exception occurs, use the L1 Scratch memory for
 838           stack storage.  You cannot place the stacks of FLAT binaries
 839           in L1 when using this option.
 840
 841           If you don't use L1 Scratch, then you should say Y here.
 842
 843 comment "Speed Optimizations"
 844 config BFIN_INS_LOWOVERHEAD
 845         bool "ins[bwl] low overhead, higher interrupt latency"
 846         default y
 847         help
 848           Reads on the Blackfin are speculative. In Blackfin terms, this means
 849           they can be interrupted at any time (even after they have been issued
 850           on to the external bus), and re-issued after the interrupt occurs.
 851           For memory - this is not a big deal, since memory does not change if
 852           it sees a read.
 853
 854           If a FIFO is sitting on the end of the read, it will see two reads,
 855           when the core only sees one since the FIFO receives both the read
 856           which is cancelled (and not delivered to the core) and the one which
 857           is re-issued (which is delivered to the core).
 858
 859           To solve this, interrupts are turned off before reads occur to
 860           I/O space. This option controls which the overhead/latency of
 861           controlling interrupts during this time
 862            "n" turns interrupts off every read
 863                 (higher overhead, but lower interrupt latency)
 864            "y" turns interrupts off every loop
 865                 (low overhead, but longer interrupt latency)
 866
 867           default behavior is to leave this set to on (type "Y"). If you are experiencing
 868           interrupt latency issues, it is safe and OK to turn this off.
 869
 870 endmenu
 871
 872 choice
 873         prompt "Kernel executes from"
 874         help
 875           Choose the memory type that the kernel will be running in.
 876
 877 config RAMKERNEL
 878         bool "RAM"
 879         help
 880           The kernel will be resident in RAM when running.
 881
 882 config ROMKERNEL
 883         bool "ROM"
 884         help
 885           The kernel will be resident in FLASH/ROM when running.
 886
 887 endchoice
 888
 889 source "mm/Kconfig"
 890
 891 config BFIN_GPTIMERS
 892         tristate "Enable Blackfin General Purpose Timers API"
 893         default n
 894         help
 895           Enable support for the General Purpose Timers API.  If you
 896           are unsure, say N.
 897
 898           To compile this driver as a module, choose M here: the module
 899           will be called gptimers.
 900
 901 choice
 902         prompt "Uncached DMA region"
 903         default DMA_UNCACHED_1M
 904 config DMA_UNCACHED_4M
 905         bool "Enable 4M DMA region"
 906 config DMA_UNCACHED_2M
 907         bool "Enable 2M DMA region"
 908 config DMA_UNCACHED_1M
 909         bool "Enable 1M DMA region"
 910 config DMA_UNCACHED_NONE
 911         bool "Disable DMA region"
 912 endchoice
 913
 914
 915 comment "Cache Support"
 916
 917 config BFIN_ICACHE
 918         bool "Enable ICACHE"
 919         default y
 920 config BFIN_ICACHE_LOCK
 921         bool "Enable Instruction Cache Locking"
 922         depends on BFIN_ICACHE
 923         default n
 924 config BFIN_EXTMEM_ICACHEABLE
 925         bool "Enable ICACHE for external memory"
 926         depends on BFIN_ICACHE
 927         default y
 928 config BFIN_L2_ICACHEABLE
 929         bool "Enable ICACHE for L2 SRAM"
 930         depends on BFIN_ICACHE
 931         depends on BF54x || BF561
 932         default n
 933
 934 config BFIN_DCACHE
 935         bool "Enable DCACHE"
 936         default y
 937 config BFIN_DCACHE_BANKA
 938         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
 939         depends on BFIN_DCACHE && !BF531
 940         default n
 941 config BFIN_EXTMEM_DCACHEABLE
 942         bool "Enable DCACHE for external memory"
 943         depends on BFIN_DCACHE
 944         default y
 945 choice
 946         prompt "External memory DCACHE policy"
 947         depends on BFIN_EXTMEM_DCACHEABLE
 948         default BFIN_EXTMEM_WRITEBACK if !SMP
 949         default BFIN_EXTMEM_WRITETHROUGH if SMP
 950 config BFIN_EXTMEM_WRITEBACK
 951         bool "Write back"
 952         depends on !SMP
 953         help
 954           Write Back Policy:
 955             Cached data will be written back to SDRAM only when needed.
 956             This can give a nice increase in performance, but beware of
 957             broken drivers that do not properly invalidate/flush their
 958             cache.
 959
 960           Write Through Policy:
 961             Cached data will always be written back to SDRAM when the
 962             cache is updated.  This is a completely safe setting, but
 963             performance is worse than Write Back.
 964
 965           If you are unsure of the options and you want to be safe,
 966           then go with Write Through.
 967
 968 config BFIN_EXTMEM_WRITETHROUGH
 969         bool "Write through"
 970         help
 971           Write Back Policy:
 972             Cached data will be written back to SDRAM only when needed.
 973             This can give a nice increase in performance, but beware of
 974             broken drivers that do not properly invalidate/flush their
 975             cache.
 976
 977           Write Through Policy:
 978             Cached data will always be written back to SDRAM when the
 979             cache is updated.  This is a completely safe setting, but
 980             performance is worse than Write Back.
 981
 982           If you are unsure of the options and you want to be safe,
 983           then go with Write Through.
 984
 985 endchoice
 986
 987 config BFIN_L2_DCACHEABLE
 988         bool "Enable DCACHE for L2 SRAM"
 989         depends on BFIN_DCACHE
 990         depends on (BF54x || BF561) && !SMP
 991         default n
 992 choice
 993         prompt "L2 SRAM DCACHE policy"
 994         depends on BFIN_L2_DCACHEABLE
 995         default BFIN_L2_WRITEBACK
 996 config BFIN_L2_WRITEBACK
 997         bool "Write back"
 998
 999 config BFIN_L2_WRITETHROUGH
1000         bool "Write through"
1001 endchoice
1002
1003
1004 comment "Memory Protection Unit"
1005 config MPU
1006         bool "Enable the memory protection unit (EXPERIMENTAL)"
1007         default n
1008         help
1009           Use the processor's MPU to protect applications from accessing
1010           memory they do not own.  This comes at a performance penalty
1011           and is recommended only for debugging.
1012
1013 comment "Asynchronous Memory Configuration"
1014
1015 menu "EBIU_AMGCTL Global Control"
1016 config C_AMCKEN
1017         bool "Enable CLKOUT"
1018         default y
1019
1020 config C_CDPRIO
1021         bool "DMA has priority over core for ext. accesses"
1022         default n
1023
1024 config C_B0PEN
1025         depends on BF561
1026         bool "Bank 0 16 bit packing enable"
1027         default y
1028
1029 config C_B1PEN
1030         depends on BF561
1031         bool "Bank 1 16 bit packing enable"
1032         default y
1033
1034 config C_B2PEN
1035         depends on BF561
1036         bool "Bank 2 16 bit packing enable"
1037         default y
1038
1039 config C_B3PEN
1040         depends on BF561
1041         bool "Bank 3 16 bit packing enable"
1042         default n
1043
1044 choice
1045         prompt "Enable Asynchronous Memory Banks"
1046         default C_AMBEN_ALL
1047
1048 config C_AMBEN
1049         bool "Disable All Banks"
1050
1051 config C_AMBEN_B0
1052         bool "Enable Bank 0"
1053
1054 config C_AMBEN_B0_B1
1055         bool "Enable Bank 0 & 1"
1056
1057 config C_AMBEN_B0_B1_B2
1058         bool "Enable Bank 0 & 1 & 2"
1059
1060 config C_AMBEN_ALL
1061         bool "Enable All Banks"
1062 endchoice
1063 endmenu
1064
1065 menu "EBIU_AMBCTL Control"
1066 config BANK_0
1067         hex "Bank 0 (AMBCTL0.L)"
1068         default 0x7BB0
1069         help
1070           These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1071           used to control the Asynchronous Memory Bank 0 settings.
1072
1073 config BANK_1
1074         hex "Bank 1 (AMBCTL0.H)"
1075         default 0x7BB0
1076         default 0x5558 if BF54x
1077         help
1078           These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1079           used to control the Asynchronous Memory Bank 1 settings.
1080
1081 config BANK_2
1082         hex "Bank 2 (AMBCTL1.L)"
1083         default 0x7BB0
1084         help
1085           These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1086           used to control the Asynchronous Memory Bank 2 settings.
1087
1088 config BANK_3
1089         hex "Bank 3 (AMBCTL1.H)"
1090         default 0x99B3
1091         help
1092           These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1093           used to control the Asynchronous Memory Bank 3 settings.
1094
1095 endmenu
1096
1097 config EBIU_MBSCTLVAL
1098         hex "EBIU Bank Select Control Register"
1099         depends on BF54x
1100         default 0
1101
1102 config EBIU_MODEVAL
1103         hex "Flash Memory Mode Control Register"
1104         depends on BF54x
1105         default 1
1106
1107 config EBIU_FCTLVAL
1108         hex "Flash Memory Bank Control Register"
1109         depends on BF54x
1110         default 6
1111 endmenu
1112
1113 #############################################################################
1114 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1115
1116 config PCI
1117         bool "PCI support"
1118         depends on BROKEN
1119         help
1120           Support for PCI bus.
1121
1122 source "drivers/pci/Kconfig"
1123
1124 config HOTPLUG
1125         bool "Support for hot-pluggable device"
1126           help
1127           Say Y here if you want to plug devices into your computer while
1128           the system is running, and be able to use them quickly.  In many
1129           cases, the devices can likewise be unplugged at any time too.
1130
1131           One well known example of this is PCMCIA- or PC-cards, credit-card
1132           size devices such as network cards, modems or hard drives which are
1133           plugged into slots found on all modern laptop computers.  Another
1134           example, used on modern desktops as well as laptops, is USB.
1135
1136           Enable HOTPLUG and build a modular kernel.  Get agent software
1137           (from <http://linux-hotplug.sourceforge.net/>) and install it.
1138           Then your kernel will automatically call out to a user mode "policy
1139           agent" (/sbin/hotplug) to load modules and set up software needed
1140           to use devices as you hotplug them.
1141
1142 source "drivers/pcmcia/Kconfig"
1143
1144 source "drivers/pci/hotplug/Kconfig"
1145
1146 endmenu
1147
1148 menu "Executable file formats"
1149
1150 source "fs/Kconfig.binfmt"
1151
1152 endmenu
1153
1154 menu "Power management options"
1155         depends on !SMP
1156
1157 source "kernel/power/Kconfig"
1158
1159 config ARCH_SUSPEND_POSSIBLE
1160         def_bool y
1161
1162 choice
1163         prompt "Standby Power Saving Mode"
1164         depends on PM
1165         default PM_BFIN_SLEEP_DEEPER
1166 config  PM_BFIN_SLEEP_DEEPER
1167         bool "Sleep Deeper"
1168         help
1169           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1170           power dissipation by disabling the clock to the processor core (CCLK).
1171           Furthermore, Standby sets the internal power supply voltage (VDDINT)
1172           to 0.85 V to provide the greatest power savings, while preserving the
1173           processor state.
1174           The PLL and system clock (SCLK) continue to operate at a very low
1175           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1176           the SDRAM is put into Self Refresh Mode. Typically an external event
1177           such as GPIO interrupt or RTC activity wakes up the processor.
1178           Various Peripherals such as UART, SPORT, PPI may not function as
1179           normal during Sleep Deeper, due to the reduced SCLK frequency.
1180           When in the sleep mode, system DMA access to L1 memory is not supported.
1181
1182           If unsure, select "Sleep Deeper".
1183
1184 config  PM_BFIN_SLEEP
1185         bool "Sleep"
1186         help
1187           Sleep Mode (High Power Savings) - The sleep mode reduces power
1188           dissipation by disabling the clock to the processor core (CCLK).
1189           The PLL and system clock (SCLK), however, continue to operate in
1190           this mode. Typically an external event or RTC activity will wake
1191           up the processor. When in the sleep mode, system DMA access to L1
1192           memory is not supported.
1193
1194           If unsure, select "Sleep Deeper".
1195 endchoice
1196
1197 config PM_WAKEUP_BY_GPIO
1198         bool "Allow Wakeup from Standby by GPIO"
1199         depends on PM && !BF54x
1200
1201 config PM_WAKEUP_GPIO_NUMBER
1202         int "GPIO number"
1203         range 0 47
1204         depends on PM_WAKEUP_BY_GPIO
1205         default 2
1206
1207 choice
1208         prompt "GPIO Polarity"
1209         depends on PM_WAKEUP_BY_GPIO
1210         default PM_WAKEUP_GPIO_POLAR_H
1211 config  PM_WAKEUP_GPIO_POLAR_H
1212         bool "Active High"
1213 config  PM_WAKEUP_GPIO_POLAR_L
1214         bool "Active Low"
1215 config  PM_WAKEUP_GPIO_POLAR_EDGE_F
1216         bool "Falling EDGE"
1217 config  PM_WAKEUP_GPIO_POLAR_EDGE_R
1218         bool "Rising EDGE"
1219 config  PM_WAKEUP_GPIO_POLAR_EDGE_B
1220         bool "Both EDGE"
1221 endchoice
1222
1223 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1224         depends on PM
1225
1226 config PM_BFIN_WAKE_PH6
1227         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1228         depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1229         default n
1230         help
1231           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1232
1233 config PM_BFIN_WAKE_GP
1234         bool "Allow Wake-Up from GPIOs"
1235         depends on PM && BF54x
1236         default n
1237         help
1238           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1239           (all processors, except ADSP-BF549). This option sets
1240           the general-purpose wake-up enable (GPWE) control bit to enable
1241           wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1242           On ADSP-BF549 this option enables the the same functionality on the
1243           /MRXON pin also PH7.
1244
1245 endmenu
1246
1247 menu "CPU Frequency scaling"
1248         depends on !SMP
1249
1250 source "drivers/cpufreq/Kconfig"
1251
1252 config BFIN_CPU_FREQ
1253         bool
1254         depends on CPU_FREQ
1255         select CPU_FREQ_TABLE
1256         default y
1257
1258 config CPU_VOLTAGE
1259         bool "CPU Voltage scaling"
1260         depends on EXPERIMENTAL
1261         depends on CPU_FREQ
1262         default n
1263         help
1264           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1265           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1266           manuals. There is a theoretical risk that during VDDINT transitions
1267           the PLL may unlock.
1268
1269 endmenu
1270
1271 source "net/Kconfig"
1272
1273 source "drivers/Kconfig"
1274
1275 source "fs/Kconfig"
1276
1277 source "arch/blackfin/Kconfig.debug"
1278
1279 source "security/Kconfig"
1280
1281 source "crypto/Kconfig"
1282
1283 source "lib/Kconfig"