2 * File: arch/blackfin/mach-bf548/head.S
3 * Based on: arch/blackfin/mach-bf537/head.S
4 * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
7 * Description: Startup code for Blackfin BF548
10 * Copyright 2004-2007 Analog Devices Inc.
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 #include <linux/linkage.h>
31 #include <asm/blackfin.h>
32 #include <asm/trace.h>
33 #if CONFIG_BFIN_KERNEL_CLOCK
34 #include <asm/mach-common/clocks.h>
35 #include <asm/mach/mem_init.h>
43 .extern _bf53x_relocate_l1_mem
45 #define INITIAL_STACK 0xFFB01000
51 /* R0: argument of command line string, passed from uboot, save it */
53 /* Set the SYSCFG register */
55 SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
58 /* Clear Out All the data and pointer Registers*/
80 /* Clear Out All the DAG Registers*/
96 trace_buffer_start(p0,r0);
100 /* Turn off the icache */
101 p0.l = LO(IMEM_CONTROL);
102 p0.h = HI(IMEM_CONTROL);
109 /* Turn off the dcache */
110 p0.l = LO(DMEM_CONTROL);
111 p0.h = HI(DMEM_CONTROL);
118 /* Initialize stack pointer */
119 SP.L = LO(INITIAL_STACK);
120 SP.H = HI(INITIAL_STACK);
124 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
125 call _bf53x_relocate_l1_mem;
126 #if CONFIG_BFIN_KERNEL_CLOCK
127 call _start_dma_code;
129 /* Code for initializing Async memory banks */
131 p2.h = hi(EBIU_AMBCTL1);
132 p2.l = lo(EBIU_AMBCTL1);
133 r0.h = hi(AMBCTL1VAL);
134 r0.l = lo(AMBCTL1VAL);
138 p2.h = hi(EBIU_AMBCTL0);
139 p2.l = lo(EBIU_AMBCTL0);
140 r0.h = hi(AMBCTL0VAL);
141 r0.l = lo(AMBCTL0VAL);
145 p2.h = hi(EBIU_AMGCTL);
146 p2.l = lo(EBIU_AMGCTL);
151 /* This section keeps the processor in supervisor mode
152 * during kernel boot. Switches to user mode at end of boot.
153 * See page 3-9 of Hardware Reference manual for documentation.
156 /* EVT15 = _real_start */
191 w[p0] = r0; /* watchdog off for now */
194 /* Code update for BSS size == 0
195 * Zero out the bss region.
204 lsetup (.L_clear_bss, .L_clear_bss ) lc0 = p2;
208 /* In case there is a NULL pointer reference
209 * Zero out region before stext
219 lsetup (.L_clear_zero, .L_clear_zero ) lc0 = p2;
223 /* pass the uboot arguments to the global value command line */
243 * load the current thread pointer and stack
245 r1.l = _init_thread_union;
246 r1.h = _init_thread_union;
259 #if CONFIG_BFIN_KERNEL_CLOCK
260 ENTRY(_start_dma_code)
262 /* Enable PHY CLK buffer output */
279 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
280 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
281 * - [7] = output delay (add 200ps of delay to mem signals)
282 * - [6] = input delay (add 200ps of input delay to mem signals)
283 * - [5] = PDWN : 1=All Clocks off
284 * - [3] = STOPCK : 1=Core Clock off
285 * - [1] = PLL_OFF : 1=Disable Power to PLL
286 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
287 * all other bits set to zero
290 p0.h = hi(PLL_LOCKCNT);
291 p0.l = lo(PLL_LOCKCNT);
296 P2.H = hi(EBIU_SDGCTL);
297 P2.L = lo(EBIU_SDGCTL);
303 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
304 r0 = r0 << 9; /* Shift it over, */
305 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
307 r1 = PLL_BYPASS; /* Bypass the PLL? */
308 r1 = r1 << 8; /* Shift it over */
309 r0 = r1 | r0; /* add them all together */
312 p0.l = lo(PLL_CTL); /* Load the address */
313 cli r2; /* Disable interrupts */
315 w[p0] = r0.l; /* Set the value */
316 idle; /* Wait for the PLL to stablize */
317 sti r2; /* Enable interrupts */
324 if ! CC jump .Lcheck_again;
326 /* Configure SCLK & CCLK Dividers */
327 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
333 p0.l = lo(EBIU_SDRRC);
334 p0.h = hi(EBIU_SDRRC);
339 p0.l = LO(EBIU_SDBCTL);
340 p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
345 P2.H = hi(EBIU_SDGCTL);
346 P2.L = lo(EBIU_SDGCTL);
349 p0.h = hi(EBIU_SDSTAT);
350 p0.l = lo(EBIU_SDSTAT);
360 R0.L = lo(mem_SDGCTL);
361 R0.H = hi(mem_SDGCTL);
369 r0.l = lo(IWR_ENABLE_ALL);
370 r0.h = hi(IWR_ENABLE_ALL);
375 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
378 /* No more interrupts to be handled*/
382 #if defined(CONFIG_MTD_M25P80)
384 * The following code fix the SPI flash reboot issue,
385 * /CS signal of the chip which is using PF10 return to GPIO mode
387 p0.h = hi(PORTF_FER);
388 p0.l = lo(PORTF_FER);
393 /* /CS return to high */
400 /* Delay some time, This is necessary */
404 lsetup (_delay_lab1,_delay_lab1_end ) lc1 = p1;
409 lsetup (_delay_lab0,_delay_lab0_end ) lc0 = p0;
418 /* Clear the bits 13-15 in SWRST if they werent cleared */
424 /* Clear the IMASK register */
430 /* Clear the ILAT register */
437 /* Disable the WDOG TIMER */
444 /* Clear the sticky bit incase it is already set */
451 /* Program the count value */
459 /* Program WDOG_STAT if necessary */
464 if !CC JUMP .LWRITESTAT;
466 if !CC JUMP .LWRITESTAT;
470 /* When watch dog timer is enabled,
471 * a write to STAT will load the contents of CNT to STAT
474 P0.h = hi(WDOG_STAT);
480 /* Enable the reset event */
490 /* Enable the wdog counter */
503 * Set up the usable of RAM stuff. Size of RAM is determined then
504 * an initial stack set up at the end.