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Merge branches 'pm-core', 'pm-clk', 'pm-domains' and 'pm-pci'
[deliverable/linux.git] / arch / mips / kvm / emulate.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * KVM/MIPS: Instruction/Exception emulation
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 */
11
12 #include <linux/errno.h>
13 #include <linux/err.h>
14 #include <linux/ktime.h>
15 #include <linux/kvm_host.h>
16 #include <linux/module.h>
17 #include <linux/vmalloc.h>
18 #include <linux/fs.h>
19 #include <linux/bootmem.h>
20 #include <linux/random.h>
21 #include <asm/page.h>
22 #include <asm/cacheflush.h>
23 #include <asm/cacheops.h>
24 #include <asm/cpu-info.h>
25 #include <asm/mmu_context.h>
26 #include <asm/tlbflush.h>
27 #include <asm/inst.h>
28
29 #undef CONFIG_MIPS_MT
30 #include <asm/r4kcache.h>
31 #define CONFIG_MIPS_MT
32
33 #include "interrupt.h"
34 #include "commpage.h"
35
36 #include "trace.h"
37
38 /*
39 * Compute the return address and do emulate branch simulation, if required.
40 * This function should be called only in branch delay slot active.
41 */
42 unsigned long kvm_compute_return_epc(struct kvm_vcpu *vcpu,
43 unsigned long instpc)
44 {
45 unsigned int dspcontrol;
46 union mips_instruction insn;
47 struct kvm_vcpu_arch *arch = &vcpu->arch;
48 long epc = instpc;
49 long nextpc = KVM_INVALID_INST;
50
51 if (epc & 3)
52 goto unaligned;
53
54 /* Read the instruction */
55 insn.word = kvm_get_inst((uint32_t *) epc, vcpu);
56
57 if (insn.word == KVM_INVALID_INST)
58 return KVM_INVALID_INST;
59
60 switch (insn.i_format.opcode) {
61 /* jr and jalr are in r_format format. */
62 case spec_op:
63 switch (insn.r_format.func) {
64 case jalr_op:
65 arch->gprs[insn.r_format.rd] = epc + 8;
66 /* Fall through */
67 case jr_op:
68 nextpc = arch->gprs[insn.r_format.rs];
69 break;
70 }
71 break;
72
73 /*
74 * This group contains:
75 * bltz_op, bgez_op, bltzl_op, bgezl_op,
76 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
77 */
78 case bcond_op:
79 switch (insn.i_format.rt) {
80 case bltz_op:
81 case bltzl_op:
82 if ((long)arch->gprs[insn.i_format.rs] < 0)
83 epc = epc + 4 + (insn.i_format.simmediate << 2);
84 else
85 epc += 8;
86 nextpc = epc;
87 break;
88
89 case bgez_op:
90 case bgezl_op:
91 if ((long)arch->gprs[insn.i_format.rs] >= 0)
92 epc = epc + 4 + (insn.i_format.simmediate << 2);
93 else
94 epc += 8;
95 nextpc = epc;
96 break;
97
98 case bltzal_op:
99 case bltzall_op:
100 arch->gprs[31] = epc + 8;
101 if ((long)arch->gprs[insn.i_format.rs] < 0)
102 epc = epc + 4 + (insn.i_format.simmediate << 2);
103 else
104 epc += 8;
105 nextpc = epc;
106 break;
107
108 case bgezal_op:
109 case bgezall_op:
110 arch->gprs[31] = epc + 8;
111 if ((long)arch->gprs[insn.i_format.rs] >= 0)
112 epc = epc + 4 + (insn.i_format.simmediate << 2);
113 else
114 epc += 8;
115 nextpc = epc;
116 break;
117 case bposge32_op:
118 if (!cpu_has_dsp)
119 goto sigill;
120
121 dspcontrol = rddsp(0x01);
122
123 if (dspcontrol >= 32)
124 epc = epc + 4 + (insn.i_format.simmediate << 2);
125 else
126 epc += 8;
127 nextpc = epc;
128 break;
129 }
130 break;
131
132 /* These are unconditional and in j_format. */
133 case jal_op:
134 arch->gprs[31] = instpc + 8;
135 case j_op:
136 epc += 4;
137 epc >>= 28;
138 epc <<= 28;
139 epc |= (insn.j_format.target << 2);
140 nextpc = epc;
141 break;
142
143 /* These are conditional and in i_format. */
144 case beq_op:
145 case beql_op:
146 if (arch->gprs[insn.i_format.rs] ==
147 arch->gprs[insn.i_format.rt])
148 epc = epc + 4 + (insn.i_format.simmediate << 2);
149 else
150 epc += 8;
151 nextpc = epc;
152 break;
153
154 case bne_op:
155 case bnel_op:
156 if (arch->gprs[insn.i_format.rs] !=
157 arch->gprs[insn.i_format.rt])
158 epc = epc + 4 + (insn.i_format.simmediate << 2);
159 else
160 epc += 8;
161 nextpc = epc;
162 break;
163
164 case blez_op: /* not really i_format */
165 case blezl_op:
166 /* rt field assumed to be zero */
167 if ((long)arch->gprs[insn.i_format.rs] <= 0)
168 epc = epc + 4 + (insn.i_format.simmediate << 2);
169 else
170 epc += 8;
171 nextpc = epc;
172 break;
173
174 case bgtz_op:
175 case bgtzl_op:
176 /* rt field assumed to be zero */
177 if ((long)arch->gprs[insn.i_format.rs] > 0)
178 epc = epc + 4 + (insn.i_format.simmediate << 2);
179 else
180 epc += 8;
181 nextpc = epc;
182 break;
183
184 /* And now the FPA/cp1 branch instructions. */
185 case cop1_op:
186 kvm_err("%s: unsupported cop1_op\n", __func__);
187 break;
188 }
189
190 return nextpc;
191
192 unaligned:
193 kvm_err("%s: unaligned epc\n", __func__);
194 return nextpc;
195
196 sigill:
197 kvm_err("%s: DSP branch but not DSP ASE\n", __func__);
198 return nextpc;
199 }
200
201 enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause)
202 {
203 unsigned long branch_pc;
204 enum emulation_result er = EMULATE_DONE;
205
206 if (cause & CAUSEF_BD) {
207 branch_pc = kvm_compute_return_epc(vcpu, vcpu->arch.pc);
208 if (branch_pc == KVM_INVALID_INST) {
209 er = EMULATE_FAIL;
210 } else {
211 vcpu->arch.pc = branch_pc;
212 kvm_debug("BD update_pc(): New PC: %#lx\n",
213 vcpu->arch.pc);
214 }
215 } else
216 vcpu->arch.pc += 4;
217
218 kvm_debug("update_pc(): New PC: %#lx\n", vcpu->arch.pc);
219
220 return er;
221 }
222
223 /**
224 * kvm_mips_count_disabled() - Find whether the CP0_Count timer is disabled.
225 * @vcpu: Virtual CPU.
226 *
227 * Returns: 1 if the CP0_Count timer is disabled by either the guest
228 * CP0_Cause.DC bit or the count_ctl.DC bit.
229 * 0 otherwise (in which case CP0_Count timer is running).
230 */
231 static inline int kvm_mips_count_disabled(struct kvm_vcpu *vcpu)
232 {
233 struct mips_coproc *cop0 = vcpu->arch.cop0;
234
235 return (vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) ||
236 (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC);
237 }
238
239 /**
240 * kvm_mips_ktime_to_count() - Scale ktime_t to a 32-bit count.
241 *
242 * Caches the dynamic nanosecond bias in vcpu->arch.count_dyn_bias.
243 *
244 * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
245 */
246 static uint32_t kvm_mips_ktime_to_count(struct kvm_vcpu *vcpu, ktime_t now)
247 {
248 s64 now_ns, periods;
249 u64 delta;
250
251 now_ns = ktime_to_ns(now);
252 delta = now_ns + vcpu->arch.count_dyn_bias;
253
254 if (delta >= vcpu->arch.count_period) {
255 /* If delta is out of safe range the bias needs adjusting */
256 periods = div64_s64(now_ns, vcpu->arch.count_period);
257 vcpu->arch.count_dyn_bias = -periods * vcpu->arch.count_period;
258 /* Recalculate delta with new bias */
259 delta = now_ns + vcpu->arch.count_dyn_bias;
260 }
261
262 /*
263 * We've ensured that:
264 * delta < count_period
265 *
266 * Therefore the intermediate delta*count_hz will never overflow since
267 * at the boundary condition:
268 * delta = count_period
269 * delta = NSEC_PER_SEC * 2^32 / count_hz
270 * delta * count_hz = NSEC_PER_SEC * 2^32
271 */
272 return div_u64(delta * vcpu->arch.count_hz, NSEC_PER_SEC);
273 }
274
275 /**
276 * kvm_mips_count_time() - Get effective current time.
277 * @vcpu: Virtual CPU.
278 *
279 * Get effective monotonic ktime. This is usually a straightforward ktime_get(),
280 * except when the master disable bit is set in count_ctl, in which case it is
281 * count_resume, i.e. the time that the count was disabled.
282 *
283 * Returns: Effective monotonic ktime for CP0_Count.
284 */
285 static inline ktime_t kvm_mips_count_time(struct kvm_vcpu *vcpu)
286 {
287 if (unlikely(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC))
288 return vcpu->arch.count_resume;
289
290 return ktime_get();
291 }
292
293 /**
294 * kvm_mips_read_count_running() - Read the current count value as if running.
295 * @vcpu: Virtual CPU.
296 * @now: Kernel time to read CP0_Count at.
297 *
298 * Returns the current guest CP0_Count register at time @now and handles if the
299 * timer interrupt is pending and hasn't been handled yet.
300 *
301 * Returns: The current value of the guest CP0_Count register.
302 */
303 static uint32_t kvm_mips_read_count_running(struct kvm_vcpu *vcpu, ktime_t now)
304 {
305 struct mips_coproc *cop0 = vcpu->arch.cop0;
306 ktime_t expires, threshold;
307 uint32_t count, compare;
308 int running;
309
310 /* Calculate the biased and scaled guest CP0_Count */
311 count = vcpu->arch.count_bias + kvm_mips_ktime_to_count(vcpu, now);
312 compare = kvm_read_c0_guest_compare(cop0);
313
314 /*
315 * Find whether CP0_Count has reached the closest timer interrupt. If
316 * not, we shouldn't inject it.
317 */
318 if ((int32_t)(count - compare) < 0)
319 return count;
320
321 /*
322 * The CP0_Count we're going to return has already reached the closest
323 * timer interrupt. Quickly check if it really is a new interrupt by
324 * looking at whether the interval until the hrtimer expiry time is
325 * less than 1/4 of the timer period.
326 */
327 expires = hrtimer_get_expires(&vcpu->arch.comparecount_timer);
328 threshold = ktime_add_ns(now, vcpu->arch.count_period / 4);
329 if (ktime_before(expires, threshold)) {
330 /*
331 * Cancel it while we handle it so there's no chance of
332 * interference with the timeout handler.
333 */
334 running = hrtimer_cancel(&vcpu->arch.comparecount_timer);
335
336 /* Nothing should be waiting on the timeout */
337 kvm_mips_callbacks->queue_timer_int(vcpu);
338
339 /*
340 * Restart the timer if it was running based on the expiry time
341 * we read, so that we don't push it back 2 periods.
342 */
343 if (running) {
344 expires = ktime_add_ns(expires,
345 vcpu->arch.count_period);
346 hrtimer_start(&vcpu->arch.comparecount_timer, expires,
347 HRTIMER_MODE_ABS);
348 }
349 }
350
351 return count;
352 }
353
354 /**
355 * kvm_mips_read_count() - Read the current count value.
356 * @vcpu: Virtual CPU.
357 *
358 * Read the current guest CP0_Count value, taking into account whether the timer
359 * is stopped.
360 *
361 * Returns: The current guest CP0_Count value.
362 */
363 uint32_t kvm_mips_read_count(struct kvm_vcpu *vcpu)
364 {
365 struct mips_coproc *cop0 = vcpu->arch.cop0;
366
367 /* If count disabled just read static copy of count */
368 if (kvm_mips_count_disabled(vcpu))
369 return kvm_read_c0_guest_count(cop0);
370
371 return kvm_mips_read_count_running(vcpu, ktime_get());
372 }
373
374 /**
375 * kvm_mips_freeze_hrtimer() - Safely stop the hrtimer.
376 * @vcpu: Virtual CPU.
377 * @count: Output pointer for CP0_Count value at point of freeze.
378 *
379 * Freeze the hrtimer safely and return both the ktime and the CP0_Count value
380 * at the point it was frozen. It is guaranteed that any pending interrupts at
381 * the point it was frozen are handled, and none after that point.
382 *
383 * This is useful where the time/CP0_Count is needed in the calculation of the
384 * new parameters.
385 *
386 * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
387 *
388 * Returns: The ktime at the point of freeze.
389 */
390 static ktime_t kvm_mips_freeze_hrtimer(struct kvm_vcpu *vcpu,
391 uint32_t *count)
392 {
393 ktime_t now;
394
395 /* stop hrtimer before finding time */
396 hrtimer_cancel(&vcpu->arch.comparecount_timer);
397 now = ktime_get();
398
399 /* find count at this point and handle pending hrtimer */
400 *count = kvm_mips_read_count_running(vcpu, now);
401
402 return now;
403 }
404
405 /**
406 * kvm_mips_resume_hrtimer() - Resume hrtimer, updating expiry.
407 * @vcpu: Virtual CPU.
408 * @now: ktime at point of resume.
409 * @count: CP0_Count at point of resume.
410 *
411 * Resumes the timer and updates the timer expiry based on @now and @count.
412 * This can be used in conjunction with kvm_mips_freeze_timer() when timer
413 * parameters need to be changed.
414 *
415 * It is guaranteed that a timer interrupt immediately after resume will be
416 * handled, but not if CP_Compare is exactly at @count. That case is already
417 * handled by kvm_mips_freeze_timer().
418 *
419 * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
420 */
421 static void kvm_mips_resume_hrtimer(struct kvm_vcpu *vcpu,
422 ktime_t now, uint32_t count)
423 {
424 struct mips_coproc *cop0 = vcpu->arch.cop0;
425 uint32_t compare;
426 u64 delta;
427 ktime_t expire;
428
429 /* Calculate timeout (wrap 0 to 2^32) */
430 compare = kvm_read_c0_guest_compare(cop0);
431 delta = (u64)(uint32_t)(compare - count - 1) + 1;
432 delta = div_u64(delta * NSEC_PER_SEC, vcpu->arch.count_hz);
433 expire = ktime_add_ns(now, delta);
434
435 /* Update hrtimer to use new timeout */
436 hrtimer_cancel(&vcpu->arch.comparecount_timer);
437 hrtimer_start(&vcpu->arch.comparecount_timer, expire, HRTIMER_MODE_ABS);
438 }
439
440 /**
441 * kvm_mips_write_count() - Modify the count and update timer.
442 * @vcpu: Virtual CPU.
443 * @count: Guest CP0_Count value to set.
444 *
445 * Sets the CP0_Count value and updates the timer accordingly.
446 */
447 void kvm_mips_write_count(struct kvm_vcpu *vcpu, uint32_t count)
448 {
449 struct mips_coproc *cop0 = vcpu->arch.cop0;
450 ktime_t now;
451
452 /* Calculate bias */
453 now = kvm_mips_count_time(vcpu);
454 vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now);
455
456 if (kvm_mips_count_disabled(vcpu))
457 /* The timer's disabled, adjust the static count */
458 kvm_write_c0_guest_count(cop0, count);
459 else
460 /* Update timeout */
461 kvm_mips_resume_hrtimer(vcpu, now, count);
462 }
463
464 /**
465 * kvm_mips_init_count() - Initialise timer.
466 * @vcpu: Virtual CPU.
467 *
468 * Initialise the timer to a sensible frequency, namely 100MHz, zero it, and set
469 * it going if it's enabled.
470 */
471 void kvm_mips_init_count(struct kvm_vcpu *vcpu)
472 {
473 /* 100 MHz */
474 vcpu->arch.count_hz = 100*1000*1000;
475 vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32,
476 vcpu->arch.count_hz);
477 vcpu->arch.count_dyn_bias = 0;
478
479 /* Starting at 0 */
480 kvm_mips_write_count(vcpu, 0);
481 }
482
483 /**
484 * kvm_mips_set_count_hz() - Update the frequency of the timer.
485 * @vcpu: Virtual CPU.
486 * @count_hz: Frequency of CP0_Count timer in Hz.
487 *
488 * Change the frequency of the CP0_Count timer. This is done atomically so that
489 * CP0_Count is continuous and no timer interrupt is lost.
490 *
491 * Returns: -EINVAL if @count_hz is out of range.
492 * 0 on success.
493 */
494 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz)
495 {
496 struct mips_coproc *cop0 = vcpu->arch.cop0;
497 int dc;
498 ktime_t now;
499 u32 count;
500
501 /* ensure the frequency is in a sensible range... */
502 if (count_hz <= 0 || count_hz > NSEC_PER_SEC)
503 return -EINVAL;
504 /* ... and has actually changed */
505 if (vcpu->arch.count_hz == count_hz)
506 return 0;
507
508 /* Safely freeze timer so we can keep it continuous */
509 dc = kvm_mips_count_disabled(vcpu);
510 if (dc) {
511 now = kvm_mips_count_time(vcpu);
512 count = kvm_read_c0_guest_count(cop0);
513 } else {
514 now = kvm_mips_freeze_hrtimer(vcpu, &count);
515 }
516
517 /* Update the frequency */
518 vcpu->arch.count_hz = count_hz;
519 vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32, count_hz);
520 vcpu->arch.count_dyn_bias = 0;
521
522 /* Calculate adjusted bias so dynamic count is unchanged */
523 vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now);
524
525 /* Update and resume hrtimer */
526 if (!dc)
527 kvm_mips_resume_hrtimer(vcpu, now, count);
528 return 0;
529 }
530
531 /**
532 * kvm_mips_write_compare() - Modify compare and update timer.
533 * @vcpu: Virtual CPU.
534 * @compare: New CP0_Compare value.
535 * @ack: Whether to acknowledge timer interrupt.
536 *
537 * Update CP0_Compare to a new value and update the timeout.
538 * If @ack, atomically acknowledge any pending timer interrupt, otherwise ensure
539 * any pending timer interrupt is preserved.
540 */
541 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare, bool ack)
542 {
543 struct mips_coproc *cop0 = vcpu->arch.cop0;
544 int dc;
545 u32 old_compare = kvm_read_c0_guest_compare(cop0);
546 ktime_t now;
547 uint32_t count;
548
549 /* if unchanged, must just be an ack */
550 if (old_compare == compare) {
551 if (!ack)
552 return;
553 kvm_mips_callbacks->dequeue_timer_int(vcpu);
554 kvm_write_c0_guest_compare(cop0, compare);
555 return;
556 }
557
558 /* freeze_hrtimer() takes care of timer interrupts <= count */
559 dc = kvm_mips_count_disabled(vcpu);
560 if (!dc)
561 now = kvm_mips_freeze_hrtimer(vcpu, &count);
562
563 if (ack)
564 kvm_mips_callbacks->dequeue_timer_int(vcpu);
565
566 kvm_write_c0_guest_compare(cop0, compare);
567
568 /* resume_hrtimer() takes care of timer interrupts > count */
569 if (!dc)
570 kvm_mips_resume_hrtimer(vcpu, now, count);
571 }
572
573 /**
574 * kvm_mips_count_disable() - Disable count.
575 * @vcpu: Virtual CPU.
576 *
577 * Disable the CP0_Count timer. A timer interrupt on or before the final stop
578 * time will be handled but not after.
579 *
580 * Assumes CP0_Count was previously enabled but now Guest.CP0_Cause.DC or
581 * count_ctl.DC has been set (count disabled).
582 *
583 * Returns: The time that the timer was stopped.
584 */
585 static ktime_t kvm_mips_count_disable(struct kvm_vcpu *vcpu)
586 {
587 struct mips_coproc *cop0 = vcpu->arch.cop0;
588 uint32_t count;
589 ktime_t now;
590
591 /* Stop hrtimer */
592 hrtimer_cancel(&vcpu->arch.comparecount_timer);
593
594 /* Set the static count from the dynamic count, handling pending TI */
595 now = ktime_get();
596 count = kvm_mips_read_count_running(vcpu, now);
597 kvm_write_c0_guest_count(cop0, count);
598
599 return now;
600 }
601
602 /**
603 * kvm_mips_count_disable_cause() - Disable count using CP0_Cause.DC.
604 * @vcpu: Virtual CPU.
605 *
606 * Disable the CP0_Count timer and set CP0_Cause.DC. A timer interrupt on or
607 * before the final stop time will be handled if the timer isn't disabled by
608 * count_ctl.DC, but not after.
609 *
610 * Assumes CP0_Cause.DC is clear (count enabled).
611 */
612 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu)
613 {
614 struct mips_coproc *cop0 = vcpu->arch.cop0;
615
616 kvm_set_c0_guest_cause(cop0, CAUSEF_DC);
617 if (!(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC))
618 kvm_mips_count_disable(vcpu);
619 }
620
621 /**
622 * kvm_mips_count_enable_cause() - Enable count using CP0_Cause.DC.
623 * @vcpu: Virtual CPU.
624 *
625 * Enable the CP0_Count timer and clear CP0_Cause.DC. A timer interrupt after
626 * the start time will be handled if the timer isn't disabled by count_ctl.DC,
627 * potentially before even returning, so the caller should be careful with
628 * ordering of CP0_Cause modifications so as not to lose it.
629 *
630 * Assumes CP0_Cause.DC is set (count disabled).
631 */
632 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu)
633 {
634 struct mips_coproc *cop0 = vcpu->arch.cop0;
635 uint32_t count;
636
637 kvm_clear_c0_guest_cause(cop0, CAUSEF_DC);
638
639 /*
640 * Set the dynamic count to match the static count.
641 * This starts the hrtimer if count_ctl.DC allows it.
642 * Otherwise it conveniently updates the biases.
643 */
644 count = kvm_read_c0_guest_count(cop0);
645 kvm_mips_write_count(vcpu, count);
646 }
647
648 /**
649 * kvm_mips_set_count_ctl() - Update the count control KVM register.
650 * @vcpu: Virtual CPU.
651 * @count_ctl: Count control register new value.
652 *
653 * Set the count control KVM register. The timer is updated accordingly.
654 *
655 * Returns: -EINVAL if reserved bits are set.
656 * 0 on success.
657 */
658 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl)
659 {
660 struct mips_coproc *cop0 = vcpu->arch.cop0;
661 s64 changed = count_ctl ^ vcpu->arch.count_ctl;
662 s64 delta;
663 ktime_t expire, now;
664 uint32_t count, compare;
665
666 /* Only allow defined bits to be changed */
667 if (changed & ~(s64)(KVM_REG_MIPS_COUNT_CTL_DC))
668 return -EINVAL;
669
670 /* Apply new value */
671 vcpu->arch.count_ctl = count_ctl;
672
673 /* Master CP0_Count disable */
674 if (changed & KVM_REG_MIPS_COUNT_CTL_DC) {
675 /* Is CP0_Cause.DC already disabling CP0_Count? */
676 if (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC) {
677 if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)
678 /* Just record the current time */
679 vcpu->arch.count_resume = ktime_get();
680 } else if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) {
681 /* disable timer and record current time */
682 vcpu->arch.count_resume = kvm_mips_count_disable(vcpu);
683 } else {
684 /*
685 * Calculate timeout relative to static count at resume
686 * time (wrap 0 to 2^32).
687 */
688 count = kvm_read_c0_guest_count(cop0);
689 compare = kvm_read_c0_guest_compare(cop0);
690 delta = (u64)(uint32_t)(compare - count - 1) + 1;
691 delta = div_u64(delta * NSEC_PER_SEC,
692 vcpu->arch.count_hz);
693 expire = ktime_add_ns(vcpu->arch.count_resume, delta);
694
695 /* Handle pending interrupt */
696 now = ktime_get();
697 if (ktime_compare(now, expire) >= 0)
698 /* Nothing should be waiting on the timeout */
699 kvm_mips_callbacks->queue_timer_int(vcpu);
700
701 /* Resume hrtimer without changing bias */
702 count = kvm_mips_read_count_running(vcpu, now);
703 kvm_mips_resume_hrtimer(vcpu, now, count);
704 }
705 }
706
707 return 0;
708 }
709
710 /**
711 * kvm_mips_set_count_resume() - Update the count resume KVM register.
712 * @vcpu: Virtual CPU.
713 * @count_resume: Count resume register new value.
714 *
715 * Set the count resume KVM register.
716 *
717 * Returns: -EINVAL if out of valid range (0..now).
718 * 0 on success.
719 */
720 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume)
721 {
722 /*
723 * It doesn't make sense for the resume time to be in the future, as it
724 * would be possible for the next interrupt to be more than a full
725 * period in the future.
726 */
727 if (count_resume < 0 || count_resume > ktime_to_ns(ktime_get()))
728 return -EINVAL;
729
730 vcpu->arch.count_resume = ns_to_ktime(count_resume);
731 return 0;
732 }
733
734 /**
735 * kvm_mips_count_timeout() - Push timer forward on timeout.
736 * @vcpu: Virtual CPU.
737 *
738 * Handle an hrtimer event by push the hrtimer forward a period.
739 *
740 * Returns: The hrtimer_restart value to return to the hrtimer subsystem.
741 */
742 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu)
743 {
744 /* Add the Count period to the current expiry time */
745 hrtimer_add_expires_ns(&vcpu->arch.comparecount_timer,
746 vcpu->arch.count_period);
747 return HRTIMER_RESTART;
748 }
749
750 enum emulation_result kvm_mips_emul_eret(struct kvm_vcpu *vcpu)
751 {
752 struct mips_coproc *cop0 = vcpu->arch.cop0;
753 enum emulation_result er = EMULATE_DONE;
754
755 if (kvm_read_c0_guest_status(cop0) & ST0_EXL) {
756 kvm_debug("[%#lx] ERET to %#lx\n", vcpu->arch.pc,
757 kvm_read_c0_guest_epc(cop0));
758 kvm_clear_c0_guest_status(cop0, ST0_EXL);
759 vcpu->arch.pc = kvm_read_c0_guest_epc(cop0);
760
761 } else if (kvm_read_c0_guest_status(cop0) & ST0_ERL) {
762 kvm_clear_c0_guest_status(cop0, ST0_ERL);
763 vcpu->arch.pc = kvm_read_c0_guest_errorepc(cop0);
764 } else {
765 kvm_err("[%#lx] ERET when MIPS_SR_EXL|MIPS_SR_ERL == 0\n",
766 vcpu->arch.pc);
767 er = EMULATE_FAIL;
768 }
769
770 return er;
771 }
772
773 enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu)
774 {
775 kvm_debug("[%#lx] !!!WAIT!!! (%#lx)\n", vcpu->arch.pc,
776 vcpu->arch.pending_exceptions);
777
778 ++vcpu->stat.wait_exits;
779 trace_kvm_exit(vcpu, WAIT_EXITS);
780 if (!vcpu->arch.pending_exceptions) {
781 vcpu->arch.wait = 1;
782 kvm_vcpu_block(vcpu);
783
784 /*
785 * We we are runnable, then definitely go off to user space to
786 * check if any I/O interrupts are pending.
787 */
788 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
789 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
790 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
791 }
792 }
793
794 return EMULATE_DONE;
795 }
796
797 /*
798 * XXXKYMA: Linux doesn't seem to use TLBR, return EMULATE_FAIL for now so that
799 * we can catch this, if things ever change
800 */
801 enum emulation_result kvm_mips_emul_tlbr(struct kvm_vcpu *vcpu)
802 {
803 struct mips_coproc *cop0 = vcpu->arch.cop0;
804 uint32_t pc = vcpu->arch.pc;
805
806 kvm_err("[%#x] COP0_TLBR [%ld]\n", pc, kvm_read_c0_guest_index(cop0));
807 return EMULATE_FAIL;
808 }
809
810 /* Write Guest TLB Entry @ Index */
811 enum emulation_result kvm_mips_emul_tlbwi(struct kvm_vcpu *vcpu)
812 {
813 struct mips_coproc *cop0 = vcpu->arch.cop0;
814 int index = kvm_read_c0_guest_index(cop0);
815 struct kvm_mips_tlb *tlb = NULL;
816 uint32_t pc = vcpu->arch.pc;
817
818 if (index < 0 || index >= KVM_MIPS_GUEST_TLB_SIZE) {
819 kvm_debug("%s: illegal index: %d\n", __func__, index);
820 kvm_debug("[%#x] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n",
821 pc, index, kvm_read_c0_guest_entryhi(cop0),
822 kvm_read_c0_guest_entrylo0(cop0),
823 kvm_read_c0_guest_entrylo1(cop0),
824 kvm_read_c0_guest_pagemask(cop0));
825 index = (index & ~0x80000000) % KVM_MIPS_GUEST_TLB_SIZE;
826 }
827
828 tlb = &vcpu->arch.guest_tlb[index];
829 /*
830 * Probe the shadow host TLB for the entry being overwritten, if one
831 * matches, invalidate it
832 */
833 kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi);
834
835 tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
836 tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
837 tlb->tlb_lo0 = kvm_read_c0_guest_entrylo0(cop0);
838 tlb->tlb_lo1 = kvm_read_c0_guest_entrylo1(cop0);
839
840 kvm_debug("[%#x] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n",
841 pc, index, kvm_read_c0_guest_entryhi(cop0),
842 kvm_read_c0_guest_entrylo0(cop0),
843 kvm_read_c0_guest_entrylo1(cop0),
844 kvm_read_c0_guest_pagemask(cop0));
845
846 return EMULATE_DONE;
847 }
848
849 /* Write Guest TLB Entry @ Random Index */
850 enum emulation_result kvm_mips_emul_tlbwr(struct kvm_vcpu *vcpu)
851 {
852 struct mips_coproc *cop0 = vcpu->arch.cop0;
853 struct kvm_mips_tlb *tlb = NULL;
854 uint32_t pc = vcpu->arch.pc;
855 int index;
856
857 get_random_bytes(&index, sizeof(index));
858 index &= (KVM_MIPS_GUEST_TLB_SIZE - 1);
859
860 tlb = &vcpu->arch.guest_tlb[index];
861
862 /*
863 * Probe the shadow host TLB for the entry being overwritten, if one
864 * matches, invalidate it
865 */
866 kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi);
867
868 tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
869 tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
870 tlb->tlb_lo0 = kvm_read_c0_guest_entrylo0(cop0);
871 tlb->tlb_lo1 = kvm_read_c0_guest_entrylo1(cop0);
872
873 kvm_debug("[%#x] COP0_TLBWR[%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx)\n",
874 pc, index, kvm_read_c0_guest_entryhi(cop0),
875 kvm_read_c0_guest_entrylo0(cop0),
876 kvm_read_c0_guest_entrylo1(cop0));
877
878 return EMULATE_DONE;
879 }
880
881 enum emulation_result kvm_mips_emul_tlbp(struct kvm_vcpu *vcpu)
882 {
883 struct mips_coproc *cop0 = vcpu->arch.cop0;
884 long entryhi = kvm_read_c0_guest_entryhi(cop0);
885 uint32_t pc = vcpu->arch.pc;
886 int index = -1;
887
888 index = kvm_mips_guest_tlb_lookup(vcpu, entryhi);
889
890 kvm_write_c0_guest_index(cop0, index);
891
892 kvm_debug("[%#x] COP0_TLBP (entryhi: %#lx), index: %d\n", pc, entryhi,
893 index);
894
895 return EMULATE_DONE;
896 }
897
898 /**
899 * kvm_mips_config1_wrmask() - Find mask of writable bits in guest Config1
900 * @vcpu: Virtual CPU.
901 *
902 * Finds the mask of bits which are writable in the guest's Config1 CP0
903 * register, by userland (currently read-only to the guest).
904 */
905 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu)
906 {
907 unsigned int mask = 0;
908
909 /* Permit FPU to be present if FPU is supported */
910 if (kvm_mips_guest_can_have_fpu(&vcpu->arch))
911 mask |= MIPS_CONF1_FP;
912
913 return mask;
914 }
915
916 /**
917 * kvm_mips_config3_wrmask() - Find mask of writable bits in guest Config3
918 * @vcpu: Virtual CPU.
919 *
920 * Finds the mask of bits which are writable in the guest's Config3 CP0
921 * register, by userland (currently read-only to the guest).
922 */
923 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu)
924 {
925 /* Config4 is optional */
926 unsigned int mask = MIPS_CONF_M;
927
928 /* Permit MSA to be present if MSA is supported */
929 if (kvm_mips_guest_can_have_msa(&vcpu->arch))
930 mask |= MIPS_CONF3_MSA;
931
932 return mask;
933 }
934
935 /**
936 * kvm_mips_config4_wrmask() - Find mask of writable bits in guest Config4
937 * @vcpu: Virtual CPU.
938 *
939 * Finds the mask of bits which are writable in the guest's Config4 CP0
940 * register, by userland (currently read-only to the guest).
941 */
942 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu)
943 {
944 /* Config5 is optional */
945 return MIPS_CONF_M;
946 }
947
948 /**
949 * kvm_mips_config5_wrmask() - Find mask of writable bits in guest Config5
950 * @vcpu: Virtual CPU.
951 *
952 * Finds the mask of bits which are writable in the guest's Config5 CP0
953 * register, by the guest itself.
954 */
955 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu)
956 {
957 unsigned int mask = 0;
958
959 /* Permit MSAEn changes if MSA supported and enabled */
960 if (kvm_mips_guest_has_msa(&vcpu->arch))
961 mask |= MIPS_CONF5_MSAEN;
962
963 /*
964 * Permit guest FPU mode changes if FPU is enabled and the relevant
965 * feature exists according to FIR register.
966 */
967 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
968 if (cpu_has_fre)
969 mask |= MIPS_CONF5_FRE;
970 /* We don't support UFR or UFE */
971 }
972
973 return mask;
974 }
975
976 enum emulation_result kvm_mips_emulate_CP0(uint32_t inst, uint32_t *opc,
977 uint32_t cause, struct kvm_run *run,
978 struct kvm_vcpu *vcpu)
979 {
980 struct mips_coproc *cop0 = vcpu->arch.cop0;
981 enum emulation_result er = EMULATE_DONE;
982 int32_t rt, rd, copz, sel, co_bit, op;
983 uint32_t pc = vcpu->arch.pc;
984 unsigned long curr_pc;
985
986 /*
987 * Update PC and hold onto current PC in case there is
988 * an error and we want to rollback the PC
989 */
990 curr_pc = vcpu->arch.pc;
991 er = update_pc(vcpu, cause);
992 if (er == EMULATE_FAIL)
993 return er;
994
995 copz = (inst >> 21) & 0x1f;
996 rt = (inst >> 16) & 0x1f;
997 rd = (inst >> 11) & 0x1f;
998 sel = inst & 0x7;
999 co_bit = (inst >> 25) & 1;
1000
1001 if (co_bit) {
1002 op = (inst) & 0xff;
1003
1004 switch (op) {
1005 case tlbr_op: /* Read indexed TLB entry */
1006 er = kvm_mips_emul_tlbr(vcpu);
1007 break;
1008 case tlbwi_op: /* Write indexed */
1009 er = kvm_mips_emul_tlbwi(vcpu);
1010 break;
1011 case tlbwr_op: /* Write random */
1012 er = kvm_mips_emul_tlbwr(vcpu);
1013 break;
1014 case tlbp_op: /* TLB Probe */
1015 er = kvm_mips_emul_tlbp(vcpu);
1016 break;
1017 case rfe_op:
1018 kvm_err("!!!COP0_RFE!!!\n");
1019 break;
1020 case eret_op:
1021 er = kvm_mips_emul_eret(vcpu);
1022 goto dont_update_pc;
1023 break;
1024 case wait_op:
1025 er = kvm_mips_emul_wait(vcpu);
1026 break;
1027 }
1028 } else {
1029 switch (copz) {
1030 case mfc_op:
1031 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
1032 cop0->stat[rd][sel]++;
1033 #endif
1034 /* Get reg */
1035 if ((rd == MIPS_CP0_COUNT) && (sel == 0)) {
1036 vcpu->arch.gprs[rt] = kvm_mips_read_count(vcpu);
1037 } else if ((rd == MIPS_CP0_ERRCTL) && (sel == 0)) {
1038 vcpu->arch.gprs[rt] = 0x0;
1039 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1040 kvm_mips_trans_mfc0(inst, opc, vcpu);
1041 #endif
1042 } else {
1043 vcpu->arch.gprs[rt] = cop0->reg[rd][sel];
1044
1045 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1046 kvm_mips_trans_mfc0(inst, opc, vcpu);
1047 #endif
1048 }
1049
1050 kvm_debug
1051 ("[%#x] MFCz[%d][%d], vcpu->arch.gprs[%d]: %#lx\n",
1052 pc, rd, sel, rt, vcpu->arch.gprs[rt]);
1053
1054 break;
1055
1056 case dmfc_op:
1057 vcpu->arch.gprs[rt] = cop0->reg[rd][sel];
1058 break;
1059
1060 case mtc_op:
1061 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
1062 cop0->stat[rd][sel]++;
1063 #endif
1064 if ((rd == MIPS_CP0_TLB_INDEX)
1065 && (vcpu->arch.gprs[rt] >=
1066 KVM_MIPS_GUEST_TLB_SIZE)) {
1067 kvm_err("Invalid TLB Index: %ld",
1068 vcpu->arch.gprs[rt]);
1069 er = EMULATE_FAIL;
1070 break;
1071 }
1072 #define C0_EBASE_CORE_MASK 0xff
1073 if ((rd == MIPS_CP0_PRID) && (sel == 1)) {
1074 /* Preserve CORE number */
1075 kvm_change_c0_guest_ebase(cop0,
1076 ~(C0_EBASE_CORE_MASK),
1077 vcpu->arch.gprs[rt]);
1078 kvm_err("MTCz, cop0->reg[EBASE]: %#lx\n",
1079 kvm_read_c0_guest_ebase(cop0));
1080 } else if (rd == MIPS_CP0_TLB_HI && sel == 0) {
1081 uint32_t nasid =
1082 vcpu->arch.gprs[rt] & KVM_ENTRYHI_ASID;
1083 if ((KSEGX(vcpu->arch.gprs[rt]) != CKSEG0) &&
1084 ((kvm_read_c0_guest_entryhi(cop0) &
1085 KVM_ENTRYHI_ASID) != nasid)) {
1086 kvm_debug("MTCz, change ASID from %#lx to %#lx\n",
1087 kvm_read_c0_guest_entryhi(cop0)
1088 & KVM_ENTRYHI_ASID,
1089 vcpu->arch.gprs[rt]
1090 & KVM_ENTRYHI_ASID);
1091
1092 /* Blow away the shadow host TLBs */
1093 kvm_mips_flush_host_tlb(1);
1094 }
1095 kvm_write_c0_guest_entryhi(cop0,
1096 vcpu->arch.gprs[rt]);
1097 }
1098 /* Are we writing to COUNT */
1099 else if ((rd == MIPS_CP0_COUNT) && (sel == 0)) {
1100 kvm_mips_write_count(vcpu, vcpu->arch.gprs[rt]);
1101 goto done;
1102 } else if ((rd == MIPS_CP0_COMPARE) && (sel == 0)) {
1103 kvm_debug("[%#x] MTCz, COMPARE %#lx <- %#lx\n",
1104 pc, kvm_read_c0_guest_compare(cop0),
1105 vcpu->arch.gprs[rt]);
1106
1107 /* If we are writing to COMPARE */
1108 /* Clear pending timer interrupt, if any */
1109 kvm_mips_write_compare(vcpu,
1110 vcpu->arch.gprs[rt],
1111 true);
1112 } else if ((rd == MIPS_CP0_STATUS) && (sel == 0)) {
1113 unsigned int old_val, val, change;
1114
1115 old_val = kvm_read_c0_guest_status(cop0);
1116 val = vcpu->arch.gprs[rt];
1117 change = val ^ old_val;
1118
1119 /* Make sure that the NMI bit is never set */
1120 val &= ~ST0_NMI;
1121
1122 /*
1123 * Don't allow CU1 or FR to be set unless FPU
1124 * capability enabled and exists in guest
1125 * configuration.
1126 */
1127 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
1128 val &= ~(ST0_CU1 | ST0_FR);
1129
1130 /*
1131 * Also don't allow FR to be set if host doesn't
1132 * support it.
1133 */
1134 if (!(current_cpu_data.fpu_id & MIPS_FPIR_F64))
1135 val &= ~ST0_FR;
1136
1137
1138 /* Handle changes in FPU mode */
1139 preempt_disable();
1140
1141 /*
1142 * FPU and Vector register state is made
1143 * UNPREDICTABLE by a change of FR, so don't
1144 * even bother saving it.
1145 */
1146 if (change & ST0_FR)
1147 kvm_drop_fpu(vcpu);
1148
1149 /*
1150 * If MSA state is already live, it is undefined
1151 * how it interacts with FR=0 FPU state, and we
1152 * don't want to hit reserved instruction
1153 * exceptions trying to save the MSA state later
1154 * when CU=1 && FR=1, so play it safe and save
1155 * it first.
1156 */
1157 if (change & ST0_CU1 && !(val & ST0_FR) &&
1158 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA)
1159 kvm_lose_fpu(vcpu);
1160
1161 /*
1162 * Propagate CU1 (FPU enable) changes
1163 * immediately if the FPU context is already
1164 * loaded. When disabling we leave the context
1165 * loaded so it can be quickly enabled again in
1166 * the near future.
1167 */
1168 if (change & ST0_CU1 &&
1169 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)
1170 change_c0_status(ST0_CU1, val);
1171
1172 preempt_enable();
1173
1174 kvm_write_c0_guest_status(cop0, val);
1175
1176 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1177 /*
1178 * If FPU present, we need CU1/FR bits to take
1179 * effect fairly soon.
1180 */
1181 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
1182 kvm_mips_trans_mtc0(inst, opc, vcpu);
1183 #endif
1184 } else if ((rd == MIPS_CP0_CONFIG) && (sel == 5)) {
1185 unsigned int old_val, val, change, wrmask;
1186
1187 old_val = kvm_read_c0_guest_config5(cop0);
1188 val = vcpu->arch.gprs[rt];
1189
1190 /* Only a few bits are writable in Config5 */
1191 wrmask = kvm_mips_config5_wrmask(vcpu);
1192 change = (val ^ old_val) & wrmask;
1193 val = old_val ^ change;
1194
1195
1196 /* Handle changes in FPU/MSA modes */
1197 preempt_disable();
1198
1199 /*
1200 * Propagate FRE changes immediately if the FPU
1201 * context is already loaded.
1202 */
1203 if (change & MIPS_CONF5_FRE &&
1204 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)
1205 change_c0_config5(MIPS_CONF5_FRE, val);
1206
1207 /*
1208 * Propagate MSAEn changes immediately if the
1209 * MSA context is already loaded. When disabling
1210 * we leave the context loaded so it can be
1211 * quickly enabled again in the near future.
1212 */
1213 if (change & MIPS_CONF5_MSAEN &&
1214 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA)
1215 change_c0_config5(MIPS_CONF5_MSAEN,
1216 val);
1217
1218 preempt_enable();
1219
1220 kvm_write_c0_guest_config5(cop0, val);
1221 } else if ((rd == MIPS_CP0_CAUSE) && (sel == 0)) {
1222 uint32_t old_cause, new_cause;
1223
1224 old_cause = kvm_read_c0_guest_cause(cop0);
1225 new_cause = vcpu->arch.gprs[rt];
1226 /* Update R/W bits */
1227 kvm_change_c0_guest_cause(cop0, 0x08800300,
1228 new_cause);
1229 /* DC bit enabling/disabling timer? */
1230 if ((old_cause ^ new_cause) & CAUSEF_DC) {
1231 if (new_cause & CAUSEF_DC)
1232 kvm_mips_count_disable_cause(vcpu);
1233 else
1234 kvm_mips_count_enable_cause(vcpu);
1235 }
1236 } else {
1237 cop0->reg[rd][sel] = vcpu->arch.gprs[rt];
1238 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1239 kvm_mips_trans_mtc0(inst, opc, vcpu);
1240 #endif
1241 }
1242
1243 kvm_debug("[%#x] MTCz, cop0->reg[%d][%d]: %#lx\n", pc,
1244 rd, sel, cop0->reg[rd][sel]);
1245 break;
1246
1247 case dmtc_op:
1248 kvm_err("!!!!!!![%#lx]dmtc_op: rt: %d, rd: %d, sel: %d!!!!!!\n",
1249 vcpu->arch.pc, rt, rd, sel);
1250 er = EMULATE_FAIL;
1251 break;
1252
1253 case mfmc0_op:
1254 #ifdef KVM_MIPS_DEBUG_COP0_COUNTERS
1255 cop0->stat[MIPS_CP0_STATUS][0]++;
1256 #endif
1257 if (rt != 0)
1258 vcpu->arch.gprs[rt] =
1259 kvm_read_c0_guest_status(cop0);
1260 /* EI */
1261 if (inst & 0x20) {
1262 kvm_debug("[%#lx] mfmc0_op: EI\n",
1263 vcpu->arch.pc);
1264 kvm_set_c0_guest_status(cop0, ST0_IE);
1265 } else {
1266 kvm_debug("[%#lx] mfmc0_op: DI\n",
1267 vcpu->arch.pc);
1268 kvm_clear_c0_guest_status(cop0, ST0_IE);
1269 }
1270
1271 break;
1272
1273 case wrpgpr_op:
1274 {
1275 uint32_t css =
1276 cop0->reg[MIPS_CP0_STATUS][2] & 0xf;
1277 uint32_t pss =
1278 (cop0->reg[MIPS_CP0_STATUS][2] >> 6) & 0xf;
1279 /*
1280 * We don't support any shadow register sets, so
1281 * SRSCtl[PSS] == SRSCtl[CSS] = 0
1282 */
1283 if (css || pss) {
1284 er = EMULATE_FAIL;
1285 break;
1286 }
1287 kvm_debug("WRPGPR[%d][%d] = %#lx\n", pss, rd,
1288 vcpu->arch.gprs[rt]);
1289 vcpu->arch.gprs[rd] = vcpu->arch.gprs[rt];
1290 }
1291 break;
1292 default:
1293 kvm_err("[%#lx]MachEmulateCP0: unsupported COP0, copz: 0x%x\n",
1294 vcpu->arch.pc, copz);
1295 er = EMULATE_FAIL;
1296 break;
1297 }
1298 }
1299
1300 done:
1301 /* Rollback PC only if emulation was unsuccessful */
1302 if (er == EMULATE_FAIL)
1303 vcpu->arch.pc = curr_pc;
1304
1305 dont_update_pc:
1306 /*
1307 * This is for special instructions whose emulation
1308 * updates the PC, so do not overwrite the PC under
1309 * any circumstances
1310 */
1311
1312 return er;
1313 }
1314
1315 enum emulation_result kvm_mips_emulate_store(uint32_t inst, uint32_t cause,
1316 struct kvm_run *run,
1317 struct kvm_vcpu *vcpu)
1318 {
1319 enum emulation_result er = EMULATE_DO_MMIO;
1320 int32_t op, base, rt, offset;
1321 uint32_t bytes;
1322 void *data = run->mmio.data;
1323 unsigned long curr_pc;
1324
1325 /*
1326 * Update PC and hold onto current PC in case there is
1327 * an error and we want to rollback the PC
1328 */
1329 curr_pc = vcpu->arch.pc;
1330 er = update_pc(vcpu, cause);
1331 if (er == EMULATE_FAIL)
1332 return er;
1333
1334 rt = (inst >> 16) & 0x1f;
1335 base = (inst >> 21) & 0x1f;
1336 offset = inst & 0xffff;
1337 op = (inst >> 26) & 0x3f;
1338
1339 switch (op) {
1340 case sb_op:
1341 bytes = 1;
1342 if (bytes > sizeof(run->mmio.data)) {
1343 kvm_err("%s: bad MMIO length: %d\n", __func__,
1344 run->mmio.len);
1345 }
1346 run->mmio.phys_addr =
1347 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1348 host_cp0_badvaddr);
1349 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1350 er = EMULATE_FAIL;
1351 break;
1352 }
1353 run->mmio.len = bytes;
1354 run->mmio.is_write = 1;
1355 vcpu->mmio_needed = 1;
1356 vcpu->mmio_is_write = 1;
1357 *(u8 *) data = vcpu->arch.gprs[rt];
1358 kvm_debug("OP_SB: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1359 vcpu->arch.host_cp0_badvaddr, vcpu->arch.gprs[rt],
1360 *(uint8_t *) data);
1361
1362 break;
1363
1364 case sw_op:
1365 bytes = 4;
1366 if (bytes > sizeof(run->mmio.data)) {
1367 kvm_err("%s: bad MMIO length: %d\n", __func__,
1368 run->mmio.len);
1369 }
1370 run->mmio.phys_addr =
1371 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1372 host_cp0_badvaddr);
1373 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1374 er = EMULATE_FAIL;
1375 break;
1376 }
1377
1378 run->mmio.len = bytes;
1379 run->mmio.is_write = 1;
1380 vcpu->mmio_needed = 1;
1381 vcpu->mmio_is_write = 1;
1382 *(uint32_t *) data = vcpu->arch.gprs[rt];
1383
1384 kvm_debug("[%#lx] OP_SW: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1385 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1386 vcpu->arch.gprs[rt], *(uint32_t *) data);
1387 break;
1388
1389 case sh_op:
1390 bytes = 2;
1391 if (bytes > sizeof(run->mmio.data)) {
1392 kvm_err("%s: bad MMIO length: %d\n", __func__,
1393 run->mmio.len);
1394 }
1395 run->mmio.phys_addr =
1396 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1397 host_cp0_badvaddr);
1398 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1399 er = EMULATE_FAIL;
1400 break;
1401 }
1402
1403 run->mmio.len = bytes;
1404 run->mmio.is_write = 1;
1405 vcpu->mmio_needed = 1;
1406 vcpu->mmio_is_write = 1;
1407 *(uint16_t *) data = vcpu->arch.gprs[rt];
1408
1409 kvm_debug("[%#lx] OP_SH: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1410 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1411 vcpu->arch.gprs[rt], *(uint32_t *) data);
1412 break;
1413
1414 default:
1415 kvm_err("Store not yet supported");
1416 er = EMULATE_FAIL;
1417 break;
1418 }
1419
1420 /* Rollback PC if emulation was unsuccessful */
1421 if (er == EMULATE_FAIL)
1422 vcpu->arch.pc = curr_pc;
1423
1424 return er;
1425 }
1426
1427 enum emulation_result kvm_mips_emulate_load(uint32_t inst, uint32_t cause,
1428 struct kvm_run *run,
1429 struct kvm_vcpu *vcpu)
1430 {
1431 enum emulation_result er = EMULATE_DO_MMIO;
1432 int32_t op, base, rt, offset;
1433 uint32_t bytes;
1434
1435 rt = (inst >> 16) & 0x1f;
1436 base = (inst >> 21) & 0x1f;
1437 offset = inst & 0xffff;
1438 op = (inst >> 26) & 0x3f;
1439
1440 vcpu->arch.pending_load_cause = cause;
1441 vcpu->arch.io_gpr = rt;
1442
1443 switch (op) {
1444 case lw_op:
1445 bytes = 4;
1446 if (bytes > sizeof(run->mmio.data)) {
1447 kvm_err("%s: bad MMIO length: %d\n", __func__,
1448 run->mmio.len);
1449 er = EMULATE_FAIL;
1450 break;
1451 }
1452 run->mmio.phys_addr =
1453 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1454 host_cp0_badvaddr);
1455 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1456 er = EMULATE_FAIL;
1457 break;
1458 }
1459
1460 run->mmio.len = bytes;
1461 run->mmio.is_write = 0;
1462 vcpu->mmio_needed = 1;
1463 vcpu->mmio_is_write = 0;
1464 break;
1465
1466 case lh_op:
1467 case lhu_op:
1468 bytes = 2;
1469 if (bytes > sizeof(run->mmio.data)) {
1470 kvm_err("%s: bad MMIO length: %d\n", __func__,
1471 run->mmio.len);
1472 er = EMULATE_FAIL;
1473 break;
1474 }
1475 run->mmio.phys_addr =
1476 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1477 host_cp0_badvaddr);
1478 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1479 er = EMULATE_FAIL;
1480 break;
1481 }
1482
1483 run->mmio.len = bytes;
1484 run->mmio.is_write = 0;
1485 vcpu->mmio_needed = 1;
1486 vcpu->mmio_is_write = 0;
1487
1488 if (op == lh_op)
1489 vcpu->mmio_needed = 2;
1490 else
1491 vcpu->mmio_needed = 1;
1492
1493 break;
1494
1495 case lbu_op:
1496 case lb_op:
1497 bytes = 1;
1498 if (bytes > sizeof(run->mmio.data)) {
1499 kvm_err("%s: bad MMIO length: %d\n", __func__,
1500 run->mmio.len);
1501 er = EMULATE_FAIL;
1502 break;
1503 }
1504 run->mmio.phys_addr =
1505 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1506 host_cp0_badvaddr);
1507 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1508 er = EMULATE_FAIL;
1509 break;
1510 }
1511
1512 run->mmio.len = bytes;
1513 run->mmio.is_write = 0;
1514 vcpu->mmio_is_write = 0;
1515
1516 if (op == lb_op)
1517 vcpu->mmio_needed = 2;
1518 else
1519 vcpu->mmio_needed = 1;
1520
1521 break;
1522
1523 default:
1524 kvm_err("Load not yet supported");
1525 er = EMULATE_FAIL;
1526 break;
1527 }
1528
1529 return er;
1530 }
1531
1532 int kvm_mips_sync_icache(unsigned long va, struct kvm_vcpu *vcpu)
1533 {
1534 unsigned long offset = (va & ~PAGE_MASK);
1535 struct kvm *kvm = vcpu->kvm;
1536 unsigned long pa;
1537 gfn_t gfn;
1538 kvm_pfn_t pfn;
1539
1540 gfn = va >> PAGE_SHIFT;
1541
1542 if (gfn >= kvm->arch.guest_pmap_npages) {
1543 kvm_err("%s: Invalid gfn: %#llx\n", __func__, gfn);
1544 kvm_mips_dump_host_tlbs();
1545 kvm_arch_vcpu_dump_regs(vcpu);
1546 return -1;
1547 }
1548 pfn = kvm->arch.guest_pmap[gfn];
1549 pa = (pfn << PAGE_SHIFT) | offset;
1550
1551 kvm_debug("%s: va: %#lx, unmapped: %#x\n", __func__, va,
1552 CKSEG0ADDR(pa));
1553
1554 local_flush_icache_range(CKSEG0ADDR(pa), 32);
1555 return 0;
1556 }
1557
1558 enum emulation_result kvm_mips_emulate_cache(uint32_t inst, uint32_t *opc,
1559 uint32_t cause,
1560 struct kvm_run *run,
1561 struct kvm_vcpu *vcpu)
1562 {
1563 struct mips_coproc *cop0 = vcpu->arch.cop0;
1564 enum emulation_result er = EMULATE_DONE;
1565 int32_t offset, cache, op_inst, op, base;
1566 struct kvm_vcpu_arch *arch = &vcpu->arch;
1567 unsigned long va;
1568 unsigned long curr_pc;
1569
1570 /*
1571 * Update PC and hold onto current PC in case there is
1572 * an error and we want to rollback the PC
1573 */
1574 curr_pc = vcpu->arch.pc;
1575 er = update_pc(vcpu, cause);
1576 if (er == EMULATE_FAIL)
1577 return er;
1578
1579 base = (inst >> 21) & 0x1f;
1580 op_inst = (inst >> 16) & 0x1f;
1581 offset = (int16_t)inst;
1582 cache = op_inst & CacheOp_Cache;
1583 op = op_inst & CacheOp_Op;
1584
1585 va = arch->gprs[base] + offset;
1586
1587 kvm_debug("CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1588 cache, op, base, arch->gprs[base], offset);
1589
1590 /*
1591 * Treat INDEX_INV as a nop, basically issued by Linux on startup to
1592 * invalidate the caches entirely by stepping through all the
1593 * ways/indexes
1594 */
1595 if (op == Index_Writeback_Inv) {
1596 kvm_debug("@ %#lx/%#lx CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1597 vcpu->arch.pc, vcpu->arch.gprs[31], cache, op, base,
1598 arch->gprs[base], offset);
1599
1600 if (cache == Cache_D)
1601 r4k_blast_dcache();
1602 else if (cache == Cache_I)
1603 r4k_blast_icache();
1604 else {
1605 kvm_err("%s: unsupported CACHE INDEX operation\n",
1606 __func__);
1607 return EMULATE_FAIL;
1608 }
1609
1610 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1611 kvm_mips_trans_cache_index(inst, opc, vcpu);
1612 #endif
1613 goto done;
1614 }
1615
1616 preempt_disable();
1617 if (KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG0) {
1618 if (kvm_mips_host_tlb_lookup(vcpu, va) < 0)
1619 kvm_mips_handle_kseg0_tlb_fault(va, vcpu);
1620 } else if ((KVM_GUEST_KSEGX(va) < KVM_GUEST_KSEG0) ||
1621 KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG23) {
1622 int index;
1623
1624 /* If an entry already exists then skip */
1625 if (kvm_mips_host_tlb_lookup(vcpu, va) >= 0)
1626 goto skip_fault;
1627
1628 /*
1629 * If address not in the guest TLB, then give the guest a fault,
1630 * the resulting handler will do the right thing
1631 */
1632 index = kvm_mips_guest_tlb_lookup(vcpu, (va & VPN2_MASK) |
1633 (kvm_read_c0_guest_entryhi
1634 (cop0) & KVM_ENTRYHI_ASID));
1635
1636 if (index < 0) {
1637 vcpu->arch.host_cp0_entryhi = (va & VPN2_MASK);
1638 vcpu->arch.host_cp0_badvaddr = va;
1639 vcpu->arch.pc = curr_pc;
1640 er = kvm_mips_emulate_tlbmiss_ld(cause, NULL, run,
1641 vcpu);
1642 preempt_enable();
1643 goto dont_update_pc;
1644 } else {
1645 struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index];
1646 /*
1647 * Check if the entry is valid, if not then setup a TLB
1648 * invalid exception to the guest
1649 */
1650 if (!TLB_IS_VALID(*tlb, va)) {
1651 vcpu->arch.host_cp0_badvaddr = va;
1652 vcpu->arch.pc = curr_pc;
1653 er = kvm_mips_emulate_tlbinv_ld(cause, NULL,
1654 run, vcpu);
1655 preempt_enable();
1656 goto dont_update_pc;
1657 } else {
1658 /*
1659 * We fault an entry from the guest tlb to the
1660 * shadow host TLB
1661 */
1662 kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb,
1663 NULL,
1664 NULL);
1665 }
1666 }
1667 } else {
1668 kvm_err("INVALID CACHE INDEX/ADDRESS (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1669 cache, op, base, arch->gprs[base], offset);
1670 er = EMULATE_FAIL;
1671 preempt_enable();
1672 goto done;
1673
1674 }
1675
1676 skip_fault:
1677 /* XXXKYMA: Only a subset of cache ops are supported, used by Linux */
1678 if (op_inst == Hit_Writeback_Inv_D || op_inst == Hit_Invalidate_D) {
1679 flush_dcache_line(va);
1680
1681 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1682 /*
1683 * Replace the CACHE instruction, with a SYNCI, not the same,
1684 * but avoids a trap
1685 */
1686 kvm_mips_trans_cache_va(inst, opc, vcpu);
1687 #endif
1688 } else if (op_inst == Hit_Invalidate_I) {
1689 flush_dcache_line(va);
1690 flush_icache_line(va);
1691
1692 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1693 /* Replace the CACHE instruction, with a SYNCI */
1694 kvm_mips_trans_cache_va(inst, opc, vcpu);
1695 #endif
1696 } else {
1697 kvm_err("NO-OP CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1698 cache, op, base, arch->gprs[base], offset);
1699 er = EMULATE_FAIL;
1700 }
1701
1702 preempt_enable();
1703 done:
1704 /* Rollback PC only if emulation was unsuccessful */
1705 if (er == EMULATE_FAIL)
1706 vcpu->arch.pc = curr_pc;
1707
1708 dont_update_pc:
1709 /*
1710 * This is for exceptions whose emulation updates the PC, so do not
1711 * overwrite the PC under any circumstances
1712 */
1713
1714 return er;
1715 }
1716
1717 enum emulation_result kvm_mips_emulate_inst(unsigned long cause, uint32_t *opc,
1718 struct kvm_run *run,
1719 struct kvm_vcpu *vcpu)
1720 {
1721 enum emulation_result er = EMULATE_DONE;
1722 uint32_t inst;
1723
1724 /* Fetch the instruction. */
1725 if (cause & CAUSEF_BD)
1726 opc += 1;
1727
1728 inst = kvm_get_inst(opc, vcpu);
1729
1730 switch (((union mips_instruction)inst).r_format.opcode) {
1731 case cop0_op:
1732 er = kvm_mips_emulate_CP0(inst, opc, cause, run, vcpu);
1733 break;
1734 case sb_op:
1735 case sh_op:
1736 case sw_op:
1737 er = kvm_mips_emulate_store(inst, cause, run, vcpu);
1738 break;
1739 case lb_op:
1740 case lbu_op:
1741 case lhu_op:
1742 case lh_op:
1743 case lw_op:
1744 er = kvm_mips_emulate_load(inst, cause, run, vcpu);
1745 break;
1746
1747 case cache_op:
1748 ++vcpu->stat.cache_exits;
1749 trace_kvm_exit(vcpu, CACHE_EXITS);
1750 er = kvm_mips_emulate_cache(inst, opc, cause, run, vcpu);
1751 break;
1752
1753 default:
1754 kvm_err("Instruction emulation not supported (%p/%#x)\n", opc,
1755 inst);
1756 kvm_arch_vcpu_dump_regs(vcpu);
1757 er = EMULATE_FAIL;
1758 break;
1759 }
1760
1761 return er;
1762 }
1763
1764 enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
1765 uint32_t *opc,
1766 struct kvm_run *run,
1767 struct kvm_vcpu *vcpu)
1768 {
1769 struct mips_coproc *cop0 = vcpu->arch.cop0;
1770 struct kvm_vcpu_arch *arch = &vcpu->arch;
1771 enum emulation_result er = EMULATE_DONE;
1772
1773 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1774 /* save old pc */
1775 kvm_write_c0_guest_epc(cop0, arch->pc);
1776 kvm_set_c0_guest_status(cop0, ST0_EXL);
1777
1778 if (cause & CAUSEF_BD)
1779 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1780 else
1781 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1782
1783 kvm_debug("Delivering SYSCALL @ pc %#lx\n", arch->pc);
1784
1785 kvm_change_c0_guest_cause(cop0, (0xff),
1786 (EXCCODE_SYS << CAUSEB_EXCCODE));
1787
1788 /* Set PC to the exception entry point */
1789 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1790
1791 } else {
1792 kvm_err("Trying to deliver SYSCALL when EXL is already set\n");
1793 er = EMULATE_FAIL;
1794 }
1795
1796 return er;
1797 }
1798
1799 enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
1800 uint32_t *opc,
1801 struct kvm_run *run,
1802 struct kvm_vcpu *vcpu)
1803 {
1804 struct mips_coproc *cop0 = vcpu->arch.cop0;
1805 struct kvm_vcpu_arch *arch = &vcpu->arch;
1806 unsigned long entryhi = (vcpu->arch. host_cp0_badvaddr & VPN2_MASK) |
1807 (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
1808
1809 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1810 /* save old pc */
1811 kvm_write_c0_guest_epc(cop0, arch->pc);
1812 kvm_set_c0_guest_status(cop0, ST0_EXL);
1813
1814 if (cause & CAUSEF_BD)
1815 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1816 else
1817 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1818
1819 kvm_debug("[EXL == 0] delivering TLB MISS @ pc %#lx\n",
1820 arch->pc);
1821
1822 /* set pc to the exception entry point */
1823 arch->pc = KVM_GUEST_KSEG0 + 0x0;
1824
1825 } else {
1826 kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n",
1827 arch->pc);
1828
1829 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1830 }
1831
1832 kvm_change_c0_guest_cause(cop0, (0xff),
1833 (EXCCODE_TLBL << CAUSEB_EXCCODE));
1834
1835 /* setup badvaddr, context and entryhi registers for the guest */
1836 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
1837 /* XXXKYMA: is the context register used by linux??? */
1838 kvm_write_c0_guest_entryhi(cop0, entryhi);
1839 /* Blow away the shadow host TLBs */
1840 kvm_mips_flush_host_tlb(1);
1841
1842 return EMULATE_DONE;
1843 }
1844
1845 enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
1846 uint32_t *opc,
1847 struct kvm_run *run,
1848 struct kvm_vcpu *vcpu)
1849 {
1850 struct mips_coproc *cop0 = vcpu->arch.cop0;
1851 struct kvm_vcpu_arch *arch = &vcpu->arch;
1852 unsigned long entryhi =
1853 (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1854 (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
1855
1856 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1857 /* save old pc */
1858 kvm_write_c0_guest_epc(cop0, arch->pc);
1859 kvm_set_c0_guest_status(cop0, ST0_EXL);
1860
1861 if (cause & CAUSEF_BD)
1862 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1863 else
1864 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1865
1866 kvm_debug("[EXL == 0] delivering TLB INV @ pc %#lx\n",
1867 arch->pc);
1868
1869 /* set pc to the exception entry point */
1870 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1871
1872 } else {
1873 kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n",
1874 arch->pc);
1875 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1876 }
1877
1878 kvm_change_c0_guest_cause(cop0, (0xff),
1879 (EXCCODE_TLBL << CAUSEB_EXCCODE));
1880
1881 /* setup badvaddr, context and entryhi registers for the guest */
1882 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
1883 /* XXXKYMA: is the context register used by linux??? */
1884 kvm_write_c0_guest_entryhi(cop0, entryhi);
1885 /* Blow away the shadow host TLBs */
1886 kvm_mips_flush_host_tlb(1);
1887
1888 return EMULATE_DONE;
1889 }
1890
1891 enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
1892 uint32_t *opc,
1893 struct kvm_run *run,
1894 struct kvm_vcpu *vcpu)
1895 {
1896 struct mips_coproc *cop0 = vcpu->arch.cop0;
1897 struct kvm_vcpu_arch *arch = &vcpu->arch;
1898 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1899 (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
1900
1901 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1902 /* save old pc */
1903 kvm_write_c0_guest_epc(cop0, arch->pc);
1904 kvm_set_c0_guest_status(cop0, ST0_EXL);
1905
1906 if (cause & CAUSEF_BD)
1907 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1908 else
1909 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1910
1911 kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n",
1912 arch->pc);
1913
1914 /* Set PC to the exception entry point */
1915 arch->pc = KVM_GUEST_KSEG0 + 0x0;
1916 } else {
1917 kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n",
1918 arch->pc);
1919 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1920 }
1921
1922 kvm_change_c0_guest_cause(cop0, (0xff),
1923 (EXCCODE_TLBS << CAUSEB_EXCCODE));
1924
1925 /* setup badvaddr, context and entryhi registers for the guest */
1926 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
1927 /* XXXKYMA: is the context register used by linux??? */
1928 kvm_write_c0_guest_entryhi(cop0, entryhi);
1929 /* Blow away the shadow host TLBs */
1930 kvm_mips_flush_host_tlb(1);
1931
1932 return EMULATE_DONE;
1933 }
1934
1935 enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
1936 uint32_t *opc,
1937 struct kvm_run *run,
1938 struct kvm_vcpu *vcpu)
1939 {
1940 struct mips_coproc *cop0 = vcpu->arch.cop0;
1941 struct kvm_vcpu_arch *arch = &vcpu->arch;
1942 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1943 (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
1944
1945 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1946 /* save old pc */
1947 kvm_write_c0_guest_epc(cop0, arch->pc);
1948 kvm_set_c0_guest_status(cop0, ST0_EXL);
1949
1950 if (cause & CAUSEF_BD)
1951 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1952 else
1953 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1954
1955 kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n",
1956 arch->pc);
1957
1958 /* Set PC to the exception entry point */
1959 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1960 } else {
1961 kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n",
1962 arch->pc);
1963 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1964 }
1965
1966 kvm_change_c0_guest_cause(cop0, (0xff),
1967 (EXCCODE_TLBS << CAUSEB_EXCCODE));
1968
1969 /* setup badvaddr, context and entryhi registers for the guest */
1970 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
1971 /* XXXKYMA: is the context register used by linux??? */
1972 kvm_write_c0_guest_entryhi(cop0, entryhi);
1973 /* Blow away the shadow host TLBs */
1974 kvm_mips_flush_host_tlb(1);
1975
1976 return EMULATE_DONE;
1977 }
1978
1979 /* TLBMOD: store into address matching TLB with Dirty bit off */
1980 enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause, uint32_t *opc,
1981 struct kvm_run *run,
1982 struct kvm_vcpu *vcpu)
1983 {
1984 enum emulation_result er = EMULATE_DONE;
1985 #ifdef DEBUG
1986 struct mips_coproc *cop0 = vcpu->arch.cop0;
1987 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1988 (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
1989 int index;
1990
1991 /* If address not in the guest TLB, then we are in trouble */
1992 index = kvm_mips_guest_tlb_lookup(vcpu, entryhi);
1993 if (index < 0) {
1994 /* XXXKYMA Invalidate and retry */
1995 kvm_mips_host_tlb_inv(vcpu, vcpu->arch.host_cp0_badvaddr);
1996 kvm_err("%s: host got TLBMOD for %#lx but entry not present in Guest TLB\n",
1997 __func__, entryhi);
1998 kvm_mips_dump_guest_tlbs(vcpu);
1999 kvm_mips_dump_host_tlbs();
2000 return EMULATE_FAIL;
2001 }
2002 #endif
2003
2004 er = kvm_mips_emulate_tlbmod(cause, opc, run, vcpu);
2005 return er;
2006 }
2007
2008 enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
2009 uint32_t *opc,
2010 struct kvm_run *run,
2011 struct kvm_vcpu *vcpu)
2012 {
2013 struct mips_coproc *cop0 = vcpu->arch.cop0;
2014 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
2015 (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
2016 struct kvm_vcpu_arch *arch = &vcpu->arch;
2017
2018 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2019 /* save old pc */
2020 kvm_write_c0_guest_epc(cop0, arch->pc);
2021 kvm_set_c0_guest_status(cop0, ST0_EXL);
2022
2023 if (cause & CAUSEF_BD)
2024 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2025 else
2026 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2027
2028 kvm_debug("[EXL == 0] Delivering TLB MOD @ pc %#lx\n",
2029 arch->pc);
2030
2031 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2032 } else {
2033 kvm_debug("[EXL == 1] Delivering TLB MOD @ pc %#lx\n",
2034 arch->pc);
2035 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2036 }
2037
2038 kvm_change_c0_guest_cause(cop0, (0xff),
2039 (EXCCODE_MOD << CAUSEB_EXCCODE));
2040
2041 /* setup badvaddr, context and entryhi registers for the guest */
2042 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
2043 /* XXXKYMA: is the context register used by linux??? */
2044 kvm_write_c0_guest_entryhi(cop0, entryhi);
2045 /* Blow away the shadow host TLBs */
2046 kvm_mips_flush_host_tlb(1);
2047
2048 return EMULATE_DONE;
2049 }
2050
2051 enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
2052 uint32_t *opc,
2053 struct kvm_run *run,
2054 struct kvm_vcpu *vcpu)
2055 {
2056 struct mips_coproc *cop0 = vcpu->arch.cop0;
2057 struct kvm_vcpu_arch *arch = &vcpu->arch;
2058
2059 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2060 /* save old pc */
2061 kvm_write_c0_guest_epc(cop0, arch->pc);
2062 kvm_set_c0_guest_status(cop0, ST0_EXL);
2063
2064 if (cause & CAUSEF_BD)
2065 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2066 else
2067 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2068
2069 }
2070
2071 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2072
2073 kvm_change_c0_guest_cause(cop0, (0xff),
2074 (EXCCODE_CPU << CAUSEB_EXCCODE));
2075 kvm_change_c0_guest_cause(cop0, (CAUSEF_CE), (0x1 << CAUSEB_CE));
2076
2077 return EMULATE_DONE;
2078 }
2079
2080 enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
2081 uint32_t *opc,
2082 struct kvm_run *run,
2083 struct kvm_vcpu *vcpu)
2084 {
2085 struct mips_coproc *cop0 = vcpu->arch.cop0;
2086 struct kvm_vcpu_arch *arch = &vcpu->arch;
2087 enum emulation_result er = EMULATE_DONE;
2088
2089 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2090 /* save old pc */
2091 kvm_write_c0_guest_epc(cop0, arch->pc);
2092 kvm_set_c0_guest_status(cop0, ST0_EXL);
2093
2094 if (cause & CAUSEF_BD)
2095 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2096 else
2097 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2098
2099 kvm_debug("Delivering RI @ pc %#lx\n", arch->pc);
2100
2101 kvm_change_c0_guest_cause(cop0, (0xff),
2102 (EXCCODE_RI << CAUSEB_EXCCODE));
2103
2104 /* Set PC to the exception entry point */
2105 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2106
2107 } else {
2108 kvm_err("Trying to deliver RI when EXL is already set\n");
2109 er = EMULATE_FAIL;
2110 }
2111
2112 return er;
2113 }
2114
2115 enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
2116 uint32_t *opc,
2117 struct kvm_run *run,
2118 struct kvm_vcpu *vcpu)
2119 {
2120 struct mips_coproc *cop0 = vcpu->arch.cop0;
2121 struct kvm_vcpu_arch *arch = &vcpu->arch;
2122 enum emulation_result er = EMULATE_DONE;
2123
2124 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2125 /* save old pc */
2126 kvm_write_c0_guest_epc(cop0, arch->pc);
2127 kvm_set_c0_guest_status(cop0, ST0_EXL);
2128
2129 if (cause & CAUSEF_BD)
2130 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2131 else
2132 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2133
2134 kvm_debug("Delivering BP @ pc %#lx\n", arch->pc);
2135
2136 kvm_change_c0_guest_cause(cop0, (0xff),
2137 (EXCCODE_BP << CAUSEB_EXCCODE));
2138
2139 /* Set PC to the exception entry point */
2140 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2141
2142 } else {
2143 kvm_err("Trying to deliver BP when EXL is already set\n");
2144 er = EMULATE_FAIL;
2145 }
2146
2147 return er;
2148 }
2149
2150 enum emulation_result kvm_mips_emulate_trap_exc(unsigned long cause,
2151 uint32_t *opc,
2152 struct kvm_run *run,
2153 struct kvm_vcpu *vcpu)
2154 {
2155 struct mips_coproc *cop0 = vcpu->arch.cop0;
2156 struct kvm_vcpu_arch *arch = &vcpu->arch;
2157 enum emulation_result er = EMULATE_DONE;
2158
2159 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2160 /* save old pc */
2161 kvm_write_c0_guest_epc(cop0, arch->pc);
2162 kvm_set_c0_guest_status(cop0, ST0_EXL);
2163
2164 if (cause & CAUSEF_BD)
2165 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2166 else
2167 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2168
2169 kvm_debug("Delivering TRAP @ pc %#lx\n", arch->pc);
2170
2171 kvm_change_c0_guest_cause(cop0, (0xff),
2172 (EXCCODE_TR << CAUSEB_EXCCODE));
2173
2174 /* Set PC to the exception entry point */
2175 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2176
2177 } else {
2178 kvm_err("Trying to deliver TRAP when EXL is already set\n");
2179 er = EMULATE_FAIL;
2180 }
2181
2182 return er;
2183 }
2184
2185 enum emulation_result kvm_mips_emulate_msafpe_exc(unsigned long cause,
2186 uint32_t *opc,
2187 struct kvm_run *run,
2188 struct kvm_vcpu *vcpu)
2189 {
2190 struct mips_coproc *cop0 = vcpu->arch.cop0;
2191 struct kvm_vcpu_arch *arch = &vcpu->arch;
2192 enum emulation_result er = EMULATE_DONE;
2193
2194 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2195 /* save old pc */
2196 kvm_write_c0_guest_epc(cop0, arch->pc);
2197 kvm_set_c0_guest_status(cop0, ST0_EXL);
2198
2199 if (cause & CAUSEF_BD)
2200 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2201 else
2202 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2203
2204 kvm_debug("Delivering MSAFPE @ pc %#lx\n", arch->pc);
2205
2206 kvm_change_c0_guest_cause(cop0, (0xff),
2207 (EXCCODE_MSAFPE << CAUSEB_EXCCODE));
2208
2209 /* Set PC to the exception entry point */
2210 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2211
2212 } else {
2213 kvm_err("Trying to deliver MSAFPE when EXL is already set\n");
2214 er = EMULATE_FAIL;
2215 }
2216
2217 return er;
2218 }
2219
2220 enum emulation_result kvm_mips_emulate_fpe_exc(unsigned long cause,
2221 uint32_t *opc,
2222 struct kvm_run *run,
2223 struct kvm_vcpu *vcpu)
2224 {
2225 struct mips_coproc *cop0 = vcpu->arch.cop0;
2226 struct kvm_vcpu_arch *arch = &vcpu->arch;
2227 enum emulation_result er = EMULATE_DONE;
2228
2229 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2230 /* save old pc */
2231 kvm_write_c0_guest_epc(cop0, arch->pc);
2232 kvm_set_c0_guest_status(cop0, ST0_EXL);
2233
2234 if (cause & CAUSEF_BD)
2235 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2236 else
2237 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2238
2239 kvm_debug("Delivering FPE @ pc %#lx\n", arch->pc);
2240
2241 kvm_change_c0_guest_cause(cop0, (0xff),
2242 (EXCCODE_FPE << CAUSEB_EXCCODE));
2243
2244 /* Set PC to the exception entry point */
2245 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2246
2247 } else {
2248 kvm_err("Trying to deliver FPE when EXL is already set\n");
2249 er = EMULATE_FAIL;
2250 }
2251
2252 return er;
2253 }
2254
2255 enum emulation_result kvm_mips_emulate_msadis_exc(unsigned long cause,
2256 uint32_t *opc,
2257 struct kvm_run *run,
2258 struct kvm_vcpu *vcpu)
2259 {
2260 struct mips_coproc *cop0 = vcpu->arch.cop0;
2261 struct kvm_vcpu_arch *arch = &vcpu->arch;
2262 enum emulation_result er = EMULATE_DONE;
2263
2264 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2265 /* save old pc */
2266 kvm_write_c0_guest_epc(cop0, arch->pc);
2267 kvm_set_c0_guest_status(cop0, ST0_EXL);
2268
2269 if (cause & CAUSEF_BD)
2270 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2271 else
2272 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2273
2274 kvm_debug("Delivering MSADIS @ pc %#lx\n", arch->pc);
2275
2276 kvm_change_c0_guest_cause(cop0, (0xff),
2277 (EXCCODE_MSADIS << CAUSEB_EXCCODE));
2278
2279 /* Set PC to the exception entry point */
2280 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2281
2282 } else {
2283 kvm_err("Trying to deliver MSADIS when EXL is already set\n");
2284 er = EMULATE_FAIL;
2285 }
2286
2287 return er;
2288 }
2289
2290 /* ll/sc, rdhwr, sync emulation */
2291
2292 #define OPCODE 0xfc000000
2293 #define BASE 0x03e00000
2294 #define RT 0x001f0000
2295 #define OFFSET 0x0000ffff
2296 #define LL 0xc0000000
2297 #define SC 0xe0000000
2298 #define SPEC0 0x00000000
2299 #define SPEC3 0x7c000000
2300 #define RD 0x0000f800
2301 #define FUNC 0x0000003f
2302 #define SYNC 0x0000000f
2303 #define RDHWR 0x0000003b
2304
2305 enum emulation_result kvm_mips_handle_ri(unsigned long cause, uint32_t *opc,
2306 struct kvm_run *run,
2307 struct kvm_vcpu *vcpu)
2308 {
2309 struct mips_coproc *cop0 = vcpu->arch.cop0;
2310 struct kvm_vcpu_arch *arch = &vcpu->arch;
2311 enum emulation_result er = EMULATE_DONE;
2312 unsigned long curr_pc;
2313 uint32_t inst;
2314
2315 /*
2316 * Update PC and hold onto current PC in case there is
2317 * an error and we want to rollback the PC
2318 */
2319 curr_pc = vcpu->arch.pc;
2320 er = update_pc(vcpu, cause);
2321 if (er == EMULATE_FAIL)
2322 return er;
2323
2324 /* Fetch the instruction. */
2325 if (cause & CAUSEF_BD)
2326 opc += 1;
2327
2328 inst = kvm_get_inst(opc, vcpu);
2329
2330 if (inst == KVM_INVALID_INST) {
2331 kvm_err("%s: Cannot get inst @ %p\n", __func__, opc);
2332 return EMULATE_FAIL;
2333 }
2334
2335 if ((inst & OPCODE) == SPEC3 && (inst & FUNC) == RDHWR) {
2336 int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
2337 int rd = (inst & RD) >> 11;
2338 int rt = (inst & RT) >> 16;
2339 /* If usermode, check RDHWR rd is allowed by guest HWREna */
2340 if (usermode && !(kvm_read_c0_guest_hwrena(cop0) & BIT(rd))) {
2341 kvm_debug("RDHWR %#x disallowed by HWREna @ %p\n",
2342 rd, opc);
2343 goto emulate_ri;
2344 }
2345 switch (rd) {
2346 case 0: /* CPU number */
2347 arch->gprs[rt] = 0;
2348 break;
2349 case 1: /* SYNCI length */
2350 arch->gprs[rt] = min(current_cpu_data.dcache.linesz,
2351 current_cpu_data.icache.linesz);
2352 break;
2353 case 2: /* Read count register */
2354 arch->gprs[rt] = kvm_mips_read_count(vcpu);
2355 break;
2356 case 3: /* Count register resolution */
2357 switch (current_cpu_data.cputype) {
2358 case CPU_20KC:
2359 case CPU_25KF:
2360 arch->gprs[rt] = 1;
2361 break;
2362 default:
2363 arch->gprs[rt] = 2;
2364 }
2365 break;
2366 case 29:
2367 arch->gprs[rt] = kvm_read_c0_guest_userlocal(cop0);
2368 break;
2369
2370 default:
2371 kvm_debug("RDHWR %#x not supported @ %p\n", rd, opc);
2372 goto emulate_ri;
2373 }
2374 } else {
2375 kvm_debug("Emulate RI not supported @ %p: %#x\n", opc, inst);
2376 goto emulate_ri;
2377 }
2378
2379 return EMULATE_DONE;
2380
2381 emulate_ri:
2382 /*
2383 * Rollback PC (if in branch delay slot then the PC already points to
2384 * branch target), and pass the RI exception to the guest OS.
2385 */
2386 vcpu->arch.pc = curr_pc;
2387 return kvm_mips_emulate_ri_exc(cause, opc, run, vcpu);
2388 }
2389
2390 enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
2391 struct kvm_run *run)
2392 {
2393 unsigned long *gpr = &vcpu->arch.gprs[vcpu->arch.io_gpr];
2394 enum emulation_result er = EMULATE_DONE;
2395
2396 if (run->mmio.len > sizeof(*gpr)) {
2397 kvm_err("Bad MMIO length: %d", run->mmio.len);
2398 er = EMULATE_FAIL;
2399 goto done;
2400 }
2401
2402 er = update_pc(vcpu, vcpu->arch.pending_load_cause);
2403 if (er == EMULATE_FAIL)
2404 return er;
2405
2406 switch (run->mmio.len) {
2407 case 4:
2408 *gpr = *(int32_t *) run->mmio.data;
2409 break;
2410
2411 case 2:
2412 if (vcpu->mmio_needed == 2)
2413 *gpr = *(int16_t *) run->mmio.data;
2414 else
2415 *gpr = *(uint16_t *)run->mmio.data;
2416
2417 break;
2418 case 1:
2419 if (vcpu->mmio_needed == 2)
2420 *gpr = *(int8_t *) run->mmio.data;
2421 else
2422 *gpr = *(u8 *) run->mmio.data;
2423 break;
2424 }
2425
2426 if (vcpu->arch.pending_load_cause & CAUSEF_BD)
2427 kvm_debug("[%#lx] Completing %d byte BD Load to gpr %d (0x%08lx) type %d\n",
2428 vcpu->arch.pc, run->mmio.len, vcpu->arch.io_gpr, *gpr,
2429 vcpu->mmio_needed);
2430
2431 done:
2432 return er;
2433 }
2434
2435 static enum emulation_result kvm_mips_emulate_exc(unsigned long cause,
2436 uint32_t *opc,
2437 struct kvm_run *run,
2438 struct kvm_vcpu *vcpu)
2439 {
2440 uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
2441 struct mips_coproc *cop0 = vcpu->arch.cop0;
2442 struct kvm_vcpu_arch *arch = &vcpu->arch;
2443 enum emulation_result er = EMULATE_DONE;
2444
2445 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2446 /* save old pc */
2447 kvm_write_c0_guest_epc(cop0, arch->pc);
2448 kvm_set_c0_guest_status(cop0, ST0_EXL);
2449
2450 if (cause & CAUSEF_BD)
2451 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2452 else
2453 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2454
2455 kvm_change_c0_guest_cause(cop0, (0xff),
2456 (exccode << CAUSEB_EXCCODE));
2457
2458 /* Set PC to the exception entry point */
2459 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2460 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
2461
2462 kvm_debug("Delivering EXC %d @ pc %#lx, badVaddr: %#lx\n",
2463 exccode, kvm_read_c0_guest_epc(cop0),
2464 kvm_read_c0_guest_badvaddr(cop0));
2465 } else {
2466 kvm_err("Trying to deliver EXC when EXL is already set\n");
2467 er = EMULATE_FAIL;
2468 }
2469
2470 return er;
2471 }
2472
2473 enum emulation_result kvm_mips_check_privilege(unsigned long cause,
2474 uint32_t *opc,
2475 struct kvm_run *run,
2476 struct kvm_vcpu *vcpu)
2477 {
2478 enum emulation_result er = EMULATE_DONE;
2479 uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
2480 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
2481
2482 int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
2483
2484 if (usermode) {
2485 switch (exccode) {
2486 case EXCCODE_INT:
2487 case EXCCODE_SYS:
2488 case EXCCODE_BP:
2489 case EXCCODE_RI:
2490 case EXCCODE_TR:
2491 case EXCCODE_MSAFPE:
2492 case EXCCODE_FPE:
2493 case EXCCODE_MSADIS:
2494 break;
2495
2496 case EXCCODE_CPU:
2497 if (((cause & CAUSEF_CE) >> CAUSEB_CE) == 0)
2498 er = EMULATE_PRIV_FAIL;
2499 break;
2500
2501 case EXCCODE_MOD:
2502 break;
2503
2504 case EXCCODE_TLBL:
2505 /*
2506 * We we are accessing Guest kernel space, then send an
2507 * address error exception to the guest
2508 */
2509 if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) {
2510 kvm_debug("%s: LD MISS @ %#lx\n", __func__,
2511 badvaddr);
2512 cause &= ~0xff;
2513 cause |= (EXCCODE_ADEL << CAUSEB_EXCCODE);
2514 er = EMULATE_PRIV_FAIL;
2515 }
2516 break;
2517
2518 case EXCCODE_TLBS:
2519 /*
2520 * We we are accessing Guest kernel space, then send an
2521 * address error exception to the guest
2522 */
2523 if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) {
2524 kvm_debug("%s: ST MISS @ %#lx\n", __func__,
2525 badvaddr);
2526 cause &= ~0xff;
2527 cause |= (EXCCODE_ADES << CAUSEB_EXCCODE);
2528 er = EMULATE_PRIV_FAIL;
2529 }
2530 break;
2531
2532 case EXCCODE_ADES:
2533 kvm_debug("%s: address error ST @ %#lx\n", __func__,
2534 badvaddr);
2535 if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) {
2536 cause &= ~0xff;
2537 cause |= (EXCCODE_TLBS << CAUSEB_EXCCODE);
2538 }
2539 er = EMULATE_PRIV_FAIL;
2540 break;
2541 case EXCCODE_ADEL:
2542 kvm_debug("%s: address error LD @ %#lx\n", __func__,
2543 badvaddr);
2544 if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) {
2545 cause &= ~0xff;
2546 cause |= (EXCCODE_TLBL << CAUSEB_EXCCODE);
2547 }
2548 er = EMULATE_PRIV_FAIL;
2549 break;
2550 default:
2551 er = EMULATE_PRIV_FAIL;
2552 break;
2553 }
2554 }
2555
2556 if (er == EMULATE_PRIV_FAIL)
2557 kvm_mips_emulate_exc(cause, opc, run, vcpu);
2558
2559 return er;
2560 }
2561
2562 /*
2563 * User Address (UA) fault, this could happen if
2564 * (1) TLB entry not present/valid in both Guest and shadow host TLBs, in this
2565 * case we pass on the fault to the guest kernel and let it handle it.
2566 * (2) TLB entry is present in the Guest TLB but not in the shadow, in this
2567 * case we inject the TLB from the Guest TLB into the shadow host TLB
2568 */
2569 enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
2570 uint32_t *opc,
2571 struct kvm_run *run,
2572 struct kvm_vcpu *vcpu)
2573 {
2574 enum emulation_result er = EMULATE_DONE;
2575 uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
2576 unsigned long va = vcpu->arch.host_cp0_badvaddr;
2577 int index;
2578
2579 kvm_debug("kvm_mips_handle_tlbmiss: badvaddr: %#lx, entryhi: %#lx\n",
2580 vcpu->arch.host_cp0_badvaddr, vcpu->arch.host_cp0_entryhi);
2581
2582 /*
2583 * KVM would not have got the exception if this entry was valid in the
2584 * shadow host TLB. Check the Guest TLB, if the entry is not there then
2585 * send the guest an exception. The guest exc handler should then inject
2586 * an entry into the guest TLB.
2587 */
2588 index = kvm_mips_guest_tlb_lookup(vcpu,
2589 (va & VPN2_MASK) |
2590 (kvm_read_c0_guest_entryhi(vcpu->arch.cop0) &
2591 KVM_ENTRYHI_ASID));
2592 if (index < 0) {
2593 if (exccode == EXCCODE_TLBL) {
2594 er = kvm_mips_emulate_tlbmiss_ld(cause, opc, run, vcpu);
2595 } else if (exccode == EXCCODE_TLBS) {
2596 er = kvm_mips_emulate_tlbmiss_st(cause, opc, run, vcpu);
2597 } else {
2598 kvm_err("%s: invalid exc code: %d\n", __func__,
2599 exccode);
2600 er = EMULATE_FAIL;
2601 }
2602 } else {
2603 struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index];
2604
2605 /*
2606 * Check if the entry is valid, if not then setup a TLB invalid
2607 * exception to the guest
2608 */
2609 if (!TLB_IS_VALID(*tlb, va)) {
2610 if (exccode == EXCCODE_TLBL) {
2611 er = kvm_mips_emulate_tlbinv_ld(cause, opc, run,
2612 vcpu);
2613 } else if (exccode == EXCCODE_TLBS) {
2614 er = kvm_mips_emulate_tlbinv_st(cause, opc, run,
2615 vcpu);
2616 } else {
2617 kvm_err("%s: invalid exc code: %d\n", __func__,
2618 exccode);
2619 er = EMULATE_FAIL;
2620 }
2621 } else {
2622 kvm_debug("Injecting hi: %#lx, lo0: %#lx, lo1: %#lx into shadow host TLB\n",
2623 tlb->tlb_hi, tlb->tlb_lo0, tlb->tlb_lo1);
2624 /*
2625 * OK we have a Guest TLB entry, now inject it into the
2626 * shadow host TLB
2627 */
2628 kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb, NULL,
2629 NULL);
2630 }
2631 }
2632
2633 return er;
2634 }
Linux kernel - Deliverables
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