arch/powerpc/include/asm/pci-bridge.h

   1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
   2 #define _ASM_POWERPC_PCI_BRIDGE_H
   3 #ifdef __KERNEL__
   4 /*
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  */
  10 #include <linux/pci.h>
  11 #include <linux/list.h>
  12 #include <linux/ioport.h>
  13
  14 struct device_node;
  15
  16 /*
  17  * PCI controller operations
  18  */
  19 struct pci_controller_ops {
  20         void            (*dma_dev_setup)(struct pci_dev *dev);
  21         void            (*dma_bus_setup)(struct pci_bus *bus);
  22
  23         int             (*probe_mode)(struct pci_bus *);
  24
  25         /* Called when pci_enable_device() is called. Returns true to
  26          * allow assignment/enabling of the device. */
  27         bool            (*enable_device_hook)(struct pci_dev *);
  28
  29         void            (*disable_device)(struct pci_dev *);
  30
  31         void            (*release_device)(struct pci_dev *);
  32
  33         /* Called during PCI resource reassignment */
  34         resource_size_t (*window_alignment)(struct pci_bus *, unsigned long type);
  35         void            (*reset_secondary_bus)(struct pci_dev *dev);
  36
  37 #ifdef CONFIG_PCI_MSI
  38         int             (*setup_msi_irqs)(struct pci_dev *dev,
  39                                           int nvec, int type);
  40         void            (*teardown_msi_irqs)(struct pci_dev *dev);
  41 #endif
  42
  43         int             (*dma_set_mask)(struct pci_dev *dev, u64 dma_mask);
  44         u64             (*dma_get_required_mask)(struct pci_dev *dev);
  45
  46         void            (*shutdown)(struct pci_controller *);
  47 };
  48
  49 /*
  50  * Structure of a PCI controller (host bridge)
  51  */
  52 struct pci_controller {
  53         struct pci_bus *bus;
  54         char is_dynamic;
  55 #ifdef CONFIG_PPC64
  56         int node;
  57 #endif
  58         struct device_node *dn;
  59         struct list_head list_node;
  60         struct device *parent;
  61
  62         int first_busno;
  63         int last_busno;
  64         int self_busno;
  65         struct resource busn;
  66
  67         void __iomem *io_base_virt;
  68 #ifdef CONFIG_PPC64
  69         void *io_base_alloc;
  70 #endif
  71         resource_size_t io_base_phys;
  72         resource_size_t pci_io_size;
  73
  74         /* Some machines have a special region to forward the ISA
  75          * "memory" cycles such as VGA memory regions. Left to 0
  76          * if unsupported
  77          */
  78         resource_size_t isa_mem_phys;
  79         resource_size_t isa_mem_size;
  80
  81         struct pci_controller_ops controller_ops;
  82         struct pci_ops *ops;
  83         unsigned int __iomem *cfg_addr;
  84         void __iomem *cfg_data;
  85
  86         /*
  87          * Used for variants of PCI indirect handling and possible quirks:
  88          *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
  89          *  EXT_REG - provides access to PCI-e extended registers
  90          *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
  91          *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
  92          *   to determine which bus number to match on when generating type0
  93          *   config cycles
  94          *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
  95          *   hanging if we don't have link and try to do config cycles to
  96          *   anything but the PHB.  Only allow talking to the PHB if this is
  97          *   set.
  98          *  BIG_ENDIAN - cfg_addr is a big endian register
  99          *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
 100          *   the PLB4.  Effectively disable MRM commands by setting this.
 101          *  FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
 102          *   link status is in a RC PCIe cfg register (vs being a SoC register)
 103          */
 104 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE          0x00000001
 105 #define PPC_INDIRECT_TYPE_EXT_REG               0x00000002
 106 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS  0x00000004
 107 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK          0x00000008
 108 #define PPC_INDIRECT_TYPE_BIG_ENDIAN            0x00000010
 109 #define PPC_INDIRECT_TYPE_BROKEN_MRM            0x00000020
 110 #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK      0x00000040
 111         u32 indirect_type;
 112         /* Currently, we limit ourselves to 1 IO range and 3 mem
 113          * ranges since the common pci_bus structure can't handle more
 114          */
 115         struct resource io_resource;
 116         struct resource mem_resources[3];
 117         resource_size_t mem_offset[3];
 118         int global_number;              /* PCI domain number */
 119
 120         resource_size_t dma_window_base_cur;
 121         resource_size_t dma_window_size;
 122
 123 #ifdef CONFIG_PPC64
 124         unsigned long buid;
 125         struct pci_dn *pci_data;
 126 #endif  /* CONFIG_PPC64 */
 127
 128         void *private_data;
 129 };
 130
 131 /* These are used for config access before all the PCI probing
 132    has been done. */
 133 extern int early_read_config_byte(struct pci_controller *hose, int bus,
 134                         int dev_fn, int where, u8 *val);
 135 extern int early_read_config_word(struct pci_controller *hose, int bus,
 136                         int dev_fn, int where, u16 *val);
 137 extern int early_read_config_dword(struct pci_controller *hose, int bus,
 138                         int dev_fn, int where, u32 *val);
 139 extern int early_write_config_byte(struct pci_controller *hose, int bus,
 140                         int dev_fn, int where, u8 val);
 141 extern int early_write_config_word(struct pci_controller *hose, int bus,
 142                         int dev_fn, int where, u16 val);
 143 extern int early_write_config_dword(struct pci_controller *hose, int bus,
 144                         int dev_fn, int where, u32 val);
 145
 146 extern int early_find_capability(struct pci_controller *hose, int bus,
 147                                  int dev_fn, int cap);
 148
 149 extern void setup_indirect_pci(struct pci_controller* hose,
 150                                resource_size_t cfg_addr,
 151                                resource_size_t cfg_data, u32 flags);
 152
 153 extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
 154                                 int offset, int len, u32 *val);
 155
 156 extern int __indirect_read_config(struct pci_controller *hose,
 157                                   unsigned char bus_number, unsigned int devfn,
 158                                   int offset, int len, u32 *val);
 159
 160 extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
 161                                  int offset, int len, u32 val);
 162
 163 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
 164 {
 165         return bus->sysdata;
 166 }
 167
 168 #ifndef CONFIG_PPC64
 169
 170 extern int pci_device_from_OF_node(struct device_node *node,
 171                                    u8 *bus, u8 *devfn);
 172 extern void pci_create_OF_bus_map(void);
 173
 174 static inline int isa_vaddr_is_ioport(void __iomem *address)
 175 {
 176         /* No specific ISA handling on ppc32 at this stage, it
 177          * all goes through PCI
 178          */
 179         return 0;
 180 }
 181
 182 #else   /* CONFIG_PPC64 */
 183
 184 /*
 185  * PCI stuff, for nodes representing PCI devices, pointed to
 186  * by device_node->data.
 187  */
 188 struct iommu_table;
 189
 190 struct pci_dn {
 191         int     flags;
 192 #define PCI_DN_FLAG_IOV_VF      0x01
 193
 194         int     busno;                  /* pci bus number */
 195         int     devfn;                  /* pci device and function number */
 196         int     vendor_id;              /* Vendor ID */
 197         int     device_id;              /* Device ID */
 198         int     class_code;             /* Device class code */
 199
 200         struct  pci_dn *parent;
 201         struct  pci_controller *phb;    /* for pci devices */
 202         struct  iommu_table_group *table_group; /* for phb's or bridges */
 203         struct  device_node *node;      /* back-pointer to the device_node */
 204
 205         int     pci_ext_config_space;   /* for pci devices */
 206
 207         struct  pci_dev *pcidev;        /* back-pointer to the pci device */
 208 #ifdef CONFIG_EEH
 209         struct eeh_dev *edev;           /* eeh device */
 210 #endif
 211 #define IODA_INVALID_PE         (-1)
 212 #ifdef CONFIG_PPC_POWERNV
 213         int     pe_number;
 214         int     vf_index;               /* VF index in the PF */
 215 #ifdef CONFIG_PCI_IOV
 216         u16     vfs_expanded;           /* number of VFs IOV BAR expanded */
 217         u16     num_vfs;                /* number of VFs enabled*/
 218         int     *pe_num_map;            /* PE# for the first VF PE or array */
 219         bool    m64_single_mode;        /* Use M64 BAR in Single Mode */
 220 #define IODA_INVALID_M64        (-1)
 221         int     (*m64_map)[PCI_SRIOV_NUM_BARS];
 222 #endif /* CONFIG_PCI_IOV */
 223         int     mps;                    /* Maximum Payload Size */
 224 #endif
 225         struct list_head child_list;
 226         struct list_head list;
 227 };
 228
 229 /* Get the pointer to a device_node's pci_dn */
 230 #define PCI_DN(dn)      ((struct pci_dn *) (dn)->data)
 231
 232 extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
 233                                            int devfn);
 234 extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
 235 extern struct pci_dn *add_dev_pci_data(struct pci_dev *pdev);
 236 extern void remove_dev_pci_data(struct pci_dev *pdev);
 237 extern void *update_dn_pci_info(struct device_node *dn, void *data);
 238
 239 static inline int pci_device_from_OF_node(struct device_node *np,
 240                                           u8 *bus, u8 *devfn)
 241 {
 242         if (!PCI_DN(np))
 243                 return -ENODEV;
 244         *bus = PCI_DN(np)->busno;
 245         *devfn = PCI_DN(np)->devfn;
 246         return 0;
 247 }
 248
 249 #if defined(CONFIG_EEH)
 250 static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
 251 {
 252         return pdn ? pdn->edev : NULL;
 253 }
 254 #else
 255 #define pdn_to_eeh_dev(x)       (NULL)
 256 #endif
 257
 258 /** Find the bus corresponding to the indicated device node */
 259 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
 260
 261 /** Remove all of the PCI devices under this bus */
 262 extern void pcibios_remove_pci_devices(struct pci_bus *bus);
 263
 264 /** Discover new pci devices under this bus, and add them */
 265 extern void pcibios_add_pci_devices(struct pci_bus *bus);
 266
 267
 268 extern void isa_bridge_find_early(struct pci_controller *hose);
 269
 270 static inline int isa_vaddr_is_ioport(void __iomem *address)
 271 {
 272         /* Check if address hits the reserved legacy IO range */
 273         unsigned long ea = (unsigned long)address;
 274         return ea >= ISA_IO_BASE && ea < ISA_IO_END;
 275 }
 276
 277 extern int pcibios_unmap_io_space(struct pci_bus *bus);
 278 extern int pcibios_map_io_space(struct pci_bus *bus);
 279
 280 #ifdef CONFIG_NUMA
 281 #define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = (NODE))
 282 #else
 283 #define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = -1)
 284 #endif
 285
 286 #endif  /* CONFIG_PPC64 */
 287
 288 /* Get the PCI host controller for an OF device */
 289 extern struct pci_controller *pci_find_hose_for_OF_device(
 290                         struct device_node* node);
 291
 292 /* Fill up host controller resources from the OF node */
 293 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 294                         struct device_node *dev, int primary);
 295
 296 /* Allocate & free a PCI host bridge structure */
 297 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
 298 extern void pcibios_free_controller(struct pci_controller *phb);
 299
 300 #ifdef CONFIG_PCI
 301 extern int pcibios_vaddr_is_ioport(void __iomem *address);
 302 #else
 303 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
 304 {
 305         return 0;
 306 }
 307 #endif  /* CONFIG_PCI */
 308
 309 #endif  /* __KERNEL__ */
 310 #endif  /* _ASM_POWERPC_PCI_BRIDGE_H */