2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/module.h>
27 #include <linux/ioport.h>
28 #include <linux/clockchips.h>
30 #include <asm/atomic.h>
33 #include <asm/mpspec.h>
34 #include <asm/pgalloc.h>
35 #include <asm/mach_apic.h>
38 #include <asm/proto.h>
39 #include <asm/timex.h>
44 int disable_apic_timer __cpuinitdata
;
45 static int apic_calibrate_pmtmr __initdata
;
47 /* Local APIC timer works in C2? */
48 int local_apic_timer_c2_ok
;
49 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
51 static struct resource
*ioapic_resources
;
52 static struct resource lapic_resource
= {
54 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
57 static unsigned int calibration_result
;
59 static int lapic_next_event(unsigned long delta
,
60 struct clock_event_device
*evt
);
61 static void lapic_timer_setup(enum clock_event_mode mode
,
62 struct clock_event_device
*evt
);
64 static void lapic_timer_broadcast(cpumask_t mask
);
66 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
);
68 static struct clock_event_device lapic_clockevent
= {
70 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
71 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
73 .set_mode
= lapic_timer_setup
,
74 .set_next_event
= lapic_next_event
,
75 .broadcast
= lapic_timer_broadcast
,
79 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
81 static int lapic_next_event(unsigned long delta
,
82 struct clock_event_device
*evt
)
84 apic_write(APIC_TMICT
, delta
);
88 static void lapic_timer_setup(enum clock_event_mode mode
,
89 struct clock_event_device
*evt
)
94 /* Lapic used as dummy for broadcast ? */
95 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
98 local_irq_save(flags
);
101 case CLOCK_EVT_MODE_PERIODIC
:
102 case CLOCK_EVT_MODE_ONESHOT
:
103 __setup_APIC_LVTT(calibration_result
,
104 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
106 case CLOCK_EVT_MODE_UNUSED
:
107 case CLOCK_EVT_MODE_SHUTDOWN
:
108 v
= apic_read(APIC_LVTT
);
109 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
110 apic_write(APIC_LVTT
, v
);
112 case CLOCK_EVT_MODE_RESUME
:
113 /* Nothing to do here */
117 local_irq_restore(flags
);
121 * Local APIC timer broadcast function
123 static void lapic_timer_broadcast(cpumask_t mask
)
126 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
130 static void apic_pm_activate(void);
132 void apic_wait_icr_idle(void)
134 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
138 unsigned int safe_apic_wait_icr_idle(void)
140 unsigned int send_status
;
145 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
149 } while (timeout
++ < 1000);
154 void enable_NMI_through_LVT0 (void * dummy
)
158 /* unmask and set to NMI */
160 apic_write(APIC_LVT0
, v
);
165 unsigned int v
, maxlvt
;
167 v
= apic_read(APIC_LVR
);
168 maxlvt
= GET_APIC_MAXLVT(v
);
173 * 'what should we do if we get a hw irq event on an illegal vector'.
174 * each architecture has to answer this themselves.
176 void ack_bad_irq(unsigned int irq
)
178 printk("unexpected IRQ trap at vector %02x\n", irq
);
180 * Currently unexpected vectors happen only on SMP and APIC.
181 * We _must_ ack these because every local APIC has only N
182 * irq slots per priority level, and a 'hanging, unacked' IRQ
183 * holds up an irq slot - in excessive cases (when multiple
184 * unexpected vectors occur) that might lock up the APIC
186 * But don't ack when the APIC is disabled. -AK
192 void clear_local_APIC(void)
197 maxlvt
= get_maxlvt();
200 * Masking an LVT entry can trigger a local APIC error
201 * if the vector is zero. Mask LVTERR first to prevent this.
204 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
205 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
208 * Careful: we have to set masks only first to deassert
209 * any level-triggered sources.
211 v
= apic_read(APIC_LVTT
);
212 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
213 v
= apic_read(APIC_LVT0
);
214 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
215 v
= apic_read(APIC_LVT1
);
216 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
218 v
= apic_read(APIC_LVTPC
);
219 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
223 * Clean APIC state for other OSs:
225 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
226 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
227 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
229 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
231 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
232 apic_write(APIC_ESR
, 0);
236 void disconnect_bsp_APIC(int virt_wire_setup
)
238 /* Go back to Virtual Wire compatibility mode */
241 /* For the spurious interrupt use vector F, and enable it */
242 value
= apic_read(APIC_SPIV
);
243 value
&= ~APIC_VECTOR_MASK
;
244 value
|= APIC_SPIV_APIC_ENABLED
;
246 apic_write(APIC_SPIV
, value
);
248 if (!virt_wire_setup
) {
250 * For LVT0 make it edge triggered, active high,
251 * external and enabled
253 value
= apic_read(APIC_LVT0
);
254 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
255 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
256 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
257 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
258 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
259 apic_write(APIC_LVT0
, value
);
262 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
265 /* For LVT1 make it edge triggered, active high, nmi and enabled */
266 value
= apic_read(APIC_LVT1
);
267 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
268 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
269 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
270 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
271 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
272 apic_write(APIC_LVT1
, value
);
275 void disable_local_APIC(void)
282 * Disable APIC (implies clearing of registers
285 value
= apic_read(APIC_SPIV
);
286 value
&= ~APIC_SPIV_APIC_ENABLED
;
287 apic_write(APIC_SPIV
, value
);
290 void lapic_shutdown(void)
297 local_irq_save(flags
);
299 disable_local_APIC();
301 local_irq_restore(flags
);
305 * This is to verify that we're looking at a real local APIC.
306 * Check these against your board if the CPUs aren't getting
307 * started for no apparent reason.
309 int __init
verify_local_APIC(void)
311 unsigned int reg0
, reg1
;
314 * The version register is read-only in a real APIC.
316 reg0
= apic_read(APIC_LVR
);
317 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
318 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
319 reg1
= apic_read(APIC_LVR
);
320 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
323 * The two version reads above should print the same
324 * numbers. If the second one is different, then we
325 * poke at a non-APIC.
331 * Check if the version looks reasonably.
333 reg1
= GET_APIC_VERSION(reg0
);
334 if (reg1
== 0x00 || reg1
== 0xff)
337 if (reg1
< 0x02 || reg1
== 0xff)
341 * The ID register is read/write in a real APIC.
343 reg0
= apic_read(APIC_ID
);
344 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
345 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
346 reg1
= apic_read(APIC_ID
);
347 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
348 apic_write(APIC_ID
, reg0
);
349 if (reg1
!= (reg0
^ APIC_ID_MASK
))
353 * The next two are just to see if we have sane values.
354 * They're only really relevant if we're in Virtual Wire
355 * compatibility mode, but most boxes are anymore.
357 reg0
= apic_read(APIC_LVT0
);
358 apic_printk(APIC_DEBUG
,"Getting LVT0: %x\n", reg0
);
359 reg1
= apic_read(APIC_LVT1
);
360 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
365 void __init
sync_Arb_IDs(void)
367 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
368 unsigned int ver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
369 if (ver
>= 0x14) /* P4 or higher */
375 apic_wait_icr_idle();
377 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
378 apic_write(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
383 * An initial setup of the virtual wire mode.
385 void __init
init_bsp_APIC(void)
390 * Don't do the setup now if we have a SMP BIOS as the
391 * through-I/O-APIC virtual wire mode might be active.
393 if (smp_found_config
|| !cpu_has_apic
)
396 value
= apic_read(APIC_LVR
);
399 * Do not trust the local APIC being empty at bootup.
406 value
= apic_read(APIC_SPIV
);
407 value
&= ~APIC_VECTOR_MASK
;
408 value
|= APIC_SPIV_APIC_ENABLED
;
409 value
|= APIC_SPIV_FOCUS_DISABLED
;
410 value
|= SPURIOUS_APIC_VECTOR
;
411 apic_write(APIC_SPIV
, value
);
414 * Set up the virtual wire mode.
416 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
418 apic_write(APIC_LVT1
, value
);
421 void __cpuinit
setup_local_APIC (void)
423 unsigned int value
, maxlvt
;
426 value
= apic_read(APIC_LVR
);
428 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f);
431 * Double-check whether this APIC is really registered.
432 * This is meaningless in clustered apic mode, so we skip it.
434 if (!apic_id_registered())
438 * Intel recommends to set DFR, LDR and TPR before enabling
439 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
440 * document number 292116). So here it goes...
445 * Set Task Priority to 'accept all'. We never change this
448 value
= apic_read(APIC_TASKPRI
);
449 value
&= ~APIC_TPRI_MASK
;
450 apic_write(APIC_TASKPRI
, value
);
453 * After a crash, we no longer service the interrupts and a pending
454 * interrupt from previous kernel might still have ISR bit set.
456 * Most probably by now CPU has serviced that pending interrupt and
457 * it might not have done the ack_APIC_irq() because it thought,
458 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
459 * does not clear the ISR bit and cpu thinks it has already serivced
460 * the interrupt. Hence a vector might get locked. It was noticed
461 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
463 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
464 value
= apic_read(APIC_ISR
+ i
*0x10);
465 for (j
= 31; j
>= 0; j
--) {
472 * Now that we are all set up, enable the APIC
474 value
= apic_read(APIC_SPIV
);
475 value
&= ~APIC_VECTOR_MASK
;
479 value
|= APIC_SPIV_APIC_ENABLED
;
481 /* We always use processor focus */
484 * Set spurious IRQ vector
486 value
|= SPURIOUS_APIC_VECTOR
;
487 apic_write(APIC_SPIV
, value
);
492 * set up through-local-APIC on the BP's LINT0. This is not
493 * strictly necessary in pure symmetric-IO mode, but sometimes
494 * we delegate interrupts to the 8259A.
497 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
499 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
500 if (!smp_processor_id() && !value
) {
501 value
= APIC_DM_EXTINT
;
502 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
505 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
506 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
509 apic_write(APIC_LVT0
, value
);
512 * only the BP should see the LINT1 NMI signal, obviously.
514 if (!smp_processor_id())
517 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
518 apic_write(APIC_LVT1
, value
);
522 maxlvt
= get_maxlvt();
523 oldvalue
= apic_read(APIC_ESR
);
524 value
= ERROR_APIC_VECTOR
; // enables sending errors
525 apic_write(APIC_LVTERR
, value
);
527 * spec says clear errors after enabling vector.
530 apic_write(APIC_ESR
, 0);
531 value
= apic_read(APIC_ESR
);
532 if (value
!= oldvalue
)
533 apic_printk(APIC_VERBOSE
,
534 "ESR value after enabling vector: %08x, after %08x\n",
538 nmi_watchdog_default();
539 setup_apic_nmi_watchdog(NULL
);
546 /* 'active' is true if the local APIC was enabled by us and
547 not the BIOS; this signifies that we are also responsible
548 for disabling it before entering apm/acpi suspend */
550 /* r/w apic fields */
551 unsigned int apic_id
;
552 unsigned int apic_taskpri
;
553 unsigned int apic_ldr
;
554 unsigned int apic_dfr
;
555 unsigned int apic_spiv
;
556 unsigned int apic_lvtt
;
557 unsigned int apic_lvtpc
;
558 unsigned int apic_lvt0
;
559 unsigned int apic_lvt1
;
560 unsigned int apic_lvterr
;
561 unsigned int apic_tmict
;
562 unsigned int apic_tdcr
;
563 unsigned int apic_thmr
;
566 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
571 if (!apic_pm_state
.active
)
574 maxlvt
= get_maxlvt();
576 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
577 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
578 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
579 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
580 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
581 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
583 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
584 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
585 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
586 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
587 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
588 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
589 #ifdef CONFIG_X86_MCE_INTEL
591 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
593 local_irq_save(flags
);
594 disable_local_APIC();
595 local_irq_restore(flags
);
599 static int lapic_resume(struct sys_device
*dev
)
605 if (!apic_pm_state
.active
)
608 maxlvt
= get_maxlvt();
610 local_irq_save(flags
);
611 rdmsr(MSR_IA32_APICBASE
, l
, h
);
612 l
&= ~MSR_IA32_APICBASE_BASE
;
613 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
614 wrmsr(MSR_IA32_APICBASE
, l
, h
);
615 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
616 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
617 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
618 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
619 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
620 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
621 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
622 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
623 #ifdef CONFIG_X86_MCE_INTEL
625 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
628 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
629 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
630 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
631 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
632 apic_write(APIC_ESR
, 0);
634 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
635 apic_write(APIC_ESR
, 0);
637 local_irq_restore(flags
);
641 static struct sysdev_class lapic_sysclass
= {
643 .resume
= lapic_resume
,
644 .suspend
= lapic_suspend
,
647 static struct sys_device device_lapic
= {
649 .cls
= &lapic_sysclass
,
652 static void __cpuinit
apic_pm_activate(void)
654 apic_pm_state
.active
= 1;
657 static int __init
init_lapic_sysfs(void)
662 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
663 error
= sysdev_class_register(&lapic_sysclass
);
665 error
= sysdev_register(&device_lapic
);
668 device_initcall(init_lapic_sysfs
);
670 #else /* CONFIG_PM */
672 static void apic_pm_activate(void) { }
674 #endif /* CONFIG_PM */
676 static int __init
apic_set_verbosity(char *str
)
679 skip_ioapic_setup
= 0;
683 if (strcmp("debug", str
) == 0)
684 apic_verbosity
= APIC_DEBUG
;
685 else if (strcmp("verbose", str
) == 0)
686 apic_verbosity
= APIC_VERBOSE
;
688 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
689 " use apic=verbose or apic=debug\n", str
);
695 early_param("apic", apic_set_verbosity
);
698 * Detect and enable local APICs on non-SMP boards.
699 * Original code written by Keir Fraser.
700 * On AMD64 we trust the BIOS - if it says no APIC it is likely
701 * not correctly set up (usually the APIC timer won't work etc.)
704 static int __init
detect_init_APIC (void)
707 printk(KERN_INFO
"No local APIC present\n");
711 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
716 #ifdef CONFIG_X86_IO_APIC
717 static struct resource
* __init
ioapic_setup_resources(void)
719 #define IOAPIC_RESOURCE_NAME_SIZE 11
721 struct resource
*res
;
728 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
731 mem
= alloc_bootmem(n
);
736 mem
+= sizeof(struct resource
) * nr_ioapics
;
738 for (i
= 0; i
< nr_ioapics
; i
++) {
740 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
741 sprintf(mem
, "IOAPIC %u", i
);
742 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
746 ioapic_resources
= res
;
751 static int __init
ioapic_insert_resources(void)
754 struct resource
*r
= ioapic_resources
;
757 printk("IO APIC resources could be not be allocated.\n");
761 for (i
= 0; i
< nr_ioapics
; i
++) {
762 insert_resource(&iomem_resource
, r
);
769 /* Insert the IO APIC resources after PCI initialization has occured to handle
770 * IO APICS that are mapped in on a BAR in PCI space. */
771 late_initcall(ioapic_insert_resources
);
774 void __init
init_apic_mappings(void)
776 unsigned long apic_phys
;
779 * If no local APIC can be found then set up a fake all
780 * zeroes page to simulate the local APIC and another
781 * one for the IO-APIC.
783 if (!smp_found_config
&& detect_init_APIC()) {
784 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
785 apic_phys
= __pa(apic_phys
);
787 apic_phys
= mp_lapic_addr
;
789 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
790 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
791 APIC_BASE
, apic_phys
);
793 /* Put local APIC into the resource map. */
794 lapic_resource
.start
= apic_phys
;
795 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
796 insert_resource(&iomem_resource
, &lapic_resource
);
799 * Fetch the APIC ID of the BSP in case we have a
800 * default configuration (or the MP table is broken).
802 boot_cpu_id
= GET_APIC_ID(apic_read(APIC_ID
));
805 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
807 struct resource
*ioapic_res
;
809 ioapic_res
= ioapic_setup_resources();
810 for (i
= 0; i
< nr_ioapics
; i
++) {
811 if (smp_found_config
) {
812 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
814 ioapic_phys
= (unsigned long)
815 alloc_bootmem_pages(PAGE_SIZE
);
816 ioapic_phys
= __pa(ioapic_phys
);
818 set_fixmap_nocache(idx
, ioapic_phys
);
819 apic_printk(APIC_VERBOSE
,
820 "mapped IOAPIC to %016lx (%016lx)\n",
821 __fix_to_virt(idx
), ioapic_phys
);
824 if (ioapic_res
!= NULL
) {
825 ioapic_res
->start
= ioapic_phys
;
826 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
834 * This function sets up the local APIC timer, with a timeout of
835 * 'clocks' APIC bus clock. During calibration we actually call
836 * this function twice on the boot CPU, once with a bogus timeout
837 * value, second time for real. The other (noncalibrating) CPUs
838 * call this function only once, with the real, calibrated value.
840 * We do reads before writes even if unnecessary, to get around the
841 * P5 APIC double write bug.
844 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
846 unsigned int lvtt_value
, tmp_value
;
848 lvtt_value
= LOCAL_TIMER_VECTOR
;
850 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
852 lvtt_value
|= APIC_LVT_MASKED
;
854 apic_write(APIC_LVTT
, lvtt_value
);
859 tmp_value
= apic_read(APIC_TDCR
);
860 apic_write(APIC_TDCR
, (tmp_value
861 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
865 apic_write(APIC_TMICT
, clocks
);
868 static void setup_APIC_timer(void)
870 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
872 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
873 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
875 clockevents_register_device(levt
);
879 * In this function we calibrate APIC bus clocks to the external
880 * timer. Unfortunately we cannot use jiffies and the timer irq
881 * to calibrate, since some later bootup code depends on getting
882 * the first irq? Ugh.
884 * We want to do the calibration only once since we
885 * want to have local timer irqs syncron. CPUs connected
886 * by the same APIC bus have the very same bus frequency.
887 * And we want to have irqs off anyways, no accidental
891 #define TICK_COUNT 100000000
893 static void __init
calibrate_APIC_clock(void)
895 unsigned apic
, apic_start
;
896 unsigned long tsc
, tsc_start
;
902 * Put whatever arbitrary (but long enough) timeout
903 * value into the APIC clock, we just want to get the
904 * counter running for calibration.
906 * No interrupt enable !
908 __setup_APIC_LVTT(250000000, 0, 0);
910 apic_start
= apic_read(APIC_TMCCT
);
911 #ifdef CONFIG_X86_PM_TIMER
912 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
913 pmtimer_wait(5000); /* 5ms wait */
914 apic
= apic_read(APIC_TMCCT
);
915 result
= (apic_start
- apic
) * 1000L / 5;
922 apic
= apic_read(APIC_TMCCT
);
924 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
925 (apic_start
- apic
) < TICK_COUNT
);
927 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
933 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
935 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
936 result
/ 1000 / 1000, result
/ 1000 % 1000);
938 /* Calculate the scaled math multiplication factor */
939 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
, 32);
940 lapic_clockevent
.max_delta_ns
=
941 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
942 lapic_clockevent
.min_delta_ns
=
943 clockevent_delta2ns(0xF, &lapic_clockevent
);
945 calibration_result
= result
/ HZ
;
948 void __init
setup_boot_APIC_clock (void)
951 * The local apic timer can be disabled via the kernel commandline.
952 * Register the lapic timer as a dummy clock event source on SMP
953 * systems, so the broadcast mechanism is used. On UP systems simply
956 if (disable_apic_timer
) {
957 printk(KERN_INFO
"Disabling APIC timer\n");
958 /* No broadcast on UP ! */
959 if (num_possible_cpus() > 1)
964 printk(KERN_INFO
"Using local APIC timer interrupts.\n");
965 calibrate_APIC_clock();
968 * If nmi_watchdog is set to IO_APIC, we need the
969 * PIT/HPET going. Otherwise register lapic as a dummy
972 if (nmi_watchdog
!= NMI_IO_APIC
)
973 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
975 printk(KERN_WARNING
"APIC timer registered as dummy,"
976 " due to nmi_watchdog=1!\n");
982 * AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the
983 * C1E flag only in the secondary CPU, so when we detect the wreckage
984 * we already have enabled the boot CPU local apic timer. Check, if
985 * disable_apic_timer is set and the DUMMY flag is cleared. If yes,
986 * set the DUMMY flag again and force the broadcast mode in the
989 void __cpuinit
check_boot_apic_timer_broadcast(void)
991 if (!disable_apic_timer
||
992 (lapic_clockevent
.features
& CLOCK_EVT_FEAT_DUMMY
))
995 printk(KERN_INFO
"AMD C1E detected late. Force timer broadcast.\n");
996 lapic_clockevent
.features
|= CLOCK_EVT_FEAT_DUMMY
;
999 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE
, &boot_cpu_id
);
1000 local_irq_disable();
1003 void __cpuinit
setup_secondary_APIC_clock(void)
1005 check_boot_apic_timer_broadcast();
1009 int setup_profiling_timer(unsigned int multiplier
)
1014 void setup_APIC_extended_lvt(unsigned char lvt_off
, unsigned char vector
,
1015 unsigned char msg_type
, unsigned char mask
)
1017 unsigned long reg
= (lvt_off
<< 4) + K8_APIC_EXT_LVT_BASE
;
1018 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
1023 * Local timer interrupt handler. It does both profiling and
1024 * process statistics/rescheduling.
1026 * We do profiling in every local tick, statistics/rescheduling
1027 * happen only every 'profiling multiplier' ticks. The default
1028 * multiplier is 1 and it can be changed by writing the new multiplier
1029 * value into /proc/profile.
1032 void smp_local_timer_interrupt(void)
1034 int cpu
= smp_processor_id();
1035 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
1038 * Normally we should not be here till LAPIC has been initialized but
1039 * in some cases like kdump, its possible that there is a pending LAPIC
1040 * timer interrupt from previous kernel's context and is delivered in
1041 * new kernel the moment interrupts are enabled.
1043 * Interrupts are enabled early and LAPIC is setup much later, hence
1044 * its possible that when we get here evt->event_handler is NULL.
1045 * Check for event_handler being NULL and discard the interrupt as
1048 if (!evt
->event_handler
) {
1050 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
1052 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
1057 * the NMI deadlock-detector uses this.
1059 add_pda(apic_timer_irqs
, 1);
1061 evt
->event_handler(evt
);
1065 * Local APIC timer interrupt. This is the most natural way for doing
1066 * local interrupts, but local timer interrupts can be emulated by
1067 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1069 * [ if a single-CPU system runs an SMP kernel then we call the local
1070 * interrupt as well. Thus we cannot inline the local irq ... ]
1072 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
1074 struct pt_regs
*old_regs
= set_irq_regs(regs
);
1077 * NOTE! We'd better ACK the irq immediately,
1078 * because timer handling can be slow.
1082 * update_process_times() expects us to have done irq_enter().
1083 * Besides, if we don't timer interrupts ignore the global
1084 * interrupt lock, which is the WrongThing (tm) to do.
1088 smp_local_timer_interrupt();
1090 set_irq_regs(old_regs
);
1094 * apic_is_clustered_box() -- Check if we can expect good TSC
1096 * Thus far, the major user of this is IBM's Summit2 series:
1098 * Clustered boxes may have unsynced TSC problems if they are
1099 * multi-chassis. Use available data to take a good guess.
1100 * If in doubt, go HPET.
1102 __cpuinit
int apic_is_clustered_box(void)
1104 int i
, clusters
, zeros
;
1106 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1108 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1110 for (i
= 0; i
< NR_CPUS
; i
++) {
1111 id
= bios_cpu_apicid
[i
];
1112 if (id
!= BAD_APICID
)
1113 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1116 /* Problem: Partially populated chassis may not have CPUs in some of
1117 * the APIC clusters they have been allocated. Only present CPUs have
1118 * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since
1119 * clusters are allocated sequentially, count zeros only if they are
1124 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1125 if (test_bit(i
, clustermap
)) {
1126 clusters
+= 1 + zeros
;
1133 * If clusters > 2, then should be multi-chassis.
1134 * May have to revisit this when multi-core + hyperthreaded CPUs come
1135 * out, but AFAIK this will work even for them.
1137 return (clusters
> 2);
1141 * This interrupt should _never_ happen with our APIC/SMP architecture
1143 asmlinkage
void smp_spurious_interrupt(void)
1149 * Check if this really is a spurious interrupt and ACK it
1150 * if it is a vectored one. Just in case...
1151 * Spurious interrupts should not be ACKed.
1153 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1154 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1157 add_pda(irq_spurious_count
, 1);
1162 * This interrupt should never happen with our APIC/SMP architecture
1165 asmlinkage
void smp_error_interrupt(void)
1171 /* First tickle the hardware, only then report what went on. -- REW */
1172 v
= apic_read(APIC_ESR
);
1173 apic_write(APIC_ESR
, 0);
1174 v1
= apic_read(APIC_ESR
);
1176 atomic_inc(&irq_err_count
);
1178 /* Here is what the APIC error bits mean:
1181 2: Send accept error
1182 3: Receive accept error
1184 5: Send illegal vector
1185 6: Received illegal vector
1186 7: Illegal register address
1188 printk (KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1189 smp_processor_id(), v
, v1
);
1196 * This initializes the IO-APIC and APIC hardware if this is
1199 int __init
APIC_init_uniprocessor (void)
1202 printk(KERN_INFO
"Apic disabled\n");
1205 if (!cpu_has_apic
) {
1207 printk(KERN_INFO
"Apic disabled by BIOS\n");
1211 verify_local_APIC();
1213 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_id
);
1214 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_id
));
1218 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1222 setup_boot_APIC_clock();
1223 check_nmi_watchdog();
1227 static __init
int setup_disableapic(char *str
)
1230 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1233 early_param("disableapic", setup_disableapic
);
1235 /* same as disableapic, for compatibility */
1236 static __init
int setup_nolapic(char *str
)
1238 return setup_disableapic(str
);
1240 early_param("nolapic", setup_nolapic
);
1242 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1244 local_apic_timer_c2_ok
= 1;
1247 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1249 static __init
int setup_noapictimer(char *str
)
1251 if (str
[0] != ' ' && str
[0] != 0)
1253 disable_apic_timer
= 1;
1256 __setup("noapictimer", setup_noapictimer
);
1258 static __init
int setup_apicpmtimer(char *s
)
1260 apic_calibrate_pmtmr
= 1;
1264 __setup("apicpmtimer", setup_apicpmtimer
);