arch/x86/power/cpu.c

   1 /*
   2  * Suspend support specific for i386/x86-64.
   3  *
   4  * Distribute under GPLv2
   5  *
   6  * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
   7  * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
   8  * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
   9  */
  10
  11 #include <linux/suspend.h>
  12 #include <linux/export.h>
  13 #include <linux/smp.h>
  14 #include <linux/perf_event.h>
  15
  16 #include <asm/pgtable.h>
  17 #include <asm/proto.h>
  18 #include <asm/mtrr.h>
  19 #include <asm/page.h>
  20 #include <asm/mce.h>
  21 #include <asm/suspend.h>
  22 #include <asm/fpu/internal.h>
  23 #include <asm/debugreg.h>
  24 #include <asm/cpu.h>
  25 #include <asm/mmu_context.h>
  26 #include <linux/dmi.h>
  27
  28 #ifdef CONFIG_X86_32
  29 __visible unsigned long saved_context_ebx;
  30 __visible unsigned long saved_context_esp, saved_context_ebp;
  31 __visible unsigned long saved_context_esi, saved_context_edi;
  32 __visible unsigned long saved_context_eflags;
  33 #endif
  34 struct saved_context saved_context;
  35
  36 static void msr_save_context(struct saved_context *ctxt)
  37 {
  38         struct saved_msr *msr = ctxt->saved_msrs.array;
  39         struct saved_msr *end = msr + ctxt->saved_msrs.num;
  40
  41         while (msr < end) {
  42                 msr->valid = !rdmsrl_safe(msr->info.msr_no, &msr->info.reg.q);
  43                 msr++;
  44         }
  45 }
  46
  47 static void msr_restore_context(struct saved_context *ctxt)
  48 {
  49         struct saved_msr *msr = ctxt->saved_msrs.array;
  50         struct saved_msr *end = msr + ctxt->saved_msrs.num;
  51
  52         while (msr < end) {
  53                 if (msr->valid)
  54                         wrmsrl(msr->info.msr_no, msr->info.reg.q);
  55                 msr++;
  56         }
  57 }
  58
  59 /**
  60  *      __save_processor_state - save CPU registers before creating a
  61  *              hibernation image and before restoring the memory state from it
  62  *      @ctxt - structure to store the registers contents in
  63  *
  64  *      NOTE: If there is a CPU register the modification of which by the
  65  *      boot kernel (ie. the kernel used for loading the hibernation image)
  66  *      might affect the operations of the restored target kernel (ie. the one
  67  *      saved in the hibernation image), then its contents must be saved by this
  68  *      function.  In other words, if kernel A is hibernated and different
  69  *      kernel B is used for loading the hibernation image into memory, the
  70  *      kernel A's __save_processor_state() function must save all registers
  71  *      needed by kernel A, so that it can operate correctly after the resume
  72  *      regardless of what kernel B does in the meantime.
  73  */
  74 static void __save_processor_state(struct saved_context *ctxt)
  75 {
  76 #ifdef CONFIG_X86_32
  77         mtrr_save_fixed_ranges(NULL);
  78 #endif
  79         kernel_fpu_begin();
  80
  81         /*
  82          * descriptor tables
  83          */
  84 #ifdef CONFIG_X86_32
  85         store_idt(&ctxt->idt);
  86 #else
  87 /* CONFIG_X86_64 */
  88         store_idt((struct desc_ptr *)&ctxt->idt_limit);
  89 #endif
  90         /*
  91          * We save it here, but restore it only in the hibernate case.
  92          * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit
  93          * mode in "secondary_startup_64". In 32-bit mode it is done via
  94          * 'pmode_gdt' in wakeup_start.
  95          */
  96         ctxt->gdt_desc.size = GDT_SIZE - 1;
  97         ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_table(smp_processor_id());
  98
  99         store_tr(ctxt->tr);
 100
 101         /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
 102         /*
 103          * segment registers
 104          */
 105 #ifdef CONFIG_X86_32
 106         savesegment(es, ctxt->es);
 107         savesegment(fs, ctxt->fs);
 108         savesegment(gs, ctxt->gs);
 109         savesegment(ss, ctxt->ss);
 110 #else
 111 /* CONFIG_X86_64 */
 112         asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
 113         asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
 114         asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
 115         asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
 116         asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
 117
 118         rdmsrl(MSR_FS_BASE, ctxt->fs_base);
 119         rdmsrl(MSR_GS_BASE, ctxt->gs_base);
 120         rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
 121         mtrr_save_fixed_ranges(NULL);
 122
 123         rdmsrl(MSR_EFER, ctxt->efer);
 124 #endif
 125
 126         /*
 127          * control registers
 128          */
 129         ctxt->cr0 = read_cr0();
 130         ctxt->cr2 = read_cr2();
 131         ctxt->cr3 = read_cr3();
 132         ctxt->cr4 = __read_cr4_safe();
 133 #ifdef CONFIG_X86_64
 134         ctxt->cr8 = read_cr8();
 135 #endif
 136         ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
 137                                                &ctxt->misc_enable);
 138         msr_save_context(ctxt);
 139 }
 140
 141 /* Needed by apm.c */
 142 void save_processor_state(void)
 143 {
 144         __save_processor_state(&saved_context);
 145         x86_platform.save_sched_clock_state();
 146 }
 147 #ifdef CONFIG_X86_32
 148 EXPORT_SYMBOL(save_processor_state);
 149 #endif
 150
 151 static void do_fpu_end(void)
 152 {
 153         /*
 154          * Restore FPU regs if necessary.
 155          */
 156         kernel_fpu_end();
 157 }
 158
 159 static void fix_processor_context(void)
 160 {
 161         int cpu = smp_processor_id();
 162         struct tss_struct *t = &per_cpu(cpu_tss, cpu);
 163 #ifdef CONFIG_X86_64
 164         struct desc_struct *desc = get_cpu_gdt_table(cpu);
 165         tss_desc tss;
 166 #endif
 167         set_tss_desc(cpu, t);   /*
 168                                  * This just modifies memory; should not be
 169                                  * necessary. But... This is necessary, because
 170                                  * 386 hardware has concept of busy TSS or some
 171                                  * similar stupidity.
 172                                  */
 173
 174 #ifdef CONFIG_X86_64
 175         memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
 176         tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */
 177         write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);
 178
 179         syscall_init();                         /* This sets MSR_*STAR and related */
 180 #endif
 181         load_TR_desc();                         /* This does ltr */
 182         load_mm_ldt(current->active_mm);        /* This does lldt */
 183
 184         fpu__resume_cpu();
 185 }
 186
 187 /**
 188  *      __restore_processor_state - restore the contents of CPU registers saved
 189  *              by __save_processor_state()
 190  *      @ctxt - structure to load the registers contents from
 191  */
 192 static void notrace __restore_processor_state(struct saved_context *ctxt)
 193 {
 194         if (ctxt->misc_enable_saved)
 195                 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
 196         /*
 197          * control registers
 198          */
 199         /* cr4 was introduced in the Pentium CPU */
 200 #ifdef CONFIG_X86_32
 201         if (ctxt->cr4)
 202                 __write_cr4(ctxt->cr4);
 203 #else
 204 /* CONFIG X86_64 */
 205         wrmsrl(MSR_EFER, ctxt->efer);
 206         write_cr8(ctxt->cr8);
 207         __write_cr4(ctxt->cr4);
 208 #endif
 209         write_cr3(ctxt->cr3);
 210         write_cr2(ctxt->cr2);
 211         write_cr0(ctxt->cr0);
 212
 213         /*
 214          * now restore the descriptor tables to their proper values
 215          * ltr is done i fix_processor_context().
 216          */
 217 #ifdef CONFIG_X86_32
 218         load_idt(&ctxt->idt);
 219 #else
 220 /* CONFIG_X86_64 */
 221         load_idt((const struct desc_ptr *)&ctxt->idt_limit);
 222 #endif
 223
 224         /*
 225          * segment registers
 226          */
 227 #ifdef CONFIG_X86_32
 228         loadsegment(es, ctxt->es);
 229         loadsegment(fs, ctxt->fs);
 230         loadsegment(gs, ctxt->gs);
 231         loadsegment(ss, ctxt->ss);
 232
 233         /*
 234          * sysenter MSRs
 235          */
 236         if (boot_cpu_has(X86_FEATURE_SEP))
 237                 enable_sep_cpu();
 238 #else
 239 /* CONFIG_X86_64 */
 240         asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
 241         asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
 242         asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
 243         load_gs_index(ctxt->gs);
 244         asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
 245
 246         wrmsrl(MSR_FS_BASE, ctxt->fs_base);
 247         wrmsrl(MSR_GS_BASE, ctxt->gs_base);
 248         wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
 249 #endif
 250
 251         fix_processor_context();
 252
 253         do_fpu_end();
 254         x86_platform.restore_sched_clock_state();
 255         mtrr_bp_restore();
 256         perf_restore_debug_store();
 257         msr_restore_context(ctxt);
 258 }
 259
 260 /* Needed by apm.c */
 261 void notrace restore_processor_state(void)
 262 {
 263         __restore_processor_state(&saved_context);
 264 }
 265 #ifdef CONFIG_X86_32
 266 EXPORT_SYMBOL(restore_processor_state);
 267 #endif
 268
 269 /*
 270  * When bsp_check() is called in hibernate and suspend, cpu hotplug
 271  * is disabled already. So it's unnessary to handle race condition between
 272  * cpumask query and cpu hotplug.
 273  */
 274 static int bsp_check(void)
 275 {
 276         if (cpumask_first(cpu_online_mask) != 0) {
 277                 pr_warn("CPU0 is offline.\n");
 278                 return -ENODEV;
 279         }
 280
 281         return 0;
 282 }
 283
 284 static int bsp_pm_callback(struct notifier_block *nb, unsigned long action,
 285                            void *ptr)
 286 {
 287         int ret = 0;
 288
 289         switch (action) {
 290         case PM_SUSPEND_PREPARE:
 291         case PM_HIBERNATION_PREPARE:
 292                 ret = bsp_check();
 293                 break;
 294 #ifdef CONFIG_DEBUG_HOTPLUG_CPU0
 295         case PM_RESTORE_PREPARE:
 296                 /*
 297                  * When system resumes from hibernation, online CPU0 because
 298                  * 1. it's required for resume and
 299                  * 2. the CPU was online before hibernation
 300                  */
 301                 if (!cpu_online(0))
 302                         _debug_hotplug_cpu(0, 1);
 303                 break;
 304         case PM_POST_RESTORE:
 305                 /*
 306                  * When a resume really happens, this code won't be called.
 307                  *
 308                  * This code is called only when user space hibernation software
 309                  * prepares for snapshot device during boot time. So we just
 310                  * call _debug_hotplug_cpu() to restore to CPU0's state prior to
 311                  * preparing the snapshot device.
 312                  *
 313                  * This works for normal boot case in our CPU0 hotplug debug
 314                  * mode, i.e. CPU0 is offline and user mode hibernation
 315                  * software initializes during boot time.
 316                  *
 317                  * If CPU0 is online and user application accesses snapshot
 318                  * device after boot time, this will offline CPU0 and user may
 319                  * see different CPU0 state before and after accessing
 320                  * the snapshot device. But hopefully this is not a case when
 321                  * user debugging CPU0 hotplug. Even if users hit this case,
 322                  * they can easily online CPU0 back.
 323                  *
 324                  * To simplify this debug code, we only consider normal boot
 325                  * case. Otherwise we need to remember CPU0's state and restore
 326                  * to that state and resolve racy conditions etc.
 327                  */
 328                 _debug_hotplug_cpu(0, 0);
 329                 break;
 330 #endif
 331         default:
 332                 break;
 333         }
 334         return notifier_from_errno(ret);
 335 }
 336
 337 static int __init bsp_pm_check_init(void)
 338 {
 339         /*
 340          * Set this bsp_pm_callback as lower priority than
 341          * cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called
 342          * earlier to disable cpu hotplug before bsp online check.
 343          */
 344         pm_notifier(bsp_pm_callback, -INT_MAX);
 345         return 0;
 346 }
 347
 348 core_initcall(bsp_pm_check_init);
 349
 350 static int msr_init_context(const u32 *msr_id, const int total_num)
 351 {
 352         int i = 0;
 353         struct saved_msr *msr_array;
 354
 355         if (saved_context.saved_msrs.array || saved_context.saved_msrs.num > 0) {
 356                 pr_err("x86/pm: MSR quirk already applied, please check your DMI match table.\n");
 357                 return -EINVAL;
 358         }
 359
 360         msr_array = kmalloc_array(total_num, sizeof(struct saved_msr), GFP_KERNEL);
 361         if (!msr_array) {
 362                 pr_err("x86/pm: Can not allocate memory to save/restore MSRs during suspend.\n");
 363                 return -ENOMEM;
 364         }
 365
 366         for (i = 0; i < total_num; i++) {
 367                 msr_array[i].info.msr_no        = msr_id[i];
 368                 msr_array[i].valid              = false;
 369                 msr_array[i].info.reg.q         = 0;
 370         }
 371         saved_context.saved_msrs.num    = total_num;
 372         saved_context.saved_msrs.array  = msr_array;
 373
 374         return 0;
 375 }
 376
 377 /*
 378  * The following section is a quirk framework for problematic BIOSen:
 379  * Sometimes MSRs are modified by the BIOSen after suspended to
 380  * RAM, this might cause unexpected behavior after wakeup.
 381  * Thus we save/restore these specified MSRs across suspend/resume
 382  * in order to work around it.
 383  *
 384  * For any further problematic BIOSen/platforms,
 385  * please add your own function similar to msr_initialize_bdw.
 386  */
 387 static int msr_initialize_bdw(const struct dmi_system_id *d)
 388 {
 389         /* Add any extra MSR ids into this array. */
 390         u32 bdw_msr_id[] = { MSR_IA32_THERM_CONTROL };
 391
 392         pr_info("x86/pm: %s detected, MSR saving is needed during suspending.\n", d->ident);
 393         return msr_init_context(bdw_msr_id, ARRAY_SIZE(bdw_msr_id));
 394 }
 395
 396 static struct dmi_system_id msr_save_dmi_table[] = {
 397         {
 398          .callback = msr_initialize_bdw,
 399          .ident = "BROADWELL BDX_EP",
 400          .matches = {
 401                 DMI_MATCH(DMI_PRODUCT_NAME, "GRANTLEY"),
 402                 DMI_MATCH(DMI_PRODUCT_VERSION, "E63448-400"),
 403                 },
 404         },
 405         {}
 406 };
 407
 408 static int pm_check_save_msr(void)
 409 {
 410         dmi_check_system(msr_save_dmi_table);
 411         return 0;
 412 }
 413
 414 device_initcall(pm_check_save_msr);