x86/boot: Synchronize trampoline_cr4_features and mmu_cr4_features directly
[deliverable/linux.git] / arch / x86 / realmode / init.c
1 #include <linux/io.h>
2 #include <linux/memblock.h>
3
4 #include <asm/cacheflush.h>
5 #include <asm/pgtable.h>
6 #include <asm/realmode.h>
7 #include <asm/tlbflush.h>
8
9 struct real_mode_header *real_mode_header;
10 u32 *trampoline_cr4_features;
11
12 /* Hold the pgd entry used on booting additional CPUs */
13 pgd_t trampoline_pgd_entry;
14
15 void __init reserve_real_mode(void)
16 {
17 phys_addr_t mem;
18 unsigned char *base;
19 size_t size = PAGE_ALIGN(real_mode_blob_end - real_mode_blob);
20
21 /* Has to be under 1M so we can execute real-mode AP code. */
22 mem = memblock_find_in_range(0, 1<<20, size, PAGE_SIZE);
23 if (!mem)
24 panic("Cannot allocate trampoline\n");
25
26 base = __va(mem);
27 memblock_reserve(mem, size);
28 real_mode_header = (struct real_mode_header *) base;
29 printk(KERN_DEBUG "Base memory trampoline at [%p] %llx size %zu\n",
30 base, (unsigned long long)mem, size);
31 }
32
33 void __init setup_real_mode(void)
34 {
35 u16 real_mode_seg;
36 const u32 *rel;
37 u32 count;
38 unsigned char *base;
39 unsigned long phys_base;
40 struct trampoline_header *trampoline_header;
41 size_t size = PAGE_ALIGN(real_mode_blob_end - real_mode_blob);
42 #ifdef CONFIG_X86_64
43 u64 *trampoline_pgd;
44 u64 efer;
45 #endif
46
47 base = (unsigned char *)real_mode_header;
48
49 memcpy(base, real_mode_blob, size);
50
51 phys_base = __pa(base);
52 real_mode_seg = phys_base >> 4;
53
54 rel = (u32 *) real_mode_relocs;
55
56 /* 16-bit segment relocations. */
57 count = *rel++;
58 while (count--) {
59 u16 *seg = (u16 *) (base + *rel++);
60 *seg = real_mode_seg;
61 }
62
63 /* 32-bit linear relocations. */
64 count = *rel++;
65 while (count--) {
66 u32 *ptr = (u32 *) (base + *rel++);
67 *ptr += phys_base;
68 }
69
70 /* Must be perfomed *after* relocation. */
71 trampoline_header = (struct trampoline_header *)
72 __va(real_mode_header->trampoline_header);
73
74 #ifdef CONFIG_X86_32
75 trampoline_header->start = __pa_symbol(startup_32_smp);
76 trampoline_header->gdt_limit = __BOOT_DS + 7;
77 trampoline_header->gdt_base = __pa_symbol(boot_gdt);
78 #else
79 /*
80 * Some AMD processors will #GP(0) if EFER.LMA is set in WRMSR
81 * so we need to mask it out.
82 */
83 rdmsrl(MSR_EFER, efer);
84 trampoline_header->efer = efer & ~EFER_LMA;
85
86 trampoline_header->start = (u64) secondary_startup_64;
87 trampoline_cr4_features = &trampoline_header->cr4;
88 *trampoline_cr4_features = mmu_cr4_features;
89
90 trampoline_pgd = (u64 *) __va(real_mode_header->trampoline_pgd);
91 trampoline_pgd[0] = trampoline_pgd_entry.pgd;
92 trampoline_pgd[511] = init_level4_pgt[511].pgd;
93 #endif
94 }
95
96 /*
97 * reserve_real_mode() gets called very early, to guarantee the
98 * availability of low memory. This is before the proper kernel page
99 * tables are set up, so we cannot set page permissions in that
100 * function. Also trampoline code will be executed by APs so we
101 * need to mark it executable at do_pre_smp_initcalls() at least,
102 * thus run it as a early_initcall().
103 */
104 static int __init set_real_mode_permissions(void)
105 {
106 unsigned char *base = (unsigned char *) real_mode_header;
107 size_t size = PAGE_ALIGN(real_mode_blob_end - real_mode_blob);
108
109 size_t ro_size =
110 PAGE_ALIGN(real_mode_header->ro_end) -
111 __pa(base);
112
113 size_t text_size =
114 PAGE_ALIGN(real_mode_header->ro_end) -
115 real_mode_header->text_start;
116
117 unsigned long text_start =
118 (unsigned long) __va(real_mode_header->text_start);
119
120 set_memory_nx((unsigned long) base, size >> PAGE_SHIFT);
121 set_memory_ro((unsigned long) base, ro_size >> PAGE_SHIFT);
122 set_memory_x((unsigned long) text_start, text_size >> PAGE_SHIFT);
123
124 return 0;
125 }
126 early_initcall(set_real_mode_permissions);
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