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[PATCH] Refactor some duplicated code in mpparse.c
[deliverable/linux.git] / arch / x86_64 / kernel / mpparse.c
1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16 #include <linux/mm.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/bootmem.h>
20 #include <linux/smp_lock.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/acpi.h>
24 #include <linux/module.h>
25
26 #include <asm/smp.h>
27 #include <asm/mtrr.h>
28 #include <asm/mpspec.h>
29 #include <asm/pgalloc.h>
30 #include <asm/io_apic.h>
31 #include <asm/proto.h>
32 #include <asm/acpi.h>
33
34 /* Have we found an MP table */
35 int smp_found_config;
36 unsigned int __initdata maxcpus = NR_CPUS;
37
38 int acpi_found_madt;
39
40 /*
41 * Various Linux-internal data structures created from the
42 * MP-table.
43 */
44 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
45 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
46
47 static int mp_current_pci_id = 0;
48 /* I/O APIC entries */
49 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
50
51 /* # of MP IRQ source entries */
52 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
53
54 /* MP IRQ source entries */
55 int mp_irq_entries;
56
57 int nr_ioapics;
58 unsigned long mp_lapic_addr = 0;
59
60
61
62 /* Processor that is doing the boot up */
63 unsigned int boot_cpu_id = -1U;
64 /* Internal processor count */
65 unsigned int num_processors __initdata = 0;
66
67 unsigned disabled_cpus __initdata;
68
69 /* Bitmask of physically existing CPUs */
70 physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE;
71
72 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
73
74
75 /*
76 * Intel MP BIOS table parsing routines:
77 */
78
79 /*
80 * Checksum an MP configuration block.
81 */
82
83 static int __init mpf_checksum(unsigned char *mp, int len)
84 {
85 int sum = 0;
86
87 while (len--)
88 sum += *mp++;
89
90 return sum & 0xFF;
91 }
92
93 static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
94 {
95 int cpu;
96 cpumask_t tmp_map;
97 char *bootup_cpu = "";
98
99 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
100 disabled_cpus++;
101 return;
102 }
103 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
104 bootup_cpu = " (Bootup-CPU)";
105 boot_cpu_id = m->mpc_apicid;
106 }
107
108 printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu);
109
110 if (num_processors >= NR_CPUS) {
111 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
112 " Processor ignored.\n", NR_CPUS);
113 return;
114 }
115
116 num_processors++;
117 cpus_complement(tmp_map, cpu_present_map);
118 cpu = first_cpu(tmp_map);
119
120 physid_set(m->mpc_apicid, phys_cpu_present_map);
121 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
122 /*
123 * bios_cpu_apicid is required to have processors listed
124 * in same order as logical cpu numbers. Hence the first
125 * entry is BSP, and so on.
126 */
127 cpu = 0;
128 }
129 bios_cpu_apicid[cpu] = m->mpc_apicid;
130 x86_cpu_to_apicid[cpu] = m->mpc_apicid;
131
132 cpu_set(cpu, cpu_possible_map);
133 cpu_set(cpu, cpu_present_map);
134 }
135
136 static void __init MP_bus_info (struct mpc_config_bus *m)
137 {
138 char str[7];
139
140 memcpy(str, m->mpc_bustype, 6);
141 str[6] = 0;
142 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
143
144 if (strncmp(str, "ISA", 3) == 0) {
145 set_bit(m->mpc_busid, mp_bus_not_pci);
146 } else if (strncmp(str, "PCI", 3) == 0) {
147 clear_bit(m->mpc_busid, mp_bus_not_pci);
148 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
149 mp_current_pci_id++;
150 } else {
151 printk(KERN_ERR "Unknown bustype %s\n", str);
152 }
153 }
154
155 static int bad_ioapic(unsigned long address)
156 {
157 if (nr_ioapics >= MAX_IO_APICS) {
158 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
159 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
160 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
161 }
162 if (!address) {
163 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
164 " found in table, skipping!\n");
165 return 1;
166 }
167 return 0;
168 }
169
170 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
171 {
172 if (!(m->mpc_flags & MPC_APIC_USABLE))
173 return;
174
175 printk("I/O APIC #%d at 0x%X.\n",
176 m->mpc_apicid, m->mpc_apicaddr);
177
178 if (bad_ioapic(m->mpc_apicaddr))
179 return;
180
181 mp_ioapics[nr_ioapics] = *m;
182 nr_ioapics++;
183 }
184
185 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
186 {
187 mp_irqs [mp_irq_entries] = *m;
188 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
189 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
190 m->mpc_irqtype, m->mpc_irqflag & 3,
191 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
192 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
193 if (++mp_irq_entries >= MAX_IRQ_SOURCES)
194 panic("Max # of irq sources exceeded!!\n");
195 }
196
197 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
198 {
199 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
200 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
201 m->mpc_irqtype, m->mpc_irqflag & 3,
202 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
203 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
204 }
205
206 /*
207 * Read/parse the MPC
208 */
209
210 static int __init smp_read_mpc(struct mp_config_table *mpc)
211 {
212 char str[16];
213 int count=sizeof(*mpc);
214 unsigned char *mpt=((unsigned char *)mpc)+count;
215
216 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
217 printk("MPTABLE: bad signature [%c%c%c%c]!\n",
218 mpc->mpc_signature[0],
219 mpc->mpc_signature[1],
220 mpc->mpc_signature[2],
221 mpc->mpc_signature[3]);
222 return 0;
223 }
224 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
225 printk("MPTABLE: checksum error!\n");
226 return 0;
227 }
228 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
229 printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n",
230 mpc->mpc_spec);
231 return 0;
232 }
233 if (!mpc->mpc_lapic) {
234 printk(KERN_ERR "MPTABLE: null local APIC address!\n");
235 return 0;
236 }
237 memcpy(str,mpc->mpc_oem,8);
238 str[8] = 0;
239 printk(KERN_INFO "MPTABLE: OEM ID: %s ",str);
240
241 memcpy(str,mpc->mpc_productid,12);
242 str[12] = 0;
243 printk("MPTABLE: Product ID: %s ",str);
244
245 printk("MPTABLE: APIC at: 0x%X\n",mpc->mpc_lapic);
246
247 /* save the local APIC address, it might be non-default */
248 if (!acpi_lapic)
249 mp_lapic_addr = mpc->mpc_lapic;
250
251 /*
252 * Now process the configuration blocks.
253 */
254 while (count < mpc->mpc_length) {
255 switch(*mpt) {
256 case MP_PROCESSOR:
257 {
258 struct mpc_config_processor *m=
259 (struct mpc_config_processor *)mpt;
260 if (!acpi_lapic)
261 MP_processor_info(m);
262 mpt += sizeof(*m);
263 count += sizeof(*m);
264 break;
265 }
266 case MP_BUS:
267 {
268 struct mpc_config_bus *m=
269 (struct mpc_config_bus *)mpt;
270 MP_bus_info(m);
271 mpt += sizeof(*m);
272 count += sizeof(*m);
273 break;
274 }
275 case MP_IOAPIC:
276 {
277 struct mpc_config_ioapic *m=
278 (struct mpc_config_ioapic *)mpt;
279 MP_ioapic_info(m);
280 mpt += sizeof(*m);
281 count += sizeof(*m);
282 break;
283 }
284 case MP_INTSRC:
285 {
286 struct mpc_config_intsrc *m=
287 (struct mpc_config_intsrc *)mpt;
288
289 MP_intsrc_info(m);
290 mpt += sizeof(*m);
291 count += sizeof(*m);
292 break;
293 }
294 case MP_LINTSRC:
295 {
296 struct mpc_config_lintsrc *m=
297 (struct mpc_config_lintsrc *)mpt;
298 MP_lintsrc_info(m);
299 mpt += sizeof(*m);
300 count += sizeof(*m);
301 break;
302 }
303 }
304 }
305 clustered_apic_check();
306 if (!num_processors)
307 printk(KERN_ERR "MPTABLE: no processors registered!\n");
308 return num_processors;
309 }
310
311 static int __init ELCR_trigger(unsigned int irq)
312 {
313 unsigned int port;
314
315 port = 0x4d0 + (irq >> 3);
316 return (inb(port) >> (irq & 7)) & 1;
317 }
318
319 static void __init construct_default_ioirq_mptable(int mpc_default_type)
320 {
321 struct mpc_config_intsrc intsrc;
322 int i;
323 int ELCR_fallback = 0;
324
325 intsrc.mpc_type = MP_INTSRC;
326 intsrc.mpc_irqflag = 0; /* conforming */
327 intsrc.mpc_srcbus = 0;
328 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
329
330 intsrc.mpc_irqtype = mp_INT;
331
332 /*
333 * If true, we have an ISA/PCI system with no IRQ entries
334 * in the MP table. To prevent the PCI interrupts from being set up
335 * incorrectly, we try to use the ELCR. The sanity check to see if
336 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
337 * never be level sensitive, so we simply see if the ELCR agrees.
338 * If it does, we assume it's valid.
339 */
340 if (mpc_default_type == 5) {
341 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
342
343 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
344 printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n");
345 else {
346 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
347 ELCR_fallback = 1;
348 }
349 }
350
351 for (i = 0; i < 16; i++) {
352 switch (mpc_default_type) {
353 case 2:
354 if (i == 0 || i == 13)
355 continue; /* IRQ0 & IRQ13 not connected */
356 /* fall through */
357 default:
358 if (i == 2)
359 continue; /* IRQ2 is never connected */
360 }
361
362 if (ELCR_fallback) {
363 /*
364 * If the ELCR indicates a level-sensitive interrupt, we
365 * copy that information over to the MP table in the
366 * irqflag field (level sensitive, active high polarity).
367 */
368 if (ELCR_trigger(i))
369 intsrc.mpc_irqflag = 13;
370 else
371 intsrc.mpc_irqflag = 0;
372 }
373
374 intsrc.mpc_srcbusirq = i;
375 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
376 MP_intsrc_info(&intsrc);
377 }
378
379 intsrc.mpc_irqtype = mp_ExtINT;
380 intsrc.mpc_srcbusirq = 0;
381 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
382 MP_intsrc_info(&intsrc);
383 }
384
385 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
386 {
387 struct mpc_config_processor processor;
388 struct mpc_config_bus bus;
389 struct mpc_config_ioapic ioapic;
390 struct mpc_config_lintsrc lintsrc;
391 int linttypes[2] = { mp_ExtINT, mp_NMI };
392 int i;
393
394 /*
395 * local APIC has default address
396 */
397 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
398
399 /*
400 * 2 CPUs, numbered 0 & 1.
401 */
402 processor.mpc_type = MP_PROCESSOR;
403 processor.mpc_apicver = 0;
404 processor.mpc_cpuflag = CPU_ENABLED;
405 processor.mpc_cpufeature = 0;
406 processor.mpc_featureflag = 0;
407 processor.mpc_reserved[0] = 0;
408 processor.mpc_reserved[1] = 0;
409 for (i = 0; i < 2; i++) {
410 processor.mpc_apicid = i;
411 MP_processor_info(&processor);
412 }
413
414 bus.mpc_type = MP_BUS;
415 bus.mpc_busid = 0;
416 switch (mpc_default_type) {
417 default:
418 printk(KERN_ERR "???\nUnknown standard configuration %d\n",
419 mpc_default_type);
420 /* fall through */
421 case 1:
422 case 5:
423 memcpy(bus.mpc_bustype, "ISA ", 6);
424 break;
425 }
426 MP_bus_info(&bus);
427 if (mpc_default_type > 4) {
428 bus.mpc_busid = 1;
429 memcpy(bus.mpc_bustype, "PCI ", 6);
430 MP_bus_info(&bus);
431 }
432
433 ioapic.mpc_type = MP_IOAPIC;
434 ioapic.mpc_apicid = 2;
435 ioapic.mpc_apicver = 0;
436 ioapic.mpc_flags = MPC_APIC_USABLE;
437 ioapic.mpc_apicaddr = 0xFEC00000;
438 MP_ioapic_info(&ioapic);
439
440 /*
441 * We set up most of the low 16 IO-APIC pins according to MPS rules.
442 */
443 construct_default_ioirq_mptable(mpc_default_type);
444
445 lintsrc.mpc_type = MP_LINTSRC;
446 lintsrc.mpc_irqflag = 0; /* conforming */
447 lintsrc.mpc_srcbusid = 0;
448 lintsrc.mpc_srcbusirq = 0;
449 lintsrc.mpc_destapic = MP_APIC_ALL;
450 for (i = 0; i < 2; i++) {
451 lintsrc.mpc_irqtype = linttypes[i];
452 lintsrc.mpc_destapiclint = i;
453 MP_lintsrc_info(&lintsrc);
454 }
455 }
456
457 static struct intel_mp_floating *mpf_found;
458
459 /*
460 * Scan the memory blocks for an SMP configuration block.
461 */
462 void __init get_smp_config (void)
463 {
464 struct intel_mp_floating *mpf = mpf_found;
465
466 /*
467 * ACPI supports both logical (e.g. Hyper-Threading) and physical
468 * processors, where MPS only supports physical.
469 */
470 if (acpi_lapic && acpi_ioapic) {
471 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
472 return;
473 }
474 else if (acpi_lapic)
475 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
476
477 printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
478
479 /*
480 * Now see if we need to read further.
481 */
482 if (mpf->mpf_feature1 != 0) {
483
484 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
485 construct_default_ISA_mptable(mpf->mpf_feature1);
486
487 } else if (mpf->mpf_physptr) {
488
489 /*
490 * Read the physical hardware table. Anything here will
491 * override the defaults.
492 */
493 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
494 smp_found_config = 0;
495 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
496 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
497 return;
498 }
499 /*
500 * If there are no explicit MP IRQ entries, then we are
501 * broken. We set up most of the low 16 IO-APIC pins to
502 * ISA defaults and hope it will work.
503 */
504 if (!mp_irq_entries) {
505 struct mpc_config_bus bus;
506
507 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
508
509 bus.mpc_type = MP_BUS;
510 bus.mpc_busid = 0;
511 memcpy(bus.mpc_bustype, "ISA ", 6);
512 MP_bus_info(&bus);
513
514 construct_default_ioirq_mptable(0);
515 }
516
517 } else
518 BUG();
519
520 printk(KERN_INFO "Processors: %d\n", num_processors);
521 /*
522 * Only use the first configuration found.
523 */
524 }
525
526 static int __init smp_scan_config (unsigned long base, unsigned long length)
527 {
528 extern void __bad_mpf_size(void);
529 unsigned int *bp = phys_to_virt(base);
530 struct intel_mp_floating *mpf;
531
532 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
533 if (sizeof(*mpf) != 16)
534 __bad_mpf_size();
535
536 while (length > 0) {
537 mpf = (struct intel_mp_floating *)bp;
538 if ((*bp == SMP_MAGIC_IDENT) &&
539 (mpf->mpf_length == 1) &&
540 !mpf_checksum((unsigned char *)bp, 16) &&
541 ((mpf->mpf_specification == 1)
542 || (mpf->mpf_specification == 4)) ) {
543
544 smp_found_config = 1;
545 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
546 if (mpf->mpf_physptr)
547 reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE);
548 mpf_found = mpf;
549 return 1;
550 }
551 bp += 4;
552 length -= 16;
553 }
554 return 0;
555 }
556
557 void __init find_smp_config(void)
558 {
559 unsigned int address;
560
561 /*
562 * FIXME: Linux assumes you have 640K of base ram..
563 * this continues the error...
564 *
565 * 1) Scan the bottom 1K for a signature
566 * 2) Scan the top 1K of base RAM
567 * 3) Scan the 64K of bios
568 */
569 if (smp_scan_config(0x0,0x400) ||
570 smp_scan_config(639*0x400,0x400) ||
571 smp_scan_config(0xF0000,0x10000))
572 return;
573 /*
574 * If it is an SMP machine we should know now.
575 *
576 * there is a real-mode segmented pointer pointing to the
577 * 4K EBDA area at 0x40E, calculate and scan it here.
578 *
579 * NOTE! There are Linux loaders that will corrupt the EBDA
580 * area, and as such this kind of SMP config may be less
581 * trustworthy, simply because the SMP table may have been
582 * stomped on during early boot. These loaders are buggy and
583 * should be fixed.
584 */
585
586 address = *(unsigned short *)phys_to_virt(0x40E);
587 address <<= 4;
588 if (smp_scan_config(address, 0x1000))
589 return;
590
591 /* If we have come this far, we did not find an MP table */
592 printk(KERN_INFO "No mptable found.\n");
593 }
594
595 /* --------------------------------------------------------------------------
596 ACPI-based MP Configuration
597 -------------------------------------------------------------------------- */
598
599 #ifdef CONFIG_ACPI
600
601 void __init mp_register_lapic_address(u64 address)
602 {
603 mp_lapic_addr = (unsigned long) address;
604 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
605 if (boot_cpu_id == -1U)
606 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
607 }
608
609 void __cpuinit mp_register_lapic (u8 id, u8 enabled)
610 {
611 struct mpc_config_processor processor;
612 int boot_cpu = 0;
613
614 if (id == boot_cpu_id)
615 boot_cpu = 1;
616
617 processor.mpc_type = MP_PROCESSOR;
618 processor.mpc_apicid = id;
619 processor.mpc_apicver = 0;
620 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
621 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
622 processor.mpc_cpufeature = 0;
623 processor.mpc_featureflag = 0;
624 processor.mpc_reserved[0] = 0;
625 processor.mpc_reserved[1] = 0;
626
627 MP_processor_info(&processor);
628 }
629
630 #define MP_ISA_BUS 0
631 #define MP_MAX_IOAPIC_PIN 127
632
633 static struct mp_ioapic_routing {
634 int apic_id;
635 int gsi_start;
636 int gsi_end;
637 u32 pin_programmed[4];
638 } mp_ioapic_routing[MAX_IO_APICS];
639
640 static int mp_find_ioapic(int gsi)
641 {
642 int i = 0;
643
644 /* Find the IOAPIC that manages this GSI. */
645 for (i = 0; i < nr_ioapics; i++) {
646 if ((gsi >= mp_ioapic_routing[i].gsi_start)
647 && (gsi <= mp_ioapic_routing[i].gsi_end))
648 return i;
649 }
650
651 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
652 return -1;
653 }
654
655 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
656 {
657 int idx = 0;
658
659 if (bad_ioapic(address))
660 return;
661
662 idx = nr_ioapics++;
663
664 mp_ioapics[idx].mpc_type = MP_IOAPIC;
665 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
666 mp_ioapics[idx].mpc_apicaddr = address;
667
668 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
669 mp_ioapics[idx].mpc_apicid = id;
670 mp_ioapics[idx].mpc_apicver = 0;
671
672 /*
673 * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
674 * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
675 */
676 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
677 mp_ioapic_routing[idx].gsi_start = gsi_base;
678 mp_ioapic_routing[idx].gsi_end = gsi_base +
679 io_apic_get_redir_entries(idx);
680
681 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, "
682 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
683 mp_ioapics[idx].mpc_apicaddr,
684 mp_ioapic_routing[idx].gsi_start,
685 mp_ioapic_routing[idx].gsi_end);
686 }
687
688 void __init
689 mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
690 {
691 struct mpc_config_intsrc intsrc;
692 int ioapic = -1;
693 int pin = -1;
694
695 /*
696 * Convert 'gsi' to 'ioapic.pin'.
697 */
698 ioapic = mp_find_ioapic(gsi);
699 if (ioapic < 0)
700 return;
701 pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
702
703 /*
704 * TBD: This check is for faulty timer entries, where the override
705 * erroneously sets the trigger to level, resulting in a HUGE
706 * increase of timer interrupts!
707 */
708 if ((bus_irq == 0) && (trigger == 3))
709 trigger = 1;
710
711 intsrc.mpc_type = MP_INTSRC;
712 intsrc.mpc_irqtype = mp_INT;
713 intsrc.mpc_irqflag = (trigger << 2) | polarity;
714 intsrc.mpc_srcbus = MP_ISA_BUS;
715 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
716 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
717 intsrc.mpc_dstirq = pin; /* INTIN# */
718
719 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
720 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
721 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
722 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
723
724 mp_irqs[mp_irq_entries] = intsrc;
725 if (++mp_irq_entries == MAX_IRQ_SOURCES)
726 panic("Max # of irq sources exceeded!\n");
727 }
728
729 void __init mp_config_acpi_legacy_irqs(void)
730 {
731 struct mpc_config_intsrc intsrc;
732 int i = 0;
733 int ioapic = -1;
734
735 /*
736 * Fabricate the legacy ISA bus (bus #31).
737 */
738 set_bit(MP_ISA_BUS, mp_bus_not_pci);
739
740 /*
741 * Locate the IOAPIC that manages the ISA IRQs (0-15).
742 */
743 ioapic = mp_find_ioapic(0);
744 if (ioapic < 0)
745 return;
746
747 intsrc.mpc_type = MP_INTSRC;
748 intsrc.mpc_irqflag = 0; /* Conforming */
749 intsrc.mpc_srcbus = MP_ISA_BUS;
750 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
751
752 /*
753 * Use the default configuration for the IRQs 0-15. Unless
754 * overridden by (MADT) interrupt source override entries.
755 */
756 for (i = 0; i < 16; i++) {
757 int idx;
758
759 for (idx = 0; idx < mp_irq_entries; idx++) {
760 struct mpc_config_intsrc *irq = mp_irqs + idx;
761
762 /* Do we already have a mapping for this ISA IRQ? */
763 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
764 break;
765
766 /* Do we already have a mapping for this IOAPIC pin */
767 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
768 (irq->mpc_dstirq == i))
769 break;
770 }
771
772 if (idx != mp_irq_entries) {
773 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
774 continue; /* IRQ already used */
775 }
776
777 intsrc.mpc_irqtype = mp_INT;
778 intsrc.mpc_srcbusirq = i; /* Identity mapped */
779 intsrc.mpc_dstirq = i;
780
781 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
782 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
783 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
784 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
785 intsrc.mpc_dstirq);
786
787 mp_irqs[mp_irq_entries] = intsrc;
788 if (++mp_irq_entries == MAX_IRQ_SOURCES)
789 panic("Max # of irq sources exceeded!\n");
790 }
791 }
792
793 #define MAX_GSI_NUM 4096
794
795 int mp_register_gsi(u32 gsi, int triggering, int polarity)
796 {
797 int ioapic = -1;
798 int ioapic_pin = 0;
799 int idx, bit = 0;
800 static int pci_irq = 16;
801 /*
802 * Mapping between Global System Interrupts, which
803 * represent all possible interrupts, to the IRQs
804 * assigned to actual devices.
805 */
806 static int gsi_to_irq[MAX_GSI_NUM];
807
808 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
809 return gsi;
810
811 /* Don't set up the ACPI SCI because it's already set up */
812 if (acpi_fadt.sci_int == gsi)
813 return gsi;
814
815 ioapic = mp_find_ioapic(gsi);
816 if (ioapic < 0) {
817 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
818 return gsi;
819 }
820
821 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
822
823 /*
824 * Avoid pin reprogramming. PRTs typically include entries
825 * with redundant pin->gsi mappings (but unique PCI devices);
826 * we only program the IOAPIC on the first.
827 */
828 bit = ioapic_pin % 32;
829 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
830 if (idx > 3) {
831 printk(KERN_ERR "Invalid reference to IOAPIC pin "
832 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
833 ioapic_pin);
834 return gsi;
835 }
836 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
837 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
838 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
839 return gsi_to_irq[gsi];
840 }
841
842 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
843
844 if (triggering == ACPI_LEVEL_SENSITIVE) {
845 /*
846 * For PCI devices assign IRQs in order, avoiding gaps
847 * due to unused I/O APIC pins.
848 */
849 int irq = gsi;
850 if (gsi < MAX_GSI_NUM) {
851 /*
852 * Retain the VIA chipset work-around (gsi > 15), but
853 * avoid a problem where the 8254 timer (IRQ0) is setup
854 * via an override (so it's not on pin 0 of the ioapic),
855 * and at the same time, the pin 0 interrupt is a PCI
856 * type. The gsi > 15 test could cause these two pins
857 * to be shared as IRQ0, and they are not shareable.
858 * So test for this condition, and if necessary, avoid
859 * the pin collision.
860 */
861 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
862 gsi = pci_irq++;
863 /*
864 * Don't assign IRQ used by ACPI SCI
865 */
866 if (gsi == acpi_fadt.sci_int)
867 gsi = pci_irq++;
868 gsi_to_irq[irq] = gsi;
869 } else {
870 printk(KERN_ERR "GSI %u is too high\n", gsi);
871 return gsi;
872 }
873 }
874
875 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
876 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
877 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
878 return gsi;
879 }
880 #endif /*CONFIG_ACPI*/
Linux kernel - Deliverables
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