2 * Derived from arch/powerpc/kernel/iommu.c
4 * Copyright IBM Corporation, 2006-2007
5 * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us>
7 * Author: Jon Mason <jdmason@kudzu.us>
8 * Author: Muli Ben-Yehuda <muli@il.ibm.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/kernel.h>
26 #include <linux/init.h>
27 #include <linux/types.h>
28 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/string.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/init.h>
34 #include <linux/bitops.h>
35 #include <linux/pci_ids.h>
36 #include <linux/pci.h>
37 #include <linux/delay.h>
38 #include <asm/proto.h>
39 #include <asm/calgary.h>
41 #include <asm/pci-direct.h>
42 #include <asm/system.h>
46 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
47 int use_calgary __read_mostly
= 1;
49 int use_calgary __read_mostly
= 0;
50 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
52 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
53 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
55 /* register offsets inside the host bridge space */
56 #define CALGARY_CONFIG_REG 0x0108
57 #define PHB_CSR_OFFSET 0x0110 /* Channel Status */
58 #define PHB_PLSSR_OFFSET 0x0120
59 #define PHB_CONFIG_RW_OFFSET 0x0160
60 #define PHB_IOBASE_BAR_LOW 0x0170
61 #define PHB_IOBASE_BAR_HIGH 0x0180
62 #define PHB_MEM_1_LOW 0x0190
63 #define PHB_MEM_1_HIGH 0x01A0
64 #define PHB_IO_ADDR_SIZE 0x01B0
65 #define PHB_MEM_1_SIZE 0x01C0
66 #define PHB_MEM_ST_OFFSET 0x01D0
67 #define PHB_AER_OFFSET 0x0200
68 #define PHB_CONFIG_0_HIGH 0x0220
69 #define PHB_CONFIG_0_LOW 0x0230
70 #define PHB_CONFIG_0_END 0x0240
71 #define PHB_MEM_2_LOW 0x02B0
72 #define PHB_MEM_2_HIGH 0x02C0
73 #define PHB_MEM_2_SIZE_HIGH 0x02D0
74 #define PHB_MEM_2_SIZE_LOW 0x02E0
75 #define PHB_DOSHOLE_OFFSET 0x08E0
77 /* CalIOC2 specific */
78 #define PHB_SAVIOR_L2 0x0DB0
79 #define PHB_PAGE_MIG_CTRL 0x0DA8
80 #define PHB_PAGE_MIG_DEBUG 0x0DA0
81 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
84 #define PHB_TCE_ENABLE 0x20000000
85 #define PHB_SLOT_DISABLE 0x1C000000
86 #define PHB_DAC_DISABLE 0x01000000
87 #define PHB_MEM2_ENABLE 0x00400000
88 #define PHB_MCSR_ENABLE 0x00100000
89 /* TAR (Table Address Register) */
90 #define TAR_SW_BITS 0x0000ffffffff800fUL
91 #define TAR_VALID 0x0000000000000008UL
92 /* CSR (Channel/DMA Status Register) */
93 #define CSR_AGENT_MASK 0xffe0ffff
94 /* CCR (Calgary Configuration Register) */
95 #define CCR_2SEC_TIMEOUT 0x000000000000000EUL
96 /* PMCR/PMDR (Page Migration Control/Debug Registers */
97 #define PMR_SOFTSTOP 0x80000000
98 #define PMR_SOFTSTOPFAULT 0x40000000
99 #define PMR_HARDSTOP 0x20000000
101 #define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */
102 #define MAX_NUM_CHASSIS 8 /* max number of chassis */
103 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
104 #define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
105 #define PHBS_PER_CALGARY 4
107 /* register offsets in Calgary's internal register space */
108 static const unsigned long tar_offsets
[] = {
115 static const unsigned long split_queue_offsets
[] = {
116 0x4870 /* SPLIT QUEUE 0 */,
117 0x5870 /* SPLIT QUEUE 1 */,
118 0x6870 /* SPLIT QUEUE 2 */,
119 0x7870 /* SPLIT QUEUE 3 */
122 static const unsigned long phb_offsets
[] = {
129 /* PHB debug registers */
131 static const unsigned long phb_debug_offsets
[] = {
132 0x4000 /* PHB 0 DEBUG */,
133 0x5000 /* PHB 1 DEBUG */,
134 0x6000 /* PHB 2 DEBUG */,
135 0x7000 /* PHB 3 DEBUG */
139 * STUFF register for each debug PHB,
140 * byte 1 = start bus number, byte 2 = end bus number
143 #define PHB_DEBUG_STUFF_OFFSET 0x0020
145 #define EMERGENCY_PAGES 32 /* = 128KB */
147 unsigned int specified_table_size
= TCE_TABLE_SIZE_UNSPECIFIED
;
148 static int translate_empty_slots __read_mostly
= 0;
149 static int calgary_detected __read_mostly
= 0;
151 static struct rio_table_hdr
*rio_table_hdr __initdata
;
152 static struct scal_detail
*scal_devs
[MAX_NUMNODES
] __initdata
;
153 static struct rio_detail
*rio_devs
[MAX_NUMNODES
* 4] __initdata
;
155 struct calgary_bus_info
{
157 unsigned char translation_disabled
;
162 static void calgary_handle_quirks(struct iommu_table
*tbl
, struct pci_dev
*dev
);
163 static void calgary_tce_cache_blast(struct iommu_table
*tbl
);
164 static void calgary_dump_error_regs(struct iommu_table
*tbl
);
165 static void calioc2_handle_quirks(struct iommu_table
*tbl
, struct pci_dev
*dev
);
166 static void calioc2_tce_cache_blast(struct iommu_table
*tbl
);
167 static void calioc2_dump_error_regs(struct iommu_table
*tbl
);
169 static struct cal_chipset_ops calgary_chip_ops
= {
170 .handle_quirks
= calgary_handle_quirks
,
171 .tce_cache_blast
= calgary_tce_cache_blast
,
172 .dump_error_regs
= calgary_dump_error_regs
175 static struct cal_chipset_ops calioc2_chip_ops
= {
176 .handle_quirks
= calioc2_handle_quirks
,
177 .tce_cache_blast
= calioc2_tce_cache_blast
,
178 .dump_error_regs
= calioc2_dump_error_regs
181 static struct calgary_bus_info bus_info
[MAX_PHB_BUS_NUM
] = { { NULL
, 0, 0 }, };
183 /* enable this to stress test the chip's TCE cache */
184 #ifdef CONFIG_IOMMU_DEBUG
185 int debugging __read_mostly
= 1;
187 static inline unsigned long verify_bit_range(unsigned long* bitmap
,
188 int expected
, unsigned long start
, unsigned long end
)
190 unsigned long idx
= start
;
192 BUG_ON(start
>= end
);
195 if (!!test_bit(idx
, bitmap
) != expected
)
200 /* all bits have the expected value */
203 #else /* debugging is disabled */
204 int debugging __read_mostly
= 0;
206 static inline unsigned long verify_bit_range(unsigned long* bitmap
,
207 int expected
, unsigned long start
, unsigned long end
)
212 #endif /* CONFIG_IOMMU_DEBUG */
214 static inline unsigned int num_dma_pages(unsigned long dma
, unsigned int dmalen
)
218 npages
= PAGE_ALIGN(dma
+ dmalen
) - (dma
& PAGE_MASK
);
219 npages
>>= PAGE_SHIFT
;
224 static inline int translate_phb(struct pci_dev
* dev
)
226 int disabled
= bus_info
[dev
->bus
->number
].translation_disabled
;
230 static void iommu_range_reserve(struct iommu_table
*tbl
,
231 unsigned long start_addr
, unsigned int npages
)
235 unsigned long badbit
;
237 index
= start_addr
>> PAGE_SHIFT
;
239 /* bail out if we're asked to reserve a region we don't cover */
240 if (index
>= tbl
->it_size
)
243 end
= index
+ npages
;
244 if (end
> tbl
->it_size
) /* don't go off the table */
247 badbit
= verify_bit_range(tbl
->it_map
, 0, index
, end
);
248 if (badbit
!= ~0UL) {
249 if (printk_ratelimit())
250 printk(KERN_ERR
"Calgary: entry already allocated at "
251 "0x%lx tbl %p dma 0x%lx npages %u\n",
252 badbit
, tbl
, start_addr
, npages
);
255 set_bit_string(tbl
->it_map
, index
, npages
);
258 static unsigned long iommu_range_alloc(struct iommu_table
*tbl
,
261 unsigned long offset
;
265 offset
= find_next_zero_string(tbl
->it_map
, tbl
->it_hint
,
266 tbl
->it_size
, npages
);
267 if (offset
== ~0UL) {
268 tbl
->chip_ops
->tce_cache_blast(tbl
);
269 offset
= find_next_zero_string(tbl
->it_map
, 0,
270 tbl
->it_size
, npages
);
271 if (offset
== ~0UL) {
272 printk(KERN_WARNING
"Calgary: IOMMU full.\n");
273 if (panic_on_overflow
)
274 panic("Calgary: fix the allocator.\n");
276 return bad_dma_address
;
280 set_bit_string(tbl
->it_map
, offset
, npages
);
281 tbl
->it_hint
= offset
+ npages
;
282 BUG_ON(tbl
->it_hint
> tbl
->it_size
);
287 static dma_addr_t
iommu_alloc(struct iommu_table
*tbl
, void *vaddr
,
288 unsigned int npages
, int direction
)
290 unsigned long entry
, flags
;
291 dma_addr_t ret
= bad_dma_address
;
293 spin_lock_irqsave(&tbl
->it_lock
, flags
);
295 entry
= iommu_range_alloc(tbl
, npages
);
297 if (unlikely(entry
== bad_dma_address
))
300 /* set the return dma address */
301 ret
= (entry
<< PAGE_SHIFT
) | ((unsigned long)vaddr
& ~PAGE_MASK
);
303 /* put the TCEs in the HW table */
304 tce_build(tbl
, entry
, npages
, (unsigned long)vaddr
& PAGE_MASK
,
307 spin_unlock_irqrestore(&tbl
->it_lock
, flags
);
312 spin_unlock_irqrestore(&tbl
->it_lock
, flags
);
313 printk(KERN_WARNING
"Calgary: failed to allocate %u pages in "
314 "iommu %p\n", npages
, tbl
);
315 return bad_dma_address
;
318 static void __iommu_free(struct iommu_table
*tbl
, dma_addr_t dma_addr
,
322 unsigned long badbit
;
323 unsigned long badend
;
325 /* were we called with bad_dma_address? */
326 badend
= bad_dma_address
+ (EMERGENCY_PAGES
* PAGE_SIZE
);
327 if (unlikely((dma_addr
>= bad_dma_address
) && (dma_addr
< badend
))) {
328 printk(KERN_ERR
"Calgary: driver tried unmapping bad DMA "
329 "address 0x%Lx\n", dma_addr
);
334 entry
= dma_addr
>> PAGE_SHIFT
;
336 BUG_ON(entry
+ npages
> tbl
->it_size
);
338 tce_free(tbl
, entry
, npages
);
340 badbit
= verify_bit_range(tbl
->it_map
, 1, entry
, entry
+ npages
);
341 if (badbit
!= ~0UL) {
342 if (printk_ratelimit())
343 printk(KERN_ERR
"Calgary: bit is off at 0x%lx "
344 "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
345 badbit
, tbl
, dma_addr
, entry
, npages
);
348 __clear_bit_string(tbl
->it_map
, entry
, npages
);
351 static void iommu_free(struct iommu_table
*tbl
, dma_addr_t dma_addr
,
356 spin_lock_irqsave(&tbl
->it_lock
, flags
);
358 __iommu_free(tbl
, dma_addr
, npages
);
360 spin_unlock_irqrestore(&tbl
->it_lock
, flags
);
363 static inline struct iommu_table
*find_iommu_table(struct device
*dev
)
365 struct pci_dev
*pdev
;
366 struct pci_bus
*pbus
;
367 struct iommu_table
*tbl
;
369 pdev
= to_pci_dev(dev
);
371 /* is the device behind a bridge? */
372 if (unlikely(pdev
->bus
->parent
))
373 pbus
= pdev
->bus
->parent
;
377 tbl
= pbus
->self
->sysdata
;
378 BUG_ON(pdev
->bus
->parent
&& (tbl
->it_busno
!= pdev
->bus
->parent
->number
));
383 static void __calgary_unmap_sg(struct iommu_table
*tbl
,
384 struct scatterlist
*sglist
, int nelems
, int direction
)
388 dma_addr_t dma
= sglist
->dma_address
;
389 unsigned int dmalen
= sglist
->dma_length
;
394 npages
= num_dma_pages(dma
, dmalen
);
395 __iommu_free(tbl
, dma
, npages
);
400 void calgary_unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
401 int nelems
, int direction
)
404 struct iommu_table
*tbl
= find_iommu_table(dev
);
406 if (!translate_phb(to_pci_dev(dev
)))
409 spin_lock_irqsave(&tbl
->it_lock
, flags
);
411 __calgary_unmap_sg(tbl
, sglist
, nelems
, direction
);
413 spin_unlock_irqrestore(&tbl
->it_lock
, flags
);
416 static int calgary_nontranslate_map_sg(struct device
* dev
,
417 struct scatterlist
*sg
, int nelems
, int direction
)
421 for (i
= 0; i
< nelems
; i
++ ) {
422 struct scatterlist
*s
= &sg
[i
];
424 s
->dma_address
= virt_to_bus(page_address(s
->page
) +s
->offset
);
425 s
->dma_length
= s
->length
;
430 int calgary_map_sg(struct device
*dev
, struct scatterlist
*sg
,
431 int nelems
, int direction
)
433 struct iommu_table
*tbl
= find_iommu_table(dev
);
440 if (!translate_phb(to_pci_dev(dev
)))
441 return calgary_nontranslate_map_sg(dev
, sg
, nelems
, direction
);
443 spin_lock_irqsave(&tbl
->it_lock
, flags
);
445 for (i
= 0; i
< nelems
; i
++ ) {
446 struct scatterlist
*s
= &sg
[i
];
449 vaddr
= (unsigned long)page_address(s
->page
) + s
->offset
;
450 npages
= num_dma_pages(vaddr
, s
->length
);
452 entry
= iommu_range_alloc(tbl
, npages
);
453 if (entry
== bad_dma_address
) {
454 /* makes sure unmap knows to stop */
459 s
->dma_address
= (entry
<< PAGE_SHIFT
) | s
->offset
;
461 /* insert into HW table */
462 tce_build(tbl
, entry
, npages
, vaddr
& PAGE_MASK
,
465 s
->dma_length
= s
->length
;
468 spin_unlock_irqrestore(&tbl
->it_lock
, flags
);
472 __calgary_unmap_sg(tbl
, sg
, nelems
, direction
);
473 for (i
= 0; i
< nelems
; i
++) {
474 sg
[i
].dma_address
= bad_dma_address
;
475 sg
[i
].dma_length
= 0;
477 spin_unlock_irqrestore(&tbl
->it_lock
, flags
);
481 dma_addr_t
calgary_map_single(struct device
*dev
, void *vaddr
,
482 size_t size
, int direction
)
484 dma_addr_t dma_handle
= bad_dma_address
;
487 struct iommu_table
*tbl
= find_iommu_table(dev
);
489 uaddr
= (unsigned long)vaddr
;
490 npages
= num_dma_pages(uaddr
, size
);
492 if (translate_phb(to_pci_dev(dev
)))
493 dma_handle
= iommu_alloc(tbl
, vaddr
, npages
, direction
);
495 dma_handle
= virt_to_bus(vaddr
);
500 void calgary_unmap_single(struct device
*dev
, dma_addr_t dma_handle
,
501 size_t size
, int direction
)
503 struct iommu_table
*tbl
= find_iommu_table(dev
);
506 if (!translate_phb(to_pci_dev(dev
)))
509 npages
= num_dma_pages(dma_handle
, size
);
510 iommu_free(tbl
, dma_handle
, npages
);
513 void* calgary_alloc_coherent(struct device
*dev
, size_t size
,
514 dma_addr_t
*dma_handle
, gfp_t flag
)
518 unsigned int npages
, order
;
519 struct iommu_table
*tbl
= find_iommu_table(dev
);
521 size
= PAGE_ALIGN(size
); /* size rounded up to full pages */
522 npages
= size
>> PAGE_SHIFT
;
523 order
= get_order(size
);
525 /* alloc enough pages (and possibly more) */
526 ret
= (void *)__get_free_pages(flag
, order
);
529 memset(ret
, 0, size
);
531 if (translate_phb(to_pci_dev(dev
))) {
532 /* set up tces to cover the allocated range */
533 mapping
= iommu_alloc(tbl
, ret
, npages
, DMA_BIDIRECTIONAL
);
534 if (mapping
== bad_dma_address
)
537 *dma_handle
= mapping
;
538 } else /* non translated slot */
539 *dma_handle
= virt_to_bus(ret
);
544 free_pages((unsigned long)ret
, get_order(size
));
550 static const struct dma_mapping_ops calgary_dma_ops
= {
551 .alloc_coherent
= calgary_alloc_coherent
,
552 .map_single
= calgary_map_single
,
553 .unmap_single
= calgary_unmap_single
,
554 .map_sg
= calgary_map_sg
,
555 .unmap_sg
= calgary_unmap_sg
,
558 static inline void __iomem
* busno_to_bbar(unsigned char num
)
560 return bus_info
[num
].bbar
;
563 static inline int busno_to_phbid(unsigned char num
)
565 return bus_info
[num
].phbid
;
568 static inline unsigned long split_queue_offset(unsigned char num
)
570 size_t idx
= busno_to_phbid(num
);
572 return split_queue_offsets
[idx
];
575 static inline unsigned long tar_offset(unsigned char num
)
577 size_t idx
= busno_to_phbid(num
);
579 return tar_offsets
[idx
];
582 static inline unsigned long phb_offset(unsigned char num
)
584 size_t idx
= busno_to_phbid(num
);
586 return phb_offsets
[idx
];
589 static inline void __iomem
* calgary_reg(void __iomem
*bar
, unsigned long offset
)
591 unsigned long target
= ((unsigned long)bar
) | offset
;
592 return (void __iomem
*)target
;
595 static inline int is_calioc2(unsigned short device
)
597 return (device
== PCI_DEVICE_ID_IBM_CALIOC2
);
600 static inline int is_calgary(unsigned short device
)
602 return (device
== PCI_DEVICE_ID_IBM_CALGARY
);
605 static inline int is_cal_pci_dev(unsigned short device
)
607 return (is_calgary(device
) || is_calioc2(device
));
610 static void calgary_tce_cache_blast(struct iommu_table
*tbl
)
615 void __iomem
*bbar
= tbl
->bbar
;
616 void __iomem
*target
;
618 /* disable arbitration on the bus */
619 target
= calgary_reg(bbar
, phb_offset(tbl
->it_busno
) | PHB_AER_OFFSET
);
623 /* read plssr to ensure it got there */
624 target
= calgary_reg(bbar
, phb_offset(tbl
->it_busno
) | PHB_PLSSR_OFFSET
);
627 /* poll split queues until all DMA activity is done */
628 target
= calgary_reg(bbar
, split_queue_offset(tbl
->it_busno
));
632 } while ((val
& 0xff) != 0xff && i
< 100);
634 printk(KERN_WARNING
"Calgary: PCI bus not quiesced, "
635 "continuing anyway\n");
637 /* invalidate TCE cache */
638 target
= calgary_reg(bbar
, tar_offset(tbl
->it_busno
));
639 writeq(tbl
->tar_val
, target
);
641 /* enable arbitration */
642 target
= calgary_reg(bbar
, phb_offset(tbl
->it_busno
) | PHB_AER_OFFSET
);
644 (void)readl(target
); /* flush */
647 static void calioc2_tce_cache_blast(struct iommu_table
*tbl
)
649 void __iomem
*bbar
= tbl
->bbar
;
650 void __iomem
*target
;
655 unsigned char bus
= tbl
->it_busno
;
658 printk(KERN_DEBUG
"Calgary: CalIOC2 bus 0x%x entering tce cache blast "
659 "sequence - count %d\n", bus
, count
);
661 /* 1. using the Page Migration Control reg set SoftStop */
662 target
= calgary_reg(bbar
, phb_offset(bus
) | PHB_PAGE_MIG_CTRL
);
663 val
= be32_to_cpu(readl(target
));
664 printk(KERN_DEBUG
"1a. read 0x%x [LE] from %p\n", val
, target
);
666 printk(KERN_DEBUG
"1b. writing 0x%x [LE] to %p\n", val
, target
);
667 writel(cpu_to_be32(val
), target
);
669 /* 2. poll split queues until all DMA activity is done */
670 printk(KERN_DEBUG
"2a. starting to poll split queues\n");
671 target
= calgary_reg(bbar
, split_queue_offset(bus
));
673 val64
= readq(target
);
675 } while ((val64
& 0xff) != 0xff && i
< 100);
677 printk(KERN_WARNING
"CalIOC2: PCI bus not quiesced, "
678 "continuing anyway\n");
680 /* 3. poll Page Migration DEBUG for SoftStopFault */
681 target
= calgary_reg(bbar
, phb_offset(bus
) | PHB_PAGE_MIG_DEBUG
);
682 val
= be32_to_cpu(readl(target
));
683 printk(KERN_DEBUG
"3. read 0x%x [LE] from %p\n", val
, target
);
685 /* 4. if SoftStopFault - goto (1) */
686 if (val
& PMR_SOFTSTOPFAULT
) {
690 printk(KERN_WARNING
"CalIOC2: too many SoftStopFaults, "
691 "aborting TCE cache flush sequence!\n");
692 return; /* pray for the best */
696 /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
697 target
= calgary_reg(bbar
, phb_offset(bus
) | PHB_PAGE_MIG_CTRL
);
698 printk(KERN_DEBUG
"5a. slamming into HardStop by reading %p\n", target
);
699 val
= be32_to_cpu(readl(target
));
700 printk(KERN_DEBUG
"5b. read 0x%x [LE] from %p\n", val
, target
);
701 target
= calgary_reg(bbar
, phb_offset(bus
) | PHB_PAGE_MIG_DEBUG
);
702 val
= be32_to_cpu(readl(target
));
703 printk(KERN_DEBUG
"5c. read 0x%x [LE] from %p (debug)\n", val
, target
);
705 /* 6. invalidate TCE cache */
706 printk(KERN_DEBUG
"6. invalidating TCE cache\n");
707 target
= calgary_reg(bbar
, tar_offset(bus
));
708 writeq(tbl
->tar_val
, target
);
710 /* 7. Re-read PMCR */
711 printk(KERN_DEBUG
"7a. Re-reading PMCR\n");
712 target
= calgary_reg(bbar
, phb_offset(bus
) | PHB_PAGE_MIG_CTRL
);
713 val
= be32_to_cpu(readl(target
));
714 printk(KERN_DEBUG
"7b. read 0x%x [LE] from %p\n", val
, target
);
716 /* 8. Remove HardStop */
717 printk(KERN_DEBUG
"8a. removing HardStop from PMCR\n");
718 target
= calgary_reg(bbar
, phb_offset(bus
) | PHB_PAGE_MIG_CTRL
);
720 printk(KERN_DEBUG
"8b. writing 0x%x [LE] to %p\n", val
, target
);
721 writel(cpu_to_be32(val
), target
);
722 val
= be32_to_cpu(readl(target
));
723 printk(KERN_DEBUG
"8c. read 0x%x [LE] from %p\n", val
, target
);
726 static void __init
calgary_reserve_mem_region(struct pci_dev
*dev
, u64 start
,
729 unsigned int numpages
;
731 limit
= limit
| 0xfffff;
734 numpages
= ((limit
- start
) >> PAGE_SHIFT
);
735 iommu_range_reserve(dev
->sysdata
, start
, numpages
);
738 static void __init
calgary_reserve_peripheral_mem_1(struct pci_dev
*dev
)
740 void __iomem
*target
;
741 u64 low
, high
, sizelow
;
743 struct iommu_table
*tbl
= dev
->sysdata
;
744 unsigned char busnum
= dev
->bus
->number
;
745 void __iomem
*bbar
= tbl
->bbar
;
747 /* peripheral MEM_1 region */
748 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_MEM_1_LOW
);
749 low
= be32_to_cpu(readl(target
));
750 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_MEM_1_HIGH
);
751 high
= be32_to_cpu(readl(target
));
752 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_MEM_1_SIZE
);
753 sizelow
= be32_to_cpu(readl(target
));
755 start
= (high
<< 32) | low
;
758 calgary_reserve_mem_region(dev
, start
, limit
);
761 static void __init
calgary_reserve_peripheral_mem_2(struct pci_dev
*dev
)
763 void __iomem
*target
;
765 u64 low
, high
, sizelow
, sizehigh
;
767 struct iommu_table
*tbl
= dev
->sysdata
;
768 unsigned char busnum
= dev
->bus
->number
;
769 void __iomem
*bbar
= tbl
->bbar
;
772 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_CONFIG_RW_OFFSET
);
773 val32
= be32_to_cpu(readl(target
));
774 if (!(val32
& PHB_MEM2_ENABLE
))
777 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_MEM_2_LOW
);
778 low
= be32_to_cpu(readl(target
));
779 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_MEM_2_HIGH
);
780 high
= be32_to_cpu(readl(target
));
781 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_MEM_2_SIZE_LOW
);
782 sizelow
= be32_to_cpu(readl(target
));
783 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_MEM_2_SIZE_HIGH
);
784 sizehigh
= be32_to_cpu(readl(target
));
786 start
= (high
<< 32) | low
;
787 limit
= (sizehigh
<< 32) | sizelow
;
789 calgary_reserve_mem_region(dev
, start
, limit
);
793 * some regions of the IO address space do not get translated, so we
794 * must not give devices IO addresses in those regions. The regions
795 * are the 640KB-1MB region and the two PCI peripheral memory holes.
796 * Reserve all of them in the IOMMU bitmap to avoid giving them out
799 static void __init
calgary_reserve_regions(struct pci_dev
*dev
)
803 struct iommu_table
*tbl
= dev
->sysdata
;
805 /* reserve EMERGENCY_PAGES from bad_dma_address and up */
806 iommu_range_reserve(tbl
, bad_dma_address
, EMERGENCY_PAGES
);
808 /* avoid the BIOS/VGA first 640KB-1MB region */
809 /* for CalIOC2 - avoid the entire first 2MB */
810 if (is_calgary(dev
->device
)) {
811 start
= (640 * 1024);
812 npages
= ((1024 - 640) * 1024) >> PAGE_SHIFT
;
813 } else { /* calioc2 */
815 npages
= (2 * 1024 * 1024) >> PAGE_SHIFT
;
817 iommu_range_reserve(tbl
, start
, npages
);
819 /* reserve the two PCI peripheral memory regions in IO space */
820 calgary_reserve_peripheral_mem_1(dev
);
821 calgary_reserve_peripheral_mem_2(dev
);
824 static int __init
calgary_setup_tar(struct pci_dev
*dev
, void __iomem
*bbar
)
828 void __iomem
*target
;
830 struct iommu_table
*tbl
;
832 /* build TCE tables for each PHB */
833 ret
= build_tce_table(dev
, bbar
);
838 tbl
->it_base
= (unsigned long)bus_info
[dev
->bus
->number
].tce_space
;
839 tce_free(tbl
, 0, tbl
->it_size
);
841 if (is_calgary(dev
->device
))
842 tbl
->chip_ops
= &calgary_chip_ops
;
843 else if (is_calioc2(dev
->device
))
844 tbl
->chip_ops
= &calioc2_chip_ops
;
848 calgary_reserve_regions(dev
);
850 /* set TARs for each PHB */
851 target
= calgary_reg(bbar
, tar_offset(dev
->bus
->number
));
852 val64
= be64_to_cpu(readq(target
));
854 /* zero out all TAR bits under sw control */
855 val64
&= ~TAR_SW_BITS
;
856 table_phys
= (u64
)__pa(tbl
->it_base
);
860 BUG_ON(specified_table_size
> TCE_TABLE_SIZE_8M
);
861 val64
|= (u64
) specified_table_size
;
863 tbl
->tar_val
= cpu_to_be64(val64
);
865 writeq(tbl
->tar_val
, target
);
866 readq(target
); /* flush */
871 static void __init
calgary_free_bus(struct pci_dev
*dev
)
874 struct iommu_table
*tbl
= dev
->sysdata
;
875 void __iomem
*target
;
876 unsigned int bitmapsz
;
878 target
= calgary_reg(tbl
->bbar
, tar_offset(dev
->bus
->number
));
879 val64
= be64_to_cpu(readq(target
));
880 val64
&= ~TAR_SW_BITS
;
881 writeq(cpu_to_be64(val64
), target
);
882 readq(target
); /* flush */
884 bitmapsz
= tbl
->it_size
/ BITS_PER_BYTE
;
885 free_pages((unsigned long)tbl
->it_map
, get_order(bitmapsz
));
891 /* Can't free bootmem allocated memory after system is up :-( */
892 bus_info
[dev
->bus
->number
].tce_space
= NULL
;
895 static void calgary_dump_error_regs(struct iommu_table
*tbl
)
897 void __iomem
*bbar
= tbl
->bbar
;
898 void __iomem
*target
;
901 target
= calgary_reg(bbar
, phb_offset(tbl
->it_busno
) | PHB_CSR_OFFSET
);
902 csr
= be32_to_cpu(readl(target
));
904 target
= calgary_reg(bbar
, phb_offset(tbl
->it_busno
) | PHB_PLSSR_OFFSET
);
905 plssr
= be32_to_cpu(readl(target
));
907 /* If no error, the agent ID in the CSR is not valid */
908 printk(KERN_EMERG
"Calgary: DMA error on Calgary PHB 0x%x, "
909 "0x%08x@CSR 0x%08x@PLSSR\n", tbl
->it_busno
, csr
, plssr
);
912 static void calioc2_dump_error_regs(struct iommu_table
*tbl
)
914 void __iomem
*bbar
= tbl
->bbar
;
915 u32 csr
, csmr
, plssr
, mck
, rcstat
;
916 void __iomem
*target
;
917 unsigned long phboff
= phb_offset(tbl
->it_busno
);
918 unsigned long erroff
;
923 target
= calgary_reg(bbar
, phboff
| PHB_CSR_OFFSET
);
924 csr
= be32_to_cpu(readl(target
));
926 target
= calgary_reg(bbar
, phboff
| PHB_PLSSR_OFFSET
);
927 plssr
= be32_to_cpu(readl(target
));
929 target
= calgary_reg(bbar
, phboff
| 0x290);
930 csmr
= be32_to_cpu(readl(target
));
932 target
= calgary_reg(bbar
, phboff
| 0x800);
933 mck
= be32_to_cpu(readl(target
));
935 printk(KERN_EMERG
"Calgary: DMA error on CalIOC2 PHB 0x%x\n",
938 printk(KERN_EMERG
"Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
939 csr
, plssr
, csmr
, mck
);
941 /* dump rest of error regs */
942 printk(KERN_EMERG
"Calgary: ");
943 for (i
= 0; i
< ARRAY_SIZE(errregs
); i
++) {
944 erroff
= (0x810 + (i
* 0x10)); /* err regs are at 0x810 - 0x870 */
945 target
= calgary_reg(bbar
, phboff
| erroff
);
946 errregs
[i
] = be32_to_cpu(readl(target
));
947 printk("0x%08x@0x%lx ", errregs
[i
], erroff
);
951 /* root complex status */
952 target
= calgary_reg(bbar
, phboff
| PHB_ROOT_COMPLEX_STATUS
);
953 rcstat
= be32_to_cpu(readl(target
));
954 printk(KERN_EMERG
"Calgary: 0x%08x@0x%x\n", rcstat
,
955 PHB_ROOT_COMPLEX_STATUS
);
958 static void calgary_watchdog(unsigned long data
)
960 struct pci_dev
*dev
= (struct pci_dev
*)data
;
961 struct iommu_table
*tbl
= dev
->sysdata
;
962 void __iomem
*bbar
= tbl
->bbar
;
964 void __iomem
*target
;
966 target
= calgary_reg(bbar
, phb_offset(tbl
->it_busno
) | PHB_CSR_OFFSET
);
967 val32
= be32_to_cpu(readl(target
));
969 /* If no error, the agent ID in the CSR is not valid */
970 if (val32
& CSR_AGENT_MASK
) {
971 tbl
->chip_ops
->dump_error_regs(tbl
);
976 /* Disable bus that caused the error */
977 target
= calgary_reg(bbar
, phb_offset(tbl
->it_busno
) |
978 PHB_CONFIG_RW_OFFSET
);
979 val32
= be32_to_cpu(readl(target
));
980 val32
|= PHB_SLOT_DISABLE
;
981 writel(cpu_to_be32(val32
), target
);
982 readl(target
); /* flush */
984 /* Reset the timer */
985 mod_timer(&tbl
->watchdog_timer
, jiffies
+ 2 * HZ
);
989 static void __init
calgary_set_split_completion_timeout(void __iomem
*bbar
,
990 unsigned char busnum
, unsigned long timeout
)
993 void __iomem
*target
;
994 unsigned int phb_shift
= ~0; /* silence gcc */
997 switch (busno_to_phbid(busnum
)) {
998 case 0: phb_shift
= (63 - 19);
1000 case 1: phb_shift
= (63 - 23);
1002 case 2: phb_shift
= (63 - 27);
1004 case 3: phb_shift
= (63 - 35);
1007 BUG_ON(busno_to_phbid(busnum
));
1010 target
= calgary_reg(bbar
, CALGARY_CONFIG_REG
);
1011 val64
= be64_to_cpu(readq(target
));
1013 /* zero out this PHB's timer bits */
1014 mask
= ~(0xFUL
<< phb_shift
);
1016 val64
|= (timeout
<< phb_shift
);
1017 writeq(cpu_to_be64(val64
), target
);
1018 readq(target
); /* flush */
1021 static void calioc2_handle_quirks(struct iommu_table
*tbl
, struct pci_dev
*dev
)
1023 unsigned char busnum
= dev
->bus
->number
;
1024 void __iomem
*bbar
= tbl
->bbar
;
1025 void __iomem
*target
;
1029 * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
1031 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_SAVIOR_L2
);
1032 val
= cpu_to_be32(readl(target
));
1034 writel(cpu_to_be32(val
), target
);
1037 static void calgary_handle_quirks(struct iommu_table
*tbl
, struct pci_dev
*dev
)
1039 unsigned char busnum
= dev
->bus
->number
;
1042 * Give split completion a longer timeout on bus 1 for aic94xx
1043 * http://bugzilla.kernel.org/show_bug.cgi?id=7180
1045 if (is_calgary(dev
->device
) && (busnum
== 1))
1046 calgary_set_split_completion_timeout(tbl
->bbar
, busnum
,
1050 static void __init
calgary_enable_translation(struct pci_dev
*dev
)
1053 unsigned char busnum
;
1054 void __iomem
*target
;
1056 struct iommu_table
*tbl
;
1058 busnum
= dev
->bus
->number
;
1062 /* enable TCE in PHB Config Register */
1063 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_CONFIG_RW_OFFSET
);
1064 val32
= be32_to_cpu(readl(target
));
1065 val32
|= PHB_TCE_ENABLE
| PHB_DAC_DISABLE
| PHB_MCSR_ENABLE
;
1067 printk(KERN_INFO
"Calgary: enabling translation on %s PHB %#x\n",
1068 (dev
->device
== PCI_DEVICE_ID_IBM_CALGARY
) ?
1069 "Calgary" : "CalIOC2", busnum
);
1070 printk(KERN_INFO
"Calgary: errant DMAs will now be prevented on this "
1073 writel(cpu_to_be32(val32
), target
);
1074 readl(target
); /* flush */
1076 init_timer(&tbl
->watchdog_timer
);
1077 tbl
->watchdog_timer
.function
= &calgary_watchdog
;
1078 tbl
->watchdog_timer
.data
= (unsigned long)dev
;
1079 mod_timer(&tbl
->watchdog_timer
, jiffies
);
1082 static void __init
calgary_disable_translation(struct pci_dev
*dev
)
1085 unsigned char busnum
;
1086 void __iomem
*target
;
1088 struct iommu_table
*tbl
;
1090 busnum
= dev
->bus
->number
;
1094 /* disable TCE in PHB Config Register */
1095 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_CONFIG_RW_OFFSET
);
1096 val32
= be32_to_cpu(readl(target
));
1097 val32
&= ~(PHB_TCE_ENABLE
| PHB_DAC_DISABLE
| PHB_MCSR_ENABLE
);
1099 printk(KERN_INFO
"Calgary: disabling translation on PHB %#x!\n", busnum
);
1100 writel(cpu_to_be32(val32
), target
);
1101 readl(target
); /* flush */
1103 del_timer_sync(&tbl
->watchdog_timer
);
1106 static void __init
calgary_init_one_nontraslated(struct pci_dev
*dev
)
1109 dev
->sysdata
= NULL
;
1111 /* is the device behind a bridge? */
1112 if (dev
->bus
->parent
)
1113 dev
->bus
->parent
->self
= dev
;
1115 dev
->bus
->self
= dev
;
1118 static int __init
calgary_init_one(struct pci_dev
*dev
)
1121 struct iommu_table
*tbl
;
1124 BUG_ON(dev
->bus
->number
>= MAX_PHB_BUS_NUM
);
1126 bbar
= busno_to_bbar(dev
->bus
->number
);
1127 ret
= calgary_setup_tar(dev
, bbar
);
1133 if (dev
->bus
->parent
) {
1134 if (dev
->bus
->parent
->self
)
1135 printk(KERN_WARNING
"Calgary: IEEEE, dev %p has "
1136 "bus->parent->self!\n", dev
);
1137 dev
->bus
->parent
->self
= dev
;
1139 dev
->bus
->self
= dev
;
1142 tbl
->chip_ops
->handle_quirks(tbl
, dev
);
1144 calgary_enable_translation(dev
);
1152 static int __init
calgary_locate_bbars(void)
1155 int rioidx
, phb
, bus
;
1157 void __iomem
*target
;
1158 unsigned long offset
;
1159 u8 start_bus
, end_bus
;
1163 for (rioidx
= 0; rioidx
< rio_table_hdr
->num_rio_dev
; rioidx
++) {
1164 struct rio_detail
*rio
= rio_devs
[rioidx
];
1166 if ((rio
->type
!= COMPAT_CALGARY
) && (rio
->type
!= ALT_CALGARY
))
1169 /* map entire 1MB of Calgary config space */
1170 bbar
= ioremap_nocache(rio
->BBAR
, 1024 * 1024);
1174 for (phb
= 0; phb
< PHBS_PER_CALGARY
; phb
++) {
1175 offset
= phb_debug_offsets
[phb
] | PHB_DEBUG_STUFF_OFFSET
;
1176 target
= calgary_reg(bbar
, offset
);
1178 val
= be32_to_cpu(readl(target
));
1180 start_bus
= (u8
)((val
& 0x00FF0000) >> 16);
1181 end_bus
= (u8
)((val
& 0x0000FF00) >> 8);
1184 for (bus
= start_bus
; bus
<= end_bus
; bus
++) {
1185 bus_info
[bus
].bbar
= bbar
;
1186 bus_info
[bus
].phbid
= phb
;
1189 bus_info
[start_bus
].bbar
= bbar
;
1190 bus_info
[start_bus
].phbid
= phb
;
1198 /* scan bus_info and iounmap any bbars we previously ioremap'd */
1199 for (bus
= 0; bus
< ARRAY_SIZE(bus_info
); bus
++)
1200 if (bus_info
[bus
].bbar
)
1201 iounmap(bus_info
[bus
].bbar
);
1206 static int __init
calgary_init(void)
1209 struct pci_dev
*dev
= NULL
;
1212 ret
= calgary_locate_bbars();
1217 dev
= pci_get_device(PCI_VENDOR_ID_IBM
, PCI_ANY_ID
, dev
);
1220 if (!is_cal_pci_dev(dev
->device
))
1222 if (!translate_phb(dev
)) {
1223 calgary_init_one_nontraslated(dev
);
1226 tce_space
= bus_info
[dev
->bus
->number
].tce_space
;
1227 if (!tce_space
&& !translate_empty_slots
) {
1228 printk("Calg: %p failed tce_space check\n", dev
);
1231 ret
= calgary_init_one(dev
);
1240 dev
= pci_get_device_reverse(PCI_VENDOR_ID_IBM
,
1244 if (!is_cal_pci_dev(dev
->device
))
1246 if (!translate_phb(dev
)) {
1250 if (!bus_info
[dev
->bus
->number
].tce_space
&& !translate_empty_slots
)
1253 calgary_disable_translation(dev
);
1254 calgary_free_bus(dev
);
1255 pci_dev_put(dev
); /* Undo calgary_init_one()'s pci_dev_get() */
1261 static inline int __init
determine_tce_table_size(u64 ram
)
1265 if (specified_table_size
!= TCE_TABLE_SIZE_UNSPECIFIED
)
1266 return specified_table_size
;
1269 * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1270 * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1271 * larger table size has twice as many entries, so shift the
1272 * max ram address by 13 to divide by 8K and then look at the
1273 * order of the result to choose between 0-7.
1275 ret
= get_order(ram
>> 13);
1276 if (ret
> TCE_TABLE_SIZE_8M
)
1277 ret
= TCE_TABLE_SIZE_8M
;
1282 static int __init
build_detail_arrays(void)
1285 int i
, scal_detail_size
, rio_detail_size
;
1287 if (rio_table_hdr
->num_scal_dev
> MAX_NUMNODES
){
1289 "Calgary: MAX_NUMNODES too low! Defined as %d, "
1290 "but system has %d nodes.\n",
1291 MAX_NUMNODES
, rio_table_hdr
->num_scal_dev
);
1295 switch (rio_table_hdr
->version
){
1297 scal_detail_size
= 11;
1298 rio_detail_size
= 13;
1301 scal_detail_size
= 12;
1302 rio_detail_size
= 15;
1306 "Calgary: Invalid Rio Grande Table Version: %d\n",
1307 rio_table_hdr
->version
);
1311 ptr
= ((unsigned long)rio_table_hdr
) + 3;
1312 for (i
= 0; i
< rio_table_hdr
->num_scal_dev
;
1313 i
++, ptr
+= scal_detail_size
)
1314 scal_devs
[i
] = (struct scal_detail
*)ptr
;
1316 for (i
= 0; i
< rio_table_hdr
->num_rio_dev
;
1317 i
++, ptr
+= rio_detail_size
)
1318 rio_devs
[i
] = (struct rio_detail
*)ptr
;
1323 static int __init
calgary_bus_has_devices(int bus
, unsigned short pci_dev
)
1328 if (pci_dev
== PCI_DEVICE_ID_IBM_CALIOC2
) {
1330 * FIXME: properly scan for devices accross the
1331 * PCI-to-PCI bridge on every CalIOC2 port.
1336 for (dev
= 1; dev
< 8; dev
++) {
1337 val
= read_pci_config(bus
, dev
, 0, 0);
1338 if (val
!= 0xffffffff)
1341 return (val
!= 0xffffffff);
1344 void __init
detect_calgary(void)
1348 int calgary_found
= 0;
1350 unsigned int offset
, prev_offset
;
1354 * if the user specified iommu=off or iommu=soft or we found
1355 * another HW IOMMU already, bail out.
1357 if (swiotlb
|| no_iommu
|| iommu_detected
)
1363 if (!early_pci_allowed())
1366 printk(KERN_DEBUG
"Calgary: detecting Calgary via BIOS EBDA area\n");
1368 ptr
= (unsigned long)phys_to_virt(get_bios_ebda());
1370 rio_table_hdr
= NULL
;
1374 * The next offset is stored in the 1st word.
1375 * Only parse up until the offset increases:
1377 while (offset
> prev_offset
) {
1378 /* The block id is stored in the 2nd word */
1379 if (*((unsigned short *)(ptr
+ offset
+ 2)) == 0x4752){
1380 /* set the pointer past the offset & block id */
1381 rio_table_hdr
= (struct rio_table_hdr
*)(ptr
+ offset
+ 4);
1384 prev_offset
= offset
;
1385 offset
= *((unsigned short *)(ptr
+ offset
));
1387 if (!rio_table_hdr
) {
1388 printk(KERN_DEBUG
"Calgary: Unable to locate Rio Grande table "
1389 "in EBDA - bailing!\n");
1393 ret
= build_detail_arrays();
1395 printk(KERN_DEBUG
"Calgary: build_detail_arrays ret %d\n", ret
);
1399 specified_table_size
= determine_tce_table_size(end_pfn
* PAGE_SIZE
);
1401 for (bus
= 0; bus
< MAX_PHB_BUS_NUM
; bus
++) {
1402 struct calgary_bus_info
*info
= &bus_info
[bus
];
1403 unsigned short pci_device
;
1406 val
= read_pci_config(bus
, 0, 0, 0);
1407 pci_device
= (val
& 0xFFFF0000) >> 16;
1409 if (!is_cal_pci_dev(pci_device
))
1412 if (info
->translation_disabled
)
1415 if (calgary_bus_has_devices(bus
, pci_device
) ||
1416 translate_empty_slots
) {
1417 tbl
= alloc_tce_table();
1420 info
->tce_space
= tbl
;
1422 printk("Calg: allocated tce_table %p for bus 0x%x\n",
1423 info
->tce_space
, bus
);
1427 printk(KERN_DEBUG
"Calgary: finished detection, Calgary %s\n",
1428 calgary_found
? "found" : "not found");
1430 if (calgary_found
) {
1432 calgary_detected
= 1;
1433 printk(KERN_INFO
"PCI-DMA: Calgary IOMMU detected.\n");
1434 printk(KERN_INFO
"PCI-DMA: Calgary TCE table spec is %d, "
1435 "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size
,
1436 debugging
? "enabled" : "disabled");
1441 for (--bus
; bus
>= 0; --bus
) {
1442 struct calgary_bus_info
*info
= &bus_info
[bus
];
1444 if (info
->tce_space
)
1445 free_tce_table(info
->tce_space
);
1449 int __init
calgary_iommu_init(void)
1453 if (no_iommu
|| swiotlb
)
1456 if (!calgary_detected
)
1459 /* ok, we're trying to use Calgary - let's roll */
1460 printk(KERN_INFO
"PCI-DMA: Using Calgary IOMMU\n");
1462 ret
= calgary_init();
1464 printk(KERN_ERR
"PCI-DMA: Calgary init failed %d, "
1465 "falling back to no_iommu\n", ret
);
1466 if (end_pfn
> MAX_DMA32_PFN
)
1467 printk(KERN_ERR
"WARNING more than 4GB of memory, "
1468 "32bit PCI may malfunction.\n");
1473 bad_dma_address
= 0x0;
1474 dma_ops
= &calgary_dma_ops
;
1479 static int __init
calgary_parse_options(char *p
)
1481 unsigned int bridge
;
1486 if (!strncmp(p
, "64k", 3))
1487 specified_table_size
= TCE_TABLE_SIZE_64K
;
1488 else if (!strncmp(p
, "128k", 4))
1489 specified_table_size
= TCE_TABLE_SIZE_128K
;
1490 else if (!strncmp(p
, "256k", 4))
1491 specified_table_size
= TCE_TABLE_SIZE_256K
;
1492 else if (!strncmp(p
, "512k", 4))
1493 specified_table_size
= TCE_TABLE_SIZE_512K
;
1494 else if (!strncmp(p
, "1M", 2))
1495 specified_table_size
= TCE_TABLE_SIZE_1M
;
1496 else if (!strncmp(p
, "2M", 2))
1497 specified_table_size
= TCE_TABLE_SIZE_2M
;
1498 else if (!strncmp(p
, "4M", 2))
1499 specified_table_size
= TCE_TABLE_SIZE_4M
;
1500 else if (!strncmp(p
, "8M", 2))
1501 specified_table_size
= TCE_TABLE_SIZE_8M
;
1503 len
= strlen("translate_empty_slots");
1504 if (!strncmp(p
, "translate_empty_slots", len
))
1505 translate_empty_slots
= 1;
1507 len
= strlen("disable");
1508 if (!strncmp(p
, "disable", len
)) {
1514 bridge
= simple_strtol(p
, &endp
, 0);
1518 if (bridge
< MAX_PHB_BUS_NUM
) {
1519 printk(KERN_INFO
"Calgary: disabling "
1520 "translation for PHB %#x\n", bridge
);
1521 bus_info
[bridge
].translation_disabled
= 1;
1525 p
= strpbrk(p
, ",");
1533 __setup("calgary=", calgary_parse_options
);
1535 static void __init
calgary_fixup_one_tce_space(struct pci_dev
*dev
)
1537 struct iommu_table
*tbl
;
1538 unsigned int npages
;
1543 for (i
= 0; i
< 4; i
++) {
1544 struct resource
*r
= &dev
->resource
[PCI_BRIDGE_RESOURCES
+ i
];
1546 /* Don't give out TCEs that map MEM resources */
1547 if (!(r
->flags
& IORESOURCE_MEM
))
1550 /* 0-based? we reserve the whole 1st MB anyway */
1554 /* cover the whole region */
1555 npages
= (r
->end
- r
->start
) >> PAGE_SHIFT
;
1558 printk(KERN_DEBUG
"Calg: dev %p [%x] tbl %p reserving "
1559 "0x%Lx-0x%Lx [0x%x pages]\n", dev
, dev
->bus
->number
,
1560 tbl
, r
->start
, r
->end
, npages
);
1562 iommu_range_reserve(tbl
, r
->start
, npages
);
1566 static int __init
calgary_fixup_tce_spaces(void)
1568 struct pci_dev
*dev
= NULL
;
1571 if (no_iommu
|| swiotlb
|| !calgary_detected
)
1574 printk(KERN_DEBUG
"Calgary: fixing tce spaces\n");
1577 dev
= pci_get_device(PCI_VENDOR_ID_IBM
, PCI_ANY_ID
, dev
);
1580 if (!is_cal_pci_dev(dev
->device
))
1582 if (!translate_phb(dev
))
1585 tce_space
= bus_info
[dev
->bus
->number
].tce_space
;
1589 calgary_fixup_one_tce_space(dev
);
1597 * We need to be call after pcibios_assign_resources (fs_initcall level)
1598 * and before device_initcall.
1600 rootfs_initcall(calgary_fixup_tce_spaces
);