cpu/ChangeLog

   1 2020-06-02  Jose E. Marchesi  <jose.marchesi@oracle.com>
   2
   3         * mep.opc (print_slot_insn): Pass the insn endianness to
   4         cgen_get_insn_value.
   5
   6 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
   7             David Faust <david.faust@oracle.com>
   8
   9         * bpf.cpu (define-alu-insn-un): Add definitions of semantics.
  10         (define-alu-insn-mov): Likewise.
  11         (daib): Likewise.
  12         (define-alu-instructions): Likewise.
  13         (define-endian-insn): Likewise.
  14         (define-lddw): Likewise.
  15         (dlabs): Likewise.
  16         (dlind): Likewise.
  17         (dxli): Likewise.
  18         (dxsi): Likewise.
  19         (dsti): Likewise.
  20         (define-ldstx-insns): Likewise.
  21         (define-st-insns): Likewise.
  22         (define-cond-jump-insn): Likewise.
  23         (dcji): Likewise.
  24         (define-condjump-insns): Likewise.
  25         (define-call-insn): Likewise.
  26         (ja): Likewise.
  27         ("exit"): Likewise.
  28         (define-atomic-insns): Likewise.
  29         (sem-exchange-and-add): New macro.
  30         * bpf.cpu ("brkpt"): New instruction.
  31         (bpfbf): Set word-bitsize to 32 and insn-endian big.
  32         (h-gpr): Prefer r0 to `a' and r6 to `ctx'.
  33         (h-pc): Expand definition.
  34         * bpf.opc (bpf_print_insn): Set endian_code to BIG.
  35
  36 2020-05-21  Alan Modra  <amodra@gmail.com>
  37
  38         * mep.opc (mep_cgen_expand_macros_and_parse_operand): Replace
  39         "if (x) free (x)" with "free (x)".
  40
  41 2020-05-19  Stafford Horne  <shorne@gmail.com>
  42
  43         PR 25184
  44         * or1k.cpu (arch or1k): Remove or64 and or64nd machs.
  45         (ORBIS-MACHS, ORFPX32-MACHS): Remove pmacros.
  46         (cpu or1k64bf, mach or64, mach or64nd): Remove definitions.
  47         * or1kcommon.cpu (h-fdr): Remove hardware.
  48         * or1korfpx.cpu (rDDF, rADF, rBDF): Remove operand definitions.
  49         (float-regreg-insn): Remove lf- mnemonic -d instruction pattern.
  50         (float-setflag-insn-base): Remove lf-sf mnemonic -d pattern.
  51         (float-cust-insn): Remove "lf-cust" cust-num "-d" pattern.
  52         (lf-rem-d, lf-itof-d, lf-ftoi-d, lf-madd-d): Remove.
  53
  54 2020-02-16  David Faust  <david.faust@oracle.com>
  55
  56         * bpf.cpu (define-cond-jump-insn): Renamed from djci.
  57         (dcji) New version with support for JMP32
  58
  59 2020-02-03  Alan Modra  <amodra@gmail.com>
  60
  61         * m32c.cpu (f-dsp-64-s16): Mask before shifting signed value.
  62
  63 2020-02-01  Alan Modra  <amodra@gmail.com>
  64
  65         * frv.cpu (f-u12): Multiply rather than left shift signed values.
  66         (f-label16, f-label24): Likewise.
  67
  68 2020-01-30  Alan Modra  <amodra@gmail.com>
  69
  70         * m32c.cpu (f-src32-rn-unprefixed-QI): Shift before inverting.
  71         (f-src32-rn-prefixed-QI, f-dst32-rn-unprefixed-QI): Likewise.
  72         (f-dst32-rn-prefixed-QI): Likewise.
  73         (f-dsp-32-s32): Mask before shifting left.
  74         (f-dsp-48-u32, f-dsp-48-s32): Likewise.
  75         (f-bitbase32-16-s11-unprefixed): Multiply signed field rather than
  76         shifting left.
  77         (f-bitbase32-24-s11-prefixed, f-bitbase32-24-s19-prefixed): Likewise.
  78         (h-gr-SI): Mask before shifting.
  79
  80 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
  81
  82         * bpf.cpu (define-alu-insn-un): The unary BPF instructions
  83         (neg and neg32) use OP_SRC_K even if they operate only in
  84         registers.
  85
  86 2020-01-18  Nick Clifton  <nickc@redhat.com>
  87
  88         Binutils 2.34 branch created.
  89
  90 2020-01-13  Alan Modra  <amodra@gmail.com>
  91
  92         * fr30.cpu (f-disp9, f-disp10, f-s10, f-rel9, f-rel12): Don't
  93         left shift signed values.
  94
  95 2020-01-06  Alan Modra  <amodra@gmail.com>
  96
  97         * m32c.cpu (f-dsp-8-u16, f-dsp-8-s16): Rearrange to mask any sign
  98         bits before shifting rather than masking after shifting.
  99         (f-dsp-16-u16, f-dsp-16-s16, f-dsp-32-u16, f-dsp-32-s16): Likewise.
 100         (f-dsp-40-u16, f-dsp-40-s16, f-dsp-48-u16, f-dsp-48-s16): Likewise.
 101         (f-dsp-64-u16, f-dsp-8-s24): Likewise.
 102         (f-bitbase32-16-s19-unprefixed): Avoid signed left shift.
 103
 104 2020-01-04  Alan Modra  <amodra@gmail.com>
 105
 106         * m32r.cpu (f-disp8): Avoid left shift of negative values.
 107         (f-disp16, f-disp24): Likewise.
 108
 109 2019-12-23  Alan Modra  <amodra@gmail.com>
 110
 111         * iq2000.cpu (f-offset): Avoid left shift of negative values.
 112
 113 2019-12-20  Alan Modra  <amodra@gmail.com>
 114
 115         * or1korbis.cpu (f-disp26, f-disp21): Don't left shift negative values.
 116
 117 2019-12-17  Alan Modra  <amodra@gmail.com>
 118
 119         * bpf.cpu (f-imm64): Avoid signed overflow.
 120
 121 2019-12-16  Alan Modra  <amodra@gmail.com>
 122
 123         * xstormy16.cpu (f-rel12a): Avoid signed overflow.
 124
 125 2019-12-11  Alan Modra  <amodra@gmail.com>
 126
 127         * epiphany.cpu (f-sdisp11): Don't sign extend with shifts.
 128         * lm32.cpu (f-branch, f-vall): Likewise.
 129         * m32.cpu (f-lab-8-16): Likewise.
 130
 131 2019-12-11  Alan Modra  <amodra@gmail.com>
 132
 133         * epiphany.cpu (f-simm8, f-simm24): Use multiply rather than
 134         shift left to avoid UB on left shift of negative values.
 135
 136 2019-11-20  Jose E. Marchesi  <jose.marchesi@oracle.com>
 137
 138         * bpf.cpu: Fix comment describing the 128-bit instruction format.
 139
 140 2019-09-09  Phil Blundell  <pb@pbcl.net>
 141
 142         binutils 2.33 branch created.
 143
 144 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 145
 146         * bpf.cpu (h-gpr): when disassembling, use %r0 and %r6 instead of
 147         %a and %ctx.
 148
 149 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 150
 151         * bpf.cpu (dlabs): New pmacro.
 152         (dlind): Likewise.
 153
 154 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 155
 156         * bpf.cpu (dlsi): ldabs and ldind instructions do not take an
 157         explicit 'dst' argument.
 158
 159 2019-06-13  Stafford Horne  <shorne@gmail.com>
 160
 161         * or1korfpx.cpu (float-setflag-insn-base): Add 'sf' to symbol.
 162
 163 2019-06-13  Stafford Horne  <shorne@gmail.com>
 164
 165         * or1k.cpu (or64nd, or32nd, or1200nd): Update comment.a
 166         (l-adrp): Improve comment.
 167
 168 2019-06-13  Stafford Horne  <shorne@gmail.com>
 169
 170         * or1korfpx.cpu (insn-opcode-float-regreg): Add SFUEQ_S, SFUNE_S,
 171         SFUGT_S, SFUGE_S, SFULT_S, SFULE_S, SFUN_S, SFUEQ_D, SFUNE_D, SFUGT_D,
 172         SFUGE_D, SFULT_D, SFULE_D, SFUN_D opcodes.
 173         (float-setflag-insn-base): New pmacro based on float-setflag-insn.
 174         (float-setflag-symantics, float-setflag-unordered-cmp-symantics,
 175         float-setflag-unordered-symantics): New pmacro for instruction
 176         symantics.
 177         (float-setflag-insn): Update to use float-setflag-insn-base.
 178         (float-setflag-unordered-insn): New pmacro for generating instructions.
 179
 180 2019-06-13  Andrey Bacherov  <avbacherov@opencores.org>
 181             Stafford Horne  <shorne@gmail.com>
 182
 183         * or1k.cpu (ORFPX64A32-MACHS): New pmacro.
 184         (ORFPX-MACHS): Removed pmacro.
 185         * or1k.opc (or1k_cgen_insn_supported): New function.
 186         (CGEN_VALIDATE_INSN_SUPPORTED): Define macro.
 187         (parse_regpair, print_regpair): New functions.
 188         * or1kcommon.cpu (h-spr, spr-shift, spr-address, h-gpr): Reorder
 189         and add comments.
 190         (h-fdr): Update comment to indicate or64.
 191         (reg-pair-reg-lo, reg-pair-reg-hi): New pmacros for register pairs.
 192         (h-fd32r): New hardware for 64-bit fpu registers.
 193         (h-i64r): New hardware for 64-bit int registers.
 194         * or1korbis.cpu (f-resv-8-1): New field.
 195         * or1korfpx.cpu (rDSF, rASF, rBSF): Update attribute to ORFPX32-MACHS.
 196         (rDDF, rADF, rBDF): Update operand comment to indicate or64.
 197         (f-rdoff-10-1, f-raoff-9-1, f-rboff-8-1): New fields.
 198         (h-roff1): New hardware.
 199         (double-field-and-ops mnemonic): New pmacro to generate operations
 200         rDD32F, rAD32F, rBD32F, rDDI and rADI.
 201         (float-regreg-insn): Update single precision generator to MACH
 202         ORFPX32-MACHS.  Add generator for or32 64-bit instructions.
 203         (float-setflag-insn): Update single precision generator to MACH
 204         ORFPX32-MACHS.  Fix double instructions from single to double
 205         precision.  Add generator for or32 64-bit instructions.
 206         (float-cust-insn cust-num): Update single precision generator to MACH
 207         ORFPX32-MACHS.  Add generator for or32 64-bit instructions.
 208         (lf-rem-s, lf-itof-s, lf-ftoi-s, lf-madd-s): Update MACH to
 209         ORFPX32-MACHS.
 210         (lf-rem-d): Fix operation from mod to rem.
 211         (lf-rem-d32, lf-itof-d32, lf-ftoi-d32, lf-madd-d32): New instruction.
 212         (lf-itof-d): Fix operands from single to double.
 213         (lf-ftoi-d): Update operand mode from DI to WI.
 214
 215 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 216
 217         * bpf.cpu: New file.
 218         * bpf.opc: Likewise.
 219
 220 2018-06-24  Nick Clifton  <nickc@redhat.com>
 221
 222         2.32 branch created.
 223
 224 2018-10-05  Richard Henderson  <rth@twiddle.net>
 225             Stafford Horne  <shorne@gmail.com>
 226
 227         * or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
 228         (insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
 229         (l-mul): Fix overflow support and indentation.
 230         (l-mulu): Fix overflow support and indentation.
 231         (l-muld, l-muldu, l-msbu, l-macu): New instructions.
 232         (l-div); Remove incorrect carry behavior.
 233         (l-divu): Fix carry and overflow behavior.
 234         (l-mac): Add overflow support.
 235         (l-msb, l-msbu): Add carry and overflow support.
 236
 237 2018-10-05  Richard Henderson  <rth@twiddle.net>
 238
 239         * or1k.opc (parse_disp26): Add support for plta() relocations.
 240         (parse_disp21): New function.
 241         (or1k_rclass): New enum.
 242         (or1k_rtype): New enum.
 243         (or1k_imm16_relocs): Define new PO and SPO relocation mappings.
 244         (parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations.
 245         (parse_imm16): Add support for the new 21bit and 13bit relocations.
 246         * or1korbis.cpu (f-disp26): Don't assume SI.
 247         (f-disp21): New pc-relative 21-bit 13 shifted to right.
 248         (insn-opcode): Add ADRP.
 249         (l-adrp): New instruction.
 250
 251 2018-10-05  Richard Henderson  <rth@twiddle.net>
 252
 253         * or1k.opc: Add RTYPE_ enum.
 254         (INVALID_STORE_RELOC): New string.
 255         (or1k_imm16_relocs): New array array.
 256         (parse_reloc): New static function that just does the parsing.
 257         (parse_imm16): New static function for generic parsing.
 258         (parse_simm16): Change to just call parse_imm16.
 259         (parse_simm16_split): New function.
 260         (parse_uimm16): Change to call parse_imm16.
 261         (parse_uimm16_split): New function.
 262         * or1korbis.cpu (simm16-split): Change to use new simm16_split.
 263         (uimm16-split): Change to use new uimm16_split.
 264
 265 2018-07-24  Alan Modra  <amodra@gmail.com>
 266
 267         PR 23430
 268         * or1kcommon.cpu (spr-reg-indices): Fix description typo.
 269
 270 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 271
 272         * or1kcommon.cpu (spr-reg-info): Typo fix.
 273
 274 2018-03-03  Alan Modra  <amodra@gmail.com>
 275
 276         * frv.opc: Include opintl.h.
 277         (add_next_to_vliw): Use opcodes_error_handler to print error.
 278         Standardize error message.
 279         (fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise.
 280
 281 2018-01-13  Nick Clifton  <nickc@redhat.com>
 282
 283         2.30 branch created.
 284
 285 2017-03-15  Stafford Horne  <shorne@gmail.com>
 286
 287         * or1kcommon.cpu: Add pc set semantics to also update ppc.
 288
 289 2016-10-06  Alan Modra  <amodra@gmail.com>
 290
 291         * mep.opc (expand_string): Add fall through comment.
 292
 293 2016-03-03  Alan Modra  <amodra@gmail.com>
 294
 295         * fr30.cpu (f-m4): Replace bogus comment with a better guess
 296         at what is really going on.
 297
 298 2016-03-02  Alan Modra  <amodra@gmail.com>
 299
 300         * fr30.cpu (f-m4): Replace -1 << 4 with -16.
 301
 302 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 303
 304         * epiphany.opc (epiphany_print_insn): Set info->bytes_per_line to
 305         a constant to better align disassembler output.
 306
 307 2014-07-20  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 308
 309         * or1korbis.cpu (l-msync, l-psync, l-csync): New instructions.
 310
 311 2014-06-12  Alan Modra  <amodra@gmail.com>
 312
 313         * or1k.opc: Whitespace fixes.
 314
 315 2014-05-08  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 316
 317         * or1korbis.cpu (h-atomic-reserve): New hardware.
 318         (h-atomic-address): Likewise.
 319         (insn-opcode): Add opcodes for LWA and SWA.
 320         (atomic-reserve): New operand.
 321         (atomic-address): Likewise.
 322         (l-lwa, l-swa): New instructions.
 323         (l-lbs): Fix typo in comment.
 324         (store-insn): Clear atomic reserve on store to atomic-address.
 325         Fix register names in fmt field.
 326
 327 2014-04-22  Christian Svensson  <blue@cmd.nu>
 328
 329         * openrisc.cpu: Delete.
 330         * openrisc.opc: Delete.
 331         * or1k.cpu: New file.
 332         * or1k.opc: New file.
 333         * or1kcommon.cpu: New file.
 334         * or1korbis.cpu: New file.
 335         * or1korfpx.cpu: New file.
 336
 337 2013-12-07  Mike Frysinger  <vapier@gentoo.org>
 338
 339         * epiphany.opc: Remove +x file mode.
 340
 341 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 342
 343         PR binutils/15241
 344         * lm32.cpu (Control and status registers): Add CFG2, PSW,
 345         TLBVADDR, TLBPADDR and TLBBADVADDR.
 346
 347 2012-11-30  Oleg Raikhman  <oleg@adapteva.com>
 348             Joern Rennecke  <joern.rennecke@embecosm.com>
 349
 350         * epiphany.cpu (keyword gr-names): Move sb/sl/ip after r9/r10/r12.
 351         (load_insn): Add NO-DIS attribute to x, p, d, dpm, dl0, dl0.l.
 352         (testset-insn): Add NO_DIS attribute to t.l.
 353         (store-insn): Add NO-DIS attribute to x.l, p.l, d.l, dpm.l, dl0.l.
 354         (move-insns): Add NO-DIS attribute to cmov.l.
 355         (op-mmr-movts): Add NO-DIS attribute to movts.l.
 356         (op-mmr-movfs): Add NO-DIS attribute to movfs.l.
 357         (op-rrr): Add NO-DIS attribute to .l.
 358         (shift-rrr): Add NO-DIS attribute to .l.
 359         (op-shift-rri): Add NO-DIS attribute to i32.l.
 360         (bitrl, movtl): Add NO-DIS attribute.
 361         (op-iextrrr): Add NO-DIS attribute to .l
 362         (op-two_operands-float, op-fabs-float): Add NO-DIS attribute to f32.l.
 363         (op-fix2float-float, op-float2fix-float, op-fextop-float): Likewise.
 364
 365 2012-02-27  Alan Modra  <amodra@gmail.com>
 366
 367         * mt.opc (print_dollarhex): Trim values to 32 bits.
 368
 369 2011-12-15  Nick Clifton  <nickc@redhat.com>
 370
 371         * frv.opc (parse_uhi16): Fix handling of %hi operator on 64-bit
 372         hosts.
 373
 374 2011-10-26  Joern Rennecke  <joern.rennecke@embecosm.com>
 375
 376         * epiphany.opc (parse_branch_addr): Fix type of valuep.
 377         Cast value before printing it as a long.
 378         (parse_postindex): Fix type of valuep.
 379
 380 2011-10-25  Joern Rennecke  <joern.rennecke@embecosm.com>
 381
 382         * cpu/epiphany.cpu: New file.
 383         * cpu/epiphany.opc: New file.
 384
 385 2011-08-22  Nick Clifton  <nickc@redhat.com>
 386
 387         * fr30.cpu: Newly contributed file.
 388         * fr30.opc: Likewise.
 389         * ip2k.cpu: Likewise.
 390         * ip2k.opc: Likewise.
 391         * mep-avc.cpu: Likewise.
 392         * mep-avc2.cpu: Likewise.
 393         * mep-c5.cpu: Likewise.
 394         * mep-core.cpu: Likewise.
 395         * mep-default.cpu: Likewise.
 396         * mep-ext-cop.cpu: Likewise.
 397         * mep-fmax.cpu: Likewise.
 398         * mep-h1.cpu: Likewise.
 399         * mep-ivc2.cpu: Likewise.
 400         * mep-rhcop.cpu: Likewise.
 401         * mep-sample-ucidsp.cpu: Likewise.
 402         * mep.cpu: Likewise.
 403         * mep.opc: Likewise.
 404         * openrisc.cpu: Likewise.
 405         * openrisc.opc: Likewise.
 406         * xstormy16.cpu: Likewise.
 407         * xstormy16.opc: Likewise.
 408
 409 2010-10-08  Pierre Muller  <muller@ics.u-strasbg.fr>
 410
 411         * frv.opc: #undef DEBUG.
 412
 413 2010-07-03  DJ Delorie  <dj@delorie.com>
 414
 415         * m32c.cpu (f-dsp-8-s24): Mask high byte after shifting it.
 416
 417 2010-02-11  Doug Evans  <dje@sebabeach.org>
 418
 419         * m32r.cpu (HASH-PREFIX): Delete.
 420         (duhpo, dshpo): New pmacros.
 421         (simm8, simm16): Delete HASH-PREFIX attribute, define with dshpo.
 422         (uimm3, uimm4, uimm5, uimm8, uimm16, imm1): Delete HASH-PREFIX
 423         attribute, define with dshpo.
 424         (uimm24): Delete HASH-PREFIX attribute.
 425         * m32r.opc (CGEN_PRINT_NORMAL): Delete.
 426         (print_signed_with_hash_prefix): New function.
 427         (print_unsigned_with_hash_prefix): New function.
 428         * xc16x.cpu (dowh): New pmacro.
 429         (upof16): Define with dowh, specify print handler.
 430         (qbit, qlobit, qhibit): Ditto.
 431         (upag16): Ditto.
 432         * xc16x.opc (CGEN_PRINT_NORMAL): Delete.
 433         (print_with_dot_prefix): New functions.
 434         (print_with_pof_prefix, print_with_pag_prefix): New functions.
 435
 436 2010-01-24  Doug Evans  <dje@sebabeach.org>
 437
 438         * frv.cpu (floating-point-conversion): Update call to fp conv op.
 439         (floating-point-dual-conversion, ne-floating-point-dual-conversion,
 440         conditional-floating-point-conversion, ne-floating-point-conversion,
 441         float-parallel-mul-add-double-semantics): Ditto.
 442
 443 2010-01-05  Doug Evans  <dje@sebabeach.org>
 444
 445         * m32c.cpu (f-dsp-32-u24): Fix mode of extract handler.
 446         (f-dsp-40-u20, f-dsp-40-u24): Ditto.
 447
 448 2010-01-02  Doug Evans  <dje@sebabeach.org>
 449
 450         * m32c.opc (parse_signed16): Fix typo.
 451
 452 2009-12-11  Nick Clifton  <nickc@redhat.com>
 453
 454         * frv.opc: Fix shadowed variable warnings.
 455         * m32c.opc: Fix shadowed variable warnings.
 456
 457 2009-11-14  Doug Evans  <dje@sebabeach.org>
 458
 459         Must use VOID expression in VOID context.
 460         * xc16x.cpu (mov4): Fix mode of `sequence'.
 461         (mov9, mov10): Ditto.
 462         (movbsrr, moveb1, jmprel, jmpseg, jmps): Fix mode of `if'.
 463         (callr, callseg, calls, trap, rets, reti): Ditto.
 464         (jb, jbc, jnb, jnbs): Fix mode of `if'.  Comment out no-op `sll'.
 465         (atomic, extr, extp, extp1, extpg1, extpr, extpr1): Fix mode of `cond'.
 466         (exts, exts1, extsr, extsr1, prior): Ditto.
 467
 468 2009-10-23  Doug Evans  <dje@sebabeach.org>
 469
 470         * m32c.opc (opc.h): cgen-types.h -> cgen/basic-modes.h.
 471         cgen-ops.h -> cgen/basic-ops.h.
 472
 473 2009-09-25  Alan Modra  <amodra@bigpond.net.au>
 474
 475         * m32r.cpu (stb-plus): Typo fix.
 476
 477 2009-09-23  Doug Evans  <dje@sebabeach.org>
 478
 479         * m32r.cpu (sth-plus): Fix address mode and calculation.
 480         (stb-plus): Ditto.
 481         (clrpsw): Fix mask calculation.
 482         (bset, bclr, btst): Make mode in bit calculation match expression.
 483
 484         * xc16x.cpu (rtl-version): Set to 0.8.
 485         (gr-names, ext-names,psw-names): Update, print-name -> enum-prefix,
 486         make uppercase.  Remove unnecessary name-prefix spec.
 487         (grb-names, conditioncode-names, extconditioncode-names): Ditto.
 488         (grb8-names, r8-names, regmem8-names, regdiv8-names): Ditto.
 489         (reg0-name, reg0-name1, regbmem8-names, memgr8-names): Ditto.
 490         (h-cr): New hardware.
 491         (muls): Comment out parts that won't compile, add fixme.
 492         (mulu, divl, divlu, jmpabs, jmpa-, jmprel, jbc, jnbs, callr): Ditto.
 493         (scxti, scxtmg, scxtm, bclear, bclr18, bset19, bitset, bmov): Ditto.
 494         (bmovn, band, bor, bxor, bcmp, bfldl, bfldh): Ditto.
 495
 496 2009-07-16  Doug Evans  <dje@sebabeach.org>
 497
 498         * cpu/simplify.inc (*): One line doc strings don't need \n.
 499         (df): Invoke define-full-ifield instead of claiming it's an alias.
 500         (dno): Define.
 501         (dnop): Mark as deprecated.
 502
 503 2009-06-22  Alan Modra  <amodra@bigpond.net.au>
 504
 505         * m32c.opc (parse_lab_5_3): Use correct enum.
 506
 507 2009-01-07  Hans-Peter Nilsson  <hp@axis.com>
 508
 509         * frv.cpu (mabshs): Explicitly sign-extend arguments of abs to DI.
 510         (DI-ext-HI, DI-ext-UHI, DI-ext-DI): New pmacros.
 511         (media-arith-sat-semantics): Explicitly sign- or zero-extend
 512         arguments of "operation" to DI using "mode" and the new pmacros.
 513
 514 2009-01-03  Hans-Peter Nilsson  <hp@axis.com>
 515
 516         * cris.cpu (cris-implemented-writable-specregs-v32): Correct size
 517         of number 2, PID.
 518
 519 2008-12-23  Jon Beniston <jon@beniston.com>
 520
 521         * lm32.cpu: New file.
 522         * lm32.opc: New file.
 523
 524 2008-01-29  Alan Modra  <amodra@bigpond.net.au>
 525
 526         * mt.opc (parse_imm16): Apply 2007-09-26 opcodes/mt-asm.c change
 527         to source.
 528
 529 2007-10-22  Hans-Peter Nilsson  <hp@axis.com>
 530
 531         * cris.cpu (movs, movu): Use result of extension operation when
 532         updating flags.
 533
 534 2007-07-04  Nick Clifton  <nickc@redhat.com>
 535
 536         * cris.cpu: Update copyright notice to refer to GPLv3.
 537         * frv.cpu, frv.opc, iq10.cpu, iq2000m.cpu, iq2000.opc, m32c.cpu,
 538         m32c.opc, m32r.cpu, m32r.opc, mt.cpu, mt.opc, sh64-compact.cpu,
 539         sh64-media.cpu, sh.cpu, sh.opc, simplify.inc, xc16x.cpu,
 540         xc16x.opc: Likewise.
 541         * iq2000.cpu: Fix copyright notice to refer to FSF.
 542
 543 2007-04-30  Mark Salter  <msalter@sadr.localdomain>
 544
 545         * frv.cpu (spr-names): Support new coprocessor SPR registers.
 546
 547 2007-04-20  Nick Clifton  <nickc@redhat.com>
 548
 549         * xc16x.cpu: Restore after accidentally overwriting this file with
 550         xc16x.opc.
 551
 552 2007-03-29  DJ Delorie  <dj@redhat.com>
 553
 554         * m32c.cpu (Imm-8-s4n): Fix print hook.
 555         (Lab-24-8, Lab-32-8, Lab-40-8): Fix.
 556         (arith-jnz-imm4-dst-defn): Make relaxable.
 557         (arith-jnz16-imm4-dst-defn): Fix encodings.
 558
 559 2007-03-20  DJ Delorie  <dj@redhat.com>
 560
 561         * m32c.cpu (f-dsp-40-u20, f-dsp-48-u20, Dsp-40-u20, Dsp-40-u20,
 562         mem20): New.
 563         (src16-16-20-An-relative-*): New.
 564         (dst16-*-20-An-relative-*): New.
 565         (dst16-16-16sa-*): New
 566         (dst16-16-16ar-*): New
 567         (dst32-16-16sa-Unprefixed-*): New
 568         (jsri): Fix operands.
 569         (setzx): Fix encoding.
 570
 571 2007-03-08  Alan Modra  <amodra@bigpond.net.au>
 572
 573         * m32r.opc: Formatting.
 574
 575 2006-05-22  Nick Clifton  <nickc@redhat.com>
 576
 577         * iq2000.cpu: Fix include paths for iq2000m.cpu and iq10.cpu.
 578
 579 2006-04-10  DJ Delorie  <dj@redhat.com>
 580
 581         * m32c.opc (parse_unsigned_bitbase): Take a new parameter which
 582         decides if this function accepts symbolic constants or not.
 583         (parse_signed_bitbase): Likewise.
 584         (parse_unsigned_bitbase8): Pass the new parameter.
 585         (parse_unsigned_bitbase11): Likewise.
 586         (parse_unsigned_bitbase16): Likewise.
 587         (parse_unsigned_bitbase19): Likewise.
 588         (parse_unsigned_bitbase27): Likewise.
 589         (parse_signed_bitbase8): Likewise.
 590         (parse_signed_bitbase11): Likewise.
 591         (parse_signed_bitbase19): Likewise.
 592
 593 2006-03-13  DJ Delorie  <dj@redhat.com>
 594
 595         * m32c.cpu (Bit3-S): New.
 596         (btst:s): New.
 597         * m32c.opc (parse_bit3_S): New.
 598
 599         * m32c.cpu (decimal-subtraction16-insn): Add second operand.
 600         (btst): Add optional :G suffix for MACH32.
 601         (or.b:S): New.
 602         (pop.w:G): Add optional :G suffix for MACH16.
 603         (push.b.imm): Fix syntax.
 604
 605 2006-03-10  DJ Delorie  <dj@redhat.com>
 606
 607         * m32c.cpu (mul.l): New.
 608         (mulu.l): New.
 609
 610 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
 611
 612         * xc16x.opc (parse_hash): Return NULL if the input was parsed or
 613         an error message otherwise.
 614         (parse_dot, parse_pof, parse_pag, parse_sof, parse_seg): Likewise.
 615         Fix up comments to correctly describe the functions.
 616
 617 2006-02-24  DJ Delorie  <dj@redhat.com>
 618
 619         * m32c.cpu (RL_TYPE): New attribute, with macros.
 620         (Lab-8-24): Add RELAX.
 621         (unary-insn-defn-g, binary-arith-imm-dst-defn,
 622         binary-arith-imm4-dst-defn): Add 1ADDR attribute.
 623         (binary-arith-src-dst-defn): Add 2ADDR attribute.
 624         (jcnd16-5, jcnd16, jcnd32, jmp16.s, jmp16.b, jmp16.w, jmp16.a,
 625         jmp32.s, jmp32.b, jmp32.w, jmp32.a, jsr16.w, jsr16.a): Add JUMP
 626         attribute.
 627         (jsri16, jsri32): Add 1ADDR attribute.
 628         (jsr32.w, jsr32.a): Add JUMP attribute.
 629
 630 2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
 631             Anil Paranjape   <anilp1@kpitcummins.com>
 632             Shilin Shakti    <shilins@kpitcummins.com>
 633
 634         * xc16x.cpu: New file containing complete CGEN specific XC16X CPU
 635         description.
 636         * xc16x.opc: New file containing supporting XC16C routines.
 637
 638 2006-02-10  Nick Clifton  <nickc@redhat.com>
 639
 640         * iq2000.opc (parse_hi16): Truncate shifted values to 16 bits.
 641
 642 2006-01-06  DJ Delorie  <dj@redhat.com>
 643
 644         * m32c.cpu (mov.w:q): Fix mode.
 645         (push32.b.imm): Likewise, for the comment.
 646
 647 2005-12-16  Nathan Sidwell  <nathan@codesourcery.com>
 648
 649         Second part of ms1 to mt renaming.
 650         * mt.cpu (define-arch, define-isa): Set name to mt.
 651         (define-mach): Adjust.
 652         * mt.opc (CGEN_ASM_HASH): Update.
 653         (mt_asm_hash, mt_cgen_insn_supported): Renamed.
 654         (parse_loopsize, parse_imm16): Adjust.
 655
 656 2005-12-13  DJ Delorie  <dj@redhat.com>
 657
 658         * m32c.cpu (jsri): Fix order so register names aren't treated as
 659         symbols.
 660         (indexb, indexbd, indexbs, indexl, indexld, indexls, indexw,
 661         indexwd, indexws): Fix encodings.
 662
 663 2005-12-12  Nathan Sidwell  <nathan@codesourcery.com>
 664
 665         * mt.cpu: Rename from ms1.cpu.
 666         * mt.opc: Rename from ms1.opc.
 667
 668 2005-12-06  Hans-Peter Nilsson  <hp@axis.com>
 669
 670         * cris.cpu (simplecris-common-writable-specregs)
 671         (simplecris-common-readable-specregs): Split from
 672         simplecris-common-specregs.  All users changed.
 673         (cris-implemented-writable-specregs-v0)
 674         (cris-implemented-readable-specregs-v0): Similar from
 675         cris-implemented-specregs-v0.
 676         (cris-implemented-writable-specregs-v3)
 677         (cris-implemented-readable-specregs-v3)
 678         (cris-implemented-writable-specregs-v8)
 679         (cris-implemented-readable-specregs-v8)
 680         (cris-implemented-writable-specregs-v10)
 681         (cris-implemented-readable-specregs-v10)
 682         (cris-implemented-writable-specregs-v32)
 683         (cris-implemented-readable-specregs-v32): Similar.
 684         (bdap-32-pc, move-m-pcplus-p0, move-m-spplus-p8): New
 685         insns and specializations.
 686
 687 2005-11-08  Nathan Sidwell  <nathan@codesourcery.com>
 688
 689         Add ms2
 690         * ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and
 691         model.
 692         (f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr,
 693         f-cb2incr, f-rc3): New fields.
 694         (LOOP): New instruction.
 695         (JAL-HAZARD): New hazard.
 696         (imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr):
 697         New operands.
 698         (mul, muli, dbnz, iflush): Enable for ms2
 699         (jal, reti): Has JAL-HAZARD.
 700         (ldctxt, ldfb, stfb): Only ms1.
 701         (fbcb): Only ms1,ms1-003.
 702         (wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs,
 703         fbcbincrs, mfbcbincrs): Enable for ms2.
 704         (loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns.
 705         * ms1.opc (parse_loopsize): New.
 706         (parse_imm16): hi16/lo16 relocs are applicable to IMM16L.
 707         (print_pcrel): New.
 708
 709 2005-10-28  Dave Brolley  <brolley@redhat.com>
 710
 711         Contribute the following change:
 712         2003-09-24  Dave Brolley  <brolley@redhat.com>
 713
 714         * frv.opc: Use CGEN_ATTR_VALUE_ENUM_TYPE in place of
 715         CGEN_ATTR_VALUE_TYPE.
 716         * m32c.opc (m32c_cgen_insn_supported): Use CGEN_INSN_BITSET_ATTR_VALUE.
 717         Use cgen_bitset_intersect_p.
 718
 719 2005-10-27  DJ Delorie  <dj@redhat.com>
 720
 721         * m32c.cpu (Imm-8-s4n, Imm-12-s4n): New.
 722         (arith-jnz16-imm4-dst-defn, arith-jnz32-imm4-dst-defn,
 723         arith-jnz-imm4-dst-mach, arith-jnz-imm4-dst): Keep track of which
 724         imm operand is needed.
 725         (adjnz, sbjnz): Pass the right operands.
 726         (unary-insn-defn, unary16-defn, unary32-defn, unary-insn-mach,
 727         unary-insn): Add -g variants for opcodes that need to support :G.
 728         (not.BW:G, push.BW:G): Call it.
 729         (stzx16-imm8-imm8-dsp8sb, stzx16-imm8-imm8-dsp8fb,
 730         stzx16-imm8-imm8-abs16): Fix operand typos.
 731         * m32c.opc (m32c_asm_hash): Support bnCND.
 732         (parse_signed4n, print_signed4n): New.
 733
 734 2005-10-26  DJ Delorie  <dj@redhat.com>
 735
 736         * m32c.cpu (f-dsp-8-s24, Dsp-8-s24): New.
 737         (mov-dspsp-dst-defn, mov-src-dspsp-defn, mov16-dspsp-dst-defn,
 738         mov16-src-dspsp-defn, mov32-dspsp-dst-defn, mov32-src-dspsp-defn):
 739         dsp8[sp] is signed.
 740         (mov.WL:S #imm,A0/A1): dsp24 is signed (i.e. -0x800000..0xffffff).
 741         (mov.BW:S r0,r1): Fix typo r1l->r1.
 742         (tst): Allow :G suffix.
 743         * m32c.opc (parse_signed24): New, for -0x800000..0xffffff.
 744
 745 2005-10-26  Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
 746
 747         * m32r.opc (parse_hi16): Do not assume a 32-bit host word size.
 748
 749 2005-10-25  DJ Delorie  <dj@redhat.com>
 750
 751         * m32c.cpu (add16-bQ-sp,add16-wQ-sp): Fix to allow either width by
 752         making one a macro of the other.
 753
 754 2005-10-21  DJ Delorie  <dj@redhat.com>
 755
 756         * m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing.
 757         (indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl,
 758         indexld, indexls): .w variants have `1' bit.
 759         (rot32.b): QI, not SI.
 760         (rot32.w): HI, not SI.
 761         (xchg16): HI for .w variant.
 762
 763 2005-10-19  Nick Clifton  <nickc@redhat.com>
 764
 765         * m32r.opc (parse_slo16): Fix bad application of previous patch.
 766
 767 2005-10-18  Andreas Schwab  <schwab@suse.de>
 768
 769         * m32r.opc (parse_slo16): Better version of previous patch.
 770
 771 2005-10-14  Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
 772
 773         * cpu/m32r.opc (parse_slo16): Do not assume a 32-bit host word
 774         size.
 775
 776 2005-07-25  DJ Delorie  <dj@redhat.com>
 777
 778         * m32c.opc (parse_unsigned8): Add %dsp8().
 779         (parse_signed8): Add %hi8().
 780         (parse_unsigned16): Add %dsp16().
 781         (parse_signed16): Add %lo16() and %hi16().
 782         (parse_lab_5_3): Make valuep a bfd_vma *.
 783
 784 2005-07-18  Nick Clifton  <nickc@redhat.com>
 785
 786         * m32c.cpu (f-16-8, f-24-8, f-32-16, f-dsp-8-u24): New opcode
 787         components.
 788         (f-lab32-jmp-s): Fix insertion sequence.
 789         (Dsp-8-u24, Lab-5-3, Lab32-jmp-s): New operands.
 790         (Dsp-40-s8): Make parameter be signed.
 791         (Dsp-40-s16): Likewise.
 792         (Dsp-48-s8): Likewise.
 793         (Dsp-48-s16): Likewise.
 794         (Imm-13-u3): Likewise. (Despite its name!)
 795         (BitBase16-16-s8): Make the parameter be unsigned.
 796         (BitBase16-8-u11-S): Likewise.
 797         (Lab-8-8, Lab-8-16, Lab-16-8, jcnd16-5, jcnd16, jcnd32, jmp16.s,
 798         jmp16.b, jmp16.w, jmp32.s, jmp32.b, jmp32.w, jsp16.w, jsr32.w): Allow
 799         relaxation.
 800
 801         * m32c.opc: Fix formatting.
 802         Use safe-ctype.h instead of ctype.h
 803         Move duplicated code sequences into a macro.
 804         Fix compile time warnings about signedness mismatches.
 805         Remove dead code.
 806         (parse_lab_5_3): New parser function.
 807
 808 2005-07-16  Jim Blandy  <jimb@redhat.com>
 809
 810         * m32c.opc (m32c_cgen_insn_supported): Use int, not CGEN_BITSET,
 811         to represent isa sets.
 812
 813 2005-07-15  Jim Blandy  <jimb@redhat.com>
 814
 815         * m32c.cpu, m32c.opc: Fix copyright.
 816
 817 2005-07-14  Jim Blandy  <jimb@redhat.com>
 818
 819         * m32c.cpu, m32c.opc: Machine description for the Renesas M32C.
 820
 821 2005-07-14  Alan Modra  <amodra@bigpond.net.au>
 822
 823         * ms1.opc (print_dollarhex): Correct format string.
 824
 825 2005-07-06  Alan Modra  <amodra@bigpond.net.au>
 826
 827         * iq2000.cpu: Include from binutils cpu dir.
 828
 829 2005-07-05  Nick Clifton  <nickc@redhat.com>
 830
 831         * iq2000.opc (parse_lo16, parse_mlo16): Make value parameter
 832         unsigned in order to avoid compile time warnings about sign
 833         conflicts.
 834
 835         * ms1.opc (parse_*): Likewise.
 836         (parse_imm16): Use a "void *" as it is passed both signed and
 837         unsigned arguments.
 838
 839 2005-07-01  Nick Clifton  <nickc@redhat.com>
 840
 841         * frv.opc: Update to ISO C90 function declaration style.
 842         * iq2000.opc: Likewise.
 843         * m32r.opc: Likewise.
 844         * sh.opc: Likewise.
 845
 846 2005-06-15  Dave Brolley  <brolley@redhat.com>
 847
 848         Contributed by Red Hat.
 849         * ms1.cpu: New file.  Written by Nick Clifton, Stan Cox.
 850         * ms1.opc: New file.  Written by Stan Cox.
 851
 852 2005-05-10  Nick Clifton  <nickc@redhat.com>
 853
 854         * Update the address and phone number of the FSF organization in
 855         the GPL notices in the following files:
 856         cris.cpu, frv.cpu, frv.opc, iq10.cpu, iq2000.opc, iq2000m.cpu,
 857         m32r.cpu, m32r.opc, sh.cpu, sh.opc, sh64-compact.cpu,
 858         sh64-media.cpu, simplify.inc
 859
 860 2005-02-24  Alan Modra  <amodra@bigpond.net.au>
 861
 862         * frv.opc (parse_A): Warning fix.
 863
 864 2005-02-23  Nick Clifton  <nickc@redhat.com>
 865
 866         * frv.opc: Fixed compile time warnings about differing signed'ness
 867         of pointers passed to functions.
 868         * m32r.opc: Likewise.
 869
 870 2005-02-11  Nick Clifton  <nickc@redhat.com>
 871
 872         * iq2000.opc (parse_jtargq10): Change type of valuep argument to
 873         'bfd_vma *' in order avoid compile time warning message.
 874
 875 2005-01-28  Hans-Peter Nilsson  <hp@axis.com>
 876
 877         * cris.cpu (mstep): Add missing insn.
 878
 879 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 880
 881         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 882         * frv.cpu: Add support for TLS annotations in loads and calll.
 883         * frv.opc (parse_symbolic_address): New.
 884         (parse_ldd_annotation): New.
 885         (parse_call_annotation): New.
 886         (parse_ld_annotation): New.
 887         (parse_ulo16, parse_uslo16): Use parse_symbolic_address.
 888         Introduce TLS relocations.
 889         (parse_d12, parse_s12, parse_u12): Likewise.
 890         (parse_uhi16): Likewise.  Fix constant checking on 64-bit host.
 891         (parse_call_label, print_at): New.
 892
 893 2004-12-21  Mikael Starvik  <starvik@axis.com>
 894
 895         * cris.cpu (cris-set-mem): Correct integral write semantics.
 896
 897 2004-11-29  Hans-Peter Nilsson  <hp@axis.com>
 898
 899         * cris.cpu: New file.
 900
 901 2004-11-15  Michael K. Lechner <mike.lechner@gmail.com>
 902
 903         * iq2000.cpu: Added quotes around macro arguments so that they
 904         will work with newer versions of guile.
 905
 906 2004-10-27  Nick Clifton  <nickc@redhat.com>
 907
 908         * iq2000m.cpu (pkrlr1, pkrlr30, rbr1, rbr30, rxr1, rxr30, wbr1,
 909         wbr1u, wbr30, wbr30u, wxr1, wxr1u, wxr30, wxr30u): Add an index
 910         operand.
 911         * iq2000.cpu (dnop index): Rename to _index to avoid complications
 912         with guile.
 913
 914 2004-08-27  Richard Sandiford  <rsandifo@redhat.com>
 915
 916         * frv.cpu (cfmovs): Change UNIT attribute to FMALL.
 917
 918 2004-05-15  Nick Clifton  <nickc@redhat.com>
 919
 920         * iq2000.opc (iq2000_cgen_insn_supported): Make 'insn' argument const.
 921
 922 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 923
 924         * m32r.opc (parse_hi16): Fixed shigh(0xffff8000) bug.
 925
 926 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 927
 928         * frv.cpu (define-arch frv): Add fr450 mach.
 929         (define-mach fr450): New.
 930         (define-model fr450): New.  Add profile units to every fr450 insn.
 931         (define-attr UNIT): Add MDCUTSSI.
 932         (define-attr FR450-MAJOR): New enum.  Add to every fr450 insn.
 933         (define-attr AUDIO): New boolean.
 934         (f-LRAE, f-LRAD, f-LRAS, f-TLBPRopx, f-TLBPRL)
 935         (f-LRA-null, f-TLBPR-null): New fields.
 936         (scr0, scr1, scr2, scr3, imavr1, damvr1, cxnr, ttbr)
 937         (tplr, tppr, tpxr, timerh, timerl, timerd, btbr): New SPRs.
 938         (LRAE, LRAD, LRAS, TLBPRopx, TLBPRL): New operands.
 939         (LRA-null, TLBPR-null): New macros.
 940         (iacc-multiply-r-r, slass, scutss, int-arith-ss-r-r): Add AUDIO attr.
 941         (load-real-address): New macro.
 942         (lrai, lrad, tlbpr): New instructions.
 943         (media-cut-acc, media-cut-acc-ss): Add fr450-major argument.
 944         (mcut, mcuti, mcutss, mcutssi): Adjust accordingly.
 945         (mdcutssi): Change UNIT attribute to MDCUTSSI.
 946         (media-low-clear-semantics, media-scope-limit-semantics)
 947         (media-quad-limit, media-quad-shift): New macros.
 948         (mqlclrhs, mqlmths, mqsllhi, mqsrahi): New instructions.
 949         * frv.opc (frv_is_branch_major, frv_is_float_major, frv_is_media_major)
 950         (frv_is_branch_insn, frv_is_float_insn, frv_is_media_insn)
 951         (frv_vliw_reset, frv_vliw_add_insn): Handle bfd_mach_fr450.
 952         (fr450_unit_mapping): New array.
 953         (fr400_unit_mapping, fr500_unit_mapping, fr550_unit_mapping): Add entry
 954         for new MDCUTSSI unit.
 955         (fr450_check_insn_major_constraints): New function.
 956         (check_insn_major_constraints): Use it.
 957
 958 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 959
 960         * frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit.
 961         (scutss): Change unit to I0.
 962         (calll, callil, ccalll): Add missing FR550-MAJOR and profile unit.
 963         (mqsaths): Fix FR400-MAJOR categorization.
 964         (media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc)
 965         (media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL.
 966         * frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1)
 967         combinations.
 968
 969 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 970
 971         * frv.cpu (r-store, r-store-dual, r-store-quad): Delete.
 972         (rstb, rsth, rst, rstd, rstq): Delete.
 973         (rstbf, rsthf, rstf, rstdf, rstqf): Delete.
 974
 975 2004-02-23  Nick Clifton  <nickc@redhat.com>
 976
 977         * Apply these patches from Renesas:
 978
 979         2004-02-10  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 980
 981         * cpu/m32r.opc (my_print_insn): Fixed incorrect output when
 982         disassembling codes for 0x*2 addresses.
 983
 984         2003-12-15  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 985
 986         * cpu/m32r.cpu: Add PIPE_O attribute to "pop" instruction.
 987
 988         2003-12-03  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 989
 990         * cpu/m32r.cpu : Add new model m32r2.
 991         Add new instructions.
 992         Replace occurrances of 'Mitsubishi' with 'Renesas'.
 993         Changed PIPE attr of push from O to OS.
 994         Care for Little-endian of M32R.
 995         * cpu/m32r.opc (CGEN_DIS_HASH, my_print_insn):
 996         Care for Little-endian of M32R.
 997         (parse_slo16): signed extension for value.
 998
 999 2004-02-20  Andrew Cagney  <cagney@redhat.com>
1000
1001         * m32r.opc, m32r.cpu: New files.  Written by , Doug Evans, Nick
1002         Clifton, Ben Elliston, Matthew Green, and Andrew Haley.
1003
1004         * sh.cpu, sh.opc, sh64-compact.cpu, sh64-media.cpu: New files, all
1005         written by Ben Elliston.
1006
1007 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
1008
1009         * frv.cpu (UNIT): Add IACC.
1010         (iacc-multiply-r-r): Use it.
1011         * frv.opc (fr400_unit_mapping): Add entry for IACC.
1012         (fr500_unit_mapping, fr550_unit_mapping): Likewise.
1013
1014 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
1015
1016         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
1017         * frv.opc (parse_ulo16, parse_uhi16, parse_d12): Fix some
1018         cut&paste errors in shifting/truncating numerical operands.
1019         2003-08-08  Alexandre Oliva  <aoliva@redhat.com>
1020         * frv.opc (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
1021         (parse_uslo16): Likewise.
1022         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
1023         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
1024         (parse_s12): Likewise.
1025         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
1026         * frv.opc (parse_ulo16): Parse gotlo and gotfuncdesclo.
1027         (parse_uslo16): Likewise.
1028         (parse_uhi16): Parse gothi and gotfuncdeschi.
1029         (parse_d12): Parse got12 and gotfuncdesc12.
1030         (parse_s12): Likewise.
1031
1032 2003-10-10  Dave Brolley  <brolley@redhat.com>
1033
1034         * frv.cpu (dnpmop): New p-macro.
1035         (GRdoublek): Use dnpmop.
1036         (CPRdoublek, FRdoublei, FRdoublej, FRdoublek): Ditto.
1037         (store-double-r-r): Use (.sym regtype doublek).
1038         (r-store-double): Ditto.
1039         (store-double-r-r-u): Ditto.
1040         (conditional-store-double): Ditto.
1041         (conditional-store-double-u): Ditto.
1042         (store-double-r-simm): Ditto.
1043         (fmovs): Assign to UNIT FMALL.
1044
1045 2003-10-06  Dave Brolley  <brolley@redhat.com>
1046
1047         * frv.cpu, frv.opc: Add support for fr550.
1048
1049 2003-09-24  Dave Brolley  <brolley@redhat.com>
1050
1051         * frv.cpu (u-commit): New modelling unit for fr500.
1052         (mwtaccg): Use frv_ref_SI to reference ACC40Sk as an input operand.
1053         (commit-r): Use u-commit model for fr500.
1054         (commit): Ditto.
1055         (conditional-float-binary-op): Take profiling data as an argument.
1056         Update callers.
1057         (ne-float-binary-op): Ditto.
1058
1059 2003-09-19  Michael Snyder  <msnyder@redhat.com>
1060
1061         * frv.cpu (nldqi): Delete unimplemented instruction.
1062
1063 2003-09-12  Dave Brolley  <brolley@redhat.com>
1064
1065         * frv.cpu (u-clrgr, u-clrfr): New units of model fr500.
1066         (clear-ne-flag-r): Pass insn profiling in as an argument. Call
1067         frv_ref_SI to get input register referenced for profiling.
1068         (clear-ne-flag-all): Pass insn profiling in as an argument.
1069         (clrgr,clrfr,clrga,clrfa): Add profiling information.
1070
1071 2003-09-11  Michael Snyder  <msnyder@redhat.com>
1072
1073         * frv.cpu: Typographical corrections.
1074
1075 2003-09-09  Dave Brolley  <brolley@redhat.com>
1076
1077         * frv.cpu (media-dual-complex): Change UNIT to FMALL.
1078         (conditional-media-dual-complex, media-quad-complex): Likewise.
1079
1080 2003-09-04  Dave Brolley  <brolley@redhat.com>
1081
1082         * frv.cpu (register-transfer): Pass in all attributes in on argument.
1083         Update all callers.
1084         (conditional-register-transfer): Ditto.
1085         (cache-preload): Ditto.
1086         (floating-point-conversion): Ditto.
1087         (floating-point-neg): Ditto.
1088         (float-abs): Ditto.
1089         (float-binary-op-s): Ditto.
1090         (conditional-float-binary-op): Ditto.
1091         (ne-float-binary-op): Ditto.
1092         (float-dual-arith): Ditto.
1093         (ne-float-dual-arith): Ditto.
1094
1095 2003-09-03  Dave Brolley  <brolley@redhat.com>
1096
1097         * frv.opc (parse_A, parse_A0, parse_A1): New parse handlers.
1098         * frv.cpu (UNIT): Add IALL, FMALL, FMLOW, STORE, SCAN, DCPL, MDUALACC,
1099         MCLRACC-1.
1100         (A): Removed operand.
1101         (A0,A1): New operands replace operand A.
1102         (mnop): Now a real insn
1103         (mclracc): Removed insn.
1104         (mclracc-0, mclracc-1): New insns replace mclracc.
1105         (all insns): Use new UNIT attributes.
1106
1107 2003-08-21  Nick Clifton  <nickc@redhat.com>
1108
1109         * frv.cpu (mbtoh): Replace input parameter to u-media-dual-expand
1110         and u-media-dual-btoh with output parameter.
1111         (cmbtoh): Add profiling hack.
1112
1113 2003-08-19  Michael Snyder  <msnyder@redhat.com>
1114
1115         * frv.cpu: Fix typo, Frintkeven -> FRintkeven
1116
1117 2003-06-10  Doug Evans  <dje@sebabeach.org>
1118
1119         * frv.cpu: Add IDOC attribute.
1120
1121 2003-06-06  Andrew Cagney  <cagney@redhat.com>
1122
1123         Contributed by Red Hat.
1124         * iq2000.cpu: New file.  Written by Ben Elliston, Jeff Johnston,
1125         Stan Cox, and Frank Ch. Eigler.
1126         * iq2000.opc: New file.  Written by Ben Elliston, Frank
1127         Ch. Eigler, Chris Moller, Jeff Johnston, and Stan Cox.
1128         * iq2000m.cpu: New file.  Written by Jeff Johnston.
1129         * iq10.cpu: New file.  Written by Jeff Johnston.
1130
1131 2003-06-05  Nick Clifton  <nickc@redhat.com>
1132
1133         * frv.cpu (FRintieven): New operand.  An even-numbered only
1134         version of the FRinti operand.
1135         (FRintjeven): Likewise for FRintj.
1136         (FRintkeven): Likewise for FRintk.
1137         (mdcutssi, media-dual-word-rotate-r-r, mqsaths,
1138         media-quad-arith-sat-semantics, media-quad-arith-sat,
1139         conditional-media-quad-arith-sat, mdunpackh,
1140         media-quad-multiply-semantics, media-quad-multiply,
1141         conditional-media-quad-multiply, media-quad-complex-i,
1142         media-quad-multiply-acc-semantics, media-quad-multiply-acc,
1143         conditional-media-quad-multiply-acc, munpackh,
1144         media-quad-multiply-cross-acc-semantics, mdpackh,
1145         media-quad-multiply-cross-acc, mbtoh-semantics,
1146         media-quad-cross-multiply-cross-acc-semantics,
1147         media-quad-cross-multiply-cross-acc, mbtoh, mhtob-semantics,
1148         media-quad-cross-multiply-acc-semantics, cmbtoh,
1149         media-quad-cross-multiply-acc, media-quad-complex, mhtob,
1150         media-expand-halfword-to-double-semantics, mexpdhd, cmexpdhd,
1151         cmhtob): Use new operands.
1152         * frv.opc (CGEN_VERBOSE_ASSEMBLER_ERRORS): Define.
1153         (parse_even_register): New function.
1154
1155 2003-06-03  Nick Clifton  <nickc@redhat.com>
1156
1157         * frv.cpu (media-dual-word-rotate-r-r): Use a signed 6-bit
1158         immediate value not unsigned.
1159
1160 2003-06-03  Andrew Cagney  <cagney@redhat.com>
1161
1162         Contributed by Red Hat.
1163         * frv.cpu: New file.  Written by Dave Brolley, Catherine Moore,
1164         and Eric Christopher.
1165         * frv.opc: New file.  Written by Catherine Moore, and Dave
1166         Brolley.
1167         * simplify.inc: New file.  Written by Doug Evans.
1168
1169 2003-05-02  Andrew Cagney  <cagney@redhat.com>
1170
1171         * New file.
1172
1173 \f
1174 Copyright (C) 2003-2012 Free Software Foundation, Inc.
1175
1176 Copying and distribution of this file, with or without modification,
1177 are permitted in any medium without royalty provided the copyright
1178 notice and this notice are preserved.
1179
1180 Local Variables:
1181 mode: change-log
1182 left-margin: 8
1183 fill-column: 74
1184 version-control: never
1185 End: